
NAGATA Makoto
Graduate School of Science, Technology and Innovation / Department of Science, Technology and Innovation | Professor |
Faculty of Engineering / Department of Computer Science and Systems Engineering | |
Graduate School of Engineering / Department of Chemical Science and Engineering | |
Graduate School of System Informatics / Department of Information Science |
Researcher Information
Research activity information
Award
- Mar. 2024 エレクトロニクス実装学会, 第33回MES2023ベストペーパー賞, 裏面埋設・電源供給配線網を有する3次元集積回路の作製プロセス
- May 2023 IEEE SSCS Japan Chapter, LSIとシステムのワークショップ IEEE SSCS Japan Chapter Academic Research Award, 大規模シリコン量子ビットの高精度制御に向けた極低温バイアス電圧生成回路の開発
- May 2023 電子情報通信学会 / 集積回路研究会, 研究会優秀若手講演賞, 大規模量子ビットアレイの高精度制御に向けた極低温DA変換器の設計
- Sep. 2022 13th International Workshop of Electromagnetic Compatibility (CEM 2022), The best oral communication for junior participant, Electromagnetic Interference of Emission Noise on Mobile Communications Inside Industrial Unmanned Aerial Vehicles
- Jun. 2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) BEST Paper Awards, Multiphysics Simulation of EM Side-Channels from Silicon Backside with ML-based Auto-POI Identification
- May 2022 電子情報通信学会 / 集積回路研究会, 研究会優秀若手講演賞, 電源ノイズシミュレーションによるサイドチャネル漏洩評価手法の検討
- Dec. 2021 電子情報通信学会 / ハードウェアセキュリティ研究専門委員会, 若手優秀賞, 大規模集積回路向け電源ノイズシミュレーションを用いた暗号モジュールのサイドチャネル漏洩評価
- May 2021 IEEE SSCS Japan Chapter, LSIとシステムのワークショップ IEEE SSCS Japan Chapter Academic Reserch Award, 車載向けICチップにおける外部擾乱のアナログ検知手法に関する検討
- Dec. 2020 IEEE / Computer society, Technical Committee on VLSI, Best Paper Award of the 6th IEEE International Symposium on Smart Electronic Systems (iSES), Fast and Comprehensive Simulation Methodology for Layout-Based Power-Noise Side-Channel Leakage Analysis
- Dec. 2020 電子情報通信学会 / ハードウェアセキュリティ研究専門委員会, 若手優秀賞, 電源ノイズシミュレーションを用いた暗号モジュールのサイドチャネル漏洩評価
- Sep. 2020 神戸大学 / 科学技術イノベーション研究科, 研究科優秀教育賞
- Dec. 2019 電子情報通信学会 / ハードウェアセキュリティ研究専門委員会, 若手優秀賞, センサーMCUのAD変換機を悪用したアナログ情報漏洩・改竄攻撃
- Oct. 2019 IEEE / EMC society The 12 th IEEE International Workshop on the Electromagnetic Compatibility of Integrated Circuits, Best Student Award, Magnetic Composite Sheets in IC Chip Packaging for Suppression of Undesired Noise Emission to Wireless Communication Channels
- May 2019 電子情報通信学会 / 集積回路研究会, 若手研究会優秀ポスター賞, オンチップモニタを用いた暗号モジュールにおけるサイドチャネル漏洩の評価
- Dec. 2018 電子情報通信学会 / ハードウェアセキュリティ研究専門委員会, 若手優秀賞, 無線結合とカオス発振を利用したチップ・パッケージング・ボード相互作用PUFの実験と評価
- Dec. 2018 電子情報通信学会 / ハードウェアセキュリティ研究専門委員会, 若手優秀賞, 基板電流センサと電源瞬断回路を利用した小面積レーザーフォールト注入攻撃対策
- Aug. 2018 神戸大学 / 科学技術イノベーション研究科, 優秀教育賞
- Sep. 2015 電子情報通信学会, エレクトロニクスソサイエティ賞, 「VLSIシステムのノイズ問題に関する先駆的貢献」
- Jun. 2015 電子情報通信学会, 第71回 (平成26年度) 論文賞, Diagnosis of Signaling and Power Noise Using In-Place Waveform Capturing for 3D chip Stacking
- May 2015 IEEE / EMC society 2015 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC), Best Symposium Paper Award, On-chip Integrated Magnetic Thin-Film Solution to Countermeasure Digital Noise on RF IC
- May 2015 電子情報通信学会 / 集積回路研究会, 優秀ポスター賞, 暗号処理回路への近傍電磁波解析攻撃を検知する完全デジタル発振器型センサ
- Oct. 2014 IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Best Paper Award, In-Place Signal and Power Noise Waveform Capturing Within 3D Chip Stacking
- Sep. 2014 IACR Workshop on Cryptographic Hardware and Embedded Systems, Best Paper Award, EM Attack is Non-Invasive? - Design Methodology and Validity Verification of EM Attack Sensor
- May 2011 (社)電子情報通信学会集積回路研究専門委員会, 優秀若手講演賞, アナログ基本回路の基板雑音感度に関する考察
- May 2009 エレクトロニクス実装学会, 平成21年技術賞, デジタルLSI電源ノイズのオンチップ観測とシミュレーション技術
- Jun. 2005 中国地域産学官コラボレーションセンター, 大学発ベンチャー功労賞, アナログ/RF回路混載LSIの設計開発と設計者人材育成~株式会社エイアールテック設立~
- May 2005 LSI IPデザイン・アワード運営委員会, 第7回LSI IPデザイン・アワード IP賞, ミックストシグナルLSIのためのオンチップマルチチャネル信号モニタ
Paper
- Apr. 2024, 電子情報通信学会論文誌C, J107-C(4) (4), 175 - 181, Japanese[Refereed]
- Last, Mar. 2024, IEEE Design, Automation and Test in Europe Conference (DATE 2024), EnglishPower-supply noise monitoring to evaluate embedded VRMs and Si-backside buried Decaps[Refereed]
- Institute of Electrical and Electronics Engineers (IEEE), 2024, IEEE Access, 12, 11642 - 11652, EnglishScientific journal
- Oct. 2023, 2023 IEEE Physical Assurance and Inspection of Electronics (PAINE), VIII-B-4, 1 - 7, EnglishNon-Destructive Hardware Trojan Circuit Screening by Backside Near Infrared Imaging[Refereed]
- Lead, IEEE, Sep. 2023, 2023 International Symposium on Electromagnetic Compatibility – EMC Europe, 281, 1 - 4, EnglishInternational conference proceedings
- IEEE, Sep. 2023, 2023 International Symposium on Electromagnetic Compatibility – EMC Europe, 279, 1 - 4, English[Refereed]International conference proceedings
- IEEE, Sep. 2023, 2023 International Symposium on Electromagnetic Compatibility – EMC Europe, 175, 1 - 6, English[Refereed]International conference proceedings
- Sep. 2023, 2023 International Symposium on Electromagnetic Compatibility - EMC Europe, 120, 1 - 5, English[Refereed]
- Sep. 2023, Extended Abstracts of International Conference on Solid State Devices and Materials, B-1-02, 69 - 70, EnglishCryogenic Inter-chip Connection for Silicon Qubit Devices[Refereed]
- Aug. 2023, 電子情報通信学会論文誌B, J-106B(8) (8), 440 - 448, Japanese[Refereed][Invited]
- Jul. 2023, IEICE Transactions on Electronics, E106.C(7) (7), 345 - 351, English[Refereed][Invited]
- Jul. 2023, ACM/IEEE Design Automation Conference (DAC 2023), English, Co-authored internationallyON THE UNPREDICTABILITY OF SPICE SIMULATIONS FOR SIDE-CHANNEL LEAKAGE VERIFICATION OF MASKED CRYPTOGRAPHIC CIRCUITS,[Refereed]
- Jun. 2023, in Proceedings of the IEEE 73rd Electronic Components and Technology Conference (ECTC 2023), 1792 - 1797, EnglishFormation and 3D Stacking Process of CMOS Chips with Backside Buried Metal Power Distribution Networks,[Refereed]
- Jun. 2023, in Proceedings of the IEEE 73rd Electronic Components and Technology Conference (ECTC 2023), 951 - 954, EnglishA Si-Interposer with Buried Cu Metal Stripes and Bonded to Si-Substrate Backside for Security IC Chips,[Refereed]
- Apr. 2023, IEICE Transactions on Electronics(Early access), English[Refereed]
- Apr. 2023, IEICE Transactions on Electronics(Early access), English[Refereed]
- Apr. 2023, Workshop on Nano Security at DATE2023, EnglishSide-Channel Leakage Evaluation of Multi-Chip Cryptographic Modules,
- Mar. 2023, IEEE International Reliability Physics Symposium (IRPS 2023), 22 - 22, English
- Mar. 2023, 2023 IEEE International Solid-State Circuits Conference (ISSCC), 216 - 217, EnglishA Triturated Sensing System[Refereed]
- Mar. 2023, 電子情報通信学会論文誌B, (3) (3), 178 - 186, Japanese[Refereed]Scientific journal
- Jan. 2023, ACM Journal on Emerging Technology in Computing System, 19(1) (1), Article 9, English, Co-authored internationally[Refereed]Scientific journal
- Lead, Jan. 2023, IEEE Solid-State Circuits Magazine, 15(1) (1), 25 - 31, English[Refereed]Scientific journal
- Oct. 2022, in IEEE Design & Test, 39(5) (5), 79 - 87, English, Co-authored internationally[Refereed]Scientific journal
- Oct. 2022, in IEEE Letters on Electromagnetic Compatibility Practice and Applications (LEMCPA), 4(4) (4), 92 - 96, English[Refereed]Scientific journal
- Sep. 2022, in Proceedings of the 2022 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC), FR-AM2-SS07-04(#1570784699) (#1570784699), 1 - 1, EnglishEvaluation of Emission Noise from PCBs Inside an Industrial Unmanned Aerial Vehicle[Refereed]International conference proceedings
- Jul. 2022, in IEEE Transactions on Components, Packaging and Manufacturing Technology, 12(7) (7), 1140 - 1149, English[Refereed]
- Jul. 2022, ACM/IEEE Design Automation Conference (DAC 2022), Engineering Tracks, English, Co-authored internationallyRTL DESIGN SECURITY VERIFICATION FOR RESISTING POWER SIDE-CHANNEL ANALYSIS[Refereed]
- Apr. 2022, IEICE Electronics Express, 19(8) (8), English[Refereed]Scientific journal
- Lead, Mar. 2022, in Proceedings of the IEEE International Reliability Physics Symposium (IRPS 2022), 11C.1, 1 - 6, EnglishExploring Fault Injection Attack Resilience of Secure IC Chips[Refereed]
- Mar. 2022, in Proceedings of IEEE International Reliability Physics Symposium (IRPS 2022), P4, 1 - 6, EnglishVoltage Surges by Backside ESD Impacts on IC Chip in Flip Chip Packaging[Refereed]International conference proceedings
- Mar. 2022, in Proceedings of the 13th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo 2021), 45 - 47, English[Refereed]International conference proceedings
- Mar. 2022, in Proceedings of the 13th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo 2021), 25 - 28, English[Refereed]International conference proceedings
- Feb. 2022, Japanese Journal of Applied Physics, 61(SC0893) (SC0893), 1 - 8, English[Refereed]
- Feb. 2022, Japanese Journal of Applied Physics, 61(SC1045) (SC1045), 1 - 7, English[Refereed]
- Dec. 2021, in Proceedings of the 2021 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 270 - 270, English, Co-authored internationally[Refereed]International conference proceedings
- Sep. 2021, in Proceedings of the 2021 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC), 1 - 4, English[Refereed]International conference proceedings
- Sep. 2021, in Extended Abstracts of the 2021 International Conference on Solid State Devices and Materials (SSDM 2021), L-3-4, 698 - 699, EnglishElectromagnetic Susceptibility of VCO-based ADC in 28 nm CMOS Technology[Refereed]
- Sep. 2021, in Extended Abstracts of the 2021 International Conference on Solid State Devices and Materials (SSDM 2021), L-2-1, 680 - 681, EnglishPhysical Attack Protection Techniques in IC Chips for IoT Security[Refereed][Invited]
- Aug. 2021, in Proc. 26th DesignCon 2021, English, Co-authored internationallyEnabling Secure SoC Design by Fast Power-noise & EM Side-channel Emission Analysis[Refereed]
- Institute of Electronics, Information and Communications Engineers (IEICE), Jul. 2021, IEICE Transactions on Electronics, English[Refereed]Scientific journal
- Institute of Electrical and Electronics Engineers (IEEE), Jun. 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1 - 10, English[Refereed]Scientific journal
- Institute of Electronics, Information and Communications Engineers (IEICE), May 2021, IEICE Electronics Express, 18(9) (9), 20210070 - 20210070, English[Refereed]Scientific journal
- May 2021, in Proceedings of the 26th IEEE European Test Symposium (ETS 2021), S1-2, 1 - 4, English, Co-authored internationallyTesting Embedded Toggle Pattern Generation Through On-Chip IR Drop Monitoring[Refereed]
- Institute of Electrical and Electronics Engineers (IEEE), Apr. 2021, IEEE Transactions on Electron Devices, 68(4) (4), 2077 - 2082, English[Refereed]Scientific journal
- IOP Publishing, Feb. 2021, Japanese Journal of Applied Physics, 60(SB) (SB), SBBL03_1 - SBBL03_9, English[Refereed]Scientific journal
- IOP Publishing, Feb. 2021, Japanese Journal of Applied Physics, 60(SB) (SB), SBBL01_1 - SBBL01_8, English[Refereed]Scientific journal
- Springer Science and Business Media LLC, Jan. 2021, Journal of Cryptographic Engineering, 1 - 10, English[Refereed]Scientific journal
- Institute of Electrical and Electronics Engineers (IEEE), 2021, IEEE Transactions on Information Forensics and Security, 16, 1351 - 1364, English, Co-authored internationally[Refereed]Scientific journal
- Dec. 2020, in Proceedings of the 66th IEEE International Electron Device Meeting (IEDM 2020), EnglishSecure 3D CMOS Chip Stacks with Backside Buried Metal Power Delivery Networks for Distributed Decoupling Capacitance[Refereed]
- Dec. 2020, in Proceedings of 2020 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), English, Co-authored internationallyFast and Comprehensive Simulation Methodology for Layout-Based Power-Noise Side-Channel Leakage Analysis[Refereed]
- Institute of Electronics, Information and Communications Engineers (IEICE), Oct. 2020, IEICE Transactions on Electronics, E103-C(10) (10), 497 - 504, English[Refereed]Scientific journal
- Institute of Electrical and Electronics Engineers (IEEE), Oct. 2020, IEEE Journal of Solid-State Circuits, 55(10) (10), 2747 - 2755, English[Refereed]Scientific journal
- IEEE, Oct. 2020, 2020 IEEE International Symposium on Circuits and Systems (ISCAS), English[Refereed]International conference proceedings
- IEEE, Sep. 2020, 2020 International Symposium on Electromagnetic Compatibility - EMC EUROPE, English[Refereed]International conference proceedings
- Sep. 2020, in Extended Abstracts of International Conference on Solid State Devices and Materials (SSDM), EnglishAn Inductive Impulse Self-Destructor in Sense-and-React Countermeasure Against Physical Attacks[Refereed]
- Sep. 2020, in Extended Abstracts of International Conference on Solid State Devices and Materials (SSDM), EnglishA Dual-mode SAR ADC Enabling On-chip Detection of Off-chip Power Noise Measurements by Attackers[Refereed]
- Sep. 2020, in Proceedings of the 2020 International Symposium on Electromagnetic Compatibility (EMC Europe 2020), EnglishFerromagnetic Noise Suppressor to be Implemented in an IC Chip Package[Refereed]
- Sep. 2020, in Proceedings of the 2020 International Symposium on Electromagnetic Compatibility (EMC Europe 2020), EnglishImpacts of Near-Field Undesired Radio Waves from Semiconductor Switching Circuits on Wireless Communications[Refereed]
- Aug. 2020, in Proceedings of the 2020 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI 2020), EnglishElectromagnetic Susceptibility of a Switched-Mode Power Supply in an Ethernet Switch[Refereed]
- Aug. 2020, in Proceedings of the 2020 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI 2020), EnglishPower Noise Suppression by Land-Side Capacitors within Fan-Out Multiple IC Chip Packaging[Refereed]
- Aug. 2020, in Proceedings of the 2020 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI 2020), EnglishEvaluation of Undesired Radio Waves by Switching Power Circuits using GaN Transistors[Refereed]
- Aug. 2020, in Proceedings of the 2020 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI 2020), EnglishMagnetic Materials for Radio Frequency Noise Suppression in Flipped IC Chip Packaging[Refereed]
- Jul. 2020, ACM/IEEE Design Automation Conference (DAC 2020), English, Co-authored internationallyFast and Comprehensive Layout-Based, Side-Channel Leakage Simulation with Simulation-to-Disclosure Metering[Refereed]
- Institute of Electrical and Electronics Engineers (IEEE), Apr. 2020, IEEE Transactions on Computers, 69(4) (4), 534 - 548, English, Co-authored internationally[Refereed]Scientific journal
- Feb. 2020, Japanese Journal of Applied Physics (JJAP), 59, 1 - 12, EnglishAn IC-level countermeasure against laser fault injection attack by information leakage sensing based on laser-induced opto-electric bulk current density[Refereed]
- IOP Publishing, Jan. 2020, Japanese Journal of Applied Physics, 59(SLLD04) (SLLD04), 1 - 7, English[Refereed]Scientific journal
- Jan. 2020, in Proc. 25th DesignCon 2020, English, Co-authored internationallyA C-P-S Simulation Technique of Power-Noise Side Channel Leakage in Cryptographic Integrated Circuits[Refereed]
- Dec. 2019, in Proceedings of the 9th International Conference on Security, Privacy, and Applied Cryptography Engineering (SPACE 2019), 1 - 5, EnglishDeployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security[Refereed][Invited]
- This paper presents a low-cost distance-spoofing attack on a mmWave Frequency Modulated Continuous Wave (FMCW) radar. It uses only a replica radar chipset and a single compact microcontroller board both in mass production. No expensive and bulky test instrument is required, and hence a low-cost and lightweight attack setup is developed. Even with the limited hardware resource in this setup, the replica radar can be precisely synchronized with the target radar for distance-spoofing capability. A half-chirp modulation scheme enables timing compensation between crystal oscillators on the replica and the target radar boards. A two-step delay insertion scheme precisely controls relative delay difference between two radars at ns-order, and as a result the attacker can manipulate distance measured at target radar with only around ±10m ranging error. This demonstrates potential feasibility of low-cost malicious attack on the commercial FMCW radar as a physical security threat. A countermeasure employing random-chirp modulation is proposed and its security level is evaluated under the proposed attack for secure and safe radar ranging.Association for Computing Machinery, Nov. 2019, Proceedings of the ACM Conference on Computer and Communications Security, 95 - 100, EnglishInternational conference proceedings
- Nov. 2019, in Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC 2019), 25 - 28, EnglishA Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices[Refereed]
- NiCuZn spinel ferrite particles were sintered into 50 μm-thick plate and mounted in between IC die and its interposer to explore their suitability as electromagnetic noise suppressor up to 10 GHz. A 50 μm thick Y-Type hexaferrite plate with density of 5.2 g/cm3 exhibits the figure-of-merit, Ploss/Pin, as high as 0.27 at 7 GHz. The test ferrite plate was embedded in between IC chip and interposer using a newly developed pre-assembly technique. This was enough to suppress on-chip conduction noise and corresponding near field emission by 4-17 dB in wireless communication channels.Oct. 2019, Proceedings of the The 12th International Workshop on the Electromagnetic Compatibility of Integrated Circuits(EMC Compo 2019), 231 - 233, English[Refereed]International conference proceedings
- Oct. 2019, in Proceedings of The 52th International Symposium on Microelectronics (IMAPS 2019), 1 - 6, EnglishDevelopment of Backside Buried Metal Layer Technology for 3D-Ics[Refereed]
- Oct. 2019, IEEE 2019 International 3D Systems Integration Conference (3DIC 2019), 1 - 4, EnglishOver-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital Ics[Refereed]
- Oct. 2019, in Proceedings of the 29th Asian Session of Advanced Metallization Conference 2019 (ADMETAplus 2019), P-5 (poster presentation), 47 - 48, EnglishDevelopment of novel Cu electroplating for electronic interconnects in advanced packaging[Refereed]
- Oct. 2019, in Proceedings of the 12th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo 2019), 1 - 3, EnglishIn-Place Power Noise and Signal Waveform Measurements on LVDS Channels in Fan-Out Multiple IC Chip Packaging[Refereed]
- Oct. 2019, in Proceedings of the 12th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo 2019), 1 - 3, EnglishMagnetic Composite Sheets in IC Chip Packaging for Suppression of Undesired Noise Emission to Wireless Communication Channels[Refereed]
- Oct. 2019, in Proceedings of the 12th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo 2019), 1 - 3, EnglishSintered Ferrite Thin Plate Noise Suppressor Mounted on IC Chip Interposer[Refereed][Invited]
- Oct. 2019, in Proceedings of the 13th IEEE International Conference on ASIC (ASICON 2019), 1 - 4, EnglishOn-Chip Protection of Cryptographic ICs Against Physical Side Channel Attacks[Refereed][Invited]
- Sep. 2019, IEEE Letters on Electromagnetic Compatibility Practice and Applications, 72 - 76, EnglishEvaluation of Undesired Radio Waves below -170 dBm/Hz from Semiconductor Switching Devices for Impact on Wireless Communication[Refereed]
- Sep. 2019, in Proceedings of the 2019 International Symposium on Electromagnetic Compatibility (EMC Europe 2019), 866 - 869, EnglishEvaluation of Near-Field Undesired Radio Waves from Semiconductor Switching Circuits[Refereed]
- Sep. 2019, in Extended Abstracts of International Conference on Solid State Devices and Materials (SSDM), 501 - 502, EnglishAn Information Leakage Sensor Based on Measurement of Laser-Induced Opto-Electric Bulk Current Density[Refereed]
- Jul. 2019, IEICE Transactions on Electronics, E102-C(7) (7), 530 - 537, EnglishA 0.72pJ/bit 400μm2 Physical Random Number Generator Utilizing SAR Technique for Secure Implementation on Sensor Nodes,[Refereed]
- Jul. 2019, in Proceedings of the 2019 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI 2019), EnglishImpacts of Undesired Radio Waves on Mobile Communications Nearby Inverter Power Devices[Refereed]
- Jul. 2019, in Proceedings of the 2019 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI 2019), EnglishCompact Simulation of Chip-to-Chip Active Noise Coupling on A System PCB Board[Refereed]
- Jul. 2019, in Proceedings of the 2019 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI 2019), English, Co-authored internationallyA Fast Side-channel Leakage Simulation Technique Based on IC Chip Power Noise Modeling[Refereed]
- Jun. 2019, Proceedings of the IEICE EMC Sapporo 2019/IEEE APEMC 2019, EnglishAnalysis of Disturbance Propagation in Silicon Substrate on SOI-BCD Process,[Refereed]
- Jun. 2019, Proceedings of the IEICE EMC Sapporo 2019/IEEE APEMC 2019, EnglishChip to Chip Noise Interference Simulation Via Package and Board,[Refereed]
- Jun. 2019, Proceedings of the IEICE EMC Sapporo 2019/IEEE APEMC 2019, English, Co-authored internationallyImmunity Simulation of ESD Protection Devices in High Voltage BiCD Technology[Refereed]
- Jun. 2019, Proceedings of the IEICE EMC Sapporo 2019/IEEE APEMC 2019, EnglishInterference of Undesired Radio Waves Near Inverter Power Devices on Mobile Communications[Refereed]
- Jun. 2019, Proceedings of the IEICE EMC Sapporo 2019/IEEE APEMC 2019, EnglishSuppression of Unnecessary Radio Wave Radiated from Power Electronics Equipment Using Noise Suppression Sheet[Refereed]
- Jun. 2019, Proceedings of the IEICE EMC Sapporo 2019/IEEE APEMC 2019, EnglishMagnetic Powder Composite Noise Suppressor for Flip Chip Mounted High Speed IC Chip[Refereed]
- Jun. 2019, Proceedings of the IEICE EMC Sapporo 2019/IEEE APEMC 2019, EnglishCollision-Based EM Analysis on ECDSA Hardware and a Countermeasure[Refereed]
- Jun. 2019, ACM/IEEE Design Automation Conference (DAC 2019), English, Co-authored internationallyA Full System Simulation Technique of Power-noise Side Channel Leakage in Cryptographic Integrated Circuits[Refereed]
- May 2019, Elsevier Microelectronics Journal,, 90, 63 - 71, EnglishSide-channel leakage from sensor-based countermeasures against fault injection attack[Refereed]
- Apr. 2019, Proceedins of the IEEE Custom Integrated Circuits Conference (CICC 2019),, 1 - 6, EnglishOn-Chip Physical Attack Protection Circuits for Hardware Security[Refereed][Invited]
- Mar. 2019, IEEE Transactions on Components, Packaging and Manufacturing Technology, 9(3) (3), 502 - 510, EnglishA Thick Cu Layer Buried in Si Interposer Backside for Global Power Routing,[Refereed]Scientific journal
- Sep. 2018, IEEE Journal of Solid-State Circuits, 53(11) (11), 3174 - 3182, EnglishA 286 F2/Cell Distributed Bulk-Current Sensor and Secure Flush Code Eraser Against Laser Fault Injection Attack on Cryptographic Processor,[Refereed]Scientific journal
- Aug. 2018, 2018 IEEE Symposium on Electromagetic Compatibility, Signal and Power Integrity (EMC+SIPI 2018), 1, EnglishSuppression of Unnecessary Radio Wave Radiated from Inverter Equipment using Noise Suppression Sheet,[Refereed]International conference proceedings
- Aug. 2018, Proceedings of the 2018 International Symposium on Electromagnetic Compatibility (EMC Europe 2018), 608 - 612, EnglishMeasurement and Magnetic Countermeasure Methodology to Deal with Inverter Noise,[Refereed]International conference proceedings
- Aug. 2018, International Symposium on Electromagnetic Compatibility (EMC Europe 2018), 445 - 450, EnglishInteraction of RF DPI with ESD protection Devices in EMS Testing of IC Chips,[Refereed]International conference proceedings
- Aug. 2018, Proceedings of the 21th Euromicro Conference on Digital System Design (DSD 2018), 508 - 515, EnglishAnalysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology,[Refereed]International conference proceedings
- Jul. 2018, IEEE Journal of Solid-State Circuits, 53(10) (10), 2889 - 2897, EnglishChip-Package-Board Interactive PUF Utilizing Coupled Chaos Oscillators with Inductor,[Refereed]Scientific journal
- Jul. 2018, IEICE Electronics Express, 15(13) (13), 1 - 8, EnglishA Study on Substrate Noise Coupling among TSVs in 3D Chip Stack[Refereed]Scientific journal
- Jul. 2018, IEEE Transactions on Circuits and Systems II: Express Briefs, 65(10) (10), 1320 - 1324, EnglishA Demonstration of a HT-Detection Method Based on Impedance Measurements of the Wiring Around ICs,[Refereed]Scientific journal
- Jun. 2018, ACM/IEEE Design Automation Conference (DAC 2018), EnglishExtended CPS Simulation for EMC Compliance of Automotive IC Chip Developments,[Refereed]International conference proceedings
- May 2018, Proceedings of 2018 IEEE International Symposium on Electromagnetic Compatibility and IEEE Asia-Pacific Symposium on Electromagnetic Compatibility (EMC/APEMC), 11, EnglishHT-Detection Method Based on Impedance Measurements of ICs,[Refereed]International conference proceedings
- May 2018, Proceedings of 2018 IEEE International Symposium on Electromagnetic Compatibility and IEEE Asia-Pacific Symposium on Electromagnetic Compatibility (EMC/APEMC), 12, EnglishEM Security Analysis of Compact ECDSA Hardware,[Refereed]International conference proceedings
- Mar. 2018, 電子情報通信学会論文誌B分冊, J101–B(3) (3), 204–211, Japanese(招待論文)不要電波の広帯域化に対応した電波環境計測技術と改善技術[Refereed]Scientific journal
- Mar. 2018, 2018 IEEE 68th Electronic Components and Technology Conference(ECTC 2018), 521 - 526, EnglishSupply-Chain Security Enhancement by Chaotic Wireless Chip-Package-Board Interactive PUF,[Refereed]International conference proceedings
- Feb. 2018, Measurement and Analysis of Power Noise Characteristics for EMI Awareness of Power Delivery Networks in 3-D Through-Silicon Via Integration,, 8(2) (2), 277 - 285, EnglishMeasurement and Analysis of Power Noise Characteristics for EMI Awareness of Power Delivery Networks in 3-D Through-Silicon Via Integration,[Refereed]Scientific journal
- Feb. 2018, Dig. Tech. Papers, 2018 IEEE International Solid-State Circuits Conference (ISSCC), 352 - 353, EnglishA 286F²/Cell Distributed Bulk-Current Sensor and Secure Flush Code Eraser Against Laser Fault Injection Attack[Refereed]International conference proceedings
- Nov. 2017, Proc. 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC 2017), 25 - 28, EnglishChaos, Deterministic Non-Periodic Flow, for Chip-Package-Board Interactive PUF[Refereed]International conference proceedings
- Sep. 2017, Proceedings of the 2017 International Symposium on Electromagnetic Compatibility (EMC Europe 2017), 1 - 5, EnglishSimulation Techniques for EMC Compliant Design of Automotive IC Chips and Modules[Refereed]International conference proceedings
- Sep. 2017, Proceedings of the IEEE 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC 2017), 49 - 56, EnglishExploiting Bitflip Detector for Non-Invasive Probing and its Application to Ineffective Fault Analysis[Refereed]International conference proceedings
- Sep. 2017, Proceedings of the 2017 International Symposium on Electromagnetic Compatibility (EMC Europe 2017), 1 - 5, EnglishEffect of Field Area on Disturbance Propagation through Silicon Substrates in SOI-BCD Process[Refereed]International conference proceedings
- Aug. 2017, Proceedings of the 2017 IEEE International Symposium on Electromagnetic Compatibility, Signal and Power Integrity, 399 - 404, EnglishEnhancing Reactive Countermeasure against EM Attacks with Low Overhead[Refereed]International conference proceedings
- Aug. 2017, Proceedings of the 2017 IEEE International Symposium on Electromagnetic Compatibility, Signal and Power Integrity, Poster, 283 - 287, EnglishAnalysis of Unnecessary Radio Wave Near the Inverter Equipment at the Carrier Frequency-Range of Mobile Terminal[Refereed]International conference proceedings
- Jul. 2017, in Proceedings of the 11th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo 2017), 59 - 63, EnglishSusceptibility Evaluation of CAN Transceiver Circuits with In-Place Waveform Capturing under RF DPI[Refereed]International conference proceedings
- Jul. 2017, in Proceedings of the 11th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo 2017), 45 - 49, EnglishAnalysis of Patterned Magnetic Thin-film Noise Suppressor for RF IC Chip[Refereed]International conference proceedings
- In this paper, a 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter (VTC) in 28 nm CMOS is presented. A two-step transition inverter raises the Voltage-to-Time (VT) conversion gain to 100 ps/V which is >10x higher than a conventional current-starved inverter. The number of required inverter stages is reduced to 4 from 64, resulting in 1/8 conversion latency and thus 13.2 dB THD suppression at a 500 MHz full Nyquist frequency. A feedback control of the bias voltage in the two-step transition inverter suppresses PVT variations in the VT conversion gain. A test-chip measurement successfully demonstrates -52.5 dB THD at 500 MHz input frequency without sampling-and-hold circuits. Effective VT conversion range over +/-64 ps time difference is measured with 1.2 Vpp differential input while keeping high linearity of less than +/-0.53 LSB INL/DNL, which results in 1 ps/LSB conversion linearity. The proposed VTC occupies 84 um(2) silicon area and consumes 0.18 mW at 1 GS/s.IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jun. 2017, IEICE TRANSACTIONS ON ELECTRONICS, E100C(6) (6), 560 - 567, English[Refereed]Scientific journal
- Jun. 2017, 2017 Symposium on VLSI Circuits, Dig. of Tech. Papers, 20.2, 266 - 267, EnglishA 2.5ns-Latency 0.39pJ/b 289µm²/Gb/s Ultra-Light-Weight PRINCE Cryptographic Processor[Refereed]International conference proceedings
- Apr. 2017, Japanese Journal of Applied Physics, Vol. 56, No. 4S, 56(4S) (4S), 04CC05 - 1-04EE06-6, EnglishSuperior decoupling capacitor for three-dimensional LSI with ultrawide communication bus,[Refereed]Scientific journal
- 電子情報通信学会, Feb. 2017, 電子情報通信学会論文誌C分冊, J100-C(2) (2), 1 - 13, JapaneseVLSIシステムのノイズ問題克服に向けた研究の取組み―エレクトロニクスソサイエティ賞の受賞によせて―,"[Refereed]Scientific journal
- IEICE, Feb. 2017, IEICE Electronics Express(ELEX), 14(2) (2), 1 - 13, EnglishProtecting cryptographic integrated circuits with side-channel information,"[Refereed]Scientific journal
- An FPGA-Compatible PLL-Based Sensor against Fault Injection AttackLaser based Fault Injection (LFI) and Electromagnetic Fault Injection (EMFI) are powerful techniques commonly for fault injection against security critical circuits. Since LFI/EMFI creates faults by incurring high energy disturbances, they can be detected in advance by sensing the disturbance using a embedded detector. In this paper, a PLL based sensor system for detecting laser fault injection is presented. Experiments show a high detection rate, with significant power security margin, whilst maintaining low hardware cost, on multiple FPGA platforms.IEEE, 2017, 2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 39 - 40, English[Refereed]International conference proceedings
- IEEE, 2017, 2017 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 270 - 270, EnglishA Permanent Digital Archive System Based on 4F(2) X-Point Multi-Layer Metal Nano-Dot Structure[Refereed]International conference proceedings
- Cu-Sn based joint material having IMC forming control capabilitiesThis paper describes development of joint materials using only base metals (Cu and Sn) for power semiconductor assembly. The optimum composition at this moment is Cu8wt% Sn92wt% (8Cu92Sn hereafter) particles: pure Cu (100Cu hereafter) particles = 20: 80 (wt% ratio), which indicates good stability under Thermal Cycling Test (TCT, -55 degrees C similar to+200 degrees C, 20cycles). The composition indicated to be effective to eliminate voids and chip cracks. As an initial choice of joint material using TLPS (Transient Liquid Phase Sintering), we considered SAC305 might have good role as TLPS trigger. But, actual TCT results indicated that existence of Ag must have negative effect to eliminate voids from the joint region. Tentative behavior model using 8Cu92Sn and 100Cu joint material is proposed. Optimized composition indicated shear force 40MPa at 300 degrees C. Re-melting point of the composition is 409 degrees C after TLPS when there is additional Cu supply from substrate and terminal of mounted die.IEEE, 2017, 2017 INTERNATIONAL CONFERENCE ON ELECTRONICS PACKAGING (ICEP), TC4-2, 171 - 176, English[Refereed]International conference proceedings
- IEEE, Dec. 2016, 2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), 1 - 6, EnglishOn-chip substrate-bounce monitoring for laser-fault countermeasure[Refereed]International conference proceedings
- A three-dimensionally stacked, large-scale integration (3D-LSI) chip naturally provides densely capacitive and low-impedance characteristics in vertically and horizontally distributed power delivery networks (PDNs). This paper reports the supremacy of a stacked and packaged 3D LSI chip in terms of EMI performance. In-stack power noise monitoring evaluates local shunts by decoupling capacitors within a chip stack for dynamic power currents. On-board near-field magnetic probing confirms global decoupling of a packaged stack from a system power source. These measurements were performed on a real 3D-LSI demonstrator and also a conventional 2D chip for comparison. The 3D-LSI demonstrator includes a Si interposer with explicit as well as implicit capacitors between a stack of active memory and logic tiers fully connected with through-silicon vias (TSVs).Institute of Electrical and Electronics Engineers Inc., Nov. 2016, IEEE International Symposium on Electromagnetic Compatibility, 2016-, 428 - 433, English[Refereed]International conference proceedings
- Sep. 2016, Extended Abstracts of the 2016 International Conference on Solid State Devices and Materials (SSDM 2016), 469 - 470, EnglishSuperiority of In-Stack Decoupling Capacitor for 3D-LSI with Wide I/O Data Bus[Refereed]International conference proceedings
- IEEE, Aug. 2016, Proc. IEEE 2016 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC 2016), 102 - 113, EnglishRing Oscillator Under Laser: Potential of PLL Based Countermeasure Against Laser Fault Injection[Refereed]International conference proceedings
- IEEE, Jun. 2016, Proc. 2016 IEEE 66th Electronic Components and Technology Conference (ECTC 2016), 426 - 431, EnglishDie Attach Material for Power Semiconductor Having Nano-Level Sn-Cu Diffusion Control[Refereed]International conference proceedings
- A 500MHz-BW-52.5dB-THD Voltage-to-Time Converter Utilizing a Two-Step Transition InverterThis paper presents a 500MHz-BW -52.5dB-THD Voltage-to-Time Converter (VTC) in 28nm CMOS. A two-step transition inverter raises the VT conversion gain to 100ps/V which is >10x higher than a conventional current-starved inverter. The number of required inverter stages is reduced to 4 from 64, resulting in 1/8 conversion latency and thus 13.2dB THD suppression at 500MHz full Nyquist. A test-chip measurement successfully demonstrates -52.5dB THD at 500MHz without sampling-and-hold. Effective VT conversion linearity is measured to be 1ps/LSB with INL/DNL of less than +/-0.53LSB. The proposed VTC consumes 84 mu m(2) silicon area and 0.18mW at 1GS/s.IEEE, 2016, ESSCIRC CONFERENCE 2016, 141 - 144, English[Refereed]International conference proceedings
- 2016, IACR Cryptology ePrint Archive, 2016, 522A Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurements (Extended Version).
- Fine Pitch Micro-Bump forming by PrintingWe have examined printing technology which is adaptable to 3DIC bump-forming for (both front-side bump and back-side bump. The materials for bumping require several features for TSV process circumstances and 3DIC stacking followed by reflow. We chose Nano-Function material for the purpose which was initially developed for power semiconductor attachment. The result shows good possibility. 20 mu m bump pitch capability was confirmed.IEEE, 2016, 2016 International Conference on Electronics Packaging (ICEP), 260 - 264, English[Refereed]International conference proceedings
- Physical Authentication Using Side-Channel InformationAuthentication based on cryptographic protocols is a key technology for recent security systems. This paper proposes a new authentication method that utilizes the side channel that already exists in many authentication systems. Side-channel analysis has been studied intensively from the attacker viewpoint and is best known for key-recovery attacks against cryptographic implementations using physical information. In this paper, reversing the traditional thought, we propose to use the key-dependent side-channel information constructively to enhance, or as an alternate to, existing cryptographic protocols. Using Advanced Encryption Standard (AES)-based authentication as an example, we demonstrate, based on experiments using an Field Programmable Gate Array (FPGA), that the side-channel information leaked from cryptographic devices is sufficiently unique for authentication.IEEE, 2016, 2016 4TH INTERNATIONAL CONFERENCE ON INFORMATION AND COMMUNICATION TECHNOLOGY (ICOICT), English[Refereed]International conference proceedings
- \Electromagnetic injection (EMI) is a powerful and precise technique for fault injection in modern ICs. This intentional fault can be utilized to steal secret information hidden inside of ICs. Unlike laser fault injection, tedious package decapsulation is not needed for EMI, which reduces an attacker's cost and thus causes a serious information security threat. In this paper, a PLL-based sensor circuit is proposed to detect EMI reactively on chip. A fully automatic design flow is devised to integrate the proposed sensor together with a cryptographic processor. A high fault detection coverage and a small hardware overhead are demonstrated experimentally on an FPGA platform.ASSOC COMPUTING MACHINERY, 2016, 2016 ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 1 - 6, English[Refereed]International conference proceedings
- EMI Performance of Power Delivery Networks in 3D TSV IntegrationA three-dimensionally stacked, large-scale integration (3D-LSI) chip naturally provides densely capacitive and low-impedance characteristics in vertically and horizontally distributed power delivery networks (PDNs). This paper reports the supremacy of a stacked and packaged 3D LSI chip in terms of EMI performance. In-stack power noise monitoring evaluates local shunts by decoupling capacitors within a chip stack for dynamic power currents. On-board near-field magnetic probing confirms global decoupling of a packaged stack from a system power source. These measurements were performed on a real 3D-LSI demonstrator and also a conventional 2D chip for comparison. The 3D-LSI demonstrator includes a Si interposer with explicit as well as implicit capacitors between a stack of active memory and logic tiers fully connected with through-silicon vias (TSVs).IEEE, 2016, PROCEEDINGS OF THE 2016 INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY - EMC EUROPE, 428 - 433, English[Refereed]International conference proceedings
- Dec. 2015, IACR Journal of Cryptology, 1 - 19, EnglishDesign Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks[Refereed]Scientific journal
- Nov. 2015, IEEE Design and Test, Vol. 32(No. 6) (No. 6), 87 - 98, EnglishIn-Place Signal and Power Noise Waveform Capturing Within 3-D Chip Stacking[Refereed]Scientific journal
- Nov. 2015, Proc. 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo), #8-1(poster), 216 - 221, EnglishAnalysis of On-Chip Digital Noise Coupling Path for Wireless Communication IC Test Chip[Refereed]International conference proceedings
- Nov. 2015, Proc. IEEE CPMT Symposium Japan (ICSJ 2015), 140 - 143, English3DIC/TSV Process Developments by Printing Technologies[Refereed]Scientific journal
- Oct. 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23(No. 10) (No. 10), 2347 - 2351, EnglishAn Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference[Refereed]Scientific journal
- Sep. 2015, Proc. 2015 International 3D Systems Integration Conference (3DIC 2015), TS5.3.1 - TS5.3.6, EnglishNano-Function Materials for TSV Technologies[Refereed]International conference proceedings
- Aug. 2015, Proc. Joint IEEE International Symposium on Electromagnetic Compatibility and EMC Europe (EMC 2015), #SS-1-7, 252 - 257, EnglishProactive and Reactive Protection Circuit Techniques Against EM Leakage and Injection[Refereed]International conference proceedings
- Aug. 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23(No. 8) (No. 8), 1429 - 1438, EnglishA Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation[Refereed]Scientific journal
- Aug. 2015, Proc. Joint IEEE International Symposium on Electromagnetic Compatibility and EMC Europe (EMC 2015), #Track N-4, 1007 - 1011, EnglishAnalysis of Intra-Chip Degital Noise Coupling Path in Fully LTE Compliant RF Receiver Test Chip[Refereed]International conference proceedings
- Jun. 2015, Proc. ACM Design Automation Conference 2015 (DAC 2015), #69.2, 1 - 6, EnglishEM Attack Sensor: Concept, Circuit, and Design-Automation Methodology (Invited)[Refereed]International conference proceedings
- May 2015, Proc. 2015 IEEE Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC 2015), #SS10-5, EnglishOn-chip Integrated Magnetic Thin-Film Solution to Countermeasure Digital Noise on RF IC[Refereed]International conference proceedings
- May 2015, Proc. 2015 IEEE 33rd VLSI Test Symposium (VTS 2015), #TE3-1, 127 - 130, EnglishAt-Product-Test Dedicated Adaptive Supply-Resonance Suppression," Proc. 2015 IEEE 33rd VLSI Test Symposium (VTS 2015)[Refereed]International conference proceedings
- Apr. 2015, Proc. 2015 International Conference on Electrnoics Packaging and iMAPS All Asia Conference (ICEP-IAAC 2015), #06A-1, 482 - 485, EnglishNano-Function Paste for Power Semiconductors[Refereed]International conference proceedings
- 電気関係学会東北支部連合大会実行委員会, 2015, 電気関係学会東北支部連合大会講演論文集, 2015, 129 - 129, Japanese
- In-band interferers due to noise coupling from baseband digital circuits significantly impact on the wireless communication performance, in the case of single-chip system-level integration. The on-chip and off-chip (on-board) noise coupling are measured for visualizing the noise couplings. In addition, the hardware-in-the-loop simulation (HILS) estimates their impacts on the performance metrics like throughputs, under the interactions of interferers with the operation of LTE-compliant RF receiver circuits in a 65 nm CMOS technology.IEEE, 2015, 2015 IEEE INTERNATIONAL SYMPOSIUM ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY (RFIT), 7 - 9, English[Refereed]International conference proceedings
- Jan. 2015, Proceedings of the 20th Asia and South Pacific Design Automation Conference, #8C-3, 749 - 754, EnglishA Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurement[Refereed]International conference proceedings
- Jan. 2015, Proceedings of the 20th Asia and South Pacific Design Automation Conference, #1S-13, 26 - 27, EnglishA DPA/DEMA/LEMA-Resistant AES Cryptographic Processor with Supply-Current Equalizer and Micro EM Probe Sensor[Refereed]International conference proceedings
- In-stack monitoring of signal and power nodes in three dimensional integrated circuitsAn on-chip waveform monitoring technique embodies in-stack evaluation of three-dimensional integrated circuits (3D IC) regarding physical connections using through silicon vias (TSV) and electronic characteristics of signal transmission as well as noise propagation. On-chip generation of reference voltage steps and sampling timings reduces the complexity of analog signal routing in a chip stack and enhances measurement throughputs. The demonstrated 7.6 effective bit resolution with a 5.8 times higher throughput is suitable for in-stack monitoring. Sinusoidal signal transmission in a two-tier 3D IC is on-chip evaluated.Institute of Electrical and Electronics Engineers Inc., Dec. 2014, IEEE International Symposium on Electromagnetic Compatibility, 2014-, 362 - 365, EnglishInternational conference proceedings
- Correlation power analysis using bit-level biased activity plaintexts against AES cores with countermeasuresAdvanced encryption standard (AES) cores suffer from information leakage through power supply currents, even with the wave dynamic differential logic (WDDL) known as one of the most tolerable countermeasure design styles against side channel attacks (SCA). The set of plaintexts having bitlevel biased activities are produced with a known secret key and used for diagnosing the vulnerability of AES cores in their development phases. The CPA with biased plaintexts revealed 128-bit secret keys with less than 4,000 traces from the WDDL AES core both by the measurements and simulations of power supply currents. The core was physically structured by using a 65-nm CMOS standard cell library and assembled on a test vehicle of 'SPACES explorer' having an on-board 1-ohm resistor for measuring power supply currents. The derived knowledge should be useful in driving the design of AES cores to be much less prone to information leakage through power supply current and electromagnetic measurements.Institute of Electrical and Electronics Engineers Inc., Dec. 2014, IEEE International Symposium on Electromagnetic Compatibility, 2014-, 306 - 309, EnglishInternational conference proceedings
- On-chip magnetic thin-film noise suppressor for IC chip level digital noise countermeasure© 2014 The Institute of Electronics, Information and Communication Engineer. Crossed anisotropy amorphous CoDec. 2014, IEEE International Symposium on Electromagnetic Compatibility, 2014-December, 354 - 357
85 Zr3 Nb12 thin film with total magnetic thickness of 2.0 μm is deposited on to the passivation of a bare IC chip to accommodate intra IC chip level digital-to-RF noise suppression and telecommunication performance. On-chip magnetic film processes can be done as the last steps of Si CMOS back end processes. Radiated emission from embedded arbitrary noise generator is suppressed by more than 10 dB. In-band spurious tone is attenuated by 10 dB. Minimum input power level to meet the 3GPP criteria is improved by 8 dB. All of these results are achieved on the fully LTE compliant RF receiver chain.[Refereed]International conference proceedings - EM radiation from a cryptographic processor IC contains side-channel information of secret data hidden inside the chip. This side-channel information leakage is a potential threat critical to our information society. This paper introduces several circuit-level countermeasures integrated with the cryptographic processor core for advanced hardware security.Institute of Electrical and Electronics Engineers Inc., Sep. 2014, IEEE International Symposium on Electromagnetic Compatibility, 2014-(September) (September), 748 - 751, English[Refereed]International conference proceedings
- Sep. 2014, Proceedings of IEEE Electronics System-Integration Technology Conference, #S14P2, EnglishA Study on Power Integrity in a 3D Chip Stack Using Dynamic Power Supply Current Emulation and Power Noise Monitoring[Refereed]International conference proceedings
- Silicon substrates can be strategically isolated or unified among tiers in a through-silicon-via (TSV)-based 3-D integrated circuit (IC) structure, for the suppression of intertier substrate noise coupling or the reduction of grounding impedance of silicon substrates as a whole, respectively. A two-tier 3-D IC demonstrator in a 130-nm CMOS technology was successfully tested and analyzed with respect to intra and intertier substrate noise coupling. Each tier in the stack includes digital noise source circuits (NSs) and substrate noise monitors, and embodies in-place measurements of substrate noise coupling. An equivalent circuit unifies power and substrate networks of the tiers and simulates the frequency-domain response of substrate noise coupling. Measurements and calculation with the equivalent circuit are consistent for frequency dependency of substrate noise coupling in a 3-D IC demonstrator. Intratier propagation is dominant, while intertier coupling is insignificant for low-frequency substrate noise components. Intertier coupling becomes comparable with and finally overwhelms intratier coupling as the frequency of substrate noise components increases. Substrate noise coupling in a multitier chip stack is strongly impacted by the parasitic capacitance of TSVs, while that coupling becomes predictable with the equivalent circuit of the entire stack.IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, Jun. 2014, IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 4(6) (6), 1026 - 1037, English[Refereed]Scientific journal
- A three dimensional (3D) chip stack featuring a 4096-bit wide I/O demonstrator incorporates an in-place waveform capturer on an intermediate interposer within the stack. The capturer includes probing channels on paths of signaling as well as in power delivery and collects analog waveforms for diagnosing circuits within 3D integration. The collection of in-place waveforms on vertical channels with through silicon vias (TSVs) are demonstrated among 128 vertical I/O channels distributed in 8 banks in a 9.9 mm x 9.9 nun die area. The analog waveforms confirm a full 1.2-V swing of signaling at the maximum data transmission bandwidth of 100 GByte/sec with sufficiently small deviations of signal skews and slews among the vertical channels. In addition, it is also experimentally confirmed that the signal swing can be reduced to 0.75 V for error free data transfer at 100 GByte/sec, achieving the energy efficiency of 0.21 pJ/bit.IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jun. 2014, IEICE TRANSACTIONS ON ELECTRONICS, E97C(6) (6), 557 - 565, English[Refereed]Scientific journal
- Substrate noise coupling in RF receiver front-end circuitry for LTE wireless communication was examined by full-chip level simulation and on-chip measurements, with a demonstrator built in a 65 nm CMOS technology. A CMOS digital noise emulator injects high-order harmonic noises in a silicon substrate and induces in-band spurious tones in an RF receiver on the same chip through substrate noise interference. A complete simulation flow of full-chip level substrate noise coupling uses a decoupled modeling approach, where substrate noise waveforms drawn with a unified package-chip model of noise source circuits are given to mixed-level simulation of RF chains as noise sensitive circuits. The distribution of substrate noise in a chip and the attenuation with distance are simulated and compared with the measurements. The interference of substrate noise at the 17th harmonics of 124.8 MHz the operating frequency of the CMOS noise emulator creates spurious tones in the communication bandwidth at 2.1 GHz.IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jun. 2014, IEICE TRANSACTIONS ON ELECTRONICS, E97C(6) (6), 546 - 556, English[Refereed]Scientific journal
- Jun. 2014, Digest of Technical Papers, IEEE 2014 Symposium on VLSI Circuits, #16.4, 172 - 173, EnglishA Local EM-Analysis Attack Resistant Cryptographic Engine with Fully-Digital Oscillator-Based Tamper-Access Sensor[Refereed]International conference proceedings
- Power supply noise waveforms within cryptographic VLSI circuits in a 65 Jun CMOS technology are captured by using an on-chip voltage waveform monitor (OCM). The waveforms exhibit the correlation of dynamic voltage drops to internal logical activities during Advance Encryption Standard (AES) processing, and causes side-channel information leakage regarding to secret key bytes. Correlation Power Analysis (CPA) is the method of an attack extracting such information leakage from the waveforms. The frequency components of power supply noise contributing the leakage are shown to be localized in an extremely low frequency region. The level of information leakage is strongly associated with the size of increment of dynamic voltage drops against the Hamming distance in the AES processing. The time window of significant importance where the leakage most likely happens is clearly designated within a single clock cycle in the final stage of AES processing. The on-chip power supply noise measurements unveil the facts about side-channel information leakage behind the traditional CPA with on-board sensing of power supply current through a resistor of 1 ohm.IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2014, IEICE TRANSACTIONS ON ELECTRONICS, E97C(4) (4), 272 - 279, English[Refereed]Scientific journal
- A noise emulator is based on the capacitor charging modeling and generates power and substrate noises expected in a CMOS digital integrated circuit. An off-chip near-magnetic-field sensor indirectly characterizes the distribution of clock timing and the adjustability of skews within on-chip digital circuits. An on-chip noise monitor captures power and substrate noise waveforms and evaluates noise frequency components in a wide frequency bandwidth. A 65 nm CMOS prototype demonstrated power and substrate noise generation in a variety of operating scenarios of digital integrated circuits. Power noise generation emulated at 125 MHz exhibits the enhancements of high-order harmonic components after deskewing at a timing resolution of 37.8 ps, as is specifically seen in more than 10 dB enlargement of the substrate noise component at 2.1 GHz. (C) 2014 The Japan Society of Applied PhysicsIOP PUBLISHING LTD, Apr. 2014, JAPANESE JOURNAL OF APPLIED PHYSICS, 53(4) (4), 04EE06 - 1-04EE06-6, English[Refereed]Scientific journal
- An LSI Chip-Package-Board integrated power noise simulation model and its validity is discussed in this paper. A unified power delivery network (PDN) of LSI chip, package, and printed circuit board (PCB) is connected with on-chip power supply current models with capacitor charging expression. The proposed modeling How is demonstrated for the 32-bit microprocessor in a 1.0 V 90 nm CMOS technology. The PDN of the system that includes a chip, bonding wires and a printed circuit board is modeled in an equivalent circuit. The on-chip power supply noise monitoring technique and the magnetic probe method is applied for validating simulation results. Simulations and measurements explore power supply noise generation with the dependency on operating frequencies in the wide range from 10 MHz to 300 MHz, under the operation mode of dynamic frequency scaling, and in the long time operation with various operation codes. It is confirmed that the proposed power supply noise simulation model is helpful for the noise estimation throughout the design phase of the LSI system.IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2014, IEICE TRANSACTIONS ON ELECTRONICS, E97C(4) (4), 264 - 271, English[Refereed]Scientific journal
- This paper presents a resilient cache memory for dynamic variation tolerance in a 40-nm CMOS. The cache can perform sustained operations under a large-amplitude voltage droop. To realize sustained operation, the resilient cache exploits 7T/14T bit-enhancing SRAM and on-chip voltage/temperature monitoring circuit. 7T/14T bit-enhancing SRAM can reconfigure itself dynamically to a reliable bit-enhancing mode. The on-chip voltage/temperature monitoring circuit can sense a precise supply voltage level of a power rail of the cache. The proposed cache can dynamically change its operation mode using the voltage/temperature monitoring result and can operate reliably under a large-amplitude voltage droop. Experimental result shows that it does not fail with 25% and 30% droop of V-dd and it provides 91 times better failure rate with a 35% droop of V-dd compared with the conventional design.IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2014, IEICE TRANSACTIONS ON ELECTRONICS, E97C(4) (4), 332 - 341, English[Refereed]Scientific journal
- This paper presents a resilient cache memory for dynamic variation tolerance in a 40-nm CMOS. The cache can perform sustained operations under a large-amplitude voltage droop. To realize sustained operation, the resilient cache exploits 7T/14T bit-enhancing SRAM and on-chip voltage/temperature monitoring circuit. 7T/14T bit-enhancing SRAM can reconfigure itself dynamically to a reliable bit-enhancing mode. The on-chip voltage/temperature monitoring circuit can sense a precise supply voltage level of a power rail of the cache. The proposed cache can dynamically change its operation mode using the voltage/temperature monitoring result and can operate reliably under a large-amplitude voltage droop. Experimental result shows that it does not fail with 25% and 30% droop of V-dd and it provides 91 times better failure rate with a 35% droop of V-dd compared with the conventional design.IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2014, IEICE TRANSACTIONS ON ELECTRONICS, E97C(4) (4), 332 - 341, English[Refereed]Scientific journal
- IEEE, Mar. 2014, Engineering Simulations for Cyber Physical Systems (ES4CPS), #3, 13 - 20, EnglishPhysical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology[Refereed]International conference proceedings
- Mar. 2014, IEEE International Symposium on Quality Electronic Design (ISQED), pp.16 - 23, EnglishA 40-nm Resilient Cache Memory for Dynamic Variation Tolerance with Bit-Enhancing Memory and On-Chip Diagnosis Structures Delivering x91 Failure Rate Improvement[Refereed]International conference proceedings
- IC Chip Level Low Noise Technology for High Speed and High Quality Telecommunication SystemsSingle chip integration of RF frontend and digital backend circuits is an obvious solution to accommodate high sensitivity and selectivity of analogue RE chains, and the high speed and large data bandwidth digital processing in an RF IC for the coming wireless communication systems including long-term evolution-advanced (LTE-A) system. This paper firstly emphasizes the necessity to suppress intra electromagnetic coupling from digital to RF circuits within the bandwidth of wireless channels. Our approach to suppress IC chip level RF noise coupling and to estimate their impact on system-level performance of wireless communication lead to major achievements on; (a)development of an in-system diagnosis platform of RF ICs consisting of a silicon emulator of on-chip interferers and a system-level RE performance simulator, (b)measurement-based substrate noise coupling analysis, measurement-based magnetic air coupling analysis, (c)an unique ferromagnetic on-chip countermeasure, and (d)board level coupling analysis in LTE receiver communication band. Their impacts on future telecommunication systems are estimated to conclude this work.IEEE, 2014, 2014 ASIA-PACIFIC MICROWAVE CONFERENCE (APMC), 540 - 542, English[Refereed]International conference proceedings
- Jan. 2014, 信学技報, vol. 113(no. 419) (no. 419), p. 59, Japanese動作環境の動的変動を考慮した動作マージン拡大機能を有する自律制御キャッシュResearch society
- IEEE, 2014, 2014 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC), 57, 216 - +, EnglishA 1mm-Pitch 80x80-Channel 322Hz-Frame-Rate Touch Sensor with Two-Step Dual-Mode Capacitance Scan[Refereed]International conference proceedings
- A Passive Supply-Resonance Suppression Filter Utilizing Inductance-Enhanced Coupled Bonding-Wire CoilsThis paper presents a low-power and compact passive supply-resonance (SR) suppression filter. By using an on-chip waveform monitor, a power-delivery network (PDN) impedance including package, and board PDNs is in-situ analyzed to identify the SR frequency f(SR). A notch filter which consists of coupled bonding-wire coils and an on-chip MOS capacitor bank is auto-tuned for the SR suppression. This passive filtering approach reduces the power loss to 1/5 similar to 1/10 and the static power to effectively zero as compared to an active SR suppression circuit [1]. The coupled bonding-wire coil enhances its self-inductance and hence shrinks the on-chip capacitor size for the layout-area saving. A 0.18 mu m CMOS test chip demonstrates SR suppression by >43% with only <7% of power loss and <0.034mm(2) layout area penalty.IEEE, 2014, 2014 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), #DR52, 121 - 124, English[Refereed]International conference proceedings
- Side-Channel Leakage on Silicon Substrate of CMOS Cryptographic ChipPower supply currents of CMOS digital circuits partly flow through a silicon substrate in their returning (ground) paths. The voltage bounce due to the substrate currents is seen wherever p+ substrate taps on a p-type die and regarded as a substrate noise. An on-chip waveform monitor confirms the side-channel leakage on the silicon substrate from an AES cryptographic module in a 65 nm CMOS demonstrator chip for the first time. The silicon substrate is essentially common to every circuit and inevitably carries the leakage to the observation taps located at the front as well as at the bottom surface of a die, even if the power and ground wires of an AES module are intentionally separated from the other building blocks. Substrate leakage channels may break the hiding of a cryptographic module regarding its location on a die. The physical properties including the distance dependency are experimentally explored.IEEE, 2014, 2014 IEEE INTERNATIONAL SYMPOSIUM ON HARDWARE-ORIENTED SECURITY AND TRUST (HOST), #3-3, 32 - 37, English[Refereed]International conference proceedings
- On-Chip Magnetic Thin-Film Noise Suppressor for IC Chip Level Digital Noise CountermeasureCrossed anisotropy amorphous Co85Zr3Nb12 thin film with total magnetic thickness of 2.0 mu m is deposited on to the passivation of a bare IC chip to accommodate intra IC chip level digital-to-RF noise suppression and telecommunication performance. On-chip magnetic film processes can be done as the last steps of Si CMOS back end processes. Radiated emission from embedded arbitrary noise generator is suppressed by more than 10 dB. In-band spurious tone is attenuated by 10 dB. Minimum input power level to meet the 3GPP criteria is improved by 8 dB. All of these results are achieved on the fully LTE compliant RF receiver chain.IEEE, 2014, 2014 INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, TOKYO (EMC'14/TOKYO), 14P1-B4, 354 - 357, English[Refereed]International conference proceedings
- In-Stack Monitoring of Signal and Power Nodes in Three Dimensional Integrated CircuitsAn on-chip waveform monitoring technique embodies in-stack evaluation of three-dimensional integrated circuits (3D IC) regarding physical connections using through silicon vias (TSV) and electronic characteristics of signal transmission as well as noise propagation. On-chip generation of reference voltage steps and sampling timings reduces the complexity of analog signal routing in a chip stack and enhances measurement throughputs. The demonstrated 7.6 effective bit resolution with a 5.8 times higher throughput is suitable for in-stack monitoring. Sinusoidal signal transmission in a two-tier 3D IC is on-chip evaluated.IEEE, 2014, 2014 INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, TOKYO (EMC'14/TOKYO), 14P2-B1, 362 - 365, English[Refereed]International conference proceedings
- Correlation Power Analysis using Bit-Level Biased Activity Plaintexts against AES Cores with CountermeasuresAdvanced encryption standard (AES) cores suffer from information leakage through power supply currents, even with the wave dynamic differential logic (WDDL) known as one of the most tolerable countermeasure design styles against side channel attacks (SCA). The set of plaintexts having bitlevel biased activities are produced with a known secret key and used for diagnosing the vulnerability of AES cores in their development phases. The CPA with biased plaintexts revealed 128-bit secret keys with less than 4,000 traces from the WDDL AES core both by the measurements and simulations of power supply currents. The core was physically structured by using a 65-nm CMOS standard cell library and assembled on a test vehicle of "SPACES explorer" having an on-board 1-ohm resistor for measuring power supply currents. The derived knowledge should be useful in driving the design of AES cores to be much less prone to information leakage through power supply current and electromagnetic measurements.IEEE, 2014, 2014 INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, TOKYO (EMC'14/TOKYO), #14P2-A3, 306 - 309, English[Refereed]International conference proceedings
- Integrated-Circuit Countermeasures Against Information Leakage Through EM RadiationEM radiation from a cryptographic processor IC contains side-channel information of secret data hidden inside the chip. This side-channel information leakage is a potential threat critical to our information society. This paper introduces several circuit-level countermeasures integrated with the cryptographic processor core for advanced hardware security.IEEE, 2014, 2014 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC), #TH-AM-3-3, 748 - 751, English[Refereed]International conference proceedings
- This paper presents a circuit technique to enhance a timing margin between internal data and clock by enlarging an eye opening of the internal data in a unique current mode transceiver [1]. This technique compensates a systematic timing offset of the internal data, which is caused by unbalanced transmission current. The test-chip exhibits 0.1UI (Unit Interval) improvement of the internal data eye opening without significant power penalty, and achieves stable data communication through 50% longer transmission lines compared to the previous work [1].IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2014, IEICE ELECTRONICS EXPRESS, 11(19) (19), 1 - 7, English[Refereed]Scientific journal
- EM Attack Is Non-invasive? - Design Methodology and Validity Verification of EM Attack SensorThis paper presents a standard-cell-based semi-automatic design methodology of a new conceptual countermeasure against electromagnetic (EM) analysis and fault-injection attacks. The countermeasure namely EM attack sensor utilizes LC oscillators which detect variations in the EM field around a cryptographic LSI caused by a micro probe brought near the LSI. A dual-coil sensor architecture with an LUT-programming-based digital calibration can prevent a variety of microprobe-based EM attacks that cannot be thwarted by conventional countermeasures. All components of the sensor core are semiautomatically designed by standard EDA tools with a fully-digital standard cell library and hence minimum design cost. This sensor can be therefore scaled together with the cryptographic LSI to be protected. The sensor prototype is designed based on the proposed methodology together with a 128bit-key composite AES processor in 0.18 mu m CMOS with overheads of only 2respectively. The validity against a variety of EM attack scenarios has been verified successfully.SPRINGER-VERLAG BERLIN, 2014, CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2014, 8731(LNCS 8731) (LNCS 8731), 1 - 16, English[Refereed]International conference proceedings
- CDM Protection of a 3D TSV Memory IC with a 100 GB/s Wide I/O Data BusFor the first time, CDM stress tests are studied on a 3D TSV stacked IC for memory applications. The stacked dies have each their ESD protection, but no dedicated ESD protection was placed on the TSVs. A CDM protection level of more than 1.5 kV is obtained.IEEE COMPUTER SOC, 2014, 2014 36TH ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM (EOS/ESD), #2A-2, 1 - 7, English[Refereed]International conference proceedings
- An on-chip monitoring technique has realized in-place diagnosis of power noise problems. On-chip voltage noise monitor (OCM) circuits are overviewed with some examples of integration in silicon chips. The OCM captures power noise waveforms in a silicon chip and provides the opportunities of diagnosis on unfavorable invisible events within a die. In-band interference of radio-frequency (RF) communication channels by power noise coupling in RF systems-on-chip (SoC) integration, and information leakage through power noise side channels from a cryptographic core are demonstrated.IEEE COMPUTER SOC, 2014, 2014 IEEE 23RD ASIAN TEST SYMPOSIUM (ATS), #6C-3, 258 - 262, English[Refereed]International conference proceedings
- An Intermittent-Driven Supply-Current Equalizer for 11x and 4x Power-Overhead Savings in CPA-Resistant 128bit AES Cryptographic ProcessorA supply-current equalizer disables a Correlation Power Analysis (CPA) attack on an AES cryptographic processor. An intermittent equalizer operation only at processing rounds critical to key disclosure suppresses the equalizer power overhead significantly. For this low-power intermittent operation, a Thru operation mode is proposed with minimum hardware overhead. A level-shift comparator hides its own power consumption in an internal equalized virtual supply to guarantee secure protection of a secret key. Test-chip measurement in 0.18 mu m CMOS successfully demonstrates CPA-attack resiliency. For the key protection against mostly-common last-round CPA, the equalizer power overhead is reduced by 11x which is only 8% of 128bit AES processor power consumption, and by 4x even including the initial/1st-rounds CPA protection capability.IEEE, 2014, 2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), #14-5, 225 - 228, English[Refereed]International conference proceedings
- IEEE, 2014, 2014 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC), 57(No. 11) (No. 11), 216 - +, EnglishA 1mm-Pitch 80x80-Channel 322Hz-Frame-Rate Touch Sensor with Two-Step Dual-Mode Capacitance Scan[Refereed]International conference proceedings
- IEICE, Dec. 2013, IEICE Transactions on Fundamentals, E96-A(12) (12), 2516 - 2523, EnglishPerformance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring[Refereed]Scientific journal
- IEEE, Dec. 2013, 2013 IEEE 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo), #IM1-3, 226 - 231, EnglishNoise Analysis using On-Chip waveform Monitor in Bandgap Voltage References[Refereed]International conference proceedings
- IEEE, Dec. 2013, 2013 IEEE 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo), #SS-4, 42 - 46, EnglishMeasurements and Simulation of Substrate Noise Coupling in RF ICs with CMOS Digital Noise Emulator[Refereed]International conference proceedings
- IEEE, Dec. 2013, 2013 IEEE 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo), #SS-3, 37 - 41, EnglishMeasurement-Based Diagnosis of Wireless Communication Performance in the Presence of In-Band Interferers in RF Ics[Refereed]International conference proceedings
- IEEE, Dec. 2013, 2013 IEEE 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo), #SS-5, 47 - 52, EnglishIn-Band Spurious Attenuation in LTE-Class RFIC Chip using a Soft Magnetic Thin Film[Refereed]International conference proceedings
- IEEE, Dec. 2013, 2013 IEEE 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo), #IM1-4, 232 - 237, EnglishImmunity Evaluation of Inverter Chains against RF Power on Power Delivery Network[Refereed]International conference proceedings
- IEICE, Dec. 2013, IEICE Transactions on Fundamentals, E96-A(12) (12), 2533 - 2541, EnglishA Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation[Refereed]Scientific journal
- IEEE, Oct. 2013, IEEE International 3D Systems Integration Conference (3DIC 2013), #3-1, 3.1.1 - 3.1.4, EnglishVery low-voltage swing while high-bandwidth data transmission through 4096 bit TSVs[Refereed]International conference proceedings
- IEEE, Sep. 2013, 2013 IEEE International Symposium on Electromagnetic Compatibility in Europe (EMC Europe 2013), 405 - 410, EnglishOn-Chip Power Noise Measurements of Cryptographic VLSI Circuits and Interpretation for Side-Channel Analysis[Refereed]International conference proceedings
- IEEE, Sep. 2013, 2013 IEEE International Test Conference (ITC 2013), #12.3, 12.3.1 - 12.3.9, EnglishIn-System Diagnosis of RF ICs for Tolerance against On-Chip In-Band Interferers[Refereed]International conference proceedings
- IEEE, Sep. 2013, Extended Abstracts of the 2013 International Conference on Solid State Devices and Materials (SSDM 2013), #PS-5-5, 124, EnglishEmulation of High Frequency Substrate Noise in CMOS Digital Circuits with Effects of Adjusting Clock Skew[Refereed]International conference proceedings
- IEEE, Aug. 2013, 2013 IEEE International Symposium on Electromagnetic Compatibility (EMC 2013), TH-AM-3-1, 657 - 661, EnglishIn-Band Spurious Attenuation in LTE-Class RFIC Chip using a Soft Magnetic Thin Film[Refereed]International conference proceedings
- IEICE, Jun. 2013, IEICE Transactions on Electronics, E96-C(6) (6), 884 - 893, EnglishMeasurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation[Refereed]Scientific journal
- IEICE, Jun. 2013, IEICE Transactions on Electronics, E96-C(6) (6), 875 - 883, EnglishEquivalent Circuit Representation of Silicon Substrate Coupling of Passive and Active RF Components[Refereed]Scientific journal
- IEEE, May 2013, IEEE 2013 International Meeting for Future of Electron Devices, Kansai (IMFEDK 2013), #PS-03, 102 - 103, EnglishPower-Noise Measurements of Small-Scale Inverter Chains[Refereed]International conference proceedings
- IEEE, May 2013, 2013 IEEE Asia-Pacific International Symposium and Exhibition on Electromagnetic Compatibility (APEMC 2013), #103, 1 - 4, EnglishPower Current Modeling of Cryptographic VLSI Circuits for Analysis of Side Channel Attacks[Refereed]International conference proceedings
- JSAP, Apr. 2013, Japanese Journal of Applied Physics, Vol. 52(4) (4), 04CE14 - 1-04CE14-5, EnglishFalse Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation[Refereed]Scientific journal
- IEICE, Apr. 2013, IEICE Transactions on Electronics, E96-C(4) (4), 538 - 545, EnglishDesign of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits[Refereed]Scientific journal
- IEEE, Mar. 2013, Proceedings of 2013 IEEE International Conference on Microelectronic Test Structures (ICMTS 2013), (#4.2) (#4.2), 77 - 80, EnglishMeasurements of SRAM Sensitivity against AC Power Noise with Effects of Device Variation[Refereed]International conference proceedings
- IEEE, Feb. 2013, Digest of Technical Papers, 2013 IEEE Intl. Solid-State Circuits Conference (ISSCC), (#24.8) (#24.8), 434 - 435, EnglishA 100GB/s Wide I/O with 4096b TSVs Through an Active Silicon Interposer with In-Place Waveform Capturing[Refereed]International conference proceedings
- IEICE, Dec. 2012, IEICE Transactions on Fundamentals, E95-A(12) (12), 2284 - 2291, EnglishCo-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits[Refereed]Scientific journal
- IEEE, Dec. 2012, Proceedings of IEEE CPMT Symposium Japan 2012, (#19-2) (#19-2), 293 - 296, EnglishCo-simulation of AC Power Noise of CMOS Microprocessor using Capacitor Charging Modeling[Refereed]International conference proceedings
- IEEE, Nov. 2012, Proceedings of 2012 IEEE Asian Solid-State Circuits Conference (A-SSCC 2012), (#4-4) (#4-4), 113 - 116, EnglishMonitoring Effective Supply Voltage within Power Rails of Integrated Circuits[Refereed]International conference proceedings
- JSAP, Sep. 2012, Extended Abstracts of the 2012 International Conference on Solid State Devices and Materials (SSDM 2012), (#J-3-1) (#J-3-1), 1128 - 1129, EnglishSensitivity of SRAM Operation against AC Power Supply Voltage Variation[Refereed]International conference proceedings
- SICE, Aug. 2012, Proceedings of SICE Annual Conference 2012, (#TuA11-05) (#TuA11-05), 313 - 316, EnglishMeasurement of Side-Channel Information from Cryptographic Devices on Security Evaluation Platform: Demonstration of SPACES Project[Refereed]International conference proceedings
- IEEE, May 2012, Proceedings of IEEE 2012 International Meeting for Future of Electron Devices, Kansai (IMFEDK 2012), (#S-1) (#S-1), 70 - 71, EnglishCo-Evaluation of Power Supply Noise of CMOS Microprocessor using On-Boar Magnetic Probing and On-Chip Waveform Capturing Techniques[Refereed]International conference proceedings
- IEICE, Apr. 2012, IEICE Transactions on Electronics, E95-C(4) (4), 586 - 593, EnglishEvaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation[Refereed]Scientific journal
- Feb. 2012, IEICE Transactions on Fundamentals, Vol. E95-A, No. 2, pp. 430-438, EnglishModeling and Analysis of Substrate Noise Coupling in Analog and RF ICs (Invited)[Refereed]Scientific journal
- Jan. 2012, IEICE Transactions on Electronics, Vol. E95-C, No. 1, pp. 137-145, EnglishOn-Chip In-Place Measurements of Vth and Signal/Substrate Response of Differential Pair Transistors[Refereed]Scientific journal
- Jan. 2012, IEEE International 3D System Integration Conference, #7-2, pp. 7.2.1-7.2.4, EnglishIn-Tier Diagnosis of Power Domains in 3D TSV Ics[Refereed]International conference proceedings
- Dec. 2011, IEEE International Symposium on Radio-Frequency Integration Technology, #FR2B-3, pp. 217-220, EnglishExtraction of Lumped RC Elements Representing Substrate Coupling of RF Devices[Refereed]International conference proceedings
- Dec. 2011, IEEE International Symposium on Radio-Frequency Integration Technology, 1), #TH3B-1, pp. 141-144, EnglishEvaluation of Substrate Noise Coupling in RFICs (Invited)[Refereed]International conference proceedings
- Nov. 2011, IEEE 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits, #S3P2, pp. 76-81, EnglishMeasurements and Co-Simulation of On-Chip and On-Board AC Power Noise in Digital Integrated Circuits[Refereed]International conference proceedings
- Nov. 2011, IEEE 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits, #S2P6, pp. 65-70, EnglishImmunity Evaluation of SRAM Core Using DPI with On-Chip Diagnosis Structures[Refereed]International conference proceedings
- A single tone pseudo-noise generator with a harmonic-eliminated waveform is proposed for measuring noise tolerance of analog IPs. In the waveform, the harmonics up to the thirteenth are eliminated by combining seven rectangular waves with 22.5- degree spacing phases. The proposed waveform includes only high region frequency harmonic components, which are easily suppressed by a low-order filter. This characteristic enables simple circuit implementation for a sine wave generator. In the circuit, the harmonic eliminated waveform generator is combined with a current controlled oscillator and a frequency adjustment circuit. The single tone pseudo-noise generator can generate power line noise from 20 MHz to 220 MHz with I MHz steps. The SFDR of 40 dB is obtained at the noise frequency of 100 MHz. The circuit enables the measurement of frequency response characteristics measurements such as PSRR.IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jun. 2011, IEICE TRANSACTIONS ON ELECTRONICS, E94C(6) (6), 1024 - 1031, English[Refereed]Scientific journal
- Jun. 2011, 2011 IEEE Intl. Symp. Hardware-Oriented Security and Trust, #P35, pp. 87-92, EnglishA Fast Power Current Analysis Methodology Using Capacitor Charging Model for Side Channel Attack Evaluation[Refereed]International conference proceedings
- A diagnosis testbench of analog IP cores characterizes their coupling strengths against on-chip environmental disturbances, specifically with regard to substrate voltage variations. The testbench incorporates multi-tone digital noise generators and a precision waveform capture with multiple probing channels. A prototype test bench fabricated in a 90-nm CMOS technology demonstrates the diagnosis of substrate coupling up to 400 MHz with dynamic range of more than 60 dB. The coefficients of noise propagation as well as noise coupling on a silicon substrate are quantitatively derived for analog IP cores processed in a target technology, and further linked with noise awared EDA tooling for the successful adoption of such IP cores in SoC integration.IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jun. 2011, IEICE TRANSACTIONS ON ELECTRONICS, E94C(6) (6), 1016 - 1023, English[Refereed]Scientific journal
- May 2011, 2011 IEEE Intl. Conf. on Integrated Circuit Design and Technology, #C3, EnglishAn On-Chip Waveform Capturer for Diagnosing Off-Chip Power Delivery (Invited)[Refereed]International conference proceedings
- Apr. 2011, IEEE Intl. Magnetics Conference (Intermag 2011), #HH-03, pp. 1-4, EnglishEvaluation of Thin Film Noise Suppressor Applied to Noise Emulator Chip Implemented in 65 nm CMOS Technology[Refereed]International conference proceedings
- An on-chip waveform capturer exhibits 8.8-bit effective accuracy at a 5-ps timing resolution and 190 mu V voltage, with an effective bandwidth of 700 MHz in a 65-nm CMOS prototype. Voltage by a digital-to-analog converter with selectable slopes and offsets is linearly translated into timing, that is used for strobing a waveform. Programmable timing and voltage generation as well as selective input channels are intended for exhaustive power noise measurements on power delivery networks (PDNs) across rail-to-rail voltage domains in a chip. The measurement procedures are totally governed by an embedded controller. The waveform capturer, in combination with a PDN exciter, realizes in situ derivation of resonance parameters by assembling oscillatory waveforms. A power noise reduction of more than 50% is accomplished through on-chip PDN diagnosis, in which the operation frequencies are selected such that the periodical appearance of PDN resonance is prevented.IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, Apr. 2011, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 46(4) (4), 789 - 796, English[Refereed]Scientific journal
- A continuous-time waveform monitoring technique for quality on-chip power noise measurements features matched probing performance among a variety of voltage domains of interest in a VLSI circuit, covering digital Vdd, analog Vdd, as well as at Vss, and multiple probing capability at various locations on power planes. A calibration flow eliminates the offset as well as gain errors among probing channels. The consistency of waveforms acquired by the proposed continuous-time monitoring and sampled-time precise digitization techniques is ensured. A 90-nm CMOS on-chip monitor prototype demonstrates dynamic power supply noise measurements with +/- 200 mV at 2.5 V, 1.0 V. and 0.0 V, respectively, with less than 4 mV deviation among 240 probing channels.IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2011, IEICE TRANSACTIONS ON ELECTRONICS, E94C(4) (4), 495 - 503, English[Refereed]Scientific journal
- Power noise waveforms of a 32-bit microprocessor were on-chip measured in a 90-nm CMOS technology. A dedicated measurement system combines an embedded programming environment and a measurement flow that ensures acquisition of noise waveforms during designated arithmetic operation. Power noise exhibits clear relation with the contents of computation, where the magnitude of power noise reflects the occupancy ratio of computing resources of a microprocessor. The level of correlation is shown to be different among static and dynamic portions of power noise. It is concluded that practical power noise analysis requires the higher-level abstraction of a large-scale integrated digital system.IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Feb. 2011, IEICE ELECTRONICS EXPRESS, 8(3) (3), 182 - 188, English[Refereed]Scientific journal
- Accurate Analysis of Substrate Sensitivity of Active Transistors in an Analog CircuitA substrate network tailored for a variety of transistor geometry including channel sizes, fingering and folding, and shapes and placements of guard bands, extends the capability and accuracy of full-chip noise coupling analysis of mixed technology VLSI integration. Analysis of substrate sensitivity of differential amplifiers in a 90 nm CMOS technology with more than 64 different geometry and operating conditions well agrees with on-chip substrate coupling measurements, with the discrepancy within 3 dB.IEEE, 2011, 2011 12TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), #1B.4, pp. 56-61, 56 - 61, English[Refereed]International conference proceedings
- A Diagnosis Testbench of Analog IP Cores Against On-Chip Environmental DisturbancesAnalog IP cores exhibit a multivariate response to dynamic variations of an operation environment, that are typically represented by power and substrate voltage changes. A testbench provides a silicon area to embed and diagnose custom IP cores with power delivery and substrate networks, where the area is surrounded by on-chip precision waveform capturing and configurable power and substrate noise generation circuits. The coefficients of noise propagation and noise coupling are quantitatively derived for fabless IP cores processed in a target technology, that will be further linked with EDA tooling for the successful adoption of such IP cores in SoC integration.IEEE COMPUTER SOC, 2011, 2011 IEEE 29TH VLSI TEST SYMPOSIUM (VTS), 70 - 75, English[Refereed]International conference proceedings
- Performance of Integrated Magnetic Thin Film Noise Suppressor Applied to CMOS Noise Test ChipsPerformance of soft magnetic CoZrNb film as a thin film noise suppressor and its application to an noise emulator chip fabricated by 90/65nm CMOS technology are discussed. Intra-chip decoupling was studied by the electromagnetic coupling between two miniature coils made on a noise test chip implemented in CMOS 90nm technology. Inter-chip decoupling (radiation) was evaluated by the coupling between parallel line currents implemented in CMOS 65nm technology chip and off-chip planar shielded-loop coil type miniature magnetic probe. The intra-decoupling was as large as 10 dB at 1.8 GHz where ferromagnetic resonance can be maximized. The inter-decoupling was 7.7 dB at 200 MHz where magnetic shielding is effective. It is found that the product of magnetic film thickness and permeability is a good measure to evaluate magnetic shielding effectiveness for IC chip level inter-decoupling.IEEE, 2011, 2011 41ST EUROPEAN MICROWAVE CONFERENCE, #03-3, pp. 49-52, 49 - 52, English[Refereed]International conference proceedings
- Nov. 2010, Proceedings of IEEE Asian Solid-State Circuits Conference 2010, #4-6, pp. 125-128, EnglishOn-Chip Sine-Wave Noise Generator for Analog IP Noise Tolerance Measurements[Refereed]International conference proceedings
- Jun. 2010, Digest of Technical Papers, IEEE 2010 Symposium on VLSI Circuits, #12-2, pp. 121-122, EnglishOn-Chip Waveform Capture and Diagnosis of Power Delivery in SoC Integration[Refereed]International conference proceedings
- Jun. 2010, IEICE Transactions on Electronics, Vol. E93-C, No. 6, pp. 842-848, EnglishChip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails[Refereed]Scientific journal
- Jun. 2010, Proceedings of IEEE 2010 International Symposium on Circuits and Systems, #C3L-M.4, pp. 3557-3560, EnglishAn On-Chip Waveform Capturing Technique Pursuing Minimum Cost of Integration[Refereed]International conference proceedings
- Jun. 2010, IEICE Transactions on Electronics, Vol. E93-C, No. 6, pp. 820-826, EnglishAn Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology[Refereed]Scientific journal
- Apr. 2010, Japanese Journal of Applied Physics, Vol. 49, pp. 04DE01-1-04DE01-5, EnglishReference Complementary Metal-Oxide-Semiconductor Circuits and Test Structures for Evaluation of Dynamic Noise in Power Delivery Networks[Refereed]Scientific journal
- Mar. 2010, Proc. IEEE Intl. Conference on Micro Test Structures 2010, #10.4, pp. 232-235, EnglishOn-Chip In-situ Measurements of Vth and AC Gain of Differential Pair Transistors[Refereed]International conference proceedings
- Feb. 2010, IEICE Transactions on Fundamentals, Vol.E93-A, No.2, pp. 440-447, EnglishModeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits[Refereed]Scientific journal
- Nov. 2009, Proc. IEEE Intl. SoC Design Conference 2010, #S9.3, pp. 198-201, EnglishOn-Chip Power Noise Measurements of High-Frequency CMOS Digital Circuits[Refereed]International conference proceedings
- Nov. 2009, Proc. 2009 IEEE Intl. Symp. on Radio-Frequency Integration Technology, #TH-IF-11, pp. 80-83, EnglishEvaluation of Environmental Noise Susceptibility of RF Circuits Using Direct Power Injection[Refereed]International conference proceedings
- Nov. 2009, Proc. IEEE Asian Solid-State Circuits Conference 2009, #3-4, pp. 97-100, EnglishAn On-Chip Continuous Time Power Supply Noise Monitoring Technique[Refereed]International conference proceedings
- Sep. 2009, Ext. Abst. 2009 Intl. Conf. on Solid State Devices and Materials, #D-7-1, pp. 1068-1069, EnglishA Reference CMOS Circuit Structure for Evaluation of Dynamic Voltage Variation in Power Delivery Networks[Refereed]International conference proceedings
- Sep. 2009, Proc. IEEE 2009 Custom Integrated Circuits Conference, #M-08, pp. 219-222, EnglishA Full Chip Integrated Power and Substrate Noise Analysis Framework for Mixed-Signal SoC Design[Refereed]International conference proceedings
- Sep. 2009, Proc. IEEE 2009 Custom Integrated Circuits Conference, #M-08, pp. 187-190, EnglishA 6-bit Arbitrary Digital Noise Emulator in 65nm CMOS Technology[Refereed]International conference proceedings
- Apr. 2009, IEICE Transactions on Electronics, Vol.E92-C, No.4, pp. 475-482, EnglishExperimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations[Refereed]Scientific journal
- Nov. 2008, Proc. IEEE Asian Solid-State Circuits Conference 2008, #7-3, pp. 209-212, EnglishChip-to-Chip Half Duplex Data Communication at 135 Mbps Over Power-Supply Rails[Refereed]International conference proceedings
- Sep. 2008, IEICE Transactions on Electronics, Vol.E91-C, No.9, pp. 1453-1462, EnglishCurrent-Mode Transceiver with Nonfeedback Clock Recovery Capability for Mobile Applications[Refereed]Scientific journal
- Jun. 2008, IEEE 2008 Symposium on VLSI Circuits Digest of Technical Papers, #15-3, pp. 150-151, EnglishExperimental Evaluation of Digital-Circuit Susceptibility to Voltage Variation in Dynamic Frequency Scaling[Refereed]International conference proceedings
- Apr. 2008, IEICE Transactions on Electronics, Vol.E91-C, No.6, pp. 936-944, EnglishMeasurement-Based Analysis of Electromagnetic Immunity in LSI Circuit Operation[Refereed]Scientific journal
- Dec. 2007, IEICE Transactions on Fundamentals, Vol. E90-A, No. 12, pp. 2651-2, EnglishChip-Level Substrate Coupling Analysis with Reference Structures for Verification[Refereed]Scientific journal
- Nov. 2007, IEEE Asian Solid-State Circuits Conference 2007 (A-SSCC), #5-5, pp. 160-163, EnglishA Low-Power Current-Mode Tranceiver with Simultaneous Data and Clock Transmission at 625 Mb/s, 3 mW in 1.5 V for Mobile Applications[Refereed]International conference proceedings
- Oct. 2007, IEEE Transactions on VLSI Systems, Vol. 15, No. 10, pp. 1101-1110, EnglishAn On-Chip Multi-Channel Waveform Monitor for Diagnosis of Systems-on-Chip Integration[Refereed]Scientific journal
- Sep. 2007, IEEE 2007 Custom Integrated Circuits Conference (CICC), #27-3, pp. 849-852,, EnglishChip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for Isolation[Refereed]International conference proceedings
- Jun. 2007, Proceedings of Design Automation Conference 2007(DAC 2007), #22.4, pp. 400-403, EnglishOn-Chip Measurements Complementary to Design Flow for Integrity in SoCs[Refereed]International conference proceedings
- Jun. 2007, IEICE Transactions on Electronics, Vol. E90-C, No. 6, pp. 1189-11, EnglishOn-Chip Analog Circuit Diagnosis in Systems-on-Chip Integration[Refereed]Scientific journal
- Jun. 2007, IEICE Transactions on Electronics, Vol. E90-C, No. 6, pp. 1282-12, EnglishExperimental Verification of Power Supply Noise Modeling for EMI Analysis through On-Board and On-Chip Noise Measurements[Refereed]Scientific journal
- Jun. 2007, IEICE Transactions on Electronics, Vol. E90-C, No. 6, pp. 1299-13, EnglishA Mixed Circuit and System Level Simulation Technique of Collision-Resistant RFID Systems[Refereed]Scientific journal
- Apr. 2007, Japanese Journal of Applied Physics, Vol. 46, No. 4B, pp. 2244-2251, EnglishOn-Die Monitoring of Substrate Coupling for Mixed-Signal Circuit Isolation[Refereed]Scientific journal
- Mar. 2007, IEICE Transactions on Electronics, Vol.E90-C, No.4, pp. 692-698, EnglishSubstrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias[Refereed]Scientific journal
- Mar. 2007, IEICE Transactions on Electronics, Vol.E90-C, No.4, pp. 675-682, EnglishAsymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations[Refereed]Scientific journal
- Feb. 2007, 2007 IEEE International Solid-State Circuits Conference (ISSCC 2007), Digest of Technical Papers, #16.3, pp. 290-291, EnglishOn-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications[Refereed]International conference proceedings
- Feb. 2007, 2007 IEEE International Solid-State Circuits Conference (ISSCC 2007), Digest of Technical Papers, #16.2, pp. 288-289, EnglishFine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs[Refereed]International conference proceedings
- Feb. 2007, IEICE Transactions on Fundamentals, Vol.E90-A, No.2, pp. 380-387, EnglishEvaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits[Refereed]Scientific journal
- Dec. 2006, Proceedings of the IEEE, Vol. 94, No. 12, pp. 2109-2138, EnglishSubstrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation (Invited)[Refereed]Scientific journal
- Nov. 2006, IEICE Transactions on Electronics, Vol.E89-C, No.11, pp. 1559-156, EnglishMeasurement-Based Analysis of Delay Variation Induced by Dynamic Power Supply Noise[Refereed]Scientific journal
- Nov. 2006, IEICE Transactions on Electronics, Vol.E89-C, No.11, pp. 1581-159, EnglishBack-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach[Refereed]Scientific journal
- Nov. 2006, IEICE Transactions on Electronics, Vol.E89-C, No.11, pp. 1535-154, EnglishAn Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs[Refereed]Scientific journal
- Sep. 2006, Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials (SSDM 2006), C-1-6, pp. 62-63, EnglishOn-Die Monitoring of Substrate Couplig for Mixed-Signal Circuit Isolation[Refereed]International conference proceedings
- Sep. 2006, IEEE 32th European Solid-State Circuits Conference (ESSCIRC 2006), A3L-E1, pp. 118-121, EnglishOn-Chip Analog Circuit Diagnosis in Systems-on-Chip Integration[Refereed]International conference proceedings
- Sep. 2006, EMC Europe, PWeB-2, pp. 209-214, EnglishEvaluation of LSI Power-Supply Noise Caused by Injected RF Power Using LECCS Model[Refereed]International conference proceedings
- Sep. 2006, IEEE 2006 Custom Integrated Circuits Conference (CICC), #29-5, pp. 865-868, EnglishDelay Variation Analysis in Consideration of Dynamic Power Supply Noise Waveform[Refereed]International conference proceedings
- Jun. 2006, IEICE Transactions on Electronics, Vol.E89-C, No.6, pp. 761-768, EnglishAn On-Chip Multi-Channel Rail-to-Rail Signal Monitoring Technique for Sub-100-nm Digital Signal Integrity[Refereed]Scientific journal
- May 2006, 2006 International Conference on IC Design & Technology (ICICDT), #C-1, pp. 44-48, EnglishAn Integrated Timing and Dynamic Noise Verification Methodology for Nanometer CMOS SoC Designs (Inited)[Refereed]International conference proceedings
- Mar. 2006, IEICE Transactions on Electronics, Vol. E89-C;No. 3;pp. 356-363, EnglishMulti-Ported Register File for Reducing the Impact of PVT Variation[Refereed]Scientific journal
- Feb. 2006, IEICE Transactions on Fundamentals, Vol. E89-A;No. 2;pp. 408-415, EnglishCommunication Scheme for a Highly Collision-Resistive RFID System[Refereed]Scientific journal
- Jan. 2006, Proceedings of Asia and South Pacific Design Automation Conference 2006, pp. 677-682, EnglishEquivalent Circuit Modeling of Guard Ring Structures for Evaluation of Substrate Crosstalk Isolation[Refereed]International conference proceedings
- Jan. 2006, Proceedings of Asia and South Pacific Design Automation Conference 2006, pp. 106-107, EnglishA Built-in Power Supply Noise Probe for Digital LSIs[Refereed]International conference proceedings
- Dec. 2005, IEICE Transactions on Fundamentals, Vol. E88-A;No. 12;pp. 3324-333, EnglishLogic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition[Refereed]Scientific journal
- Nov. 2005, 2005 IEEE Asian Solid-State Circuits Conference Proceedings of Technical Papers, pp. 165-168, EnglishMeasurements of Digital Signal Delay Variation Due to Dynamic Power Supply Noise[Refereed]International conference proceedings
- Oct. 2005, IEICE Transactions on Electronics, Vol. E88-C;No. 10;pp. 2001-200, EnglishHigh-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition[Refereed]Scientific journal
- Sep. 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, pp. 35-38, EnglishSubstrate-Noise and Random-Fluctuations Reduction with Self-Adjusted Forward Body Bias[Refereed]International conference proceedings
- Sep. 2005, Proceedings of the 31th European Solid-State Circuits Conference, pp. 295-298, EnglishAn On-Chip Multi-Channel Waveform Monitor for Mixed Signal VLSI Diagnostics[Refereed]International conference proceedings
- Sep. 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, pp. 31-34, EnglishAn Integrated Timing and Dynamic Supply Noise Verification for Nano-meter CMOS SoC Designs[Refereed]International conference proceedings
- Jun. 2005, 2005 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 276-279, EnglishIsolation Strategy against Substrate Coupling in CMOS Mixed-Signal/RF Circuits[Refereed]International conference proceedings
- Apr. 2005, IEICE Transactions on Electronics, Vol. E88-C;pp. 589-596, EnglishDynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits[Refereed]Scientific journal
- Apr. 2005, IEEE Journal of Solid-State Circuits, Vol. 40;pp. 813-819, EnglishA Built-in Technique for Probing Power Supply and Ground Noise Distribution Within Large-Scale Digital Integrated Circuits[Refereed]Scientific journal
- Mar. 2005, Proceedings of the Design Automation and Test in Europe 2005, Volume1-2C1, 146-151, EnglishOn-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits[Refereed]International conference proceedings
- Feb. 2005, 2005 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 266-267, EnglishSubstrate Integrity beyond 1 GHz[Refereed]Scientific journal
- Oct. 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 509-512, EnglishFull-chip Vectorless Dynamic Power Integrity Analysis and Verification Against 100uV/100ps-Resolution Measurement[Refereed]International conference proceedings
- Sep. 2004, Extended Abstructs of the 2004 International Conference on solid-state Devices and Materials 2004, 400-401, EnglishDesign of RFID Front-end Circuitry Enabling CDMA-based Collision Resistance[Refereed]Scientific journal
- Aug. 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, 438-439, EnglishA Design of Transponder IC for Highly Collision Resistive RFID Systems[Refereed]International conference proceedings
- Jun. 2004, 2004 Symposium on VLSI Circuits Digest of Technical Papers, 98-101, EnglishA Built-in Technique for Probing Power-Supply Noise Distribution within Large-Scale Digital Integrated Circuits[Refereed]Scientific journal
- 2004, 2004 Symposium on VLSI Circuits Digest of Technical Papers, 94-97, EnglishDynamic Power-Supply and Well Noise Measurement and Analysis for High Frequency Body-Biased Cirsuits[Refereed]Scientific journal
- 2003, Proceedings of IEEE 2003 Custom Integrated Circuits Conference, 369-372, EnglishA Substrate Noise Analysis Methodology for Large-Scale Mixed-Signal Ics[Refereed]International conference proceedings
- 2003, IEEE Transactions on Nanotechnology, 2(3),158-164, EnglishA Multinanodot Floating-Gate MOSFET Circuit for Spiking Neuron Models.[Refereed]Scientific journal
- 2003, Proceedings of 5th Asia-Pacific Symposium on Information and Telecommunication Technologies, 223-228, EnglishA Highly Collision Resistive RFID System[Refereed]International conference proceedings
MISC
- Lead, Apr. 2023, 電子情報通信学会・エレクトロニクスソサイエティニュースレター, 189, 1 - 2, Japaneseエレクトロニクスソサイエティと学術誌(2)
- Lead, Oct. 2022, IEICE Fundamentals Review, 16(2) (2), 93 - 99, Japanese
- Apr. 2022, 電子情報通信学会・エレクトロニクスソサイエティニュースレター, (185) (185), 1 - 2, Japaneseエレクトロニクスソサイエティと学術誌
- Jan. 2022, KEC情報, 260, 13 - 16, Japaneseハードウェアセキュリティ~セキュアICチップの実装攻撃と対策~
- Apr. 2021, KEC情報, 257, 15 - 19, Japanese5G時代のIoTデバイスに向けた不要電波の評価と対策
- Mar. 2020, The Innovation Platform, 340 - 341, EnglishDeployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security
- Jan. 2020, 電子情報通信学会エレクトロニクスソサイエティ・ニュースレター, 176, 23, Japanese電子産業を支える集積回路:若手人材の育成に向けた取組み
- Nov. 2019, Sci TechEurope Quarterly, 33, 38 - 39, EnglishHardware Security and Safety
- Jan. 2015, IEICE Fundamentals Review, Vol. 8(No. 3) (No. 3), 177 - 182, JapaneseICチップの真正性の確保と対策 -ハードウェアセキュリティの根源的課題に向き合うIntroduction scientific journal
- Oct. 2014, 電磁環境工学情報(EMC), No. 318, 31-37, Japaneseオンチップノイズの発生と干渉の評価Introduction scientific journal
- Dec. 2013, 日本信頼性学会誌(REAJ), Vol. 35, 439 - 440, JapaneseVLSIにおける電磁環境雑音概説[Invited]Introduction scientific journal
- Dec. 2013, 日本信頼性学会誌(REAJ), Vol. 35, 441, JapaneseSRAMの電源ノイズとイミュニティ[Invited]Introduction scientific journal
- Oct. 2013, 電磁環境工学情報(EMC), No. 306, 31 - 39, Japaneseサイドチャネル攻撃評価のための電源ノイズモデル[Invited]Introduction scientific journal
- 科学技術出版, Feb. 2013, 電磁環境工学情報(EMC), (298) (298), 77 - 88, JapaneseVLSI電源ノイズの観測・解析と究明[Invited]Introduction scientific journal
- 無線機器内のRF部における高速信号伝送の品質の向上を目的として,LTE(Long Term Evolution)級RFトランシーバを想定したTEG(Test Element Group)チップ上に磁性膜を集積化し,LTE信号帯域へ混入する高周波ノイズ抑制効果を示した.高周波ノイズに関しては,TEGチップ内に設計した任意雑音発生回路を用いて,デジタル回路のスイッチングにより生じるノイズを発生した.その結果,磁性膜の集積化により,約10dBのLTE帯域内ノイズ抑制効果が得られた.The Japan Institute of Electronics Packaging, 2013, Proceedings of JIEP Annual Meeting, 27(0) (0), 67 - 68, Japanese
- Mar. 2012, エレクトロニクス実装学会誌, Vol. 15, No. 2, pp. 158, Japanese研究室訪問:神戸大学大学院システム情報学研究科情報科学専攻・情報システム(永田)研究室Introduction scientific journal
- Sep. 2010, 電子材料, 第49巻、第9号、pp. 54-55, Japanese2010VLSIサーキットシンポジウム報告Introduction scientific journal
- Jul. 2010, エレクトロニクス実装学会誌, Vol. 13, No. 4, pp. 259-262, JapaneseVLSIチップの電源電流シミュレーション[Refereed]Introduction scientific journal
- Jul. 2010, 電子ジャーナル, 第196号, pp. 58-59, Japanese2010 Symposium on VLSI Circuits ReportIntroduction scientific journal
- Dec. 2009, エレクトロニクス実装学会誌, Vol. 12, No. 7, pp. 581-586, JapaneseデジタルLSI電源ノイズのオンチップ観測とシミュレーション技術[Refereed]Introduction scientific journal
- May 2009, M&E, Vol. 36, No. 5, pp. 119-122, JapaneseLSIノイズのオンチップ測定とモデリングによる対策Introduction scientific journal
- Jan. 2009, 電子情報通信学会誌, Vol. 92, No. 1, pp. 55-60, JapaneseLSI電源雑音の研究[Refereed]Introduction scientific journal
- Nov. 2007, 日本信頼性学会誌(REAJ), Vol. 29, No. 7, pp. 446-455, JapaneseLSIと電子機器の電磁環境性能向上技術[Refereed]Introduction scientific journal
- Jul. 2007, 電磁環境工学情報(EMC), No. 231, pp. 106-113, JapaneseCMOSアナログ回路のオンチップ雑音対策Introduction scientific journal
- 2004, Electronic Design and Solution Fair 2004 資料集, 73-85, JapaneseデジタルLSIの高速化設計と雑音解析技術Others
- 2003, NEDO平成15年度研究助成事業成果報告会予稿集, 188-193, Japanese高性能LSIのためのデジタル電源/グラウンド雑音低減化設計及び診断技術の開発Others
- 2003, Electronic Design and Solution Fair 2003 資料集, 61-69, JapaneseミックストシグナルLSIのための基盤雑音解析技術[Refereed]Others
Books And Other Publications
- pp. 125-133, シーエムシー出版, Mar. 2023, Japanese「ドローンの電磁ノイズと電磁環境(第12章)」ワイヤレス電力伝送と5G通信の連携・融合に向けた干渉対策と今後の展望Scholarly book
- Others, オーム社, Mar. 2013, Japanese, ISBN: 9784274213441OHM大学テキスト アナログ電子回路Scholarly book
- Joint work, 丸善, Jan. 2009, JapaneseアナログCMOS集積回路の設計--演習編--Textbook
- Joint work, CRC Press, Mar. 2006, EnglishEDA for IC Implementation, Circuit Design, and Process Technology, Eds: Scheffer, Lavagno, and Martin, Chapter 23.3Scholarly book
Lectures, oral presentations, etc.
- 2024年電子情報通信学会総合大会, Mar. 2024, Japanese無線通信を利用する自律移動体の電磁ノイズ課題と解決に向けて[Invited]
- 2024年電子情報通信学会総合大会, Mar. 2024, Japanese電磁ノイズ特性とGPS位置情報精度劣化の関係
- 2024年電子情報通信学会総合大会, Mar. 2024, Japanese複数の産業用ドローンにおける電磁ノイズの類似性評価
- 2024年電子情報通信学会総合大会, Mar. 2024, JapaneseICチップの磁性材料による電磁ノイズ低減効果評価法の検討
- 2024年電子情報通信学会総合大会, Mar. 2024, Japaneseディジタル回路の消費電荷量に着目したハードウェアトロイ検知手法
- 2024年電子情報通信学会総合大会, Mar. 2024, Japanese裏面電圧故障注入による攻撃精度評価
- 2024年電子情報通信学会総合大会, Mar. 2024, Japanese大規模シリコン量子ビットの高精度制御に向けた極低温バイアス電圧生成DA変換回路の開発
- ハードウェアセキュリティ研究会(HWS), Mar. 2024, JapaneseオンチップLDOによる電磁波照射ノイズ低減効果の検討
- 集積回路研究会(ICD), Feb. 2024, Japaneseマルチチップアッセンブリにおけるチップ近傍の排熱特性の評価と解析
- シリコン材料・デバイス研究会(SDM), Feb. 2024, Japanese3 次元集積回路の電源品質改善のための裏面埋設配線技術の開発[Invited]
- 熊本大学半導体セミナー, Feb. 2024, Japanese半導体チップの先端パッケージング技術とハードウエアセキュリティ
- COSIC Seminar, KU Leuven, Jan. 2024, EnglishSi-Substrate Backside of an IC Chip for Performance Improvements and Security
- COSIC Seminar, KU Leuven, Jan. 2024, EnglishExploration of full-chip level SCA simulation
- 電子情報通信学会・集積回路研究会, 学生・若手研究会, Dec. 2023, Japanese暗号ICチップに対する電磁的故障注入攻撃における故障感度の検討
- EMCシンポジウムIIDA2023, Nov. 2023, Japaneseドローン機体の電磁ノイズ課題と対策[Invited]
- ハードウェアセキュリティフォーラム2023, Dec. 2023, Japaneseマスキング対策を施した暗号モジュールのサイドチャネル漏洩検証 におけるトランジスタレベルシミュレーションの不確かさ
- デザインガイア2023, Nov. 2023, Japanese裏面電圧故障注入を用いた差分故障解析による秘密鍵導出
- デザインガイア2023, Nov. 2023, Japaneseチップ裏面シリコン基板電位によるサイドチャネル攻撃とシミュレーション
- 2023年ICD・HWS研究会, Oct. 2023, Japaneseセキュリティ向け三次元積層チップの検討
- 環境電磁工学研究会(EMCJ), Oct. 2023, Japanese産業用ドローンを対象とした5G受信感度の電磁ノイズ成分に対する応答解析
- POSTECH, Oct. 2023, EnglishOn-Chip Physical Attack Protection Circuits and Design for Hardware Security[Invited]
- 2023年電子情報通信学会ソサイエティ大会, Sep. 2023, JapaneseICチップレベル電源電流シミュレーションによるハードウェアトロイ検知可能性の検討
- 2023年電子情報通信学会ソサイエティ大会, Sep. 2023, Japanese無線通信シミュレーションにおける無線実機性能の取り込み手法について
- 2023年電子情報通信学会ソサイエティ大会, Sep. 2023, Japanese裏面電圧故障注入を用いた差分故障解析による攻撃実現性の検討
- エレクトロニクス実装学会・第33回マイクロエレクトロニクスシンポジウム(MES2023), Sep. 2023, Japanese裏面埋設・電源供給配線網を有する3次元集積回路の作製プロセス
- 応用物理学会超集積エレクトロニクス産学連携委員会・夏の学校, Aug. 2023, JapaneseセキュアICチップの実装攻撃と対策の初級講座[Invited]
- 集積回路研究会, Aug. 2023, Japanese量子コンピュータ向けフリップチップシリコンインターポーザの極低温評価
- EdgeTech+ West 2023, Jul. 2023, Japaneseハードウェアセキュリティ~セキュアICチップの実装攻撃と対策
- ACM/IEEE Design Automation Conference (DAC 2023), Jul. 2023, EnglishOn-Chip and In-System Side-Channel Measurements and Assessments
- The 38th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2023), Jun. 2023, EnglishHardware Security and Safety of IC Chips (Invited)[Invited]
- International Hardware Security Forum, Jun. 2023, EnglishVertically Integrated Si Techniques for Hardware Security Attack Countermeasures (Invited)[Invited]
- 環境電磁工学研究会(EMCJ), Jun. 2023, Japaneseスイッチング半導体チップの高次スプリアス成分による電磁ノイズ評価法の検討
- 環境電磁工学研究会(EMCJ), Jun. 2023, Japanese産業用ドローンにおける電磁ノイズと移動通信システムの干渉評価と対策
- 環境電磁工学研究会(EMCJ), Jun. 2023, Japanese産業用ドローンの近傍電磁ノイズとGPSモジュールの干渉評価
- IEEE The 1st International Symposium on Integrated Magnetics (iSIM), May 2023, EnglishMagnetic Thin Films for In-Package Noise Suppression of Semiconductor Switching Circuits (Invited)[Invited]
- LSIとシステムのワークショップ2023, May 2023, Japaneseシリコン量子ビットの大規模化に向けたパッケージング構造の極低温評価
- LSIとシステムのワークショップ202, May 2023, Japanese暗号ICチップへの電磁的故障注入攻撃と回路応答解析,
- LSIとシステムのワークショップ2023, May 2023, Japanese大規模シリコン量子ビットの高精度制御に向けた極低温バイアス電圧生成回路の開発
- IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2023, EnglishOn-Chip and In-System Side-Channel Measurements and Assessments
- ハードウェアセキュリティ研究会, Apr. 2023, Japanese暗号ICチップの電磁的故障注入攻撃とチップ内部電圧応答の解析
- ハードウェアセキュリティ研究会, Apr. 2023, Japanese暗号ICチップの電磁的故障注入攻撃における解析手法の検討
- ハードウェアセキュリティ研究会, Apr. 2023, Japaneseハードウェアトロージャン検知に向けた電源電流シミュレーション手法の検討
- 2023年電子情報通信学会総合大会, Mar. 2023, Japanese長時間に渡る高強度な不要電波の発生頻度解析システムの構築Oral presentation
- 2023年電子情報通信学会総合大会, Mar. 2023, Japanese自律移動体における不要電波とGPS信号の干渉評価Oral presentation
- 2023年電子情報通信学会総合大会, Mar. 2023, Japanese高速非同期逐次比較型AD変換器におけるサイドチャネル漏洩特性の評価Oral presentation
- 2023年電子情報通信学会総合大会, Mar. 2023, Japaneseセキュリティ半導体システムにおける電源結合網の評価Oral presentation
- 2023年電子情報通信学会総合大会, Mar. 2023, Japanese暗号マルチチップモジュールのサイドチャネル漏洩評価Oral presentation
- 2023年電子情報通信学会総合大会, Mar. 2023, Japanese産業用ドローンにおける不要電波と移動通信システムの電磁干渉評価Oral presentation
- 2023年電子情報通信学会総合大会, Mar. 2023, Japanese高い周波数の 5G通信帯域におけるICチップ放射ノイズの評価Oral presentation
- ハードウェアセキュリティ研究会, Mar. 2023, Japanese暗号マルチチップモジュールのサイドチャネル漏洩評価Oral presentation
- ハードウェアセキュリティ研究会, Mar. 2023, Japaneseセキュリティ半導体システムにおける電源結合網の評価Oral presentation
- 電子情報通信学会・情報セキュリティ研究会, 2023年 暗号と情報セキュリティシンポジウム, Jan. 2023, Japanese暗号ICチップの裏面サイドチャネル攻撃とシミュレーション
- JEITA先端半導体パッケージング技術WG/大阪大学 F3D実装コンソーシアム・オンライン, Jan. 2023, Japanese半導体のノイズについて," 公開セミナー/先端半導体パッケージング開発において考慮すべきこと
- 電子情報通信学会・集積回路研究会, 学生・若手研究会, Dec. 2022, Japanese高速非同期逐次比較型AD変換器におけるサイドチャネル漏洩特性の評価
- 電子情報通信学会・集積回路研究会, 学生・若手研究会, Dec. 2022, Japanese暗号ICチップにおける電源電流シミュレーションによるサイドチャネル評価手法の構築
- 電子情報通信学会・集積回路研究会, 学生・若手研究会, Dec. 2022, JapaneseフリップチップパッケージングIC裏面に印加した電圧擾乱に対するICチップ応答の評価
- 電子情報通信学会・ハードウェアセキュリティフォーラム2022, Dec. 2022, Japanese暗号ICチップにおけるサイドチャネル漏洩のチップ厚さによる効果の評価
- 電子情報通信学会・ハードウェアセキュリティフォーラム2022, Dec. 2022, Japaneseディジタルセキュリティを支えるアナログ技術
- Ansys IDEAS 2022, Dec. 2022, EnglishSimulating Power Side Channel Leakages from Architectural Exploration to Physical Implementation of Crypto ICs
- デザインガイア, Nov. 2022, Japaneseセキュア半導体システムにおける電源結合網の評価Oral presentation
- デザインガイア, Nov. 2022, Japanese暗号モジュール搭載チップのシステムレベルセキュリティ評価Oral presentation
- ハードウエアセキュリティ研究会, Oct. 2022, Japanese暗号ICチップの電源電流シミュレーションとサイドチャネル漏洩評価Oral presentation
- 環境電磁工学研究会(EMCJ), Oct. 2022, Japaneseドローン用移動通信における機体の電磁遮蔽効果による感度劣化評価Oral presentation
- IEEE Asian Solid-State Circuits Conference (A-SSCC), Oct. 2022, EnglishCircuits and Packaging Systems for Security Chips (Invited)Invited oral presentation
- 【関西DX実装イニシアティブ】サイバーセキュリティ・リレー講座, Sep. 2022, Japaneseハードウェアセキュリティ~セキュアICチップの実装攻撃と対策~
- 2022年電子情報通信学会ソサイエティ大会, Sep. 2022, Japanese産業用ドローンにおける移動通信受信感度劣化評価
- 2022年電子情報通信学会ソサイエティ大会, Sep. 2022, Japaneseフリップチップパッケージングにおける裏面電圧擾乱印加によるオンチップ電圧変動の評価
- 2022年電子情報通信学会ソサイエティ大会, Sep. 2022, Japanese, Co-authored internationally電源ノイズシミュレーションを用いた暗号モジュールのサイドチャネル漏洩評価
- The 13th edition of International Workshop of Electromagnetic Compatibility (CEM 2022), Sep. 2022, EnglishELECTROMAGNETIC INTERFERENCE OF EMISSION NOISE ON MOBILE COMMUNICATIONS INSIDE INDUSTRIAL UNMANNED AERIAL VEHICLES
- 応用物理学会超集積エレクトロニクス産学連携委員会・夏の学校, Aug. 2022, JapaneseセキュアICチップの実装攻撃と対策の初級講座
- 集積回路研究会, Aug. 2022, Japanese大規模量子ビットアレイの高精度制御に向けた極低温DA変換器の設計
- 集積回路研究会, Aug. 2022, Japaneseフリップチップパッケージングにおける裏面電圧擾乱印加とICチップ応答の評価
- Ansys Customer Workshop at DAC 2022, EnglishRTL DESIGN SECURITY VERIFICATION FOR RESISTING POWER SIDE-CHANNEL ATTACK
- Lectures In the frame of Erasmus+ International program, Jun. 2022, EnglishTesting Embedded Toggle Pattern Generation Through On-Chip IR Drop Monitoring
- Lectures In the frame of Erasmus+ International program, Jun. 2022, EnglishHardware Security and Safety of IC Chips
- 環境電磁工学研究会(EMCJ), Jun. 2022, Japaneseイーサネット通信システムへのバルク電流注入による外部擾乱耐性の評価(2)
- 環境電磁工学研究会(EMCJ), Jun. 2022, Japaneseドローンから発生する放射ノイズの時間領域解析および移動通信干渉の評価
- 環境電磁工学研究会(EMCJ), Jun. 2022, Japaneseワイドバンドギャップ半導体を用いた電源モジュールの広帯域放射ノイズ評価
- NICT/EMC-net 第3回将来課題研究会, Apr. 2022, Japanese5G時代のIoTデバイスに向けた不要電波の評価と解析
- 2022年電子情報通信学会総合大会, Mar. 2022, JapaneseSoC 向け電源ノイズシミュレーションを用いた暗号モジュールのサイドチャネル漏洩分布評価
- 2022年電子情報通信学会総合大会, Mar. 2022, Japanese30 GHz帯における電磁ノイズの近傍評価
- IEEE EMC Society Sendai Chapter, Feb. 2022, Japanese磁性材料による半導体ICチップの不要電波低減効果の評価と解析
- IEEE EMC Society Sendai Chapter, Feb. 2022, Japanese次世代パワー半導体を用いた電源モジュールにおける放射ノイズの広帯域評価
- 電子情報通信学会技術報告, Jan. 2022, Japaneseイーサネット通信システムへのバルク電流注入による外部擾乱耐性の評価
- ACM/IEEE 27th Asia and South Pacific Design Automation Conference (ASP-DAC 2022), Jan. 2022, EnglishOn-Chip and In-System Side-Channel Measurements and Assessments
- IEEE Solid-State Circuits Society, Japan Chapter Virtual DL Seminar, Dec. 2021, EnglishDeployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security
- 電子情報通信学会・集積回路研究会, 学生・若手研究会, Dec. 2021, Japanese電源ノイズシミュレーションによるサイドチャネル漏洩評価手法の検討
- 電子情報通信学会・集積回路研究会, 学生・若手研究会, Dec. 2021, Japanese電源ノイズ解析による電源経路の特徴量抽出
- 電子情報通信学会・ハードウェアセキュリティ研究会, ハードウェアセキュリティフォーラム, Dec. 2021, Japanese電源ノイズ解析による電源経路の特徴量抽出
- IEEE Solid-State Circuits Society, Taipei Chapter Virtual DL Seminar, Dec. 2021, EnglishRF Noise Coupling -- Understanding, Mitigation and Impacts on Wireless Communication Performance
- 電子情報通信学会技術報告, Dec. 2021, Japaneseオンチップモニタを用いたダイナミック電圧ドロップ診断
- 電子情報通信学会技術報告, Dec. 2021, JapaneseデュアルモードSAR ADCを用いた電源ノイズ解析攻撃の検知手法の考案
- The 23rd ACM/IEEE International Workshop on System-Level Interconnect Pathfinding (SLIP 2021), Nov. 2021, EnglishChip Stacking and Packaging Technology Explorations for Hardware Security (Invited Talk)[Invited]
- 電子情報通信学会技術報告, Oct. 2021, Japanese暗号モジュールからのサイドチャネル漏洩評価に向けた効率の良い電源ノイズシミュレーション手法
- 電子情報通信学会技術報告, Oct. 2021, Japaneseスイッチング電源回路における放射ノイズと5G通信への干渉評価
- 電子情報通信学会技術報告, Oct. 2021, Japanese産業用ドローン内部における放射ノイズ評価
- IEEE EDS Kansai Chapter, Sep. 2021, EnglishSecure 3D CMOS Chip Stacks with Backside Buried Metal Power Delivery Networks for Distributed Decoupling Capacitance [IEDM]
- 電気学会研究会, Sep. 2021, JapaneseGaN素子を用いたスイッチング電源回路近傍における放射ノイズの広帯域評価
- 2021年電子情報通信学会ソサイエティ大会, Sep. 2021, Japanese大規模集積回路向け電源ノイズシミュレーションを用いた暗号モジュールのサイドチャネル漏洩評価
- 2021年電子情報通信学会ソサイエティ大会, Sep. 2021, JapaneseGaN電源モジュールにおける制御回路の不要電波評価
- IEEE Solid-State Circuits Society, Singapore Chapter Virtual DL Seminar, Sep. 2021, EnglishOn-Chip Physical Attack Protection Circuits for Hardware Security
- IEEE 47th European Solid-State Circuits Conference (ESSCIRC 2021), Sep. 2021, EnglishSide-channel Leakages, Attacks and Simulation for Hardware Security
- 電子情報通信学会技術報告, vol. 121, no. 139, ICD2021-14, pp. 68-71, Aug. 2021, Japanese高速非同期逐次比較型AD変換器におけるサイドチャネル漏洩特性の評価
- NXP, 2XP Distinguished Lecturer Series Virtual Seminar, Jul. 2021, EnglishIC-Chip Level Physical Attack Protections for IoT Security
- 2021年 KECセミナー, Jul. 2021, Japaneseハードウェアセキュリティ ~セキュアICチップの実装攻撃と対策~
- 電子情報通信学会技術報告, Jul. 2021, Japanese小型ドローン近傍における不要電波評価
- IEEE Solid-State Circuits Society, Poland Chapter Virtual DL Seminar, Jun. 2021, EnglishRF Noise Coupling - Understanding, Mitigation and Impacts on Wireless Communication Performance
- IEEE Solid-State Circuits Society, Poland Chapter Virtual DL Seminar, Jun. 2021, EnglishIC Chip and Packaging Interactions in Design for SI, PI, EMC and ESD
- 2021 Symposia on VLSI Technology and Circuits, Short course, Jun. 2021, EnglishIC-Chip Level Physical Attack Protections for IoT Security
- IEEE Solid-State Circuits Society, Israel Chapter Virtual DL Seminar, Jun. 2021, EnglishHardware Security and Safety of IC Chips
- Beijing Chapter Virtual DL Seminar, May 2021, EnglishRF Noise Coupling - Understanding, Mitigation and Impacts on Wireless Communication Performance
- LSIとシステムのワークショップ2021, May 2021, JapaneseVLSI向けパワーノイズシミュレーションを用いた暗号モジュールのサイドチャネル漏洩評価
- LSIとシステムのワークショップ2021, May 2021, JapaneseGaN素子を用いたスイッチングデバイスにおける放射不要電波の広帯域評価
- LSIとシステムのワークショップ2021, May 2021, Japanese車載向けICチップにおける外部擾乱のアナログ検知手法に関する検討
- IEEE Solid-State Circuits Society, Switzerland Chapter Virtual DL Seminar, Apr. 2021, EnglishIC Chip and Packaging Interactions in Design for SI, PI, EMC and ESD
- IEEE Solid-State Circuits Society, Apr. 2021, EnglishHardware Security and Safety of IC Chips
- 電子情報通信学会技術報告, vol. 120, no. 401, HWS2020-60, pp. 97-101, Mar. 2021, Japanese楕円曲線ディジタル署名チップを用いたマルチノードIoTシステムにおけるデータ真正性の検証実験Oral presentation
- 電子情報通信学会技術報告, vol. 120, no. 401, HWS2020-52, pp. 50-54, Mar. 2021, Japanese半導体チップに潜むハードウェアトロージャンを見つけ出す高効率シミュレーション手法Oral presentation
- 電子情報通信学会・集積回路研究会, 学生・若手研究会, Mar. 2021, Japanese車載電子機器における電磁擾乱応答の評価とin-situ検知技術Oral presentation
- 電子情報通信学会・集積回路研究会, 学生・若手研究会, Mar. 2021, Japanese暗号プロセッサへの物理攻撃に対するマルチモーダル検知・反応回路技術Oral presentation
- 電子情報通信学会・集積回路研究会, 学生・若手研究会, Mar. 2021, Japaneseオンチップ電源モニタリングを用いたマルチチップ搭載電子ボードの意図的改変検知技術Oral presentation
- IEEE Solid-State Circuits Society, Croatia Chapter Virtual DL Seminar, Feb. 2021, English, International conferenceIC Chip and Packaging Interactions in Design for SI, PI, EMC and ESDOral presentation
- 電子情報通信学会技術報告, vol. 120, no. 352, SDM2020-51, pp. 8-12, Jan. 2021, JapaneseCMOS裏面埋設配線による電源供給網と電源容量の形成 およびセキュリティ向け三次元積層チップへの応用[Invited]Invited oral presentation
- 電子情報通信学会技術報告, vol. 120, no. 333, EMCJ2020-71, pp. 40-43, Jan. 2021, JapaneseIoTデバイスにおける不要電波の評価と対策Oral presentation
- 電子情報通信学会技術報告, vol. 120, no. 333, EMCJ2020-70, pp. 35-39, Jan. 2021, JapaneseGaN素子を用いたパワーモジュールにおける放射ノイズの広帯域評価Oral presentation
- ワークショップ「マグネティックスによるパワーエレクトロニクスの革新と協創」, 電気学会マグネティックス技術委員会, Jan. 2021, Japanese半導体スイッチングデバイスにおける不要電波の発生と磁性材料による抑制Oral presentation
- IEEE Solid-State Circuits Society, Austria Chapter Virtual DL Seminar, Jan. 2021, English, International conferenceRF Noise Coupling - Understanding, Mitigation and Impacts on Wireless Communication PerformanceOral presentation
- 電子情報通信学会・集積回路研究会, Dec. 2020, Japaneseオンチップモニタを用いた電磁擾乱in-situ検知手法の提案Poster presentation
- 電子情報通信学会・ハードウェアセキュリティ研究会, Dec. 2020, Japaneseオンチップモニタを用いた意図的外部擾乱の検知手法に関する検討Poster presentation
- IEEE Solid-State Circuits Society, Austria Chapter Virtual DL Seminar, Dec. 2020, English, International conferenceDeployment of EMC-Compliant IC Chip Techniques in Design for Hardware SecurityOral presentation
- 電子情報通信学会技術報告, vol. 120, no. 235, ICD2020-52, pp. 118-121, Nov. 2020, Japanese楕円曲線ディジタル署名(ECDSA)ハードウェアモジュールの動作性能評価(II)Oral presentation
- 電子情報通信学会技術報告, vol. 120, no. 235, ICD2020-51, pp. 115-117, Nov. 2020, Japaneseオンチップ電源ノイズモニタリングによるマルチチップ搭載ボード電源結合網の評価Oral presentation
- 電子情報通信学会技術報告, vol. 120, no. 212, ICD2020-30, pp. 94-98, Oct. 2020, JapaneseセキュアICチップにおける物理設計改竄の検出に向けた高効率シミュレーション手法の検討Oral presentation
- 電子情報通信学会技術報告, vol. 120, no. 211, HWS2020-35, pp. 59-64, Oct. 2020, Japanese半導体チップのハードウェアトロージャンに対する物理レベルの取り組み(Ⅱ)Oral presentation
- 第25回EMC関西2020, KEC関西電子工業振興センター, Oct. 2020, Japanese5G 時代の IoT デバイスに向けた不要電波の評価と対策Oral presentation
- 2020年電子情報通信学会ソサイエティ大会, A-19-3, pp. 101, Sep. 2020, Japanese電源ノイズシミュレーションを用いた暗号モジュールのサイドチャネル漏洩評価Oral presentation
- 2020年電子情報通信学会ソサイエティ大会, B-4-24, pp. 200, Sep. 2020, Japanese展示会場における不要電波の評価と磁性体による抑制基礎評価Oral presentation
- 2020年電子情報通信学会ソサイエティ大会, C-12-23, pp. 58, Sep. 2020, Japaneseオンチップ擾乱検知に向けたSAR ADC搭載ICチップの評価Oral presentation
- 2020年電子情報通信学会ソサイエティ大会, B-4-16, pp. 192, Sep. 2020, Japanese小型ドローンにおける近傍磁界の広帯域評価Invited oral presentation
- IEEE Solid-State Circuits Society, Seoul Chapter Virtual DL Seminar, Sep. 2020, English, International conferenceOn-Chip Physical Attack Protection Circuits for Hardware SecurityOral presentation
- 電子情報通信学会技術報告, vol. 120, no. 127, ICD2020-5, pp. 19-24, Aug. 2020, Japanese裏面埋設配線を有する2.5D積層ICチップの 電源インピーダンス低減効果Oral presentation
- IEEE Solid-State Circuits Society, Bangladesh Chapter Virtual DL Seminar, Jul. 2020, English, International conferenceOn-Chip Physical Attack Protection Circuits for Hardware SecurityOral presentation
- IEEE Solid-State Circuits Society, Oregon Chapter Virtual DL Seminar, Jun. 2020, English, International conferenceIC Chip and Packaging Interactions in Design for SI, PI, EMC and ESDOral presentation
- 電子情報通信学会・ハードウェアセキュリティ研究会, Jun. 2020, Japanese誘導インパルス型の瞬時自己破壊回路を利用した検知後対処に基づく物理攻撃対策Oral presentation
- 電子情報通信学会・ハードウェアセキュリティ研究会, Jun. 2020, Japanese暗号回路における基板電流検出型レーザー故障注入攻撃対策の軽量設計法Oral presentation
- 電子情報通信学会・ハードウェアセキュリティ研究会, Jun. 2020, Japanese, Co-authored internationallyICチップレベル電源雑音シミュレーョンによる暗号モジュールのサイドチャネル漏洩評価Oral presentation
- Ansys Simulation World, Jun. 2020, English, International conferenceA C-P-S Simulation Technique of Power-Noise Side Channel Leakage in Cryptographic Integrated CircuitsOral presentation
- 電子情報通信学会技術報告, Mar. 2020, Japanese誘導インパルス型の瞬時自己破壊回路を利用した検知後対処に基づく物理攻撃対策
- 電子情報通信学会技術報告, Mar. 2020, Japanese, Co-authored internationallyICチップレベル電源雑音シミュレーョンによる暗号モジュールのサイドチャネル漏洩評価
- 電子情報通信学会技術報告, Mar. 2020, Japanese暗号回路における基板電流検出型レーザー故障注入攻撃対策の軽量設計法
- 2020年電子情報通信学会総合大会, Mar. 2020, Japaneseパワー半導体インバータ回路における放射ノイズの広帯域評価
- 2020年電子情報通信学会総合大会, Mar. 2020, Japaneseマイクロウェーブ展会場における不要電波の評価
- 2020年電子情報通信学会総合大会, Mar. 2020, JapaneseICチップパッケージングにおけるノイズ抑制磁性材料の導入と評価
- 33rd International Conference on VLSI Design/19th International Conference on Embedded Design (VLSIdesign 2020), Jan. 2020, English, International conferenceSide-Channel Attack Analysis and Simulation Techniques
- 電子情報通信学会・集積回路研究会, Dec. 2019, Japanese, 奄美大島, Domestic conferenceオンチップモニタを用いたチップ・チップ間ノイズ結合の評価Poster presentation
- 電子情報通信学会・集積回路研究会, Dec. 2019, Japanese, 奄美大島, Domestic conference半導体集積回路(IC)技術によるECDSAハードウェアモジュールの多重接続性能評価Poster presentation
- 電子情報通信学会技術報告, Nov. 2019, Japaneseペアリング暗号ハードウェアの相関電磁波解析に関する検討
- 電子情報通信学会技術報告, Nov. 2019, Japanese, Co-authored internationally暗号モジュールにおける電源ノイズとサイドチャネル漏洩の対策(Ⅱ)
- 電子情報通信学会技術報告, Nov. 2019, Japanese半導体チップのハードウェアトロージャンに対する物理レベルの取り組み(I)
- 電子情報通信学会技術報告, Nov. 2019, Japanese楕円曲線ディジタル署名(ECDSA)ハードウェアモジュールの動作性能評価
- エレクトロニクス実装学会/超高速・高周波エレクトロニクス実装研究会, 令和元年度第3回公開研究会論文集, Nov. 2019, Japanese半導体チップの異種パッケージングにおける電源ノイズ特性の評価
- MWE2019 Microwave Workshop Digest, Nov. 2019, Japanese, International conference電力用インバータ機器からの不要放射によるモバイル通信への干渉評価
- MWE2019 Microwave Workshop Digest, Nov. 2019, Japanese, International conferenceGHz帯に対応するノイズ抑制シートを用いたインバータ機器からの不要電波の抑制
- 第25回EMC環境フォーラム, Nov. 2019, Japanese, 東京, Domestic conferenceIoTデバイスのエミッション評価と対策Invited oral presentation
- 電子情報通信学会技術報告, Oct. 2019, JapaneseICチップパッケージング内における磁性膜による不要電波抑制技術及び無線通信品質の向上
- 26th IEEE Electronic Design Process Symposium (EDPS 2019), Oct. 2019, English, Milpitas, International conferenceSide Channel Attacks (Invited)[Invited]Invited oral presentation
- Keysight Design Forum 2019, Oct. 2019, Japanese, 東京, Domestic conference不要電波干渉のEMC評価とシステムシミュレーションOral presentation
- 2019年電子情報通信学会ソサイエティ大会, Sep. 2019, JapaneseIC チップレベル消費電流シミュレーションによる 暗号モジュールのサイドチャネル漏洩評価
- 2019年電子情報通信学会ソサイエティ大会, Sep. 2019, JapaneseディジタルIC チップにおける不要ノイズ低減対策のオンチップ及びオンボード評価
- エレクトロニクス実装学会第29回マイクロエレクトロニクスシンポジウム(MES), Sep. 2019, Japanese3次元集積回路の電源品質改善のための裏面埋設配線の形成プロセス
- 電子情報通信学会技術報告, Aug. 2019, Japanese磁性体を利用したディジタルICチップノイズ対策手法の評価
- The 14th Asia Joint Conference on Information Security (AsiaJCIS 2019), Aug. 2019, English, 神戸, International conferenceDeployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security[Invited]Invited oral presentation
- 電子情報通信学会技術報告, Jul. 2019, JapaneseICチップレベル消費電流シミュレーションによる暗号モジュールのサイドチャネル漏洩評価
- 電子情報通信学会技術報告, Jul. 2019, Japanese, Co-authored internationally乗法的オフセットに基づく高効率AESハードウェアアーキテクチャの設計
- 電子情報通信学会技術報告, Jul. 2019, Japaneseセンサデバイスの非理想特性を利用した固有性抽出法
- 電子情報技術産業協会(JEITA) 2019年度先端電子材料・デバイス技術フォーラム, Jul. 2019, Japanese, 東京, Domestic conferenceハードウェアトロイとその対策の技術動向Oral presentation
- 2019 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI 2019), Jul. 2019, English, New Orleans, International conferencePower Noise Simulation of IC Chips for Hardware SecurityOral presentation
- Ansys Workshop at DAC 2019, Jun. 2019, English, Las Vegas, International conferenceC-P-S Simulation Techniques for Safety and SecurityOral presentation
- IEEE Diversity Luncheon at VLSI Symposium, Jun. 2019, English, 京都, International conferenceDiversity in IC labs.Oral presentation
- DSD 2018, May 2019, English, Co-authored internationallyAnalysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology[Invited]
- LSIとシステムのワークショップ2019, May 2019, Japanese, 東京, Domestic conference暗号モジュールにおける電源ノイズとサイドチャネル漏洩の対策設計と評価法の検討Oral presentation
- LSIとシステムのワークショップ2019, May 2019, Japanese, 東京, Domestic conferenceICチップの電源ノイズ特性に着目したパッケージング構造の評価Oral presentation
- LSIとシステムのワークショップ2019, May 2019, Japanese, 東京, Domestic conferenceインバータ電源装置における不要電波の広帯域測定とノイズ低減手法の評価Oral presentation
- The 5th France-Japan Cybersecurity Workshop, May 2019, English, 京都, International conferenceDeployment of EMC-Compliant IC Chip Techniques in Design for Hardware SecurityOral presentation
- The 2nd Croatia - Japan Electromagnetic Compatibility Workshop (CJEMC 2019), May 2019, English, 仙台, International conferenceUndesired Radio Waves of IoT Devices: Evaluation and Countermeasures (Invited)[Invited]Invited oral presentation
- ANSYS Webinar, Apr. 2019, English, Domestic conferenceLeveraging Chip Power Models for System-Level EMC Simulation of Automotive IcsOral presentation
- 電子情報通信学会技術報告, Mar. 2019, JapanesePRINCEファミリ暗号プロセッサの超軽量実装
- 電子情報通信学会技術報告, Mar. 2019, Japanese無線カオス発振型チップ・パッケージ・ボード相互作用PUFの統合回路設計手法とその評価
- 電子情報通信学会技術報告, Mar. 2019, Japaneseインバータ電源装置における不要電波の高感度測定と無線通信への干渉の評価
- 2019年電子情報通信学会総合大会, Mar. 2019, Japaneseインバータ電源装置近傍における不要電波と移動通信への干渉評価
- 電子情報通信学会技術報告, Mar. 2019, JapaneseオンチップLC発振器の電磁ノイズ注入同期現象の測定とその応用
- 2019年電子情報通信学会総合大会, Mar. 2019, Japaneseオンチップ電源回路によるサイドチャネル漏洩抑制効果の解析
- 2019年電子情報通信学会総合大会, Mar. 2019, JapaneseセンサーMCUのAD変換器を悪用したアナログ情報漏洩・改竄攻撃
- 電子情報通信学会技術報告, Mar. 2019, Japanese楕円曲線デジタル署名アルゴリズムのASICチップ実装と評価
- 2019年暗号と情報セキュリティシンポジウム(SCIS2019), Jan. 2019, Japaneseミリ波レーダの環境擾乱応答評価システムの軽量実装と精度解析
- 2019年暗号と情報セキュリティシンポジウム(SCIS2019), Jan. 2019, Japanese, Co-authored internationally低遅延暗号における中間ラウンドからのサイドチャネル漏えいとそのRSMに基づく効率的な対策
- VCCI協会技術シンポジウム, Jan. 2019, Japanese, 東京, Domestic conferenceIoTデバイスにおける不要電波の評価と対策Keynote oral presentation
- ICD研究会, Dec. 2018, Japaneseオンチップモニタを用いた暗号モジュールにおけるサイドチャネル漏洩の評価
- 電子情報通信学会技術報告, Dec. 2018, JapaneseデジタルICチップの電源ノイズ特性におけるパッケージング実装形態依存性の解析
- IEICE Techinical Report EMCJ2018, Nov. 2018, EnglishElectromagnetic Radiation by IC Chip and Evaluation of Mobile Communication Interference
- 電子情報通信学会学術報告, Oct. 2018, Japanese暗号モジュールにおける電源ノイズとサイドチャネル漏洩の対策(Ⅰ)
- 電子情報通信学会ソサイエティ大会, Sep. 2018, JapaneseICチップによる電磁輻射と移動通信干渉の評価
- 電子情報通信学会ソサイエティ大会, Sep. 2018, JapaneseICチップによる電磁輻射のパッケージング依存性
- 電気学会電子回路研究会, Sep. 2018, JapaneseSOI-BCDプロセスにおける支持基板伝播ノイズ解析技術の検討
- 電子情報通信学会ソサイエティ大会, Sep. 2018, Japaneseノイズ抑制シートによるインバータ機器の不要電波抑制効果
- 電子情報通信学会ソサイエティ大会, Sep. 2018, Japanese無線結合とカオス発振を利用したチップ・パッケージ・ボード相互作用PUFの実験と評価
- ECE Seminar, Sep. 2018, English, Singapore, International conferenceDeployment of EMC-Compliant IC Chip Techniques in Design for Hardware SecurityInvited oral presentation
- 電子情報通信学会学術報告, Aug. 2018, JapaneseデジタルICチップにおける電源ノイズの評価及び解析
- DAシンポジウム2018論文集, Aug. 2018, Japaneseレーザー故障注入攻撃対策を備えた暗号ICの設計手法
- IoTセキュリティ・フォーラム, Aug. 2018, Japanese, 東京, Domestic conferenceハードウェアセキュリティを担うアナログ技術Invited oral presentation
- The 1st Croatia-Japan EMC Workshop, May 2018, English, Zagreb, International conferenceToward EMC Compliant Design of IC Chips in Automotive ApplicationsInvited oral presentation
- 電子情報通信学会学術報告, Apr. 2018, JapanesePhysical-Cyber境界におけるアナログ計測セキュリティ技術
- 電子情報通信学会学術報告, Apr. 2018, Japanese基板電流センサと電源瞬断回路を利用した小面積レーザーフォールト注入攻撃対策
- 計測セキュリティフォーラム2018, Apr. 2018, Japanese, 東京, Domestic conferenceアナログ計測セキュリティ技術 -センサデータ漏洩を防ぐセキュアAD変換器Poster presentation
- ハードウェアセキュリティ研究会, Mar. 2018, Japanese, Domestic conferenceレーザーフォールト攻撃対策である電源遮断回路実装時のサイドチャネル耐性評価Oral presentation
- 電子情報通信学会総合大会, Mar. 2018, Japanese楕円曲線署名の小規模実装に対する耐タンパー性評価
- 電子情報通信学会総合大会, Mar. 2018, Japanese逐次比較型AD変換器に対するサイドチャネル攻撃とその対策
- 電子情報通信学会総合大会, Mar. 2018, Japanese3kW級WPT用GaNインバータ電源装置による不要電波の無線通信品質への影響評価
- ハードウェアセキュリティ研究会, Mar. 2018, Japanese, Domestic conferenceミリ波レーダの環境擾乱応答の評価システムのハードウェア実装Oral presentation
- COSIC Seminar, Mar. 2018, English, International conferenceChallenges: Deployment of EMC-Compliant IC Chip Techniques in Design for Hardware SecurityPublic discourse
- 2018年暗号と情報セキュリティシンポジウム(SCIS2018), Jan. 2018, JapaneseFMCWレーダにおけるチャープ信号のランダム化
- 2018年暗号と情報セキュリティシンポジウム(SCIS2018), Jan. 2018, Japaneseハードウェアトロ―ジャン検出に向けたIC周辺配線のインピーダンス計測手法
- 2018年暗号と情報セキュリティシンポジウム(SCIS2018), Jan. 2018, Japaneseフォルト検出センサを悪用した非侵襲プロービング攻撃
- 2018年暗号と情報セキュリティシンポジウム(SCIS2018), Jan. 2018, Japaneseミリ波レーダの環境擾乱応答の評価システムの構築
- 2018年暗号と情報セキュリティシンポジウム(SCIS2018), Jan. 2018, Japanese電荷再配分型SAR-ADCの変換基準電圧入力を悪用した情報改竄攻撃
- 電子情報通信学会技術報告, Dec. 2017, Japaneseカオス発振を利用したチップ・パッケージ・ボードインタラクティブPUF
- ハードウェアセキュリティフォーラム2017, Dec. 2017, Japanese, Domestic conferenceチップ・パッケージ・ボード非接触インターラクションとカオス発振を利用したPUFPoster presentation
- ハードウェアセキュリティフォーラム2017, Dec. 2017, Japanese, Domestic conferenceインピーダンス計測に基づくICの周辺に実装されたHT検出手法の検討Poster presentation
- ハードウェアセキュリティフォーラム2017, Dec. 2017, Japanese, Domestic conferenceICチップのハードウェア・トロージャンと対策の技術動向Invited oral presentation
- MIITEC Advanced Testing Technology Seminar, Dec. 2017, English, International conference3D Design for Diagnosis and Characterization with In-Place Waveform Capturing (Invited)Public discourse
- The 16th International Conference on Computers, Communications, and Systems (ICCCS 2017), Nov. 2017, EnglishLaser fault injection attack countermeasure by abnormal substrate potential bounce monitoring
- 電子情報通信学会技術報告, Nov. 2017, Chinese, Co-authored internationally車載ICチップにおけるEMS特性の高精度モデリングおよびシミュレーション手法
- 電子情報通信学会技術報告, Oct. 2017, Japaneseディジタル回路における不要電波:移動通信に影響する高次高調波の評価
- 2017 IEEE 12th International Conference on ASIC (ASICON 2017), Oct. 2017, English, International conferenceProtecting Cryptographic Integrated Circuits with Side-Channel InformationPublic discourse
- ANSYS Day 2017, Oct. 2017, Japanese, Domestic conferenceICチップレベルのEMCシミュレーションPublic discourse
- ANSYS Day 2017, Oct. 2017, Japanese, Domestic conferenceEMI性能の獲得に向けたICチップの電源ノイズシミュレーションPoster presentation
- 電子情報通信学会ソサイエティ大会, Sep. 2017, Japaneseインバータ機器から放射される不要電波強度の電界強度換算
- 電子情報通信学会ソサイエティ大会, Sep. 2017, Japaneseディジタル回路の高次高調波ノイズによる移動通信への影響の評価
- ハードウエアセキュリティ研究会, Sep. 2017, Japanese, Domestic conference高密度半導体永久ストレージの研究Invited oral presentation
- 電気学会電子回路研究会, Aug. 2017, JapaneseICチップのEMC性能改善に向けた電源ノイズシミュレーション手法
- ACM IEEE Design Automation Conference (DAC 2017), Jun. 2017, English, International conference, Co-authored internationallySimulation Techniques for EMC compliant Design of Automotive IC Chips and ModulesPoster presentation
- ハードウェアセキュリティ研究会, Jun. 2017, Japanese, Domestic conferencePRINCE暗号プロセッサの超軽量実装Oral presentation
- LSIとシステムのワークショップ2017, May 2017, Japanese, Domestic conference二段階遷移型インバータを利用した500MHz -52.5dB-THD電圧時間変換回路Poster presentation
- LSIとシステムのワークショップ2017, May 2017, Japanese, Domestic conferenceEMI性能の獲得に向けたICチップの電源ノイズシミュレーションPoster presentation
- 電子情報通信学会技術報告 ICD2017, Apr. 2017, Japanese(招待講演)ナノドット型恒久メモリーの研究[Invited]
- 電子情報通信学会総合大会, Mar. 2017, Japaneseディジタル回路における不要電波:高次高調波の評価
- 電子情報通信学会総合大会, Mar. 2017, Japanese暗号モジュール搭載VLSIチップの電源ノイズシミュレーション
- 電子情報通信学会総合大会, Mar. 2017, Japanese基板電流検知回路を用いたレーザーフォールト注入攻撃対策のオーバヘッド推定
- 電子情報通信学会総合大会, Mar. 2017, Japanese近接電磁波解析攻撃センサの高感度化手法の提案とその評価
- 電子情報通信学会総合大会, Mar. 2017, Japanese複合磁性ペーストを用いたノイズ抑制体の実装方法
- IEEE SSCS Kansai Chapter Technical Seminar, Feb. 2017, Japanese, Domestic conferenceA Permanent Digital Archive System Based on 4F^2 X-Point Multi-Layer Metal Nano-Dot StructureInvited oral presentation
- 電子情報通信学会技術報告, Jan. 2017, Japaneseインバータ機器の近傍における携帯電話帯域の不要電波の測定
- 2017年暗号と情報セキュリティシンポジウム(SCIS2017), Jan. 2017, Japaneseミリ波レーダのチャープ信号のランダム化
- 2017年暗号と情報セキュリティシンポジウム(SCIS2017), Jan. 2017, Japaneseミリ波レーダの環境擾乱応答の評価及び解析
- 2017年暗号と情報セキュリティシンポジウム(SCIS2017), Jan. 2017, Japanese近接電磁波解析攻撃に対する高感度プローブセンサの設計と検出性能の解析
- JEITA ハードウェアセキュリティ技術分科会, 2017, Japanese, Domestic conferenceハードウェアセキュリティ:トロイと対策の技術動向Invited oral presentation
- 電子情報通信学会技術報告, Nov. 2016, JapaneseTSVを用いた三次元実装LSIの電源配線におけるEMI特性
- Proc. IEEE Intl. SoC Design Conference (ISOCC 2016), Oct. 2016, EnglishHardware Security of Semiconductor IC Chips
- 電気学会電子・情報・システム部門大会, Sep. 2016, JapaneseIoT時代に対応する電子回路教育の舵取りとは?
- 電子情報通信学会ソサイエティ大会, Sep. 2016, JapaneseFPGA実装した暗号コアからの情報漏洩量と放射電磁ノイズ量の相関評価
- 電子情報通信学会ソサイエティ大会, Sep. 2016, JapaneseICチップにおける電源ノイズのオンチップ測定及びオンボード測定
- 電子情報通信学会ソサイエティ大会, Sep. 2016, Japaneseインバータ機器から発射される携帯電話帯域の不要電波の測定
- 電子情報通信学会ソサイエティ大会, Sep. 2016, Japaneseインバータ機器の不要電磁波と無線通信
- 日本磁気学会学術講演会, Sep. 2016, Japaneseパターン化した磁性薄膜による集積化デジタルノイズ抑制体
- 電子情報通信学会ソサイエティ大会, Sep. 2016, Japanese, Domestic conference基板電位変動モニタリングによるレーザーフォールト注入攻撃対策Oral presentation
- International Conference of Asian Union of Magnetics Societies (ICAUMS 2016), Aug. 2016, EnglishOn-chip Magnetic Thin-Film Noise Suppressor to Countermeasure Digital Noise from Switching Power Electronic Equipment (invited)
- IEEE International Conference on Microwave Magnetics (ICMM2016), Jun. 2016, English, IEEEPatterned Magnetic Thin-film Digital Noise Suppressor for Future Telecommunication Systems RF IC
- 電気学会電磁環境研究会, Mar. 2016, JapaneseICチップにおけるオンチップノイズと電磁ノイズの観測と評価
- 電子情報通信学会技術報告, Mar. 2016, Japanese三次元積層IC における電源供給特性のインスタック診断手法
- シリコンアナログRF研究会, Mar. 2016, Japanese, Domestic conference高解像度・高速タッチセンサのノイズ耐性評価とノイズ低減手法の検討Oral presentation
- 電子情報通信学会・2016年暗号と情報セキュリティシンポジウム, Jan. 2016, Japaneseレーザーフォールト注入時のIC基板電位変動のオンチップ測定
- 電子情報通信学会技術報告, Jan. 2016, Japanese印刷によるTSV形成技術の開発[Invited]
- 電子情報通信学会・2016年暗号と情報セキュリティシンポジウム, Jan. 2016, Japanese並列化RNSアーキテクチャによる高速ペアリング実装に関する検討
- LSIとシステムのワークショップ2016, 2016, Japanese, Domestic conference基板電位変動モニタリングによるレーザーフォールト注入攻撃対策Poster presentation
- ハードウェアセキュリティフォーラム2016, 2016, Japanese, Domestic conferenceチップ・パッケージ・ボードレベルの物理攻撃対策回路技術Invited oral presentation
- Keysight 5G AKIBA Summit, 2016, Japanese, Domestic conferenceSystemVueのHILS応用による物理層ノイズの評価と解析(招待講演)[Invited]Public discourse
- The 7th Asia-Pacific International Symposium on Electromagnetic Compatibility & Signal Integrity and Technical Exhibition (APEMC 2016), 2016, English, International conferenceSiP Packaging-Compatible Magnetic Thin-Film Noise Suppressor to Countermeasure Digital Noise from Power Electronics Devices (invited)Invited oral presentation
- 第5回移動体通信(LTE)を例としたICチップレベルの自家中毒と通信性能へのインパクト, 2016, Japanese, Domestic conferenceIoT時代、混雑する無線機器の内外環境における通信品質向上のための課題と開発の基礎―干渉、ノイズ、EMC等の品質劣化要因の理解と対策の勘所―Public discourse
- エネルギーインテグリティーシステム研究センターシンポジウム, 2016, Japanese, Domestic conferenceIoT時代に向けた不要電波対策技術Invited oral presentation
- 2016 IEEE Metro Area Workshop in Kansai, 2016, Japanese, Domestic conferenceICチップのハードウェアセキュリティ:真正性の確保と攻撃への対策Invited oral presentation
- LSIとシステムのワークショップ2016, 2016, Japanese, Domestic conferenceFPGA実装した暗号コアからの放射電磁波ノイズ量と情報漏洩量の相関評価Poster presentation
- 2016 IEEE International Solid-State Circuits Conference, Jan. 2016, English, International conferenceNoise Simulation in Mixed-Signal SoCsPublic discourse
- 電子情報通信学会技術報告, Dec. 2015, Japanese適応調律型電源共振抑制フィルタのEMS評価
- 電気学会電子回路研究会, Dec. 2015, Japanese半導体モジュールにおける電源供給特性のチューニング手法
- 電子情報通信学会ソサイエティ大会, Sep. 2015, JapaneseVLSIシステムのノイズ問題に関する先駆的貢献
- 電子情報通信学会ソサイエティ大会, Sep. 2015, Japaneseサイドチャネル近傍電磁波解析攻撃センサの提案とセキュリティ耐性評価
- 電子情報通信学会ソサイエティ大会, Sep. 2015, Japanese実装環境に適応する電源共振ノイズ抑制フィルタの提案と評価
- 電子情報通信学会ソサイエティ大会, Sep. 2015, Japanese電源電流イコライザの電力オーバーヘッド低減手法の提案と実証
- Proc. ICDV 2015/VJMW2015, Aug. 2015, EnglishAdaptive Suppression of Power Delivery Network Resonance with Chip-Package-Board Interaction[Invited]
- Proc. 2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT 2015), Aug. 2015, EnglishOn-Chip and On-Board RF Noise Coupling and Impacts on LTE Wireless Communication Performance[Invited]
- 日本情報技術センター, Jul. 2015, Japanese, Domestic conferenceIoT時代、混雑する無線機器の内外環境における通信品質向上のための課題と開発の基礎~干渉、ノイズ、EMC等の品質劣化要因の理解と対策の勘所~第5回移動体通信(LTE)を例としたICチップレベルの自家中毒と通信性能へのインパクトPublic discourse
- International Technical Conference on Circuits Systems /Computers and Communcations 2015 (ITC-CSCC 2015), Jul. 2015, English, International conferenceIC Chips to be Dependable, Secure, and RobustKeynote oral presentation
- International Symposium on IoT Enabling Chips, Jun. 2015, English, International conferenceSecuring Cryptographic Engines -- Circuit Techniques against EM AttacksInvited oral presentation
- Design for three dimensional integration (D43D), Jun. 2015, English, International conferenceDiagnosis, Protection, and Configurability of I/O Circuits for 3D Chip StackingInvited oral presentation
- LSIとシステムのワークショップ2015, May 2015, Japanese, Domestic conference製品テストにおける適応型電源共振ノイズ抑制フィルタPoster presentation
- LSIとシステムのワークショップ2015, May 2015, Japanese, Domestic conference暗号処理回路への近傍電磁波解析攻撃を検知する完全デジタル発振器型センサPoster presentation
- CESCA, May 2015, English, International conferenceIC Chips to Be Dependable, Secure, and RobustKeynote oral presentation
- IEICE technical report. Electromagnetic compatibility, Mar. 2015, Japanese, The Institute of Electronics, Information and Communication Engineers, Digital circuits in a mobile communication IC Chip become more enormous for LTE class design. This potentially causes the undesigned noise coupling in the receiver circuit and leads to the deterioration of overall system communication quality. In this study, noise reduction techniques have been explored. A prototype chip having a digital noise generator, LTE-class wireless receiver circuit and on-chip voltage waveform monitor, EMI tester, and the system level simulator for measuring communication quality are prepared for this study. We measured and analyzed the effect of three terminal capacitor on the chip and board level noise coupling. As a result, it exhibits a noise reduction effect of 5dB at the system level in the 2GHz band used in LTE. This will improve communication quality.Effects of On-Board Noise Remedy at IC Chip Level Noise Reduction : A Case Study in LTE-Class IC Chip
- ST Microelectronics Internal Seminar, Mar. 2015, English, ST Microelectronics, Crolles, International conferenceIn-Place Diagnosis of Undesired Power Domain Problems in IC Chips and StacksPublic discourse
- DATE 2015 Workshop on 3D Integration, Mar. 2015, English, IEEE, Grenoble, International conference, Co-authored internationallyBroadband Metal-Insulator-Metal Capacitors on Silicon Interposer for Low Impedance Power Distribution NetworkOral presentation
- ICシステムセキュリティ協会, Feb. 2015, Japanese, 神田, Domestic conferenceICチップの真正性の確保と対策 ~ハードウェアセキュリティの根源的課題に向き合う~Public discourse
- ANSYS Electronics Simulation EXPO 2014, Feb. 2015, English, Ansys, San Jose, International conferenceIC Chip Immunity Measurements and AnalysisPublic discourse
- 2015年暗号と情報セキュリティシンポジウム講演論文集, Jan. 2015, Japanese, 電子情報通信学会電磁波攻撃センサの設計と実証
- ACM and IEEE 20th Asia and South Pacific Design Automation Conference, Jan. 2015, English, ACM and IEEE, 幕張, International conferenceSide Channel Leakage in Cryptographic Modules: Introduction to Physical Origins and Attack ModelsPublic discourse
- ECT-14-107, Dec. 2014, Japanese, 電気学会電子回路研究会VLSI チップにおける電源雑音の評価とモデリング[Invited]
- ICD2014-67, Nov. 2014, Japanese, 電子情報通信学会サイドチャネル情報漏洩対策のための集積回路技術
- IEICE 2014 Asia-Pacific Microwave Conference, Nov. 2014, English, 電子情報通信学会, 仙台, Domestic conferenceIC Chip Level Low Noise Technology for High Speed and High Quality Telecommunication SystemsOral presentation
- 2014年度第4回TSV応用研究会, Oct. 2014, Japanese, 四谷, Domestic conference貫通シリコンビアとアクティブインタポーザを用いた4096 bit幅100 Gbyte/秒ワイドI/Oの設計と診断Oral presentation
- ANSYS Electronics Simulation EXPO 2014, Oct. 2014, Japanese, ANSYS, 東京, Domestic conferenceRF-ICチップにおける基板結合ノイズの解析と実測Nominated symposium
- Fifth IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Oct. 2014, English, IEEE, Seattle, International conferenceCDM ESD Testing of a 3D TSV Stacked IC ChipOral presentation
- 電気学会電子・情報・システム部門大会, Sep. 2014, Japanese, 電気学会, 島根, Domestic conferenceバンドギャップ基準電圧回路のオンチップモニタを使ったノイズ解析Oral presentation
- 電気学会電子・情報・システム部門大会, Sep. 2014, Japanese, 電気学会, 島根, Domestic conferenceVLSIチップにおける電源雑音の評価とモデリングOral presentation
- ICD2014-20, Jul. 2014, Japanese, 電子情報通信学会二段階デュアルモード容量スキャン方式を用いた1mm-Pitch 80x80-Channel 322Hz-Frame-Rateタッチセンサの設計
- IEICE technical report. Electromagnetic compatibility, Jun. 2014, Japanese, The Institute of Electronics, Information and Communication Engineers, The integrated simulation was constructed using the full wave 3-dimensional electromagnetic field simulator and the circuit analysis in order to analyze the mechanism of the on-chip conductive and the inductive noise coupling in LTE-class RFIC. From the constructed simulation, the main EM noise coupling on the chip revealed as the conductive and the inductive noise coupling. Furthermore, the noise suppression mechanism using the magnetic thin film was discussed.Analysis of Conductive and Inductive Noise Couplings on TEG Chip with Magnetic Thin Film
- EMCJ2014-10, Jun. 2014, Japanese, 電子情報通信学会, Co-authored internationallyCMOS暗号回路におけるシリコン基板からのサイドチャネル漏洩
- 第57回STARCアドバンストセミナー, Jun. 2014, Japanese, 半導体理工学研究センター, 横浜, Domestic conference半導体チップにおける電源ノイズとEMCの実際Public discourse
- JIEP最先端実装技術シンポジウム, Jun. 2014, Japanese, エレクトロニクス実装学会, 東京, Domestic conferenceICチップレベルのサイドチャネル情報漏洩の計測とシミュレーションPublic discourse
- LSIとシステムのワークショップ2014 ポスターセッション, May 2014, Japanese, 小倉, Domestic conference動作環境変動に応じて動的に動作マージンを拡大する自律制御キャッシュPoster presentation
- 電子情報通信学会集積回路研究会・LSIとシステムのワークショップ2014, May 2014, Japanese, 電子情報通信学会集積回路研究会, 北九州, Domestic conference基板ノイズによるLTE通信品質への影響のシステムレベル評価Poster presentation
- 2014 18th IEEE Workshop on Signal and Power Integrity, May 2014, English, IEEE, Ghent, International conferencePower Noise Awareness in Design and Diagnosis of VLSI SystemsInvited oral presentation
- 2014 International Symposium on Electromagnetic Compatibility, Tokyo, May 2014, English, IEEJ, IEICE, IEEE, Tokyo, International conferenceMeasurements and Simulation of RF Noise Coupling and Its Impacts on LTE Wireless Communication Performance[Invited]Nominated symposium
- 暗号と情報セキュリティシンポジウム, Jan. 2014, Co-authored internationallyチップ内外での電源電圧取得によるサイドチャネル漏洩情報の一考察
- 2013 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), Dec. 2013, English, IEEE, Nara, International conferencePower Noise Awareness in Design and Diagnosis of VLSI SystemsKeynote oral presentation
- 2013 IEEE International Symposium on Electromagnetic Compatibility (EMC 2013), Sep. 2013, English, IEEE, Denver, International conferencePower-Noise Measurements and Simulation Techniques for Side-Channel Analysis[Invited]Nominated symposium
- Fourth IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST), Sep. 2013, English, IEEE, Anaheim, International conferenceIn-Place Signal and Power Noise Waveform Capturing within 3D Chip StackingOral presentation
- 2013 IEEE International Test Conference (ITC 2013), Sep. 2013, English, IEEE, Anaheim, International conferenceIn-Place Signal and Power Noise Waveform Capturing within 3D Chip StackingPoster presentation
- Design Automation Conference 2013 (DAC 2013), Jun. 2013, English, ACM/IEEE, Austin, International conferenceDesign Strategies using 2D Toolsets for 3D TSV Chip Stacks featuring 4096b Wide I/O at 100GB/sPoster presentation
- シリコンアナログRF研究会, Mar. 2013, Japanese, 電子情報通信学会, Chuo University, Domestic conference(招待講演)VLSIチップ-パッケージ-ボードを統合した電源系ノイズの実測と解析[Invited]Invited oral presentation
- 第27回エレクトロニクス実装学会春季講演大会, Mar. 2013, Japanese, エレクトロニクス実装学会, Tohoku University, Domestic conference動的電源電圧変動に対するSRAM コアの動作不良感度Oral presentation
- 電子情報通信学会総合大会, Mar. 2013, Japanese, 電子情報通信学会, Gifu University, Domestic conferenceバッテリー駆動型オンチップ電源雑音モニタシステムの構築Oral presentation
- 電子情報通信学会総合大会, Mar. 2013, Japanese, 電子情報通信学会, Gifu University, Domestic conferenceオンチップ波形モニタ回路における可変スロープ・可変オフセット電圧発生回路の改良Oral presentation
- 第27回エレクトロニクス実装学会春季講演大会, Mar. 2013, Japanese, エレクトロニクス実装学会, Tohoku University, Domestic conferenceTEG チップ上に集積化した磁性薄膜によるLTE 帯域内ノイズ抑制効果Oral presentation
- 電子情報通信学会総合大会, Mar. 2013, Japanese, 電子情報通信学会, Gifu University, Domestic conferenceSRAMのAC電源変動に対する不良応答と素子ばらつきの影響Oral presentation
- 電子情報通信学会総合大会, Mar. 2013, Japanese, 電子情報通信学会, Gifu University, Domestic conferenceRF基板結合評価のためのマルチトーンノイズ発生回路Oral presentation
- 2013年暗号と情報セキュリティシンポジウム, Jan. 2013, Japanese, 電子情報通信学会容量充電モデルを用いたシミュレーションによるサイドチャネル情報漏洩探索手法
- 2013年暗号と情報セキュリティシンポジウム, Jan. 2013, Japanese, 電子情報通信学会容量充電モデルを用いたシミュレーションによる相関電力解析の考察
- 電子情報通信学会技術報告, Nov. 2012, Japanese, 電子情報通信学会デジタルLSIにおけるLSIチップ・パッケージ・ボードを統合した電源雑音協調評価
- Electronic Design and Solution Fair 2012, Nov. 2012, Japanese, 電子情報技術産業協会, 横浜市, Domestic conferenceLPB統合ノイズ解析~テストチップにおけるオンチップとオンボードのノイズを例題として~【特別展示】LPBゾーン・IBISゾーンにおける講演及び出展Invited oral presentation
- The 7th International Workshop on Security (IWSEC2012), Nov. 2012, English, 電子情報通信学会, Kyushu University, Domestic conferenceA Simulation Methodology Aearching Side-Channel Leakage Using Capacitor Charging ModelPoster presentation
- 第29回「センサ・マイクロマシンと応用システム」シンポジウム, Oct. 2012, Japanese, 電気学会, 北九州市, Domestic conferenceノイズとLSI回路設計技術Invited oral presentation
- 電子情報通信学会技術報告, Aug. 2012, Japanese, 電子情報通信学会, Co-authored internationally三次元積層LSIチップにおける基板ノイズの層間評価
- LSIとシステムのワークショップ2012, May 2012, Japanese, 電子情報通信学会, 北九州市, Domestic conference移動体通信RF-LSIにおける基板雑音の影響評価手法の提案Oral presentation
- LSIとシステムのワークショップ2012, May 2012, Japanese, 電子情報通信学会, 北九州市, Domestic conferenceLSIとシステムのノイズ問題(招待講演)Invited oral presentation
- LSIとシステムのワークショップ2012, May 2012, Japanese, 電子情報通信学会, 北九州市, Domestic conferenceLSIチップ・パッケージ・ボード(LPB)統合電源インピーダンスを考慮した電源雑音の測定と解析Oral presentation
- 電子情報通信学会技術報告, Apr. 2012, Japanese, 電子情報通信学会デジタルLSIの電源ノイズに関するオンボードおよびオンチップ測定の統合評価
- 電子情報通信学会総合大会, Mar. 2012, Japanese, 電子情報通信学会, 岡山市, Domestic conference差動増幅回路における基板雑音感度の評価Oral presentation
- 電子情報通信学会総合大会, Mar. 2012, Japanese, 電子情報通信学会, 岡山市, Domestic conferenceオンチップ電源ノイズ離散化手法とRF 直接電力注入によるSRAMのイミュニティ評価への応用Oral presentation
- Workshop on Synthesis and System Integration of Mixed Information Technologies, Mar. 2012, English, IEEE, 別府市, International conferenceVariation of Substrate Sensitivity in Differential Pair TransistorsPoster presentation
- 電子情報通信学会・電子デバイス研究会特別ワークショップ, Mar. 2012, Japanese, 電子情報通信学会, 東京都, Domestic conferenceCMOSデジタル回路における動的ノイズInvited oral presentation
- 電子情報通信学会・2012年暗号と情報セキュリティシンポジウム, Jan. 2012, Japanese容量充電モデルを用いた高速なサイドチャネル攻撃評価手法
- 電気学会・高度化アナログ電子回路の高効率化設計技術調査専門委員会, Jan. 2012, Japanese, 電気学会, 東京都, Domestic conferenceVLSIチップの電源ノイズ ~シリコン基板から電磁環境まで~Invited oral presentation
- 電子情報通信学会技術報告, Dec. 2011, Japanese(招待講演)VLSIチップの電源ノイズ~シリコン基板から電磁環境まで~[Invited]
- IEEE EMC Society Sendai Chapter・東北大学EMC仙台ゼミナール共催学生発表会, Dec. 2011, Japanese, IEEE, 仙台市, Domestic conferenceVLSIチップの電源ノイズとEMCInvited oral presentation
- 電子情報通信学会技術報告, Nov. 2011, Japaneseオンチップ診断機構とDPIを用いたSRAMコアのイミュニティ評価
- 電子情報通信学会技術報告, Nov. 2011, JapaneseデジタルLSIにおけるオンチップ・オンボード電源雑音の評価・協調解析手法
- IEEE Workshop on Variability Modeling and Characterization, Nov. 2011, English, IEEE, San Jose, USA, International conferenceVariation of Substrate Sensitivity in Differential Pair TransistorsPoster presentation
- 電子情報通信学会ソサイエティ大会, Sep. 2011, Japanese, 電子情報通信学会, 札幌市, Domestic conferenceデジタルLSIのオンボード電流ノイズおよびPDNインピーダンスの測定評価Oral presentation
- 電子情報通信学会ソサイエティ大会, Sep. 2011, Japanese, 電子情報通信学会, 札幌市, Domestic conferenceデジタルLSIのオンチップ電源ノイズ測定とPDNインピーダンスモデリングOral presentation
- CHES2011, Sep. 2011, English, IACR, 奈良市, International conferenceA Fast Power Current Analysis Methodology using Capacitor Charging Model for Side Channel Attack EvaluationPoster presentation
- 学振第165委員会 VLSI夏の学校, Aug. 2011, English, 学振第165委員会, 豊中市, Domestic conferenceVLSIの電源ノイズ・基板ノイズと測定技術Invited oral presentation
- 電子情報通信学会技術報告, Jul. 2011, Japanese(招待講演)LTE級携帯端末におけるRFICの受信部の低ノイズ化技術―近傍磁界ノイズ計測・対策の立場から―[Invited]
- 電子情報通信学会技術報告, Jul. 2011, Japaneseアナログ基本回路における基板雑音感度の解析法
- 電子情報通信学会技術報告, Jul. 2011, Japaneseオンチップ環境擾乱に対するアナログIPコアの診断テストベンチの提案
- ICDシリコンアナログRF研究会, May 2011, Japanese, 電子情報通信学会, 北九州市, Domestic conference高周波LSIにおける基板結合の評価とモデリングOral presentation
- 電子情報通信学会 総合大会, Mar. 2011, Japanese, 電子情報通信学会, 東京都, Domestic conference差動対トランジスタにおける基板ノイズ応答のオンチップ評価と解析Oral presentation
- 電子情報通信学会 総合大会, Mar. 2011, Japanese, 電子情報通信学会, 東京都, Domestic conference高分解能オンチップモニタシステムを用いたミックストシグナルSoCの診断技術Oral presentation
- 電子情報通信学会 総合大会, Mar. 2011, Japanese, 電子情報通信学会, 東京都, Domestic conferenceCMOSデジタル回路における動的ノイズInvited oral presentation
- 電子情報通信学会技術報告, Dec. 2010, Japaneseグラウンド雑音の評価
- 電子情報通信学会技術報告, Nov. 2010, JapaneseCMOSデジタルLSIにおける電源雑音の周波数成分評価
- 電子情報通信学会技術報告, Nov. 2010, JapaneseSRAMコアにおけるオンチップ電源雑音の発生と注入の評価
- 電子情報通信学会技術報告, Nov. 2010, Japaneseアナログ基本回路の基板雑音感度に関する考察
- IEEE Workshop on Variability Modeling and Characterization, Nov. 2010, English, IEEE, San Jose, USA, International conferenceOn-chip In-situ Measurements of Vth, Signal Gain, and Substrate Sensitivity of Differential Pair TransistorsPoster presentation
- 学振第165委員会 VLSI夏の学校, Aug. 2010, Japanese, 学振第165委員会, 東京都, Domestic conferenceVLSIの電源ノイズ・基板ノイズと測定技術Invited oral presentation
- ICD in Vietnam 2010, Aug. 2010, English, 電子情報通信学会, Ho Chi Minh, Vietnam, International conferenceEvaluation of Power Noises in VLSI Circuits (Invited)Invited oral presentation
- ICD サマーワークショップ2010, Aug. 2010, Japanese, 電子情報通信学会, 廿日市市, Domestic conference2010 Symposium on VLSI Circuits OverviewInvited oral presentation
- マルチメディア,分散,協調とモバイル (DICOMO2010) シンポジウム講演論文集, Jul. 2010暗号LSIの電源ノイズシミュレーションによるサイドチャネル解析
- 電子情報通信学会技術報告, Jul. 2010, Japanese90 nm CMOS差動対トランジスタのVthとAC応答のその場評価
- 電子情報通信学会技術報告, Jul. 2010, Japaneseオンチップモニタの最簡搭載とチップ内環境の観測
- 電子情報通信学会技術報告, Jul. 2010, Japaneseオンチップモニタを用いたSoC電源供給系の診断法
- 2010最先端実装技術シンポジウム, Jun. 2010, Japanese, エレクトロニクス実装学会, 東京都, Domestic conferenceSoCのオンチップ雑音評価技術Invited oral presentation
- ICD LSIとシステムのワークショップ2010, May 2010, Japanese, 電子情報通信学会, 北九州市, Domestic conference差動増幅回路におけるVthとAC応答のその場評価技術Poster presentation
- IEEE International Solid-State Circuits Conference 2010, Feb. 2010, English, IEEE, San Francisco, International conferenceOn-Chip Power Noise Monitoring and DiagnosisInvited oral presentation
- 電子情報通信学会技術報告, Dec. 2009, Japanese(招待講演)電源雑音とプロセッサ動作エラーのオンチップ評価技術[Invited]
- 集積回路研究会若手研究会, Dec. 2009, Japanese, 電子情報通信学会, 静岡市, Domestic conferenceCMOSデジタル回路における雑音発生のモデル化と実証Poster presentation
- 集積回路研究会若手研究会, Dec. 2009, Japanese, 電子情報通信学会, 静岡市, Domestic conferenceCMOSアナログ回路における基板ノイズ応答の解析Poster presentation
- 集積回路研究会若手研究会, Dec. 2009, Japanese, 電子情報通信学会, 静岡市, Domestic conferenceCMOS-RF回路における基板結合の評価と解析Poster presentation
- 電子情報通信学会技術報告, Nov. 2009, JapaneseCMOSデジタルLSIにおける電源雑音評価のためのリファレンス回路
- 電子情報通信学会技術報告, Oct. 2009, Japanese65nmCMOSテクノロジによる6bit任意デジタル雑音エミュレータの開発
- 電子情報通信学会技術報告, Oct. 2009, Japaneseマイクロプロセッサにおける基板ノイズの評価と解析
- 電子情報通信学会技術報告, Oct. 2009, Japanese電源線を用いた135Mbps双方向チップ間通信技術
- IEEE SSCS Kansai Chapter Technical Seminar, Oct. 2009, Japanese, IEEE SSC Society Kansai Chapter, 神戸市, Domestic conferenceオンチップ・ノイズモニタ技術Invited oral presentation
- 情報処理学会関西支部大会, Sep. 2009, Japanese, 情報処理学会, 神戸市, Domestic conferenceスタンダードセルベースCMOSデジタル回路の電源雑音解析手法Oral presentation
- STARCフォーラム/シンポジウム, Aug. 2009, Japanese, 半導体理工学研究センター, 横浜市, Domestic conferenceオンチップモニタの搭載技術Poster presentation
- Design Automation Conference 2009, Jul. 2009, English, IEEE, San Francisco, International conferencePower Supply and Substrate Noise Analysis; Reference Tool Experience with Silicon ValidationOral presentation
- 2009 VLSI Circuits Short Course, Jun. 2009, English, IEEE, 京都市, International conferenceOn-Chip Power Supply Noise MeasurementsInvited oral presentation
- LSIとシステムのワークショップ2009, May 2009, Japanese, 電子情報通信学会, 北九州市, Domestic conferenceばらつきを含めたオンチップモニタ回路の性能評価Poster presentation
- 平成20年技術賞受賞記念講演, May 2009, Japanese, エレクトロニクス実装学会, 東京都, Domestic conferenceデジタルLSI電源ノイズのオンチップ観測とシミュレーション技術[Invited]Invited oral presentation
- LSIとシステムのワークショップ2009, May 2009, Japanese, 電子情報通信学会, 北九州市, Domestic conferenceチップ間電源線通信を用いたオンチップモニタの搭載容易化手法Poster presentation
- 第6回 IEEE CPMT Society Japan Chapter イブニングミーティング, May 2009, Japanese, IEEE CPMT Society Japan Chapter, 東京都, Domestic conferenceオンチップ・ノイズモニタ技術Invited oral presentation
- Design, Automation and Test in Europe 2009 (DATE), Friday Workshop on 3D Integration, Apr. 2009, English, IEEE, Nice, International conferenceOn-Chip Waveform Capturing Functionality Partitioned for 3D RealizationPoster presentation
- エレクトロニクス実装学術講演大会, Mar. 2009, Japanese, (社)エレクトロニクス実装学会, 神奈川, Domestic conference(招待講演)オンチップノイズモニタ技術とLSIの電源インテグリティ評価[Invited]Oral presentation
- 電子情報通信学会技術報告, Dec. 2008, JapaneseLSIのEMC~チップとボードを統合した電源ノイズの評価・解析手法~
- 電子情報通信学会技術報告, Dec. 2008, JapaneseデジタルLSIにおける電源ノイズと動作不良の解析手法
- 電子情報通信学会技術報告, Dec. 2008, JapaneseミックストシグナルSoCのためのオンチップモニタ構築技術
- 電子情報通信学会技術報告, Nov. 2008, Japanese容量充電モデルによるプロセッサ電源雑音解析の高速化手法
- Workshop on Test Structure Design for Variability Characterization, Nov. 2008, Japanese, IEEE, San Jose, Domestic conferencePerformance Variability of On-chip Noise Monitor CircuitsPoster presentation
- 電子情報通信学会技術報告, Oct. 2008, Japaneseオンチップ・マルチチャネルモニタにおける波形取得アルゴリズムの実装と評価
- 電子情報通信学会, Sep. 2008, Japanese, (社)電子情報通信学会, 横浜, Domestic conferenceプロセッサ動作エラー検出のための命令レベルプログラミング手法Oral presentation
- 電子情報通信学会, Sep. 2008, Japanese, (社)電子情報通信学会, 横浜, Domestic conferenceサブ100-nmデジタル回路におけるダイナミック電源雑音を考慮した信号遅延変動の評価と解析Oral presentation
- 電子情報通信学会, Sep. 2008, Japanese, (社)電子情報通信学会, 横浜, Domestic conferenceLSIチップ電源配線網の等価回路表現と評価Oral presentation
- STARCフォーラム/シンポジウム 2008, Jul. 2008, Japanese, (株)半導体理工学研究センター, 横浜, Domestic conferenceミックストシグナルSoCのためのオンチップモニタ技術Oral presentation
- STARCフォーラム/シンポジウム 2008, Jul. 2008, Japanese, (株)半導体理工学研究センター, 横浜, Domestic conferenceオンチップモニタのためのバックエンドデータ処理系の構築と波形取得性能の評価Oral presentation
- 電子情報通信学会技術報告, May 2008, Japanese(招待講演)LSIのノイズ問題:アプローチとチャレンジ
- 電子情報通信学会技術報告, Jan. 2008, Japanese(特別招待講演)オンチップモニタ技術と電源インテグリティ評価
- 電子情報通信学会技術報告, Jan. 2008, JapaneseデジタルLSIにおけるオンチップ電源雑音とオフチップ電磁雑音の統合評価
- Electronic Design and Solution Fair 2008, Jan. 2008, Japanese, 電子情報技術産業協会(JEITA), 横浜市, Domestic conferenceSoCのインテグリティ:オンチップ・モニタとノイズ解析技術Others
- Electronic Design and Solution Fair 2008, Jan. 2008, Japanese, 電子情報技術産業協会(JEITA), 横浜市, Domestic conference(基調講演)LSIを高性能化する設計技術の挑戦--インテグリティを指向する設計へInvited oral presentation
- 電子情報通信学会技術報告, Dec. 2007, Japanese携帯機器向け625Mbps/3mW/1.5V電流モード通信回路
- システム実装CAE研究会公開研究会, Dec. 2007, Japanese, エレクトロニクス実装学会(JIEP), 東京, Domestic conference(招待講演)オンチップモニタによるLSIとPCBのノイズ評価[Invited]Invited oral presentation
- 第11回システムLSIワークショップ, Nov. 2007, Japanese, 電子情報通信学会(IEICE), 北九州市, Domestic conference埋め込み型検出回路を用いたプロセッサの電源ノイズ評価Poster presentation
- 電子情報通信学会技術報告, Oct. 2007, Japanese超多重RFIDシステム設計のためのミックストシグナル・シミュレーション手法
- VDEC LSIデザイナーフォーラム2007, Sep. 2007, Japanese, 東京大学VDEC, 石狩郡, Domestic conference埋め込み型検出回路によるプロセッサの電源雑音評価Oral presentation
- STARCシンポジウム2007, Sep. 2007, Japanese, 半導体理工学研究センター(STARC), 大阪, Domestic conferenceオンチップモニタ・システムのSoC搭載設計法と評価Poster presentation
- 電子情報通信学会ソサイエティ大会, Sep. 2007, Japanese, 電子情報通信学会, 鳥取市, Domestic conferenceTS-CDMAによる超多重RFIDランスポンダ向け同期回路の検討Oral presentation
- 電子情報通信学会技術報告, Aug. 2007, JapaneseSoCの電源雑音向け微細埋め込み方連続時間雑音検出手法
- 2007最先端実装技術シンポジウム(JPCA show 2007), May 2007, Japanese, 日本電子回路工業会(JPCA), 東京, Domestic conference(招待講演)SoCのオンチップ雑音測定と評価[Invited]Invited oral presentation
- 電子情報通信学会技術報告, Mar. 2007, Japaneseサブ100nmデジタルシグナルインテグリティのためのオンチップモニタ
- 電子情報通信学会技術報告, Mar. 2007, Japanese基板クロストーク対策のためのガードリング構造の等価回路モデル化手法
- 電子情報通信学会技術報告, Jan. 2007, Japaneseダイナミック電源雑音波形を考慮したデジタル信号遅延変動解析
- 電子情報通信学会技術報告, Jan. 2007, Japaneseミックストシグナル回路における基板結合のオンチップモニタリング
- 電子情報通信学会技術報告, Dec. 2006, Japaneseオンチップマルチチャネル信号モニタによるアナログ回路動作診断
- 電子情報通信学会技術報告, Nov. 2006, Japanese高速モードと低消費電力モードを有する2線式論理回路の設計手法
- 第10回システムLSIワークショップ予稿集, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, Domestic conferenceアナログ回路のオンチップ動作診断技術Poster presentation
- 電子情報通信学会技術報告, Oct. 2006, Japanese超多重RFIDシステムの高位モデル化とバックエンド設計への応用
- VDEC LSIデザイナーフォーラム2006, Sep. 2006, Japanese, 東京大学, 高知, Domestic conferenceダイナミック電源雑音によるデジタル信号遅延変動の評価Poster presentation
- 電子情報通信学会技術報告, Jul. 2006, Japaneseオンチップマルチチャネル信号モニタを用いたチップ内部信号測定システムの構築
- IEICE Technical Report, Mar. 2006, JapaneseA Simulation Technique of Dynamic Power Supply/Ground Noise
- Siricon Analog RF Group Meeting, Feb. 2006, Japanese, シリコンアナログRF時限研究専門委員会, Yokohama city, Domestic conferenceDesign of High-Frequency Substrate Noise Detector Considering Substarate ModelOral presentation
- IEICE Technical Report, Jan. 2006, JapaneseMeasurements of Digital Signal Delay Variation Due to Dynamic Power Supply Noise
- Electronic Design and Solution Fair 2006, Jan. 2006, Japanese, (社)電子情報技術産業協会, Yokohama city, Domestic conferenceChip-Level Analysis and On-Chip Evaluation of Noise in SoCOthers
- 11th Micro-wave simulator workshop, Dec. 2005, Japanese, マイクロ波シミュレータ時限研究専門委員会, Musashino city, Domestic conferenceNoise Analysis in Mixed Analog-Digital LSIInvited oral presentation
- IEICE Technical Report, Nov. 2005, JapaneseLogic Synthesis Technique for High Speed Dynamic Logic with Asymmetric Slope Transition
- 9th System LSI Workshop, Nov. 2005, Japanese, 集積回路研究専門委員会, Kitakyushu city, Domestic conferenceSubstrate Crosstalk Analysis and RemedyPoster presentation
- IEICE Technical Report, Oct. 2005, JapaneseSubstrate-Noise and Random-Fluctuations Reduction with Self-Adjusted Forward Body Bias
- NEDO産業技術助成事業:技術シーズ懇話会, Oct. 2005, Japanese, NEDO, Kawasaki city, Domestic conferencePower-Supply/Ground Noise Reduction and Measurements for High-Performance LSIsInvited oral presentation
- STARC Symposium, Sep. 2005, Japanese, (株)半導体理工学研究センター, Osaka City, Domestic conferenceOn-Chip Diagosis for Mixed-Signal LSIPoster presentation
- DA Symposium 2005, Aug. 2005, JapaneseSoC Design Flow for Noise and On-Chip Measurements in Sub-100-nm Era (Invited Talk)[Invited]
- DA Symposium 2005, Aug. 2005, JapaneseChip-Level Substrate Noise Analysis Technique
- IEICE Technical Report, Aug. 2005, JapaneseIsolation Strategy against Substrate Coupling in CMOS Mixed-Signal/RF Circuits
- VDEC LSI Designers Forum 2005, Aug. 2005, Japanese, 東京大学大規模集積システム設計教育研究センター, Yugawara, Domestic conferenceOn-Chip Multi-Channel Monitor for Signal Measurements in LSIPoster presentation
- IEICE Technical Report, Jul. 2005, JapaneseEvaluation of Digital Crosstalk Noise to CMOS-PLL through Si Substrate
- IEICE Technical Report, Jul. 2005, JapaneseOn-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits
- IEICE Technical Report, May 2005, JapaneseSubstrate Integrity beyond 1 GHz
- Siricon Analog RF Group Meeting, May 2005, Japanese, シリコンアナログRF時限研究専門委員会, Kobe city, Domestic conferenceModulator/Demodulator Circuits for Highly Multiplexed RFID TAGsOral presentation
- 第19回エレクトロニクス実装学術講演大会, Mar. 2005, Japanese, エレクトロニクス実装学会, 東京理科大学野田キャンパス, Domestic conferenceデジタルLSIにおける電源/グラウンド雑音の評価とモデリングOral presentation
- 電子情報通信学会 総合大会, Mar. 2005, Japanese, 電子情報通信学会, 未記入, Domestic conferenceSoCにおけるデジタルノイズOral presentation
- シリコン超集積化システム学振第165委員会, Jan. 2005, Japanese, シリコン超集積化システム第165委員会, 未記入, Domestic conference基盤雑音のオンチップ測定とモデル化手法Oral presentation
- Electronic Design and Solution Fair 2005, Jan. 2005, Japanese, 未記入, 未記入, Domestic conferenceデジタルLSIの電源系雑音評価技術と適用事例Oral presentation
- 電子情報通信学会技術報告, Dec. 2004, JapaneseTD-CDMAによる輻輳制御を用いたRFID向けトランスポンダのIC設計と評価
- 電子情報通信学会技術報告, Dec. 2004, Japanese非対称な信号遷移を用いた高速論理回路方式
- 第8回システムLSIワークショップ, Nov. 2004, Japanese, 未記入, 未記入, Domestic conferenceデジタルLSIの埋め込み型電源雑音検出手法Oral presentation
- 映像情報メディア学会 若手研究者のためのイメージセンサLSI設計フォーラム, Oct. 2004, Japanese, 映像情報メディア学会, 東京理科大学, Domestic conferenceアナログLSIチップ開発ノウハウOral presentation
- 電子情報通信学会技術報告, Sep. 2004, Japanese高速ウェル制御回路のダイナミック電源・ウェルノイズの測定および解析方法
- イノベーション・ジャパン2004, Sep. 2004, Japanese, イノベーションジャパン2004組織委員会, 東京国際フォーラム, Domestic conference高性能LSIのためのデジタル電源/グラウンド雑音低減化設計及び診断技術の開発Oral presentation
- 電子情報通信学会 ソサエティ大会, Sep. 2004, Japanese, 電子情報通信学会, 未記入, Domestic conferenceデジタルLSI における電源/グラウンド雑音の評価とモデリングOral presentation
- STARCシンポジウム, Sep. 2004, Japanese, (株)半導体理工学研究センター, 新横浜国際ホテル, Domestic conferenceオンチップ信号モニタ回路の構成と評価Oral presentation
- 電子情報通信学会技術報告, 2004, Japaneseデジタル回路における電源/ウェル雑音の高分解能測定技術
- 電子情報通信学会技術報告, 2004, Japanese高速論理回路方式ASDDL/ASD-CMOSの論理合成手法
- 電子情報通信学会 総合大会, 2004, Japanese, 電子情報通信学会, 東京工業大学, Domestic conference日本の大学における集積回路設計紹介 --VDECユーザ事例紹介--Oral presentation
- システムデザインセミナー, 2004, Japanese, 未記入, 未記入, Domestic conferenceアナ・デジ混載SoCの下流設計・検証技術Oral presentation
- IEEE International Solid-State Circuits Conference, 2004, English, IEEE, San Francisco, International conferenceSubstrate Noise Measurements and Analysis Case StudiesOral presentation
- DAシンポジウム2003, Jul. 2003, Japanese超多重応答を可能にするRFIDシステムのLSI設計と評価
- 電子情報通信学会技術報告, 2003, Japanese2線2相式論理回路方式ASDDL/ASD-CMOSの論理合成手法
- 電子情報通信学会技術報告, 2003, Japanese大規模デジタル回路におけるグラウンド雑音の解析
- 第7回システムLSIワークショップ, 2003, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市国際会議場, Domestic conference超多重応答を可能にするRFIDシステムのLSI設計と評価Oral presentation
- 第7回システムLSIワークショップ, 2003, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市国際会議場, Domestic conferenceオンチップ電源/グラウンド測定技術Oral presentation
- 第7回システムLSIワークショップ, 2003, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市国際会議場, Domestic conferenceアナログ系設計ツールの課題と基板クロストーク対策Oral presentation
- VDEC LSIデザイナーフォーラム, 2003, Japanese, 東京大学大規模集積システム設計教育センター, 未記入, Domestic conferenceVDECユーザのためのアナログ系LSI設計フローと作法Oral presentation
- 第7回システムLSIワークショップ, 2003, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市国際会議場, Domestic conferenceRF混載LSIにおける3GHz帯の基板雑音検出回路の研究Oral presentation
Research Themes
- 科学研究費補助金/基盤研究(A), Apr. 2014 - Mar. 2017, Principal investigatorCompetitive research funding
- 電子商取引安全技術研究組合, 戦略的イノベーション創造プログラム, 2017, Principal investigator戦略的イノベーション創造プログラム(SIP)/重要インフラ等におけるサイバーセキュリティの確保/(a4)IoT向けのセキュリティ確認技術(IoT向けのセキュリティ確認技術の研究開発)Competitive research funding
- 国立研究開発法人新エネルギー・産業技術総合開発機構, IoT推進のための横断技術開発プロジェクト, 2017, Principal investigatorSensor-to-Cloud Security~ビッグデータを守る革新的IoTセキュリティ基盤技術の研究開発Competitive research funding
- 戦略的イノベーション創造プログラム(SIP), 2016, Principal investigator戦略的イノベーション創造プログラム(SIP)/重要インフラ等におけるサイバーセキュリティの確保/(a4)IoT向けのセキュリティ確認技術(IoT向けのセキュリティ確認技術の研究開発)Competitive research funding
- IoT推進のための横断技術開発プロジェクト, 2016, Principal investigatorSensor-to-Cloud Security~ビッグデータを守る革新的IoTセキュリティ基盤技術の研究開発Competitive research funding
- 電波資源拡大のための研究開発, 2013, Principal investigator高速・高品質な無線通信実現のためのICチップレベルの低ノイズ化技術の研究開発Competitive research funding
- 電波資源拡大のための研究開発, 2012, Principal investigator高速・高品質な無線通信実現のためのICチップレベルの低ノイズ化技術の研究開発Competitive research funding
- 科学研究費補助金/基盤研究(B), 2011, Principal investigatorCompetitive research funding
- 電波資源拡大のための研究開発, 2011, Principal investigator高速・高品質な無線通信実現のためのICチップレベルの低ノイズ化技術の研究開発Competitive research funding
Industrial Property Rights
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- 半導体装置特願2017-203848, 20 Oct. 2017, 神戸大学, 特許7010428, 17 Jan. 2022, 永田真;三浦典之;三木拓司;電子商取引安全技術研究組合Patent right
- デジタルアナログ変換アレイ特願2021-210686, 24 Dec. 2021, 神戸大学Patent right
- 積層半導体パッケージ特願2021-163849, 05 Oct. 2021Patent right
- 逐次比較型AD変換装置、半導体装置及び電子機器特願2017-214644, 07 Nov. 2017, 神戸大学, 特許6950130, 28 Sep. 2021, 永田真;三浦典之;三木拓司;電子商取引安全技術研究組合Patent right
- 改ざん検知回路及び改ざん検知方法特願2021-157183, 27 Sep. 2021Patent right
- インプランタブルデバイス特願2021-077771, 30 Apr. 2021Patent right
- 不要電波評価システム神戸大学, 東北大学, 特許6789533, 06 Dec. 2020, ※特願2020-503430 (2019.2.20), 特願2018-037924 (2018.3.2,優先権)Patent right
- 半導体装置特願2020-215195, 2020, 神戸大学Patent right
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- オンチップモニタ回路及び半導体チップKobe University, Telecom ParisTech, 特許6555486, 19 Jul. 2019, ※特願2016-569363 (2016.1.12), 特願2015-04346 (2015.1.13,優先権)Patent right
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