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KAWAGUCHI Hiroshi
Graduate School of Science, Technology and Innovation / Department of Science, Technology and Innovation
Professor

Researcher basic information

■ Research Areas
  • Informatics / Computer systems
■ Committee History
  • 情報処理学会システムLSI設計技術研究運営委員会, 運営委員

Research activity information

■ Award
  • 2018 電子情報通信学会, 電子情報通信学会ELEX Best Paper Award, A low power, VLSI object recognition processorusing Sparse FIND Feature for 60fps HDTV resolution video
    Matsukawa Go, Kodamda Taisuke, Nishizumi Yuri, Kajihara Koichi, Nakanishi Chikako, IZUMI Shintaro, KAWAGUCHI Hiroshi, Goto Toshio, Kato Takeo, YOSHIMOTO Masahiko
    Official journal

  • Sep. 2017 IEEE International Workshop on Machine Learning for Signal Processing (MLSP), Sep. 2017., Best Student Paper Award, A Layer-Block-Wise Pipeline For Memory And Bandwidth Reduction In Distributed Deep Learning
    MORI Haruki, YOUKAWA Tetsuya, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, INOUE Atsuki
    International society

  • May 2016 電子情報通信学会集積回路研究専門委員会, LSIとシステムのワークショップ2016 優秀ポスター賞(学生部門), プロセスばらつき耐性を有する低電圧動作STT-MRAM向けカウンターベース読出し回路
    UMEKI Yohei, YANAGIDA Kouji, YOSHIMOTO Shusuke, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, TSUNODA Koji, SUGII Toshihiro
    Japan society

  • May 2014 電子情報通信学会集積回路研究専門委員会, 優秀ポスター賞, 38μAウェアラブル生体情報計測プロセッサ
    中井 陽三郎, IZUMI SHINTARO, 山下 顕, 中野 将尚, 藤井 貴英, 小西 恵大, KAWAGUCHI HIROSHI, 木村 啓明, 丸元 共治, 渕上 貴昭, 藤森 敬和, 中嶋 宏, 志賀 利一, YOSHIMOTO MASAHIKO
    Japan society

  • Jul. 2008 株式会社 半導体理工学研究センター, 優秀ポスター賞, 発話推定を用いたインテリジェント認識システムの低消費電力化技術
    NOGUCHI Hiroki, KAWAGUCHI Hiroshi

  • Jul. 2008 STARC, STARCフォーラム/シンポジウム2008 学生ポスターセッション 優秀ポスター賞受賞, 発話推定を用いたインテリジェント認識システムの低消費電力化技術
    野口 紘希, 川口 博

  • Apr. 2008 財団法人 電気・電子学術振興財団, 第10回LSI IPデザイン・アワード 研究助成賞, 長波帯標準電波を用いた低電力センサノードの垂直統合設計
    OTAKE Yu, ICHIEN Masumi, TAKEUCHI Takashi, GION Akihiro, MIKAMI Shinji, FUJIWARA Hidehiro, KAWAGUCHI Hirosi, OHTA Chikara, YOSHIMOTO Masahiko

  • Apr. 2008 財団法人 電気・電子学術振興財団, 第10回LSI IPデザイン・アワード IP賞 2, サブ100mW H.264/AVC MP@L4.1 HDTV 解像度対応整数画素精度動き検出プロセッサコア
    MIZUNO Kosuke, MIYAKOSHI Junichi, MURACHI Yuichiro, HAMAMOTO Masaki, IINUMA Takahiro, ISHIHARA Tomokazu, 印 芳, KAMINO Tetsuya, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  • Apr. 2008 財団法人 電気・電子学術振興財団, 第10回LSI IPデザイン・アワード IP賞 1, VGA 30fps 実時間動画像認識応用オプティカルフロープロセッサコア
    MURACHI Yuichiro, FUKUYAMA Yuki, YAMANOTO Ryo, MIYAKOSHI Junichi, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, ISHIHARA Hajime, MIYAMA Masahiko, MATSUDA Yoshio

  • Dec. 2007 IEEE, SENSORCOMM 2007 ENOPT 2008 Workshop Best Paper Award, Cross-Layer Design for Low-Power Wireless Sensor Node Using Long-Wave Standard Time Code
    OTAKE Yu, ICHIEN Masumi, TAKEUCHI Takashi, GION Akihiro, MIKAMI Shinji, FUJIWARA Hidehiro, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  • Nov. 2007 電子情報通信学会, 第11回システムLSIワークショップ IEEEシステムLSI技術賞, DVS環境下での小面積・低電圧動作8T SRAMの設計-32nm世代以降で8Tセルが小面積・低電圧動作を同時に実現
    MORITA Yasuhiro, FUJIWARA Hidehiro, NOGUCHI Hiroki, IGUCHI Yusuke, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  • Sep. 2007 東京大学大規模集積システム設計教育研究センター, IEEE SSCS Japan Chapter Outstanding Design Award, ビット線電力を削減する,動画像処理応用 10T 非プリチャージ 2-port SRAM
    IGUCHI Yusuke, NOGUCHI Hiroki, OKUMURA Syunsuke, FUJIWARA Hidehiro, MORITA Yasuhiro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  • Apr. 2007 財団法人 電気・電子学術振興財団, 第9回LSI IPデザイン・アワード 開発奨励賞, 消費電力を50%削減する動的電圧/周波数スケーリング型H.264 Main Profile@Level 4ビデオデコーダLSI
    KAWAKAMI Kentaro, TAKEMURA Jun, KURODA Mitsuhiko, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  • Apr. 2007 財団法人 電気・電子学術振興財団, 第9回LSI IPデザイン・アワード IP賞 2, ット線電力を53%削減できる実時間動画像処理応用2ポートSRAM
    FUJIWARA Hidehiro, NII Koji, MIYAKOSHI Junichi, MURACHI Yuichiro, MORITA Yasuhiro, NOGUCHI Hiroki, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  • Apr. 2007 財団法人 電気・電子学術振興財団, 第9回LSI IPデザイン・アワード IP賞 1, 超並列画像処理のための,任意位置・水平垂直連続複数画素を同時アクセスできるメモリアーキテクチャ
    ISHIHARA Tokokazu, MIYAKOSHI Junichi, MURACHI Yuichiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  • Feb. 2007 IEEE, IEEE Kansai Section 2006 Gold Award, 低電力回路技術によるIEEEへの貢献
    KAWAGUCHI Hiroshi

  • Feb. 2005 IEEE International Solid-State Circuits Conference, IEEE International Solid-State Circuits Conference Takuo Sugano Outstanding Paper Award, Cut-and-Paste Organic FET Customized ICs for Application to Artificial Skin
    SOMEYA Takao, KAWAGUCHI Hiroshi, SAKURAI Takayasu

■ Paper
  • Tatsuya Sugimoto, Nobuhito Taniguchi, Ryoto Yoshikura, Hiroshi Kawaguchi, Shintaro Izumi
    This study aimed to evaluate walking independence in acute-care hospital patients using neural networks based on acceleration and angular velocity from two walking tests. Forty patients underwent the 10-m walk test and the Timed Up-and-Go test at normal speed, with or without a cane. Physiotherapists divided the patients into two groups: 24 patients who were monitored or independent while walking with a cane or without aids in the ward, and 16 patients who were not. To classify these groups, the Transformer model analyzes the left gait cycle data from eight inertial sensors. The accuracy using all the sensor data was 0.836. When sensor data from the right ankle, right wrist, and left wrist were excluded, the accuracy decreased the most. When analyzing the data from these three sensors alone, the accuracy was 0.795. Further reducing the number of sensors to only the right ankle and wrist resulted in an accuracy of 0.736. This study demonstrates the potential of a neural network-based analysis of inertial sensor data for clinically assessing a patient's level of walking independence.
    May 2024, Bioengineering (Basel, Switzerland), 11(6) (6), English, International magazine
    Scientific journal

  • Tatsuya Sugimoto, Ryoto Yoshikura, Toshiyuki Maezawa, Kojiro Mekata, Yuya Ueda, Hiroshi Kawaguchi, Shintaro Izumi
    The purpose of this study was to compare the acceleration and surface electromyography (EMG) of the lower extremity and trunk muscles during straight-leg raising (SLR) in patients with incomplete cervical cord injury according to their levels of walking independence. Twenty-four patients were measured acceleration and EMG during SLR held for 10 s. Data were analyzed separately for the dominant and nondominant sides and compared between the nonindependent (NI) and independent (ID) groups based on their levels of walking independence. Frequency analysis of the EMG showed that the high-frequency (HF) band of the contralateral biceps femoris (BF) in the ID group and bands below the medium-frequency (MF) of the BF and the HF and MF bands of the rectus abdominis in the NI group were significantly higher during dominant and nondominant SLR. During the nondominant SLR, the low-frequency band of the internal oblique and the MF band of the external oblique were significantly higher in the NI group. The ID group mobilized muscle fiber type 2 of the BF, whereas the NI group mobilized type 1 of the BF and types 2 and 1 of the trunk muscles to stabilize the pelvis. This result was more pronounced during the nondominant SLR.
    Feb. 2024, Scientific reports, 14(1) (1), 4363 - 4363, English, International magazine
    Scientific journal

  • Ryotaro Ohara, Atsushi Fukunaga, Masakazu Taichi, Masaya Kabuto, Riku Hamabe, Masato Ikegawa, Shintaro Izumi, Hiroshi Kawaguchi
    We investigated the improvement achieved in the performance of a deep-learning inference processor by changing its cache memory from SRAM to spin-orbit torque magnetoresistive random-access memory (SOT-MRAM). The implementation of SOT-MRAM doubled the capacity in the same area compared to SRAM. It is also expected to reduce the main memory transfer without changing the chip area, thereby reducing the energy. As a case study, we simulated how much the performance could be improved by replacing SRAM with MRAM in a deep learning processor. The NVIDIA deep-learning accelerator (NVDLA) was used as a motif processor, and SegNet and U-Net were used as the target networks for the segmentation task. The image size was set to 512 × 1024 pixels. We evaluated the performance of the NVDLA with a 512-KB buffer and cache memory sizes of 1, 2, 4, and 8 MB for its on-chip memory, replacing these two memories with MRAM implementations. As a result, when both the buffer and cache were replaced with SOT-MRAM, the energy consumption and speed could be reduced by 18.6% and 17.9%, respectively. In addition, the performance per unit area was improved by more than 36.4%. Replacing SRAM with spin-transfer torque MRAM is not suitable for inference devices, because the latency is significantly worse as a result of its slow write operation.
    Feb. 2024, IPSJ Transactions on System LSI Design Methodology, 17, 7 - 15
    Scientific journal

  • Hiroshi Kawaguchi
    2024, Ieee Uffc Latin America Ultrasonics Symposium, Laus
    Scientific journal

  • Ryotaro Ohara, Atsushi Fukunaga, Masakazu Taichi, Masaya Kabuto, Riku Hamabe, Masato Ikegawa, Shintaro Izumi, Hiroshi Kawaguchi 0001
    2024, IPSJ Trans. Syst. LSI Des. Methodol., 17, 7 - 15
    Scientific journal

  • Ryo Takamatsu, Shintaro Izumi, Hiroshi Kawaguchi 0001
    2024, ICCE, 1 - 6
    International conference proceedings

  • Shun Sato, Ryotaro Ohara, M. Shahrul Amir Kamarulzaman, Yuto Yasuda, Shintaro Izumi, Hiroshi Kawaguchi 0001
    2024, ICCE, 1 - 5
    International conference proceedings

  • Yusaku Goto, Shintaro Izumi, Ryotaro Ohara, Teppei Araki, Sho Murase, Hiroshi Kawaguchi 0001
    2024, ICCE, 1 - 5
    International conference proceedings

  • A Mixed-Precision Quantization Method without Accuracy Degradation Using Semilayers
    Hiroshi Kawaguchi
    2023, Proceedings of Machine Learning Research
    Scientific journal

  • Shun Sato, Yuto Yasuda, Ryotaro Ohara, Riku Hamabe, Takayuki Genda, Shoya Imanaka, Shintaro Izumi, Hiroshi Kawaguchi
    In bathrooms, a fall can lead to severe injuries or even drowning. While taking preventive measures against such accidents is crucial, it's equally important to swiftly detect and request rescue when they occur. In such scenarios, knowing the exact location of the person in the bathroom becomes critical. However, concerns related to privacy and costs make the use of cameras and lidar impractical. To address these issues, we propose a method for estimating the 3D location of a person within the bathroom using ultrasound correlation values as input for a deep neural network. To validate our approach, we conduct experiments using two sensors in this study. The results are promising, as we achieved a mean square error of just 10.48 cm.
    2023, IEEE International Ultrasonics Symposium, IUS
    International conference proceedings

  • Kousei Kawai, Ryotaro Ohara, Shun Sato, Toru Ishii, Shintaro Izumi, Hiroshi Kawaguchi
    Respiration is an important vital sign to detect abnormalities in the respiratory organ. However, conventional respiration sensors require contact with the human body, which poses challenges in terms of ease of use and infection control. In this study, we proposed a noncontact method for measuring respiration using ultrasound. We applied the proposed method to a seated subject wearing clothes and evaluated the accuracy of the respiration measurement. The results showed that the RMSEs of the respiration interval under the conditions of 20 cm, 30 cm, and 50 cm were 61.08 ms, 84.89 ms, and 110.98 ms, respectively.
    2023, IEEE International Ultrasonics Symposium, IUS
    International conference proceedings

  • M. Shahrul Amir Kamarulzaman, Riku Hamabe, Yuto Yasuda, Ryotaro Ohara, Shun Sato, Shintaro Izumi, Hiroshi Kawaguchi
    This paper presents a simulation method for bathroom surveillance using an ultrasonic raytracing technique. First, we explain the signal-capturing methods for the waves reflected by an object. Then, results obtained using this method are discussed. Object detection in an environment with significant interference is achieved through a signal-processing method, called beamforming. Evaluation results demonstrate that the proposed method achieved an average of 76.1% accuracy across seven different postures and positions, with an error range of 25 cm. Further evaluation shows that the results of our method were identical to the real measurements, which provides a foundation for future accuracy improvements through machine-learning techniques.
    2023, IEEE International Ultrasonics Symposium, IUS
    International conference proceedings

  • Tatsuya Sugimoto, Ryoto Yoshikura, Hiroshi Kawaguchi 0001, Shintaro Izumi
    2023, BSN, 1 - 4
    International conference proceedings

  • Ishibashi, M., Izumi, S., Takamatsu, R., Yoshimoto, S., Noda, Y., Araki, T., Uemura, T., Sekitani, T., Kawaguchi, H.
    2023, IEEE Sensors Letters, 7(9) (9)
    Scientific journal

  • Yasufumi Sakai, Thang Dang, Shigeki Fukuta, Koichi Shirahata, Atsushi Ishikawa, Atsuki Inoue, Hiroshi Kawaguchi, Árni Björn Höskuldsson, Egill Skúlason
    2023, INNS DLIA@IJCNN, 458 - 467
    International conference proceedings

  • Tomoya Matsuda, Kengo Matsumoto, Atsuki Inoue, Hiroshi Kawaguchi, Yasufumi Sakai
    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2023, ICANN (9), 14262 LNCS, 283 - 295
    International conference proceedings

  • Ryotaro Ohara, Masaya Kabuto, Masakazu Taichi, Atsushi Fukunaga, Yuto Yasuda, Riku Hamabe, Shintaro Izumi, Hiroshi Kawaguchi
    2023, AICAS, 1 - 5
    International conference proceedings

  • Ryotaro Ohara, Yuto Yasuda, Riku Hamabe, Ishii Toru, Shintaro Izumi, Hiroshi Kawaguchi
    IEEE, Oct. 2022, 2022 IEEE International Ultrasonics Symposium (IUS)

  • Toru, I., Yasuda, Y., Sato, S., Izumi, S., Kawaguchi, H.
    Institute of Electrical and Electronics Engineers ({IEEE}), Aug. 2022, IEEE Sensors Journal, 22(16) (16), 16202 - 16211
    Scientific journal

  • Ayaka Shintomi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    The purpose of this study is to evaluate the effectiveness of heartbeat error and compensation methods on heart rate variability (HRV) with mobile and wearable sensor devices. The HRV analysis extracts multiple indices related to the heart and autonomic nervous system from beat-to-beat intervals. These HRV analysis indices are affected by the heartbeat interval mismatch, which is caused by sampling error from measurement hardware and inherent errors from the state of human body. Although the sampling rate reduction is a common method to reduce power consumption on wearable devices, it degrades the accuracy of the heartbeat interval. Furthermore, wearable devices often use photoplethysmography (PPG) instead of electrocardiogram (ECG) to measure heart rate. However, there are inherent errors between PPG and ECG, because the PPG is affected by blood pressure fluctuations, vascular stiffness, and body movements. This paper evaluates the impact of these errors on HRV analysis using dataset including both ECG and PPG from 28 subjects. The evaluation results showed that the error compensation method improved the accuracy of HRV analysis in time domain, frequency domain and non-linear analysis. Furthermore, the error compensation by the algorithm was found to be effective for both PPG and ECG.
    Institution of Engineering and Technology ({IET}), Feb. 2022, Healthcare Technology Letters, 9(1-2) (1-2), 9 - 15, English, International magazine
    Scientific journal

  • Tsuji, S., Yamada, F., Kawaguchi, H., Inoue, A., Sakai, Y.
    2022, Neural Computing and Applications
    Scientific journal

  • Yasufumi Sakai, Akinori Iwakawa, Tsuguchika Tabaru, Atsuki Inoue, Hiroshi Kawaguchi
    IEEE, 2022, 26th International Conference on Pattern Recognition(ICPR), 2561 - 2567
    International conference proceedings

  • Kazuki Okado, Kengo Matsumoto, Atsuki Inoue, Hiroshi Kawaguchi, Yasufumi Sakai
    ACM, 2022, ICMLT 2022: 7th International Conference on Machine Learning Technologies(ICMLT), 56 - 61
    International conference proceedings

  • Ryoto Yoshikura, Shintaro Izumi, Tatsuya Sugimoto, Hiroshi Kawaguchi
    IEEE, 2022, 2022 IEEE Sensors, 1 - 4
    International conference proceedings

  • Shintaro Izumi, Sho Murase, Itsumi Fukuda, Kenta Taki, Kazunori Toyama, Tadashi Inuzuka, Hideki Mochizuki, Hiroshi Kawaguchi
    IEEE, 2022, 2022 IEEE Sensors, 1 - 4
    International conference proceedings

  • Masayasu Harada, Shintaro Izumi, Ryosuke Kozeni, Yukiko Yoshikawa, Toru Ishii, Hiroshi Kawaguchi, Shohei Uemura, Kaname Araki
    IEEE, 2022, 19th IEEE Annual Consumer Communications & Networking Conference(CCNC), 181 - 186
    International conference proceedings

  • Narukage, R., Okada, G., Kawaguchi, H.
    2021, Journal of Laser Micro Nanoengineering, 16(2) (2)
    Scientific journal

  • Fuyuka Yamada, Satoki Tsuji, Hiroshi Kawaguchi, Atsuki Inoue, Yasufumi Sakai
    Springer, 2021, KI 2021: Advances in Artificial Intelligence - 44th German Conference on AI(KI), 12873 LNAI, 109 - 115
    International conference proceedings

  • Greedy Search Algorithm for Mixed Precision in Post-Training Quantization of Convolutional Neural Network Inspired by Submodular Optimization.
    Satoki Tsuji, Hiroshi Kawaguchi, Atsuki Inoue, Yasufumi Sakai, Fuyuka Yamada
    PMLR, 2021, Asian Conference on Machine Learning(ACML), 886 - 901
    International conference proceedings

  • Yukiko Yoshikawa, Yuto Yasuda, Toru Ishii, Shintaro Izumi, Hiroshi Kawaguchi
    IEEE, 2021, IEEE International Instrumentation and Measurement Technology Conference(I2MTC), 1 - 6
    International conference proceedings

  • Toru Ishii, Yukiko Yoshikawa, Shintaro Izumi, Hiroshi Kawaguchi
    2021, IEEE Trans. Instrum. Meas., 70, 1 - 8
    Scientific journal

  • Kento Watanabe, Shintaro Izumi, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This study presents a method for improving the heartbeat interval accuracy of photoplethysmographic (PPG) sensors at ultra-low sampling rates. Although sampling rate reduction can extend battery life, it increases the sampling error and degrades the accuracy of the extracted heartbeat interval. To overcome these drawbacks, a sampling-error compensation method is proposed in this study. The sampling error is reduced by using linear interpolation and autocorrelation based on the waveform similarity of heartbeats in PPG. Furthermore, this study introduces two-line approximation and first derivative PPG (FDPPG) to improve the waveform similarity at ultra-low sampling rates. The proposed method was evaluated using measured PPG and reference electrocardiogram (ECG) of seven subjects. The results reveal that the mean absolute error (MAE) of 4.11 ms was achieved for the heartbeat intervals at a sampling rate of 10 Hz, compared with 1-kHz ECG sampling. The heartbeat interval error was also evaluated based on a heart rate variability (HRV) analysis. Furthermore, the mean absolute percentage error (MAPE) of the low-frequency/high-frequency (LF/HF) components obtained from the 10-Hz PPG is shown to decrease from 38.3% to 3.3%. This error is small enough for practical HRV analysis.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jun. 2020, IEICE TRANSACTIONS ON COMMUNICATIONS, E103B(6) (6), 645 - 652, English
    Scientific journal

  • GPQ: Greedy Partial Quantization of Convolutional Neural Networks Inspired by Submodular Optimization
    Hiroshi Kawaguchi
    2020, 5TH INTERNATIONAL CONFERENCE ON SOFT COMPUTING & MACHINE INTELLIGENCE (ISCMI)
    Scientific journal

  • Toru Ishii, Yukiko Yoshikawa, Shintaro Izumi, Hiroshi Kawaguchi
    IEEE, 2020, 2020 IEEE International Instrumentation and Measurement Technology Conference(I2MTC), 1 - 6
    International conference proceedings

  • Reiya Kawamoto, Masakazu Taichi, Masaya Kabuto, Daisuke Watanabe, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Go Matsukawa, Toshio Goto, Motoshi Kojima
    2020, IEEE J. Sel. Top. Signal Process., 14(4) (4), 634 - 645
    Scientific journal

  • Kento Watanabe, Shintaro Izumi, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto
    2020, IEICE Trans. Commun., 103-B(6) (6), 645 - 652
    Scientific journal

  • Daisuke Watanabe, Yuji Yano, Shintaro Izumi, Hiroshi Kawaguchi, Kiyoshi Takeuchi, Toshiro Hiramoto, Shoichi Iwai, Masami Murakata, Masahiko Yoshimoto
    IEEE, 2020, 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems(AICAS), 305 - 309
    [Refereed]
    International conference proceedings

  • Reiya Kawamoto, Masakazu Taichi, Masaya Kabuto, Daisuke Watanabe, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    IEEE, 2020, 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems(AICAS), 203 - 207
    [Refereed]
    International conference proceedings

  • Kana Sasai, Shintaro Izumi, Kento Watanabe, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a low-power photoplethysmography (PPG) sensor circuit using a current integration circuit. PPG sensors are widely used in modern healthcare products for monitoring cardiovascular information. However, the PPG circuits generally have a large power consumption because the LED driver consumes considerable energy to obtain the required amount of reflected light from the human body. A simple way to reduce the power requirements of PPG circuits is to lower the duty cycle of the LED through intermittent operation of the LED. However, this causes accuracy degradation because the target signal is susceptible to interference from various noises. To reduce the power consumption while maintaining accuracy, the correlated double sampling (CDS) method that we introduced in our previous work was used. In our previous work, wherein the PPG was placed on fingertips, the heartbeat error was 5 ms. This paper presents a signal-to-noise ratio improvement method for CDS by using a PPG sensor with current integration circuits. This enables SNR improvement and measurements to be taken from any part of the body. In the proposed method, the target PPG signal is extracted by canceling noise and DC components using two sensors. The proposed circuit was evaluated using actual measurements and the total consumption current was 26.9 μA. The root mean square error of the heartbeat interval was 4.27 ms, even though the sensor was worn on the wrist during the experiment.
    Institute of Electrical and Electronics Engineers Inc., Oct. 2019, Proceedings of IEEE Sensors, 2019-, English
    International conference proceedings

  • Yuji Yano, Seiya Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Tetsuya Hirose, Masaya Miyahara, Teruki Someya, Kenichi Okada, Ippei Akita, Yoshihiko Kurui, Hideyuki Tomizawa, Masahiko Yoshimoto
    IEEE, 2019, IEEE Asian Solid-State Circuits Conference(A-SSCC), 267 - 270
    [Refereed]
    International conference proceedings

  • Seiya Yoshida, Shintaro Izumi, Yuki Nishikawa, Kento Watanabe, Kana Sasai, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto
    IEEE, 2019, 2019 IEEE Biomedical Circuits and Systems Conference(BioCAS), 1 - 4
    [Refereed]
    International conference proceedings

  • Seiya Yoshida, Shintaro Izumi, Koichi Kajihara, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents an energy-efficient spectral analysis method for the Internet of Things (IoT). The objective of this paper is to reduce the energy consumption of edge devices. The proposed method uses an autoregressive (AR) model for spectral analysis instead of the discrete Fourier transform, and its calculation process is distributed to the edge device and a base station by considering the energy consumption tradeoff of the data processing and the data communication. In this paper, the Yule-Walker method is employed for the AR coefficient calculation. The calculation process of Yule-Walker method can be divided into two parts: an autocorrelation calculation and an AR coefficient calculation. The autocorrelation calculation is implemented in the edge devices, and its dedicated hardware is designed using Verilog HDL. Meanwhile, the AR coefficient is calculated in the base station and is used for the spectral analysis. According to this distributed processing approach, the energy consumption of the edge device can be reduced compared with conventional DFT approaches using the fast Fourier transform (FFT). The system level energy consumption is evaluated assuming the IoT edge device, which has a wireless transceiver using Bluetooth low energy. The evaluation results show that the proposed method can reduce 79% of the edge device energy consumption for spectral analysis in a practical application.
    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2019, IEEE Trans. Circuits Syst. I Regul. Pap., 66-I(10) (10), 3896 - 3905, English
    [Refereed]
    Scientific journal

  • Takaaki Okano, Shintaro Izumi, Takumi Katsuura, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This article describes a multimodal cardiovascular information measurement method using a wearable device composed of piezoelectric transducers. Cardiovascular diseases are increasing with the aging population, and they constitute a significant portion of the causes of death and long-term care. In recent years, daily-life monitoring using wearable sensor devices has attracted particular attention for the prevention and early detection of cardiovascular diseases. However, recent wearable devices can only measure limited cardiovascular information such as the heart rate. In contrast, the proposed method can simultaneously measure heart rate variability, pulse wave propagation velocity, and blood flow velocity using only a piezoelectric transducer array.
    SPRINGER, 2019, J. Signal Process. Syst., 91(9) (9), 1053 - 1062, English
    [Refereed]
    Scientific journal

  • Shintaro Izumi, Takaaki Okano, Daichi Matsunaga, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a non-contact and noise-tolerant heart rate monitoring system using a 24-GHz microwave Doppler sensor. The microwave Doppler sensor placed at some distance from the user's chest detects the small vibrations of the body surface due to the heartbeats. The objective of this work is to detect the instantaneous heart rate (IHR) using this non-contact system in a car, because the possible application of the proposed system is a driver health monitoring based on heart rate variability analysis. IHR can contribute to preventing heart-triggered disasters and to detect mental stress state. However, the Doppler sensor system is very sensitive and it can be easily contaminated by motion artifacts and road noise especially while driving. To address this problem, time-frequency analysis using the parametric method and template matching method are employed. Measurement results show that the Doppler sensor, which is pasted on the clothing surface, can successfully extract the heart rate through clothes. The proposed method achieves 13.1-ms RMS error in IHR measurements conducted on 11 subjects in a car on an ordinary road.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2019, IEICE Trans. Commun., 102-B(6) (6), 1088 - 1096, English
    [Refereed]
    Scientific journal

  • Kento Watanabe, Shintaro Izumi, Kana Sasai, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This study designs a low-power photoplethysmography (PPG) sensor based on the error compensation method for heartbeat interval acquisition. To perform heartbeat monitoring in daily life, it is necessary to obtain long-term and accurate heartbeat interval data with low power consumption, because of the limited size and battery capacity of the PPG sensor. Effective reduction in the power consumption of the sensor requires the duty-cycled LEDs and lowering pulse repetition frequency (PRF), i.e., decreasing the sampling rate. However, these methods reduce the accuracy of the heartbeat interval measurement because of signal-to-noise ratio (SNR) degradation and sampling errors. We propose an algorithm for heartbeat interval error compensation and incorporate a low-noise readout circuit to improve SNR. The readout circuit uses current integration to achieve low duty-cycle LED driving. A correlated double sampling (CDS) is introduced to minimize the random noise arising from the switching operation of the integration circuit. An error compensation method based on the PPG waveform similarity is also introduced using the autocorrelation and linear interpolation. The measurement results obtained from nine subjects show that a total current consumption of 28.2A is achieved with a 20-Hz PRF and 0.3 LED duty cycle. The proposed design effectively reduces the mean absolute error (MAE) of the heartbeat interval to an average of 6.2 ms.
    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2019, IEEE Trans. Biomed. Circuits and Systems, 13(6) (6), 1552 - 1562, English, International magazine
    [Refereed]
    Scientific journal

  • Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents a low-energy 64-Kb eighttransistor (8T) one-read/one-write dual-port image memory with a 28-nm fully depleted SOI (FD-SOI) process technology. Our proposed SRAM adopts a selective sourceline drive (SSD) scheme and a consecutive data write technique for improving active energy efficiency at low voltage. The novel SSD scheme controls sourceline voltage and eliminates leakage energy at unselected columns in read operations. We fabricated a 64-Kb 8T dual-port SRAM in the 28-nm FD-SOI process technology. The 81 SRAM cell size is 0.291 x 1.457 mu m(2). The test chip exhibits 0A8-V operation at an access time of 135 ns. The energy minimum point is at a supply voltage of 0.56 V and an access time of 35 ns, where 265.0 fJ/cycle in write operations and 389.6 fJ/cycle in read operations are achieved. These factors are, respectively, 30% and 26% smaller than those of the 8T dual-port SRAM with the conventional scheme.
    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2019, IEEE Trans. Circuits Syst. I Regul. Pap., 66-I(4) (4), 1442 - 1453, English
    [Refereed]
    Scientific journal

  • Motofumi Nakanishi, Shintaro Izumi, Sho Nagayoshi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Toshikazu Shiga, Takafumi Ando, Satoshi Nakae, Chiyoko Usui, Tomoko Aoyama, Shigeho Tanaka
    BACKGROUND: Herein, an algorithm that can be used in wearable health monitoring devices to estimate metabolic equivalents (METs) based on physical activity intensity data, particularly for certain activities in daily life that make MET estimation difficult. RESULTS: Energy expenditure data were obtained from 42 volunteers using indirect calorimetry, triaxial accelerations and heart rates. The proposed algorithm used the percentage of heart rate reserve (%HRR) and the acceleration signal from the wearable device to divide the data into a middle-intensity group and a high-intensity group (HIG). The two groups were defined in terms of estimated METs. Evaluation results revealed that the classification accuracy for both groups was higher than 91%. To further facilitate MET estimation, five multiple-regression models using different features were evaluated via leave-one-out cross-validation. Using this approach, all models showed significant improvements in mean absolute percentage error (MAPE) of METs in the HIG, which included stair ascent, and the maximum reduction in MAPE for HIG was 24% compared to the previous model (HJA-750), which demonstrated a 70.7% improvement ratio. The most suitable model for our purpose that utilized heart rate and filtered synthetic acceleration was selected and its estimation error trend was confirmed. CONCLUSION: For HIG, the MAPE recalculated by the most suitable model was 10.5%. The improvement ratio was 71.6% as compared to the previous model (HJA-750C). This result was almost identical to that obtained from leave-one-out cross-validation. This proposed algorithm revealed an improvement in estimation accuracy for activities in daily life; in particular, the results included estimated values associated with stair ascent, which has been a difficult activity to evaluate so far.
    Jul. 2018, Biomedical engineering online, 17(1) (1), 100 - 100, English, International magazine
    [Refereed]
    Scientific journal

  • Kento Watanabe, Shintaro Izumi, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents a low-power Photoplethysmography (PPG) sensing method. The PPG is commonly used in recent wearable devices to detect cardiovascular information including heartbeat. The heartbeat is useful for physical activity and stress monitoring. However, the PPG circuit consumes large power because it consists of LED and photodiode. To reduce its power consumption without accuracy degradation, a cooperative design of circuits and algorithms is proposed in this work. A straightforward way to reduce the power is intermittent driving of LED, but there is a disadvantage that the signal is contaminated by a noise while circuit switching. To overcome this problem, we introduce correlated double sampling (CDS) method, which samples an integration circuit output twice with short intervals after the LED turns on and uses the difference of these voltage. Furthermore, an up-conversion method using linear interpolation, and an error correction using autocorrelation are introduced. The proposed PPG sensor, which consists of the LED, the photodiode, the current integration circuit, a CMOS switch, an A/D converter, and an MCU, is prototyped. It is evaluated by actual measurement with 22-year-old subject. The measurement results show that 22-μA total current consumption is achieved with 5-ms mean absolute error.
    Jul. 2018, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2018, 5566 - 5569, English, International magazine
    [Refereed]
    Scientific journal

  • Yuki Nishikawa, Shintaro Izumi, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This report describes a sampling rate reduction method for heart rate variability monitoring with a wearable device. This work was conducted to realize low-power measurement of biological signals necessary for heart rate variability (HRV) analysis. Continuous operation of the wearable device is an important factor for daily life monitoring. Therefore, the active time of the measuring circuit must be minimized. To reduce the required sampling rate, we propose a sampling error reduction method using interpolation and correlation of the heartbeat waveform. The proposed method is evaluated using measured electrocardiograms from five subjects. Evaluation results demonstrate that the sampling rate can be reduced to 32 Hz with 1 ms RMS error in heartbeat interval and 1.04% LF/HF degradation in HRV analysis.
    Institute of Electrical and Electronics Engineers Inc., Apr. 2018, Proceedings - IEEE International Symposium on Circuits and Systems, 2018-, English
    International conference proceedings

  • Nakanishi, Motofumi, Izumi, Shintaro, Tsukahara, Mio, Kawaguchi, Hiroshi, Kimura, Hiromitsu, Marumoto, Kyoji, Fuchikami, Takaaki, Fujimori, Yoshikazu, Yoshimoto, Masahiko
    This paper presents an algorithm for a physical activity (PA) classification and metabolic equivalents (METs) monitoring and its System-on-a-Chip (SoC) implementation to realize both power reduction and high estimation accuracy. Long-term PA monitoring is an effective means of preventing lifestyle-related diseases. Low power consumption and long battery life are key features supporting the wider dissemination of the monitoring system. As described herein, an adaptive sampling method is implemented for longer battery life by minimizing the active rate of acceleration without decreasing accuracy. Furthermore, advanced PA classification using both the heart rate and acceleration is introduced. The proposed algorithms are evaluated by experimentation with eight subjects in actual conditions. Evaluation results show that the root mean square error with respect to the result of processing with fixed sampling rate is less than 0.22 [METs], and the mean absolute error is less than 0.06 [METs]. Furthermore, to minimize the system-level power dissipation, a dedicated SoC is implemented using 130-nm CMOS process with FeRAM. A nonvolatile CPU using non-volatile memory and a flip-flop is used to reduce the stand-by power. The proposed algorithm, which is implemented using dedicated hardware, reduces the active rate of the CPU and accelerometer. The current consumption of the SoC is less than 3-mu A. And the evaluation system using the test chip achieves 74% system-level power reduction. The total current consumption including that of the accelerometer is 11.3-mu A on average.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2018, IEICE TRANSACTIONS ON ELECTRONICS, E101C(4) (4), 233 - 242, English
    [Refereed]
    Scientific journal

  • マイクロ波ドップラーセンサを用いた非接触生体認証
    OKANO Takaaki, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    電子情報通信学会, Mar. 2018, 信学技報, vol. 117, no. 511, MICT2017-54, pp. 17-20, 2018年3月, 117(511) (511), 17 - 20, Japanese
    Symposium

  • Hiroshi Kawaguchi
    2018, VLSI Design and Test for Systems Dependability
    Scientific journal

  • Hiroshi Kawaguchi
    2018, VLSI Design and Test for Systems Dependability
    Scientific journal


  • Hiroshi Kawaguchi
    2018, International Journal of Clinical Oncology
    Scientific journal

  • Secondary Thyroid Cancer After the Diagnosis of Childhood Cancer: Hospital-Based Case Series
    Hiroshi Kawaguchi
    2018, Pediatric Blood and Cancer
    Scientific journal

  • Tetsuya Youkawa, Haruki Mori, Yuki Miyauchi, Kazuki Yamada, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    This paper presents a proposal of a data-parallel stochastic gradient descent (SGD) using delayed weight update. A large-scale neural network appears to solve advanced problems, but its processing time increases concomitantly with the network scale. For conventional data parallelism, workers must wait for data communication to and from a server during weight updating. Using the proposed data-parallel method, the network weight has a delay. It is therefore stale. Nevertheless, it gives faster convergence time by hiding the latency of the weight communication for the server. The server concurrently carries out the weight communication and weight update while workers calculate their gradients. The experimentally obtained results demonstrate that, in the proposed data parallel method, the final accuracy converges within degradation of 1.5% compared with the conventional method in both VGG and ResNet At maximum, the convergence speedup factor theoretically reaches double that of conventional data parallelism.
    IEEE, 2018, 2018 IEEE GLOBAL CONFERENCE ON SIGNAL AND INFORMATION PROCESSING (GLOBALSIP 2018), 663 - 667, English
    [Refereed]
    International conference proceedings

  • Go Matsukawa, Taisuke Kodama, Yuri Nishizumi, Koichi Kajihara, Chikako Nakanishi, Shintaro Izumi, Hiroshi Kawaguchi, Toshio Goto, Takeo Kato, Masahiko Yoshimoto
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2018, IEICE Electronic Express, 15(12) (12), 20188003 - 20188003, English
    [Refereed]
    Scientific journal

  • Layer Skip Learning using LARS variables for 39% Faster Conversion Time and Lower Bandwidth
    Miyauchi, Yuki, Mori, Haruki, Youkawa, Tetsuya, Yamada, Kazuki, Izumi, Shintaro, Yoshimoto, Masahiko, Kawaguchi, Hiroshi, Inoue, Atsuki
    In this paper, a method for the improvement of the relationship between calculation time and recognition accuracy in deep learning is proposed. A major problem with respect to deep learning is that a large calculation time is required for higher recognition accuracy. Because of this problem, the implementation of deep learning in hardware and its application to real problems are limited. In this study, layer-wise adaptive rate scaling (LARS) variables are adopted to evaluate the necessity of the learning of each layer. When the variable of a certain convolution layer exceeds the threshold value, the learning for that layer is considered unnecessary; thus, the layer is skipped. When a layer recognized as the layer that does not require learning, only the lower layers below than that layer are learned in the next epoch. By adaptively skipping the layer, the calculation time is reduced. Furthermore, the recognition accuracy is improved. Consequently, the proposed methods accelerate the calculation time in VGG-F to achieve the highest accuracy for the top1 and top5 test accuracy by a speed up factor of 2.14, and 2.25, respectively. Moreover, the respective topl and top5 test accuracy was improved by 3.0 %, and 2.8% which obtained as the final accuracy. In addition, the operation process was reduced by approximately 39.0 %, and required bandwidth was reduced by 38.9 %, when compared with the case of conventional full layer learning.
    IEEE, 2018, 2018 25TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 673 - 676, English
    [Refereed]
    International conference proceedings

  • Sampling Rate Reduction for Wearable Heart Rate Variability Monitoring
    Nishikawa, Yuki, Izumi, Shintaro, Yano, Yuji, Kawaguchi, Hiroshi, Yoshimoto, Masahiko
    This report describes a sampling rate reduction method for heart rate variability monitoring with a wearable device. This work was conducted to realize low-power measurement of biological signals necessary for heart rate variability (HRV) analysis. Continuous operation of the wearable device is an important factor for daily life monitoring. Therefore, the active time of the measuring circuit must be minimized. To reduce the required sampling rate, we propose a sampling error reduction method using interpolation and correlation of the heartbeat waveform. The proposed method is evaluated using measured electrocardiograms from five subjects. Evaluation results demonstrate that the sampling rate can be reduced to 32 Hz with 1 ms RMS error in heartbeat interval and 1.04% LF/HF degradation in HRV analysis.
    IEEE, 2018, 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), English
    [Refereed]
    International conference proceedings

  • Hardware Implementation of Autoregressive Model Estimation Using Burg's Method for Low-Energy Spectral Analysis
    Kajihara, Koichi, Izumi, Shintaro, Yoshida, Seiya, Yano, Yuji, Kawaguchi, Hiroshi, Yoshimoto, Masahiko
    We present a hardware implementation of Burg's method, which is used for autoregressive (AR) model estimation. The AR model is a linear predictive modeling technique. It assumes that the current value of a signal can be described by a finite linear aggregate of the previous values. The AR model can be used for spectral analysis as an alternative to the Fourier transform. This approach is a parametric method, and it can yield higher resolutions than nonparametric methods in cases when the signal length is short. Although Burg's method requires a large computational capacity, especially with higher model orders, a fast Burg's method has been proposed for improving this draw back. In this study, we evaluate the influence of the order and the data length of Burg's method on the computational capacity. The hardware implementation method of the fast Burg's method including a two-stage pipeline architecture and a parallelization technique for autocorrelation calculations is proposed. The proposed method is implemented using Verilog HDL and its energy consumption is estimated with the 65-nm CMOS process. The evaluation result shows that the proposed method achieves an energy consumption of 21.6-361.4 nJ for the spectral estimation with a data length of 128-2048 points when the model order is 5.
    IEEE, 2018, PROCEEDINGS OF THE 2018 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), 199 - 204, English
    [Refereed]
    International conference proceedings

  • Adaptive Learning Rate Adjustment with Short-Term Pre-Training in Data-Parallel Deep Learning
    Yamada, Kazuki, Mori, Haruki, Youkawa, Tetsuya, Miyauchi, Yuki, Izumi, Shintaro, Yoshimoto, Masahiko, Kawaguchi, Hiroshi
    This paper introduces a method to adaptively choose a learning rate (LR) with short-term pre-training (STPT). This is useful for quick model prototyping in data-parallel deep learning. For unknown models, it is necessary to tune numerous hyperparameters. The proposed method reduces computational time and increases efficiency in finding an appropriate LR; multiple LRs are evaluated by STPT in data-parallel deep learning. STPT means training only with the beginning iterations in an epoch. When eight LRs are evaluated using eight parallel workers, the proposed method can easily reduce the computational time by 87.5% in comparison with the conventional method. The accuracy is also improved by 4.8% in comparison with the conventional method with a reference LR of 0.1; thus, no deterioration in accuracy is observed. For an unknown model, this method shows a better training curve trend than other cases with fixed LRs.
    IEEE, 2018, PROCEEDINGS OF THE 2018 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), 100 - 105, English
    [Refereed]
    International conference proceedings

  • 28-nm FD-SOI Dual-Port SRAM with MSB-Based Inversion Logic for Low-Power Deep Learning
    Mori, Haruki, Izumi, Shintaro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko
    This paper presents low-power and low-energy 8T dual-port SRAM with a novel MSB-based (most-significant-bit-based) inversion logic for an image processor such a deep learning processor. Our proposed SRAM is suitable for real-time and low-power image processing, in which data have statistical correlation and data bit reordering are exploited. The proposed MSB-based inversion logic eliminates an additional flag bit in a majority logic; the MSB digit in an input datum judges whether or not to invert the datum. Thus, the area overhead of 12.5 % for the 8-bit conventional majority logic is dramatically saved. The area overhead of the proposed SRAM is merely 0.6% for the MSB-based inversion logic. We verified that, with the proposed technique, 14.76 % of total energy can be saved in a 28-nm 64-kb FD-SOI SRAM when a set of images are read out. Furthermore, the saving factor is extended to 17.31 % when image processing in the VGG-F convolutional neural network (CNN) is considered, where 304.81 fJ/cycle in the read operation is achieved.
    IEEE, 2018, 2018 25TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 161 - 164, English
    [Refereed]
    International conference proceedings

  • Non-Contact Biometric Identification and Authentication Using Microwave Doppler Sensor
    OKANO Takaaki, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Oct. 2017, The 13th IEEE BioMedical Circuits and Systems Conference(BioCAS), pp.392-395, Oct. 2017., 392 - 395, English
    [Refereed]
    International conference proceedings

  • Ryota Nakamura, Shintaro Izumi, Hiroshi Kawaguchi, Hidetoshi Ohta, Masahiko Yoshimoto
    This paper presents a swallowable sensor device that can be ingested orally, later passing to the stomach, where the device can indwell for long periods. Using wireless communication, it can be egested at any time after it is triggered. This device can indwell using a silicone balloon in the gastrointestinal tract. A chemical reaction inflates the balloon inside the stomach. Then it is deflated to egest the sensor device using an actuator with electrolysis of water. Energy for the actuator with electrolysis can be fed wirelessly. Near field communication and a flexible antenna are used for power feeding and wireless data communication. Because of the flexible balloon and the flexible antenna, the device size can be minimized without performance degradation.
    Jul. 2017, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2017, 3040 - 3043, English, International magazine
    [Refereed]
    Scientific journal

  • A contact-less heart rate sensor system for driver health monitoring
    IZUMI Shintaro, MATSUNAGA Daichi, NAKAMURA Ryota, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Jul. 2017, The 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC’17), July. 2017, English
    International conference proceedings

  • Matsukawa, Go, Kodama, Taisuke, Nishizumi, Yuri, Kajihara, Koichi, Nakanishi, Chikako, Izumi, Shintaro, Kawaguchi, Hiroshi, Goto, Toshio, Kato, Takeo, Yoshimoto, Masahiko
    This paper describes a low-power object recognition processor VLSI for HDTV resolution video at 60 frames per second (fps) using an object recognition algorithm with Sparse FIND features. The VLSI processor features two-stage feature extraction processing by HOG and Sparse FIND, a highly parallel classification in the support vector machine (SVM), and a block-parallel processing for RAM access cycle reduction. Compared to the accuracy by the original Sparse FIND algorithm, the two-stage object detection demonstrates insignificant accuracy degradation. Using this architectural design, a 60 fps performance for object recognition of HDTV resolution video was attained at an operating frequency of 130 MHz. This 3.35 x 3.35 mm(2) chip, designed with 40 nm CMOS technology, contains 8.22 M gates and 5 Mb SRAM in the chip of 3.35 x 3.35 mm(2). The simulated power consumption at 133 MHz were 528 mW and 702 mW at the slow process condition (SS, 0.81 V, -40 degrees C) and typical process condition (TT, 0.9 V, 25 degrees C), respectively.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2017, IEICE ELECTRONICS EXPRESS, 14(15) (15), 1 - 12, English
    [Refereed]
    Scientific journal

  • UMEKI Yohei, IZUMI Shintaro, KITAHARA Hiroto, NAKAGAWA Tomoki, YANAGIDA Kouji, YOSHIMOTO Shusuke, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, KIMURA Hiromitsu, MARUMOTO Kyoji, FUCHIKAMI Takaaki, FUJIMORI Yoshikazu
    神戸大学大学院工学研究科, Feb. 2017, Memoirs of the Graduate Schools of Engineering and SystemInformatics Kobe University, no. 8, pp. 5-8, Feb. 2017., 8, English
    [Refereed]
    Research institution

  • A 19-mu A Metabolic Equivalents Monitoring SoC using Adaptive Sampling
    Tsukahara, Mio, Izumi, Shintaro, Nakanashi, Motofumi, Kawaguchi, Hiroshi, Yoshimoto, Masahiko, Kimura, Hiromitsu, Maromoto, Kyoji, Fuchikami, Takaaki, Fujimori, Yoshikazu
    This paper presents a low-power metabolic equivalents (METs) estimation SoC for monitoring physical activity with wearable sensor. Long-term continuous METs monitoring can contribute to detection of non-communicable diseases. The proposed SoC consists of a non-volatile CPU and a dedicated hardware for heart rate extraction and METs estimation to reduce the power consumption. A test chip is fabricated in a 130-nm CMOS process. Evaluation results show that the proposed system, which consists of the test chip and an accelerometer, consumes about 19-mu A on average.
    IEEE, 2017, 2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 37 - 38, English
    [Refereed]
    International conference proceedings

  • A LAYER-BLOCK-WISE PIPELINE FOR MEMORY AND BANDWIDTH REDUCTION IN DISTRIBUTED DEEP LEARNING
    Mori, Haruki, Youkawa, Tetsuya, Izumi, Shintaro, Yoshimoto, Masahiko, Kawaguchi, Hiroshi, Inoue, Atsuki
    This paper describes a pipelined stochastic gradient descent (SGD) algorithm and its hardware architecture with a memory distributed structure. In the proposed architecture, a pipeline stage takes charge of multiple layers: a "layer block." The layer-block-wise pipeline has much less weight parameters for network training than conventional multithreading because weight memory is distributed to workers assigned to pipeline stages. The memory capacity of 2.25 GB for the four-stage proposed pipeline is about half of the 3.82 GB for multithreading when a batch size is 32 in VGG-F. Unlike multithreaded data parallelism, no parameter server for weight update or shared I/O data bus is necessary. Therefore, the memory bandwidth is drastically reduced. The proposed four-stage pipeline only needs memory bandwidths of 36.3 MB and 17.0 MB per batch, respectively, for forward propagation and backpropagation processes, whereas four-thread multithreading requires a bandwidth of 974 MB overall for send and receive processes to unify its weight parameters. At the parallelization degree of four, the proposed pipeline maintains training convergence by a factor of 1.12, compared with the conventional multithreaded architecture although the memory capacity and the memory bandwidth are decreased.
    IEEE, 2017, 2017 IEEE 27TH INTERNATIONAL WORKSHOP ON MACHINE LEARNING FOR SIGNAL PROCESSING, English
    [Refereed]
    International conference proceedings

  • Takumi Katsuura, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Shusuke Yoshimoto, Tsuyoshi Sekitani
    IEEE, 2017, Proc. of IEEE Biomedical Circuits and Systems Conference (BioCAS), pp. 721–724, Oct. 2017, 1 - 4, English
    [Refereed]
    International conference proceedings

  • Multimodal Cardiovascular Information Monitor using Piezoelectric Transducers for Wearable Healthcare
    Okano, Takaaki, Izumi, Shintaro, Katsuura, Takumi, Kawaguchi, Hiroshi, Yoshimoto, Masahiko
    This report describes a multimodal cardiovascular information measurement method using a wearable sensor device. With the progress of aging populations worldwide, cardiovascular diseases are increasing. Such diseases account for a large share of causes of death and constitute the main cause of long-term care. Along with the miniaturization and longer life of measuring instruments in recent years, constant monitoring of biological information using a wearable biosensor has attracted attention for the prevention and early detection of cardiovascular diseases. However, today's wearable devices can only measure limited cardiovascular information such as the heart rate. Therefore, we propose a method that can simultaneously measure heart rate variation, pulse wave propagation velocity, and blood flow velocity with a single device equipped with a piezoelectric transducer array.
    IEEE, 2017, 2017 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), English
    [Refereed]
    International conference proceedings

  • FPGA Implementation of Object Recognition Processor for HDTV Resolution Video Using Sparse FIND Feature
    Nishizumi, Yuri, Matsukawa, Go, Kajihara, Koichi, Kodama, Taisuke, Izumi, Shintaro, Kawaguchi, Hiroshi, Nakanishi, Chikako, Goto, Toshio, Kato, Takeo, Yoshimoto, Masahiko
    This paper describes FPGA implementation of object recognition processor for HDTV resolution 30 fps video using the Sparse FIND feature. Two-stage feature extraction processing by HOG and Sparse FIND, a highly parallel classification in the support vector machine (SVM), and a block-parallel processing for RAM access cycle reduction are proposed to perform a real time object recognition with enormous computational complexity. From implementation of the proposed architecture in the FPGA, it was confirmed that detection using the Sparse FIND feature was performed for HDTV images at 47.63 fps, on average, at 90 MHz. The recognition accuracy degradation from the original Sparse FIND-base object detection algorithm implemented on software was 0.5%, which shows that the FPGA system provides sufficient accuracy for practical use.
    IEEE, 2017, 2017 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), English
    [Refereed]
    International conference proceedings

  • Yuki Nagasato, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    IEEE, 2017, The 13th IEEE BioMedical Circuits and Systems Conference(BioCAS), pp.400-403, Oct. 2017., 1 - 4, English
    [Refereed]
    International conference proceedings

  • A METABOLIC EQUIVALENTS ESTIMATION ALGORITHM USING TRIAXIAL ACCELEROMETER AND ADAPTIVE SAMPLING FOR WEARABLE DEVICES
    Nakanishi, Motofumi, Izumi, Shintaro, Tsukahara, Mio, Kawaguchi, Hiroshi, Yoshimoto, Masahiko
    This study describes a low-power metabolic equivalents estimation method. Low-power consumption is a key feature of wearable devices because it requires longer battery-life with small battery capacity. The proposed algorithm employs adaptive sampling for reducing the energy consumed by an accelerometer and by signal processing. The sampling frequency is adaptively changed according to an estimated physical activity group. Evaluation of the results shows that the sampling rate can be reduced by 86%, and there is 0.1 metabolic equivalents RMS error compared with a reference values. And it is seen that there is no significant error compared with other prediction methods in spite of very low average sampling frequency with proposed algorithm.
    IEEE, 2017, 2017 IEEE LIFE SCIENCES CONFERENCE (LSC), 107 - 110, English
    [Refereed]
    International conference proceedings

  • Multimodal Cardiovascular Information Monitor using Piezoelectric Transducers for Wearable Healthcare
    Okano, Takaaki, Izumi, Shintaro, Katsuura, Takumi, Kawaguchi, Hiroshi, Yoshimoto, Masahiko
    This report describes a multimodal cardiovascular information measurement method using a wearable sensor device. With the progress of aging populations worldwide, cardiovascular diseases are increasing. Such diseases account for a large share of causes of death and constitute the main cause of long-term care. Along with the miniaturization and longer life of measuring instruments in recent years, constant monitoring of biological information using a wearable biosensor has attracted attention for the prevention and early detection of cardiovascular diseases. However, today's wearable devices can only measure limited cardiovascular information such as the heart rate. Therefore, we propose a method that can simultaneously measure heart rate variation, pulse wave propagation velocity, and blood flow velocity with a single device equipped with a piezoelectric transducer array.
    IEEE, 2017, 2017 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), 1 - 10, English
    [Refereed][Invited]
    International conference proceedings

  • 消化管内へ留置する飲み込型センサの検討
    NAKAMURA Ryota, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, OHTA Hidetoshi
    Sep. 2016, 電気学会C部門大会, 2016年9月1日,神戸, 2016, Japanese
    Symposium

  • 加速度センサを用いた低消費電力運動強度推定アルゴリズム
    TSUKAHARA Mio, NAKANISHI Motofumi, IZUMI Shintaro, NAKAI Yozaburo, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Sep. 2016, 電気学会C部門大会, 2016年9月1日,神戸., 2016, Japanese
    Symposium

  • 加速度センサを用いた低消費電力運動強度推定アルゴリズム
    TSUKAHARA Mio, NAKANISHI Motofumi, IZUMI Shintaro, NAKAI Yozaburo, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Sep. 2016, IEICEソサイエティ大会, 2016年9月21日,札幌, 2016, Japanese
    Symposium

  • Ryota Nakamura, Shintaro Izumi, Hiroshi Kawaguchi, Hidetoshi Ohta, Masahiko Yoshimoto
    This paper presents a swallowable sensor device that can be ingested orally, later arriving to the stomach, where the device can indwell for a long term and can be egested at any time after it is triggered using wireless communication. This device can inflate a silicone balloon in the gastrointestinal tract using a chemical reaction. The balloon can be deflated later using electrolysis of water at the time of egestion. A motorless chemical-reaction-based egestion method is proposed to minimize the sensor device size. This device can achieve long-term monitoring in the gastrointestinal tract.
    Aug. 2016, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2016, 3039 - 3042, English, International magazine
    [Refereed]
    Scientific journal

  • Mio Tsukahara, Motofumi Nakanishi, Shintaro Izumi, Yozaburo Nakai, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a proposed low-power metabolic equivalent estimation algorithm that can calculate the value of metabolic equivalents (METs) from triaxial acceleration at an adaptively changeable sampling rate. This algorithm uses four rates of 32, 16, 8 and 4 Hz. The mode of switching them is decided from synthetic acceleration. Applying this proposed algorithm to acceleration measured for 1 day, we achieved the low root mean squared error (RMSE) of calculated METs, with current consumption that was 41.5 % of the value at 32 Hz, and 75.4 % of the value at 16 Hz.
    Aug. 2016, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2016, 1878 - 1881, English, International magazine
    [Refereed]
    Scientific journal

  • Haruki Mori, Yohei Umeki, Shusuke Yoshimoto, Shintaro Izumi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using 28-nm FD-SOI process technology. Our proposed SRAM accommodates eight-transistor bit cells comprising one-write/two-read ports and a majority logic circuit to save active energy. The test chip operates at a supply voltage of 0.46V and access time of 140 ns. The minimum energy point is a supply voltage of 0.54V and an access time of 55 ns (= 18.2 MHz), at which 484 fJ/cycle in a write operation and 650 fJ/cycle in a read operation are achieved assisted by majority logic. These factors are 69% and 47% smaller than those in a conventional 6T SRAM using the 28-nm FD-SOI process technology.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Aug. 2016, IEICE TRANSACTIONS ON ELECTRONICS, E99C(8) (8), 901 - 908, English
    [Refereed]
    Scientific journal

  • Go Matsukawa, Yuta Kimi, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    As technology nodes continue to shrink, the impact of radiation-induced soft error on processor reliability increases. Estimation of processor reliability and identification of vulnerable flip-flops requires accurate soft error rate (SER) analysis techniques. This paper presents a proposal for a soft error propagation analysis technique. We specifically examine single event upset (SEU) occurring at a flip-flop in sequential circuits. When SEUs propagate in sequential circuits, the faults can be masked temporally and logically. Conventional soft error propagation analysis techniques do not consider error convergent timing on re-convergent paths. The proposed technique can analyze soft error propagation while considering error-convergent timing on a re-convergent path by combinational analysis of temporal and logical effects. The proposed technique also considers the case in which the temporal masking is disabled with an enable signal of the erroneous flip-flop negated. Experimental results show that the proposed technique improves inaccuracy by 70.590, on average, compared with conventional techniques using ITC 99 and ISCAS 89 benchmark circuits when the enable probability is 1/3, while the runtime overhead is only 1.79( on average.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jun. 2016, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E99A(6) (6), 1198 - 1205, English
    [Refereed]
    Scientific journal

  • 298-fJ/writecycle 650-fJ/readcycle を実現する画像処理プロセッサ向け 28-nm FD-SOI 8T 3ポートSRAM
    MORI Haruki, NAKAGAWA Tomoki, KITAHARA Yuki, KAWAMOTO Yuta, TAKAGI Kenta, YOSHIMOTO Shusuke, IZUMI Shintaro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    電子情報通信学会, Apr. 2016, 信学技報, vol.116, no.3, pp.13-16, 2016年4月14日,東京., 116(3) (3), 13 - 16, Japanese
    Symposium

  • Process variation tolerant counter base read circuit for low-voltage operating STT-MRAM
    UMEKI Yohei, YANAGIDA Kouji, KUROTSU Hiroaki, KITAHARA Hiroto, MORI Haruki, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, YOSHIMOTO Shusuke, TSUNODA Koji, SUGII Toshihiro
    Mar. 2016, DATE EMS Workshop, Mar. 2016, English
    [Refereed]
    International conference proceedings

  • Capacitively Coupled ECG Sensor using a Single Electrode with Adaptive Power-Line Noise Cancellation
    Yuta Kawamoto, Shintaro Izumi, Yoshito Tanaka, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This report describes a small heartbeat monitoring system using capacitively coupled ECG sensors. Capacitively coupled sensors using an insulated electrode have been proposed to obtain ECG signals without pasting electrodes directly onto the skin. Although the sensors have better usability than conventional ECG sensors, it is difficult to remove noise contamination. Power-line noise can be a severe noise source that increases when only a single electrode is used. However, a multiple electrode system degrades usability. To address this problem, we propose a noise cancellation technique using an adaptive noise feedback approach, which can improve the availability of the capacitive ECG sensor using a single electrode. An instrumental amplifier is used in the proposed method for the first stage amplifier instead of voltage follower circuits. A microcontroller predicts the noise waveform from an ADC output. To avoid saturation caused by power-line noise, the predicted noise waveform is fed back to an amplifier input through a DAC. We implemented the prototype sensor system to evaluate the noise reduction performance. Measurement results using a prototype board show that the proposed method can suppress 28-dB power-line noise.
    IEEE, 2016, 2016 3RD IEEE EMBS INTERNATIONAL CONFERENCE ON BIOMEDICAL AND HEALTH INFORMATICS, 212 - 215, English
    [Refereed][Invited]
    International conference proceedings

  • An Soft Error Propagation Analysis Considering Logical Masking Effect on Re-convergent Path
    Shuhei Yoshida, Go Matsukawa, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents an accurate soft error propagation analysis technique. Especially, we focus on Single Event Upset (SEU) in flip-flop. The proposed technique can calculate the accurate error propagation probability considering logical masking on re-convergent paths with SAT solver efficiently. Experimental result shows that the proposed technique improves the computation time by 94.6% compared with the method with only SAT solver and the accuracy by 93.3% compared with the conventional method respectively.
    IEEE, 2016, 2016 IEEE 22ND INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS), 13 - 16, English
    [Refereed]
    International conference proceedings

  • Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii
    In this paper, in order to realize 0.4V operation of STT-MRAM, we propose the counter base read circuit. The proposed read circuit has tolerance for process variation and temperature fluctuation by changing dynamically the load curve in a time-axis at the read operation. We confirmed that the proposed read circuit can operate at the conditions of five process corners (TT, FF, FS, SF, and SS) and three temperatures (-20°C, 25°C, and 100°C) by HSPICE simulations. At the condition of TT corner and 25°C, read time of the proposed circuit is 271 ns, and energy consumption is 1.05 pJ at "1" read operation and 1.23 pJ at "0" read operation.
    Information Processing Society of Japan, 2016, IPSJ Transactions on System LSI Design Methodology, 9, 79 - 83, English
    [Refereed]
    Scientific journal

  • Adaptive Noise Cancellation Method for Capacitively Coupled ECG Sensor using Single Insulated Electrode
    Yoshito Tanaka, Shintaro Izumi, Yuta Kawamoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a noise reduction method for capacitively coupled ECG sensors. Capacitively coupled sensors using an insulated electrode have been proposed to obtain ECG signals without pasting electrodes directly onto the skin. It can achieve better usability than conventional ECG sensors. However, it is difficult to remove noise contamination, because the high input impedance and low input capacitance are required to realize the capacitively coupled ECG sensor. Especially, base-line drift and power-line noise are more serious problem when using a single electrode structure. To address this problem, we propose a noise cancellation technique using an adaptive noise feedback approach, which can improve the availability of the capacitive ECG sensor using a single electrode. An instrumental amplifier is used in the proposed method for the first stage amplifier instead of voltage follower circuits. A microcontroller predicts the noise waveform from an ADC output. To avoid saturation caused by base-line drift and power-line noise, the predicted noise waveform is fed back to an amplifier input through a DAC. We implemented the prototype sensor system to evaluate the noise reduction performance. Measurement results show that the proposed method can suppress both of base-line drift and power-line noise simultaneously.
    IEEE, 2016, PROCEEDINGS OF 2016 IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE (BIOCAS), 296 - 299, English
    [Refereed]
    International conference proceedings

  • Daichi Matsunaga, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a non-contact heart rate monitoring system using a microwave Doppler sensor. It can achieve better usability than conventional heart rate sensors, which require direct skin contact. The objective of this work is to detect an instantaneous heart rate using this non-contact system. The instantaneous heart rate can contribute to prevent heart disasters and to detect mental stress state. However, the Doppler sensor system is very sensitive and it can be easily contaminated by a body motion artifact including breathing. To address this problem, we introduce time frequency analysis with short window length. The heart rate extraction performance with various parameters is evaluated using a measured Doppler sensor output with 4 subjects. The proposed method achieves 4.5-ms RMS error with 50-cm distance for heart rate extraction from 60 s duration data.
    IEEE, 2016, 2016 IEEE 16TH INTERNATIONAL CONFERENCE ON BIOINFORMATICS AND BIOENGINEERING (BIBE), 172 - 175, English
    [Refereed]
    International conference proceedings

  • An Low-Energy 8T Dual-Port SRAM for Image Processor with Selective Sourceline Drive Scheme in 28-nm FD-SOI Process Technology
    Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents a low-energy and low-voltage 64-kb 8T dual-port image memory in a 28-nm FD-SOI process technology. Our proposed SRAM adopts the selective sourceline drive (SSD) scheme and the consecutive data write technique for improving active energy efficiency at the low voltage. We fabricated a 64-Kb 8T dual-port SRAM in the 28-nm FD-SOI process technology; the test chip exhibits 0.48 V operation and an access time of 135 ns. The energy minimum point is at a supply voltage of 0.56 V and an access time of 35 ns, where 265.0 fJ/cycle in write operation and 389.6 fJ/cycle in read operation are achieved; these factors are 30% and 26% smaller than those in the 8T dual-port SRAM with the conventional selective sourceline control (SSLC) scheme, respectively.
    IEEE, 2016, 23RD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS CIRCUITS AND SYSTEMS (ICECS 2016), 532 - 535, English
    [Refereed]
    International conference proceedings

  • A 15-mu A Metabolic Equivalents Monitoring System using Adaptive Acceleration Sampling and Normally Off Computing
    Mio Tsukahara, Shintaro Izumi, Motofumi Nakanishi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori
    This paper describes a low-power metabolic equivalents (METs) estimation method for monitoring physical activity. Long-term continuous METs monitoring can contribute to detection of non-communicable diseases. The proposed system consists of dedicated METs estimation hardware and a nonvolatile CPU. A test is fabricated in a 130-nm CMOS with a ferroelectric capacitor process. Evaluation results show that the proposed system, which consists of the test chip and an accelerometer, requires about 15-A on average.
    IEEE, 2016, 23RD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS CIRCUITS AND SYSTEMS (ICECS 2016), 61 - 64, English
    [Refereed]
    International conference proceedings

  • A. Tanaka, T. Douseki, Y. Umeki, H. Kawaguchi, M. Yoshimoto, K. Tsunoda, T. Sugii
    A batteryless sensorless bicycle speed recorder system with a hub dynamo that functions as both a power source and a speed sensor has been developed. The hub dynamo produces a voltage waveform with more than ten AC cycles per rotation of the bicycle wheel, which enables precise determination of speed and acceleration. The data is stored in a spin-transfer-torque magnetoresistive random-access memory (STT-MRAM) that has perpendicular magnetic tunnel junctions (MTJs) and an infinite rewriting capability. For writing operation, the MRAM employs an intermittent write operation, which involves high-speed writing with a duty cycle of less than 0.01%. This reduces the average power dissipation of the MRAM to that of the standby mode. A road test showed that a fabricated speed recorder mounted on a bicycle stored and reproduced accurate values of a large acceleration and its duration when the brakes were suddenly applied while the bicycle was being ridden.
    Institute of Electrical and Electronics Engineers Inc., Dec. 2015, 2015 IEEE SENSORS - Proceedings, English
    [Refereed]
    International conference proceedings

  • Keisuke Okuno, Shintaro Izumi, Kana Masaki, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This report describes an all-digital phase-locked loop (ADPLL) using a temperature compensated settling time reduction technique. The novelty of this work is autonomous oscillation control word estimation without a look-up table or memory circuits. The proposed ADPLL employs a multi-phase digitally controlled oscillator (DCO). In the proposed estimation method, the optimum oscillator tuning word (OTW) is estimated from the DCO frequency characteristic in the setup phase of ADPLL. The proposed ADPLL, which occupies 0.27 x 0.36mm(2), is fabricated by a 65 nm CMOS process. The temperature compensation PLL controller (TCPC) is implemented using an FPGA. Although the proposed method has 20% area overhead, measurement results show that the 47% settling time is reduced. The average settling time at 25 degrees C is 3 mu s. The average reduction energy is at least 42% from 0 degrees C to 100 degrees C.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Dec. 2015, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E98A(12) (12), 2592 - 2599, English
    [Refereed]
    Scientific journal

  • Shintaro Izumi, Ken Yamashita, Masanao Nakano, Shusuke Yoshimoto, Tomoki Nakagawa, Yozaburo Nakai, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto
    This paper describes an electrocardiograph (ECG) monitoring SoC using a non-volatile MCU (NVMCU) and a noise-tolerant instantaneous heartbeat detector. The novelty of this work is the combination of the non-volatile MCU for normally off computing and a noise-tolerant-QRS (heartbeat) detector to achieve both low-power and noise tolerance. To minimize the stand-by current of MCU, a non-volatile flip-flop and a 6T-4C NVRAM are used. Proposed plate-line charge-share and bit-line non-precharge techniques also contribute to mitigate the active power overhead of 6T-4C NVRAM. The proposed accurate heartbeat detector uses coarse-fine autocorrelation and a template matching technique. Accurate heartbeat detection also contributes system-level power reduction because the active ratio of ADC and digital block can be reduced using heartbeat prediction. Measurement results show that the fully integrated ECG-SoC consumes 6.14 μ A including 1.28- μA non-volatile MCU and 0.7- μA heartbeat detector.
    IEEE, Oct. 2015, IEEE transactions on biomedical circuits and systems, 9(5) (5), 641 - 51, English, International magazine
    [Refereed]
    Scientific journal

  • Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto
    To prevent lifestyle diseases, wearable bio-signal monitoring systems for daily life monitoring have attracted attention. Wearable systems have strict size and weight constraints, which impose significant limitations of the battery capacity and the signal-to-noise ratio of bio-signals. This report describes an electrocardiograph (ECG) processor for use with a wearable healthcare system. It comprises an analog front end, a 12-bit ADC, a robust Instantaneous Heart Rate (IHR) monitor, a 32-bit Cortex-M0 core, and 64 Kbyte Ferroelectric Random Access Memory (FeRAM). The IHR monitor uses a short-term autocorrelation (STAC) algorithm to improve the heart-rate detection accuracy despite its use in noisy conditions. The ECG processor chip consumes 13.7 μA for heart rate logging application.
    IEEE, Oct. 2015, IEEE transactions on biomedical circuits and systems, 9(5) (5), 733 - 42, English, International magazine
    [Refereed]
    Scientific journal

  • Motofumi Nakanishi, Shintaro Izumi, Sho Nagayoshi, Hironori Sato, Hiroshi Kawaguchi, Masahiko Yoshimoto, Takafumi Ando, Satoshi Nakae, Chiyoko Usui, Tomoko Aoyama, Shigeho Tanaka
    As described in this paper, a physical activity classification algorithm is proposed for energy expenditure estimation. The proposed algorithm can improve the classification accuracy using both the triaxial acceleration and heart rate. The optimal classification also contributes to improvement of the accuracy of the energy expenditures estimation. The proposed algorithm employs three indices: the heart rate reserve (%HRreserve), the filtered triaxial acceleration, and the ratio of filtered and unfiltered acceleration. The percentage HRreserve is calculated using the heart rate at rest condition and the maximum heart rate, which is calculated using Karvonen Formula. Using these three indices, a decision tree is constructed to classify physical activities into five classes: sedentary, household, moderate (excluding locomotive), locomotive, and vigorous. Evaluation results show that the average classification accuracy for 21 activities is 91%.
    37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society(EMBC), Aug. 2015, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2015, 510 - 3, English, International magazine
    [Refereed][Invited]
    International conference proceedings

  • Taisuke Kodama, Shintaro Izumi, Kana Masaki, Hiroshi Kawaguchi, Kazusuke Maenaka, Masahiko Yoshimoto
    Recently, given Japan's aging society background, wearable healthcare devices have increasingly attracted attention. Many devices have been developed, but most devices have only a sensing function. To expand the application area of wearable healthcare devices, an interactive communication function with the human body is required using an actuator. For example, a device must be useful for medication assistance, predictive alerts of a disease such as arrhythmia, and exercise. In this work, a haptic stimulus actuator using a piezoelectric pump is proposed to realize a large displacement in wearable devices. The proposed actuator drives tactile sensation of the human body. The measurement results obtained using a sensory examination demonstrate that the proposed actuator can generate sufficient stimuli even if adhered to the chest, which has fewer tactile receptors than either the fingertip or wrist.
    37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society(EMBC), Aug. 2015, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2015, 1172 - 5, English, International magazine
    [Refereed][Invited]
    Scientific journal

  • Tomoki Nakagawa, Shintaro Izumi, Koji Yanagida, Yuki Kitahara, Shusuke Yoshimoto, Yohei Umeki, Haruki Mori, Hiroto Kitahara, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Masahiko Yoshimoto
    This report describes a low power 6T-4C nonvolatile memory design using a bit-line non-precharge and plate-line charge-share techniques. Two proposed techniques contribute to decrease energy consumption. The bit-line non-precharge technique can reduce 73% of write energy consumption and 76% of read energy consumption. The plate-line charge-share technique can reduce 22% of store energy consumption and 11% of recall energy consumption.
    Institute of Electrical and Electronics Engineers Inc., Jul. 2015, Proceedings - IEEE International Symposium on Circuits and Systems, 2015-, 2904 - 2907, English
    [Refereed]
    International conference proceedings

  • Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    We present a low-jitter design for a 10-bit second-order frequency shift oscillator time-to-digital converter (FSOTDC). As described herein, we analyze the relation between performance and FSOTDC parameters and provide insight to support the design of the FSOTDC. Results show that an oscillator jitter limits the FSOTDC resolution, particularly during the first stage. To estimate and design an FSOTDC, the frequency shift oscillator requires an inverter of a certain size. In a standard 65-nm CMOS process, an SNDR of 64 dB is achievable at an input signal frequency of 10 kHz and a sampling clock of 2MHz. Measurements of the test chip confirmed that the measurements match the analyses.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jul. 2015, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E98A(7) (7), 1475 - 1481, English
    [Refereed]
    Scientific journal

  • Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    We present an I/O-size second-order analog to digital converter (ADC) combined with a time-to-digital converter (TDC) and a voltage-to-time converter (VTC). Our proposed VTC is optimized for metal-oxide-metal (MOM) capacitances, and is charged to the MOM capacitances by an input voltage. In a standard 65-nm CMOS process, a signal to noise and distortion ratio (SNDR) of 50 dB (8 bits) is achievable at an input signal frequency of 78 kHz and a sampling rate of 20 MHz, where the respective area and power are 6468 mm(2) and 509 mu W. The measured maximum integral nonlinearity (INL) of the proposed ADC is 1.41 LSBs. The active area of the proposed ADC is smaller than an I/O buffer. The proposed ADC is useful as an ADC I/O.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jun. 2015, IEICE TRANSACTIONS ON ELECTRONICS, E98C(6) (6), 489 - 495, English
    [Refereed]
    Scientific journal

  • Shintaro Izumi, Masanao Nakano, Ken Yamashita, Yozaburo Nakai, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This report describes a robust method of instantaneous heart rate (IHR) extraction from noisy electrocardiogram (ECG) signals. Generally, R-waves are extracted from ECG using a threshold to calculate the IHR from the interval of R-waves. However, noise increases the incidence of misdetection and false detection in wearable healthcare systems because the power consumption and electrode distance are limited to reduce the size and weight. To prevent incorrect detection, we propose a short-time autocorrelation (STAC) technique. The proposed method extracts the IHR by determining the search window shift length which maximizes the correlation coefficient between the template window and the search window. It uses the similarity of the QRS complex waveform beat-by-beat. Therefore, it has no threshold calculation process. Furthermore, it is robust against noisy environments. The proposed method was evaluated using MIT-BIH arrhythmia and noise stress test databases. Simulation results show that the proposed method achieves a state-of-the-art success rate of IHR extraction in a noise stress test using a muscle artifact and a motion artifact.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, May 2015, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E98D(5) (5), 1095 - 1103, English
    [Refereed]
    Scientific journal

  • Go Matsukawa, Yohei Nakata, Yasuo Sugure, Shigeru Oho, Yuta Kimi, Masafumi Shimozawa, Shuhei Yoshida, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents a novel architecture for a fault-tolerant and dual modular redundancy (DMR) system using a checkpoint recovery approach. The architecture features exploitation of SRAM with simultaneous copy and instantaneous compare function. It can perform low-latency data copying between dual cores. Therefore, it can carry out fast backup and rollback. Furthermore, it can reduce the power consumption during data comparison process compared to the cyclic redundancy check (CRC). Evaluation results show that, compared with the conventional checkpoint/restart DMR, the proposed architecture reduces the cycle overhead by 97.8% and achieves a 3.28% low-latency execution cycle even if a one-time fault occurs when executing the task. The proposed architecture provides high reliability for systems with a real-time requirement.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2015, IEICE TRANSACTIONS ON ELECTRONICS, E98C(4) (4), 333 - 339, English
    [Refereed]
    Scientific journal

  • A 298-fJ/writecycle 650-fJ/readcycle 8T Three-Port SRAM in 28-nm FD-SOI Process Technology for Image Processor
    Haruki Mori, T. Nakagawa, Y. Kitahara, Y. Kawamoto, K. Takagi, S. Yoshimoto, S. Izumi, K. Nii, H. Kawaguchi, M. Yoshimoto
    This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using a 28-nm FD-SOI process technology. Our proposed SRAM accommodates eight-transistor bitcells comprising one-write/two-read ports and a majority logic circuit to save active energy. The test chip can operate at a supply voltage of 0.46 V and an access time of 140 ns. The energy minimum point is a supply voltage of 0.54 V and an access time of 55 ns (= 18.2 MHz), at which 298 fJ/cycle in a write operation and 650 fJ/cycle in a read operation are achieved with the help of the majority logic; these factor are 87% and 52% smaller than those in a 28-nm FD-SOI 6T SRAM.
    IEEE, 2015, 2015 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), English
    [Refereed]
    International conference proceedings

  • Kimi, Yuta, Matsukawa, Go, Yoshida, Shuhei, Izumi, Shintaro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko
    As technology nodes continue to shrink, the impact of radiation-induced soft error on processor reliability increases. Estimation of processor reliability and identification of vulnerable flip-flops requires accurate soft error rate (SER) analysis techniques. This paper presents a proposal for a soft error propagation analysis technique. We specifically examine single event upset (SEU) occurring at a flip-flop in sequential circuits. When SEUs propagate in sequential circuits, the faults can be masked temporally and logically. Conventional soft error propagation analysis techniques do not consider error convergent timing on re-convergent paths. The proposed technique can analyze soft error propagation while considering error-convergent timing on a re-convergent path by combinational analysis of temporal and logical effects. The proposed technique also considers the case in which the temporal masking is disabled with an enable signal of the erroneous flip-flop negated. Experimental results show that the proposed technique improves inaccuracy by 70.5%, on average, compared with conventional techniques using ITC 99 and ISCAS 89 benchmark circuits when the enable probability is 1/3, while the runtime overhead is only 1.7% on average.
    IEEE COMPUTER SOC, 2015, 2015 IEEE 24TH ASIAN TEST SYMPOSIUM (ATS), 139 - 144, English
    [Refereed]
    International conference proceedings

  • A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance with Bit-Enhancing Memory and On-Chip Diagnosis Structures Delivering x91 Failure Rate Improvement
    Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents a resilient cache memory for dynamic variation tolerance in a 40-nm CMOS. The cache can perform sustained operations under a large-amplitude voltage droop. To realize sustained operation, the resilient cache exploit 7T/14T bit-enhancing SRAM and on-chip voltage/temperature monitoring circuit. 7T/14T bitenhancing SRAM can reconfigure itself dynamically to a reliable bit-enhancing mode. An on-chip monitoring circuit can sense a precise supply voltage level of a power rail of the cache. The proposed cache can dynamically change its operation mode using the voltage/temperature monitoring result and can operate reliably under a large-amplitude voltage droop. Experimental result shows that it does not fail with 25% and 30% droop of Vdd and it provides 91 times better failure rate with a 35% droop of Vdd compared with the conventional design. The processor simulator shows that the proposed cache running in the bit-enhancing mode results in 2.88% IPC loss on average.
    IEEE, 2015, PROCEEDINGS OF THE FIFTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2014), 16 - +, English
    [Refereed]
    International conference proceedings

  • A Negative-Resistance Sense Amplifier for Low-Voltage Operating STT-MRAM
    Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, Koji Tsunoda, Toshihiro Sugii
    Jan. 2015, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) University LSI Design Contest, pp. 8 - 9, English
    [Refereed]
    International conference proceedings

  • A 14 mu A ECG Processor with Noise Tolerant Heart Rate Extractor and FeRAM for Wearable Healthcare Systems
    Yozaburo Nakai, Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This report describes an electrocardiograph (ECG) processor for use with a wearable healthcare system. It comprises an analog front end, a 12-bit ADC, a robust Instantaneous Heart Rate (IHR) monitor, a 32-bit Cortex-M0 core, and 64 Kbyte Ferroelectric Random Access Memory (FeRAM). The IHR monitor uses a short-term autocorrelation (STAC) algorithm to improve the heart-rate detection accuracy despite its use in noisy conditions. The ECG processor chip consumes 13.7 mu A for heart rate logging application.
    IEEE, 2015, 2015 20TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 16 - 17, English
    [Refereed]
    International conference proceedings

  • A Low Power 6T-4C Non-volatile Memory using Charge Sharing and Non-precharge Techniques
    Tomoki Nakagawa, Shintaro Izumi, Koji Yanagida, Yuki Kitahara, Shusuke Yoshimoto, Yohei Umeki, Haruki Mori, Hiroto Kitahara, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Masahiko Yoshimoto
    This report describes a low power 6T-4C nonvolatile memory design using a bit-line non-precharge and plate-line charge-share techniques. Two proposed techniques contribute to decrease energy consumption. The bit-line non-precharge technique can reduce 73% of write energy consumption and 76% of read energy consumption. The plate-line charge-share technique can reduce 22% of store energy consumption and 11% of recall energy consumption.
    IEEE, 2015, 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2904 - 2907, English
    [Refereed][Invited]
    International conference proceedings

  • An Accurate Soft Error Propagation Analysis Technique Considering Temporal Masking Disablement
    Yuta Kimi, Go Matsukawa, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents an accurate soft error propagation analysis technique for processor SER evaluation. Especially, we focus on Single Event Upset (SEU) in flip-flop which is a main contributor of processor SER. SEUs in flip-flops propagate combinational circuits with temporal masking and logical masking effects. The temporal masking is disabled when the erroneous flip-flop is disabled. The proposed technique is able to evaluate temporal masking disablement by combined analysis of temporal and logical effects. Experimental result shows that the proposed technique reduces 49.87% inaccuracy in average compared with the technique ignoring temporal masking disablement when the enabled probability of the erroneous flip-flop is 0.1.
    IEEE, 2015, 2015 IEEE 21ST INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), 23 - 25, English
    [Refereed][Invited]
    International conference proceedings

  • Daichi Matsunag, Shintaro Izumi, Keisuke Okuno, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a non-contact and noise-tolerant heart beat monitoring system. The proposed system comprises a microwave Doppler sensor and range imagery using Microsoft Kinect™. The possible application of the proposed system is a driver health monitoring. We introduce the sensor fusion approach to minimize the heart beat detection error. The proposed algorithm can subtract a body motion artifact from Doppler sensor output using time-frequency analysis. The body motion artifact is a crucially important problem for biosignal monitoring using microwave Doppler sensor. The body motion speed is obtainable from range imagery, which has 5-mm resolution at 30-cm distance. Measurement results show that the success rate of the heart beat detection is improved about 75% on average when the Doppler wave is degraded by the body motion artifact.
    37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society(EMBC), 2015, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2015, 6118 - 21, English, International magazine
    [Refereed][Invited]
    Scientific journal

  • A Ferroelectric-Based Non-Volatile Flip-Flop for Wearable Healthcare Systems
    Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Hiromitsu Kimura, Takaaki Fuchikami, Kyoji Marumoto, Yoshikazu Fujimori
    The low-power FE-based NVFF is developed by reduction of FE capacitor size. In the proposed NVFF, coupled FE capacitors with complementary data storage are introduced. The use of complementarily stored data in coupled FE capacitors achieves 88% FE capacitor size reduction while maintaining a wide read voltage margin of 240 mV (minimum) at 1.5 V, which results in 2.4 pJ low access energy with 10-year, 85 degrees C data retention capability. An access speed of FE capacitors can be adaptively changed according to required retention time, which becomes 1.6 mu s for 10-year data retention, and 170 ns for 10-hour data retention. Especially, short-term data retention is suitable for power gating implementation. As a design example, the proposed NVFF is applied to 32-bit CPU in a vital sensor LSI for wearable healthcare applications. The vital sensor LSI consists of an electrocardiogram (ECG) sensor, the 32-bit CPU core with NVFF, and a 16-Kbyte FE-based non-volatile memory (NVRAM) for data and instruction. Because the frequency range of vital signals is low, both the standby power reduction and sleep time maximization is important to system level power reduction. Its standby current can be cut when the state of CPU core transits to deep sleep. Then the data in the memory and register values of CPU core in the NVFF are stored sequentially to ferroelectric capacitors. The implementation result demonstrates that 87% of total power dissipation during measurement of the heart rate can be reduced with 64% area overhead using 130-nm CMOS with Pb(Zr,Ti)O-3(PZT) thin films.
    IEEE, 2015, 2015 15TH NON-VOLATILE MEMORY TECHNOLOGY SYMPOSIUM (NVMTS), pp.1 - 4, English
    [Refereed][Invited]
    International conference proceedings

  • 不揮発マイコンを用いたノーマリーオフ生体計測SoC
    松永 大地, 中井 陽三郎, 河本 優太, 中川 知己, 奥野 圭祐, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO
    Dec. 2014, 信学技報, vol. 114(no. 345) (no. 345), p. 49, Japanese
    Research society

  • ウェアラブル生体センサのための心電計測方法
    田中 義人, 河本 優太, 中井 陽三郎, 奥野 圭祐, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO
    Dec. 2014, 信学技報, vol. 114(no. 345) (no. 345), p. 47, Japanese
    Research society

  • Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii
    This paper reports a 65 nm 8 Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at a single supply voltage with a process-variation-tolerant sense amplifier. The proposed sense amplifier comprises a boosted-gate nMOS and negative-resistance pMOSs as loads, which maximizes the readout margin at any process corner. The STT-MRAM achieves a cycle time of 1.9 mu s (= 0.526 MHz) at 0.38 V. The operating power is 1.70 mu W at this voltage. The minimum energy per access is 1.12 pJ/bit when the supply voltage is 0.44 V. The proposed STT-MRAM operates at a lower energy than an SRAM when the utilization of the memory bandwidth is 14% or less.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Dec. 2014, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A(12) (12), 2411 - 2417, English
    [Refereed]
    Scientific journal

  • Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a soft-error tolerant and margin-enhanced nMOS-pMOS reversed 6T SRAM cell. The 6T SRAM bitcell comprises pMOS access and driver transistors, and nMOS load transistors. Therefore, the nMOS and pMOS masks are reversed in comparison with those of a conventional bitcell. In scaled process technology, The pMOS transistors present advantages of small random dopant fluctuation, strain-enhanced saturation current, and small soft-error sensitivity. The four-pMOS and two-nMOS structure improves the soft-error rate plus operating margin. We conduct SPICE and neutron-induced soft-error simulations to evaluate the n-p reversed 6T SRAM bitcell in 130-nm to 22-nm processes. At the 22-nm node, a multiple-cell-upset and single-bit-upset SERs are improved by 34% and 51% over a conventional 6T cell. Additionally, the static noise margin and read cell current are 2.04x and 2.81x improved by leveraging the pMOS benefits.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Sep. 2014, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A(9) (9), 1945 - 1951, English
    [Refereed]
    Scientific journal

  • Takagi, Kenta, Tanaka, Kotaro, Izumi, Shintaro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko
    As described in this paper, a real-time object detection system using a Histogram of Oriented Gradients (HOG) feature extraction accelerator VLSI is presented. The VLSI [1, 2] enables the system to achieve real-time performance and scalability for multiple object detection under limited power condition. The VLSI employs three techniques: a VLSI-oriented HOG algorithm with early classification in Support Vector Machine (SVM) classification, a dual-core architecture for parallel feature extraction, and a detection-window-size scalable architecture with a reconfigurable MAC array for processing objects of different shapes. The test chip was fabricated using 65 nm CMOS technology. The measurement result shows that the VLSI consumes 43 mW at 42.9 MHz and 1.1 V to process HDTV (1920 x 1080 pixels) at 30 frames per second (fps). A multiple object detection system and a multiple scale object detection system are presented to demonstrate the system flexibility and scalability realized by VLSI and applicability for versatile application of object detection. On the multiple object detection system, a real-time object detection for HDTV resolution video is achieved with 84 mW of power consumption on a task to detect 2 types of targets while keeping comparable detection accuracy as software-based system. On the multiple scale object detection system, a task to detect 5 scales of a target is accomplished using a single VLSI. The power consumption of the VLSI is estimated to 102 mW on the task.
    SPRINGER, Sep. 2014, JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 76(3) (3), 261 - 274, English
    [Refereed]
    Scientific journal

  • Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents a resilient cache memory for dynamic variation tolerance in a 40-nm CMOS. The cache can perform sustained operations under a large-amplitude voltage droop. To realize sustained operation, the resilient cache exploits 7T/14T bit-enhancing SRAM and on-chip voltage/temperature monitoring circuit. 7T/14T bit-enhancing SRAM can reconfigure itself dynamically to a reliable bit-enhancing mode. The on-chip voltage/temperature monitoring circuit can sense a precise supply voltage level of a power rail of the cache. The proposed cache can dynamically change its operation mode using the voltage/temperature monitoring result and can operate reliably under a large-amplitude voltage droop. Experimental result shows that it does not fail with 25% and 30% droop of V-dd and it provides 91 times better failure rate with a 35% droop of V-dd compared with the conventional design.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2014, IEICE TRANSACTIONS ON ELECTRONICS, E97C(4) (4), 332 - 341, English
    [Refereed]
    Scientific journal

  • A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM
    G.Matsukawa, Y.Nakata, Y.Kimi, Y.Sugure, M.Shimozawa, S.Oho, H.Kawaguchi, M.Yoshimoto
    Feb. 2014, ARCS VERFE Workshop, pp.1 - 5, English
    [Refereed]
    Symposium

  • Low-Power SRAM in 28-nm FD-SOI for Image Processor
    KAWAMOTO Yuta, YOSHIMOTO Shusuke, NAKAGAWA Tomomki, KITAHARA Yuki, MORI Haruki, TAKAGI Kenta, IZUMI Shintaro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    The Institute of Electronics, Information and Communication Engineers, Jan. 2014, Technical report of IEICE. ICD, 113(419) (419), 41 - 41, Japanese
    Research society

  • Yamada, A., Higami, Y., Takagi, K., Amagasaki, M., Ikeda, M., Ishihara, T., Ito, K., Usami, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kurokawa, A., Shibata, Y., Seto, K., Song, T., Takashima, Y., Takahashi, A., Takenaka, T., Togawa, N., Tomiyama, H., Nakatake, S., Nakamura, Y., Hashimoto, M., Hamaguchi, K., Higuchi, H., Hirose, T., Fukuda, D., Matsumoto, T., Miura, Y., Minato, S.-I., Minami, F., Yamashita, S., Yuminaka, Y., Yoshikawa, M., Watanabe, T.
    2014, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E97A(12) (12), 2366 - 2366
    Scientific journal

  • Yamada, A., Higami, Y., Takagi, K., Amagasaki, M., Ikeda, M., Ishihara, T., Ito, K., Usami, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kurokawa, A., Shibata, Y., Seto, K., Song, T., Takashima, Y., Takahashi, A., Takenaka, T., Togawa, N., Tomiyama, H., Nakatake, S., Nakamura, Y., Hashimoto, M., Hamaguchi, K., Higuchi, H., Hirose, T., Fukuda, D., Matsumoto, T., Miura, Y., Minato, S.-I., Minami, F., Yamashita, S., Yuminaka, Y., Yoshikawa, M., Watanabe, T.
    2014, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E97A(12) (12), 2366 - 2366
    Scientific journal

  • Yamada, A., Higami, Y., Takagi, K., Amagasaki, M., Ikeda, M., Ishihara, T., Ito, K., Usami, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kurokawa, A., Shibata, Y., Seto, K., Song, T., Takashima, Y., Takahashi, A., Takenaka, T., Togawa, N., Tomiyama, H., Nakatake, S., Nakamura, Y., Hashimoto, M., Hamaguchi, K., Higuchi, H., Hirose, T., Fukuda, D., Matsumoto, T., Miura, Y., Minato, S.-I., Minami, F., Yamashita, S., Yuminaka, Y., Yoshikawa, M., Watanabe, T.
    2014, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E97A(12) (12), 2366 - 2366
    Scientific journal

  • Yamada, A., Higami, Y., Takagi, K., Amagasaki, M., Ikeda, M., Ishihara, T., Ito, K., Usami, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kurokawa, A., Shibata, Y., Seto, K., Song, T., Takashima, Y., Takahashi, A., Takenaka, T., Togawa, N., Tomiyama, H., Nakatake, S., Nakamura, Y., Hashimoto, M., Hamaguchi, K., Higuchi, H., Hirose, T., Fukuda, D., Matsumoto, T., Miura, Y., Minato, S.-I., Minami, F., Yamashita, S., Yuminaka, Y., Yoshikawa, M., Watanabe, T.
    2014, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E97A(12) (12), 2366 - 2366
    Scientific journal

  • Tomoki Nakagawa, Shintaro Izumi, Shusuke Yoshimoto, Koji Yanagida, Yuki Kitahara, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This report describes a high speed 6T-4C shadow memory design using a word line boosting and a plate line driver boosting. The proposed methods utilize a characteristic of ferroelectric capacitor. The word line and the plate line boosting method respectively reduce 21% write time and 33% plate line charging time. © 2014 IEEE.
    Institute of Electrical and Electronics Engineers Inc., 2014, Proceedings - IEEE International Symposium on Circuits and Systems, 2736 - 2739, English
    [Refereed]
    International conference proceedings

  • 動作環境の動的変動を考慮した動作マージン拡大機能を有する自律制御キャッシュ
    KIMI Yuta, NAKATA Yohei, OKUMURA Syunsuke, JUNG Jinwook, 沢田 卓也, 利川 托, 永田 真, 中野 博文, 薮内 誠, 藤原 英弘, 新居 浩二, 河合 浩行, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Jan. 2014, 信学技報, vol. 113(no. 419) (no. 419), p. 59, Japanese
    Research society

  • 磁性変化型メモリの書き込み速度を改善するメモリアーキテクチャ
    MORI Haruki, YANAGIDA Kouji, UMEKI Youhei, YOSHIMOTO Shusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, 角田 浩司, 杉井 寿博
    Jan. 2014, 信学技報, vol. 113(no. 419) (no. 419), p. 27, Japanese
    Research society

  • 強誘電体メモリの高速回路技術
    NAKAGAWA Tomoki, YOSHIMOTO Shusuke, KITAHARA Yuki, YANAGIDA Kouji, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Jan. 2014, 信学技報, vol. 113(no. 419) (no. 419), p. 39, Japanese
    Research society

  • ディペンダブルメモリを用いた低遅延デュアルコアロックステップアーキテクチャ
    MATSUKAWA Go, NAKATA Yohei, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Jan. 2014, 信学技報, vol. 113(no. 419) (no. 419), p. 57, Japanese
    Research society

  • ウェアラブル生体センサのための心電図解析方法
    NAKAI Yozaburo, IZUMI Shintaro, NAKANO Masanao, YAMASHITA Ken, FUJI Takahide, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Jan. 2014, 信学技報, vol. 113(no. 419) (no. 419), p. 61, Japanese
    Research society

  • Guangji He, Yuki Miyamoto, Kumpei Matsuda, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition. We implement parallel and pipelined architecture for GMM computation and Viterbi processing. It includes a 8-path Viterbi transition architecture to maximize the processing speed and adopts tri-gram language model to improve the recognition accuracy. A two-level cache architecture is implemented for the demo system. Measured results show that our implementation achieves 25% required frequency reduction (62.5 MHz) and 26% power consumption reduction (54.8mW) for 60 k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 3.02x and 2.25x times faster than real-time at 200MHz using the bigram and trigram language models, respectively.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2014, IEICE ELECTRONICS EXPRESS, 11(2) (2), pp. 1 - 9, English
    [Refereed]
    Scientific journal

  • Normally-Off Technologies for Healthcare Appliance
    Izumi, Shintaro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko, Fujimori, Yoshikazu
    Battery mass and power consumption of wearable system must be reduced because the key factors affecting wearable system usability are miniaturization and weight reduction. This report describes a wearable biosignal monitoring system using normally-off technologies to minimize the power consumption. Especially we focused on daily-life monitoring and electrocardiograph (ECG) processor. Our system employs Ferroelectric Random Access Memory (FeRAM) and Near Field Communication (NFC) for normally-off data logging and normally-off data communication. A robust heart rate monitor and Cortex M0 core are used to on-node processing for logging data reduction.
    IEEE, 2014, 2014 19TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 17 - 20, English
    [Refereed]
    International conference proceedings

  • A 6T-4C Shadow Memory using Plate Line and Word Line Boosting
    Nakagawa, Tomoki, Izumi, Shintaro, Yoshimoto, Shusuke, Yanagida, Koji, Kitahara, Yuki, Kawaguchi, Hiroshi, Yoshimoto, Masahiko
    This report describes a high speed 6T-4C shadow memory design using a word line boosting and a plate line driver boosting. The proposed methods utilize a characteristic of ferroelectric capacitor. The word line and the plate line boosting method respectively reduce 21% write time and 33% plate line charging time.
    IEEE, 2014, 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2736 - 2739, English
    [Refereed]
    International conference proceedings

  • Yozaburo Nakai, Shintaro Izumi, Masanao Nakano, Ken Yamashita, Takahide Fujii, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a robust method for heart beat detection from noisy electrocardiogram (ECG) signals. Generally, the QRS-complex of heart beat is extracted from the ECG using a threshold. However, in a noisy condition such a mobile and wearable bio-signal monitoring system, noise increases the incidence of misdetection and false detection of QRS-complex. To prevent incorrect detection, we introduce a novel template matching algorithm. The template waveform can be generated autonomously using a short-term autocorrelation method, which leverages the similarity of QRS-complex waveforms. Simulation results show the proposed method achieves state-of-the-art noise tolerance of heart beat detection.
    2014, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2014, 34 - 7, English, International magazine
    [Refereed]
    Scientific journal

  • A 6.14 mu A Normally-Off ECG-SoC with Noise Tolerant Heart Rate Extractor for Wearable Healthcare Systems
    Shintaro Izumi, Ken Yamashita, Masanao Nakano, Tomoki Nakagawa, Yuki Kitahara, Koji Yanagida, Shusuke Yoshimoto, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto
    This paper describes an electrocardiograph (ECG) monitoring SoC using a non-volatile MCU (NVMCU) and a noise tolerant instantaneous heart rate (IHR) monitor. The novelty of this work is the combination of the non-volatile MCU for normally-off computing and a noise-tolerant-QRS (heart beat) detection algorithm to achieve both low-power and noise tolerance. To minimize the stand-by current of MCU, a nonvolatile flip-flop and a 6T-4C NVRAM are employed. Proposed plate-line charge-share and bit-line non-precharge techniques also contribute to mitigate the active power overhead of 6T-4C NVRAM. The proposed accurate heart beat detector employs a coarse-fine autocorrelation and a template matching technique. Accurate heart beat detection also contributes system level power reduction because the active ratio of ADC and digital block can be reduced using a heart beat prediction. Then, at least 25% active time can be reduced. Measurement results show the fully integrated ECG-SoC consumes 6.14 mu A including 1.28-mu A nonvolatile MCU and 0.7-mu A heart rate extractor.
    IEEE, 2014, 2014 IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE (BIOCAS), 280 - 283, English
    [Refereed]
    International conference proceedings

  • A 2.4 pJ Ferroelectric-Based Non-Volatile Flip-Flop with 10-Year Data Retention Capability
    Kimura, Hiromitsu, Fuchikami, Takaaki, Marumoto, Kyoji, Fujimori, Yoshikazu, Izumi, Shintaro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko
    A ferroelectric-based (FE-based) non-volatile flip-flop (NVFF) is proposed for low-power LSI. Since leakage current in a logic circuit can be cut off by non-volatile storage capability of NVFFs, the standby power is reduced to zero. The use of complementarily stored data in coupled FE capacitors makes it possible to achieve 88% reduction of FE capacitor size while maintaining a wide read voltage margin of 240mV (minimum) at 1.5V, which results in 2.4pJ low access energy with 10-year, 85 degrees C data retention capability. An access speed of FE capacitors can be adaptively changed according to required retention time, which becomes 1.6 mu s for 10-year data retention, and 170ns for 10-hour data retention. Especially, short-term data retention is suitable for power gating implementation. Applying the proposed circuitry in 32bit CPU of a vital sensor LSI, its power consumption becomes 13% of that of conventional one with area overhead of 64% using 130nm CMOS with Pb(Zr,Ti)O-3(PZT) thin films.
    IEEE, 2014, 2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 21 - 24, English
    [Refereed]
    International conference proceedings

  • An 8-bit I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter
    Okuno, Keisuke, Konishi, Toshihiro, Izumi, Shintaro, Yoshimoto, Masahiko, Kawaguchi, Hiroshi
    We present an I/O-sized second-order analog to digital converter (ADC) combined with a time-to-digital converter (TDC) and a voltage-to-time converter (VTC). Our proposed VTC is optimized for metal-oxide-metal (MOM) capacitances, and is charged to the MOM capacitances by an input voltage. In a standard 65-nm CMOS process, an SNR of 50 dB (8 bits) is achievable at an input signal frequency of 78 kHz and a sampling rate of 20 MHz, where the respective area and power are 6468 mm(2) and 509 mu W. The active area of the proposed ADC is smaller than an I/O buffer. The proposed ADC is useful as an ADC I/O.
    IEEE, 2014, 2014 21ST IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 223 - 226, English
    [Refereed]
    International conference proceedings

  • A 2.23 ps RMS Jitter 3 mu s Fast Settling ADPLL using Temperature Compensation PLL Controller
    Okuno, Keisuke, Masaki, Kana, Izumi, Shintaro, Konishi, Toshihiro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko
    This report describes an all-digital phase-locked loop (ADPLL) with temperature-compensated settling time reduction. The novelty of this work is autonomous oscillation control word estimation without a look-up table or memory circuits. The proposed ADPLL includes a multi-phase oscillator as a digitally controlled oscillator (DCO). Digital timing error correction circuits are integrated to minimize the settling time that is degraded by phase conversion error. The ADPLL is fabricated using a 65 nm CMOS process. The test chip occupies 0.27 x 0.36 mm(2). It achieves 2.23 ps RMS jitter and -224 dB FoM at 2.4 GHz output frequency with 8.85 mW power dissipation. Measurement results show that the 47% settling time is reduced by the proposed estimation block. The average settling time at 25 degrees C is 3 mu s.
    IEEE, 2014, 2014 21ST IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 68 - 71, English
    [Refereed]
    International conference proceedings

  • A 2.4x-Real-Time VLSI Processor for 60-kWord Continuous Speech Recognition
    HE Guangji, MIYAMOTO Yuki, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). We implement parallel and pipelined architecture for GMM computation and Viterbi processing. It includes a 8-path Viterbi transition architecture to maximize the processing speed and adopts tri-gram language model to improve the recognition accuracy. A two-level cache architecture is implemented for the demo system. The test chip, fabricated in 40 nm CMOS technology, occupies 1.77 mm × 2.18 mm containing 2.98 M transistors for logic and 4.29 Mbit on-chip memory. The measured results show that our implementation achieves 25% required frequency reduction (62.5 MHz) and 26% power consumption reduction (54.8 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 3.02× and 2.25× times faster than real-time at 200 MHz using the bigram and trigram language models, respectively.
    The Institute of Electronics, Information and Communication Engineers, Oct. 2013, Technical report of IEICE. ICD, 113(236) (236), 29 - 34, Japanese
    Research society

  • Soft-Error Tolerant N-P Reversed 6T SRAM Cell
    S. Yoshimoto, S. Izumi, H. Kawaguchi, YOSHIMOTO Masahiko
    Jul. 2013, IEEE Nuclear and Space Radiation Effects Conference (NSREC), PG - 3, English
    [Refereed]
    International conference proceedings

  • Shusuke Yoshimoto, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents a proposed NMOS-centered 6T SRAM cell layout that reduces a neutron-induced multiple-cell-upset (MCU) SER on a same wordline. We implemented an 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67-98% compared with a general macro that has PMOS-centered 6T SRAM cells.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jul. 2013, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E96A(7) (7), 1579 - 1585, English
    [Refereed]
    Scientific journal

  • NMOS-Centered 6T SRAM Layout Reducing Neutron-Induced Multiple Cell Upsets
    YOSHIMOTO Shusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    This paper presents a proposed NMOS-centered 6T SRAM cell layout that reduces a neutron-induced multiple-cell-upset (MCU) SER on a same wordline. We implemented an 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67-98% compared with a general macro that has PMOS-centered 6T SRAM cells.
    The Institute of Electronics, Information and Communication Engineers, Apr. 2013, Technical report of IEICE. ICD, 113(1) (1), 121 - 126, Japanese
    Research society

  • ゼロデータフラグを用いた低エネルギーSTT-RAMキャッシュ
    KIMI Yuta, JUNG Jinwook, NAKATA Yohei, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi
    Apr. 2013, 信学技報, vol. 113(no. 1) (no. 1), pp.47 - 52, Japanese
    Research society

  • Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents an adaptive cache architecture for wide-range reliable low-voltage operations. The proposed associativity-reconfigurable cache consists of pairs of cache ways so that it can exploit the recovery feature of the novel 7T/14T SRAM cell. Each pair has two operating modes that can be selected based upon the required voltage level of current operating conditions: normal mode for high performance and dependable mode for reliable low-voltage operations. We can obtain reliable low-voltage operations by application of the dependable mode to weaker pairs that cannot operate reliably at low voltages. Meanwhile leaving stronger pairs in the normal mode, we can minimize performance losses. Our chip measurement results show that the proposed cache can trade off its associativity with the minimum operating voltage. Moreover, it can decrease the minimum operating voltage by 140 mV achieving 67.48% and 26.70% reduction of the power dissipation and energy per instruction. Processor simulation results show that designing the on-chip caches using the proposed scheme results in 2.95% maximum IPC losses, but it can be chosen various performance levels. Area estimation results show that the proposed cache adds area overhead of 1.61% and 5.49% in 32-KB and 256-KB caches, respectively.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2013, IEICE TRANSACTIONS ON ELECTRONICS, E96C(4) (4), 528 - 537, English
    [Refereed]
    Scientific journal

  • Kosuke Mizuno, Kenta Takagi, Yosuke Terachi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a Histogram of Oriented Gradients (HOG) feature extraction accelerator that features a VLSI-oriented HOG algorithm with early classification in Support Vector Machine (SVM) classification, dual core architecture for parallel feature extraction and multiple object detection, and detection-window-size scalable architecture with reconfigurable MAC array for processing objects of several shapes. To achieve low-power consumption for mobile applications, early classification reduces the amount of computations in SVM classification efficiently with no accuracy degradation. The dual core architecture enables parallel feature extraction in one frame for high-speed or low-power computing and detection of multiple objects simultaneously with low power consumption by HOG feature sharing. Objects of several shapes, a vertically long object, a horizontally long object, and a square object, can be detected because of cooperation between the two cores. The proposed methods provide processing capability for HDTV resolution video (1920 x 1080 pixels) at 30 frames per second (fps). The test chip, which has been fabricated using 65 nm CMOS technology, occupies 4.2 x 2.1 mm(2) containing 502 Kgates and 1.22 Mbit on-chip SRAMs. The simulated data show 99.5 mW power consumption at 42.9 MHz and 1.1 V.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2013, IEICE TRANSACTIONS ON ELECTRONICS, E96C(4) (4), 433 - 443, English
    [Refereed]
    Scientific journal

  • Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    We present a small-area second-order all-digital time-to-digital converter (TDC) with two frequency shift oscillators (FSOs) comprising inverter chains and dynamic flipflops featuring low jitter. The proposed FSOs can maintain their phase states through continuous oscillation, unlike conventional gated ring oscillators (GROs) that are affected by transistor leakage. Our proposed FSOTDC is more robust and is eligible for all-digital TDC architectures in recent leaky processes. Low-jitter dynamic flipflops are adopted as a quantization noise propagator (QNP). A frequency mismatch occurring between the two FSOs can be canceled out using a least mean squares (LMS) filter so that second-order noise shaping is possible. In a standard 65-nm CMOS process, an SNDR of 61 dB is achievable at an input bandwidth of 500 kHz and a sampling rate of 16 MHz, where the respective area and power are 700 mu m(2) and 281 mu W.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2013, IEICE TRANSACTIONS ON ELECTRONICS, E96C(4) (4), 546 - 552, English
    [Refereed]
    Scientific journal

  • Guangji He, Takanobu Sugahara, Yuki Miyamoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). It features a compression-decoding scheme to reduce the external memory bandwidth for Gaussian Mixture Model (GMM) computation and multi-path Viterbi transition units. We optimize the internal SRAM size using the max-approximation GMM calculation and adjusting the number of look-ahead frames. The test chip, fabricated in 40 nm CMOS technology, occupies 1.77 mm x 2.18 mm containing 2.52 M transistors for logic and 4.29 Mbit on-chip memory. The measured results show that our implementation achieves 34.2% required frequency reduction (83.3 MHz), 48.5% power consumption reduction (74.14 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work while 30% of the area is saved with recognition accuracy of 90.9%. This chip can maximally process 2.4x faster than real-time at 200 MHz and 1.1 V with power consumption of 168 mW. By increasing the beam width, better recognition accuracy (91.45%) can be achieved. In that case, the power consumption for real-time processing is increased to 97.4 mW and the max-performance is decreased to 2.08x because of the increased computation workload.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2013, IEICE TRANSACTIONS ON ELECTRONICS, E96C(4) (4), 444 - 453, English
    [Refereed]
    Scientific journal

  • SRAM Failure Injection to a Vehicle ECU and Its Behavior Evaluation
    Y. Takeuchi, Y. Nakata, Y. Ito, Y. Sugure, S. Oho, H. Kawaguchi, YOSHIMOTO MASAHIKO
    Mar. 2013, DATE RIIF Workshop, English
    [Refereed]
    International conference proceedings

  • Model-Based Fault Injection for Large-Scale Failure Effect Analysis with 600-Node Cloud Computers
    Y. Nakata, Y. Ito, Y. Takeuchi, Y. Sugure, S. Oho, H. Kawaguchi, YOSHIMOTO MASAHIKO
    Mar. 2013, DATE RIIF Workshop, English
    [Refereed]
    International conference proceedings

  • Kosuke Mizuno, Yosuke Terachi, Kenta Takagi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a Histogram of Oriented Gradients (HOG)-based object detection processor. It features a simplified HOG algorithm with cell-based scanning and simultaneous Support Vector Machine (SVM) calculation, cell-based pipeline architecture, and parallelized modules. To evaluate the effectiveness of our approach, the proposed architecture is implemented onto a FPGA prototyping board. Results show that the proposed architecture can generate HOG features and detect objects with 40MHz for SVGA resolution video (800 × 600 pixels) at 72 frames per second (fps). © 2013 Information Processing Society of Japan.
    Feb. 2013, IPSJ Transactions on System LSI Design Methodology, 6, 42 - 51, English
    [Refereed]
    International conference proceedings

  • Konishi, Toshihiro, Okuno, Keisuke, Izumi, Shintaro, Yoshimoto, Masahiko, Kawaguchi, Hiroshi
    This paper presents a second-order Delta Sigma analog-to-digital converter (ADC) operating in a time domain. In the proposed ADC architecture, a voltage-controlled delay unit (VCDU) converts an input analog voltage to a delay time. Then, the clocks outputs from a gated ring oscillator (GRO) are counted during the delay time. No switched capacitor or opamp is used. Therefore, the proposed ADC can be implemented in a small area and with low power. For that reason, it has process scalability: it can keep pace with Moore's law. A time error is propagated to the second GRO by a multi-stage noise-shaping (MASH) topology, which provides second-order noise-shaping. In a standard 40-nm CMOS process, a SNDR of 45 dB is achievable at input bandwidth of 16 kHz and a sampling rate of 8 MHz, where the power is 408.5 mu W. Its area is 608 mu m(2).
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Feb. 2013, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E96A(2) (2), 434 - 442, English
    [Refereed]
    Scientific journal

  • Guangji He, Yuki Miyamoto, Kumpei Matsuda, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a low-power VLSI chip for speakerindependent 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). We implement parallel and pipelined architecture for GMM computation and Viterbi processing. It includes a 8-path Viterbi transition architecture to maximize the processing speed and adopts tri-gram language model to improve the recognition accuracy. A two-level cache architecture is implemented for the demo system. The test chip, fabricated in 40 nm CMOS technology, occupies 1.77 mm × 2.18 mm containing 2.98 M transistors for logic and 4.29 Mbit on-chip memory. The measured results show that our implementation achieves 25% required frequency reduction (62.5 MHz) and 26% power consumption reduction (54.8 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 3.02× and 2.25× times faster than real-time at 200 MHz using the bigram and trigram language models, respectively. © 2013 IEEE.
    Institute of Electrical and Electronics Engineers Inc., 2013, IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, 147 - 152, English
    International conference proceedings

  • Yasuo Sugure, Yasuhiro Ito, Yohei Nakata, Yusuke Takeuchi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Shigeru Oho
    We propose a virtual prototyping system that can evaluate failure mode and effect analysis (FMEA). The virtual prototyping system which consists of co-simulation environment between mechanics model and microcontroller model is integrated a fault-injection system that can inject faults into SRAM. This approach was applied to a validation of vehicle engine control. We observed that an abnormal system behavior occurred by SRAM fault. Thus the virtual prototyping system with faultinjection system can be performed a vehicle engine control behavior without actual components when fault occurred.
    2013, IFAC Proceedings Volumes (IFAC-PapersOnline), 7(1) (1), 562 - 563, English
    [Refereed]
    International conference proceedings

  • A Physical Unclonable Function Chip Exploiting Load Transistors' Variation in SRAM Bitcells
    S. Okumura, S. Yoshimoto, H. Kawaguchi, M. Yoshimoto
    We propose a chip identification (ID) generating scheme with random variation of transistor characteristics in SRAM bitcells. In the proposed scheme, a unique fingerprint is generated by grounding both bitlines. It has high speed, and it can be implemented in a very small area overhead. We fabricated test chips in a 65-nm process and obtained 12,288 sets of unique 128-bit fingerprints, which are evaluated in this paper. The failure rate of the IDs is found to be 2.1 x 10(-12).
    IEEE, 2013, 2013 18TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 79 - 80, English
    [Refereed]
    International conference proceedings

  • A 40-nm 144-mW VLSI Processor for Real-time 60-kWord Continuous Speech Recognition
    Guangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We have developed a low-power VLSI chip for 60- kWord real-time continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). Our implementation includes a cache architecture using locality of speech recognition, beam pruning using a dynamic threshold, two-stage language model searching, highly parallel Gaussian Mixture Model (GMM) computation based on the mixture level, a variable-frame look-ahead scheme, and elastic pipeline operation between the Viterbi transition and GMM processing. Results show that our implementation achieves 95% bandwidth reduction (70.86 MB/s) and 78% required frequency reduction (126.5 MHz). The test chip, fabricated using 40 nm CMOS technology, contains 1.9 M transistors for logic and 7.8 Mbit on-chip memory. It dissipates 144 mW at 126.5 MHz and 1.1 V for 60 kWord real-time continuous speech recognition.
    IEEE, 2013, 2013 18TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 71 - 72, English
    [Refereed]
    International conference proceedings

  • S. Yoshimoto, M. Terada, S. Okumura, T. Suzuki, S. Miyano, H. Kawaguchi, M. Yoshimoto
    This paper presents a novel disturb mitigation technique which achieves low-power and low-voltage SRAM. Our proposed technique consists of a floating bitline technique and a low-swing bitline driver (LSBD). We fabricated a 512-Kb 8T SRAM test chip that operates at a single 0.5-V supply voltage. The proposed technique achieves 1.52-pJ/access active energy in a write cycle and 72.8-μW leakage power, which are 59.4% and 26.0% better than the conventional write-back technique. © 2013 IEEE.
    2013, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 77 - 78, English
    [Refereed]
    International conference proceedings

  • Energy-Efficient Spin-Transfer Torque RAM Cache Exploiting Additional All-Zero-Data Flags
    Jinwook Jung, Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi
    Large on-chip caches account for a considerable fraction of the total energy consumption in modern microprocessors. In this context, emerging Spin-Transfer Torque RAM (STT-RAM) has been regarded as a promising candidate to replace large on-chip SRAM caches in virtue of its nature of the zero leakage. However, large energy requirement of STT-RAM on write operations, resulting in a huge amount of dynamic energy consumption, precludes it from application to on-chip cache designs. In order to reduce the write energy of the STT-RAM cache thereby the total energy consumption, this paper provides an architectural technique which exploits the fact that many applications process a large number of zero data. The proposed design appends additional flags in cache tag arrays and set these additional bits if the corresponding data in the cache line is the zero-valued data in which all data bits are zero. Our experimental results show that the proposed cache design can reduce 73.78% and 69.30% of the dynamic energy on write operations at the byte and word granularities, respectively; total energy consumption reduced by 36.18% and 42.51%, respectively. In addition to the energy reduction, performance evaluation results indicate that the proposed cache improves the processor performance by 5.44% on average.
    IEEE, 2013, PROCEEDINGS OF THE FOURTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2013), 216 - 222, English
    [Refereed]
    International conference proceedings

  • A SUB-100-MILLIWATT DUAL-CORE HOG ACCELERATOR VLSI FOR REAL-TIME MULTIPLE OBJECT DETECTION
    Kenta Takagi, Kosuke Mizuno, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    In this paper, a Histogram of Oriented Gradients (HOG) feature extraction accelerator for real-time multiple object detection is presented. The processor employs three techniques: a VLSI-oriented HOG algorithm with early classification in Support Vector Machine (SVM) classification, a dual core architecture for parallel feature extraction, and a detection-window-size scalable architecture with a reconfigurable MAC array for processing objects of different shapes. Early classification reduces the number of computations in SVM classification. The dual core architecture and the detection-window-size scalable architecture enable the processor to operate in several modes: highspeed mode, low-power mode, multiple object detection mode, and multiple shape object detection mode. These techniques expand the processor flexibility required for versatile application. The test chip was fabricated using 65 nm CMOS technology. The proposed architecture is designed to process HDTV resolution video (1920 x 1080 pixels) at 30 frames per second (fps). The performance of this accelerator is demonstrated on a pedestrian detection system.
    IEEE, 2013, 2013 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING (ICASSP), 2533 - 2537, English
    [Refereed]
    International conference proceedings

  • Temperature Compensation using Least Mean Squares for Fast Settling All-Digital Phase-Locked Loop
    Keisuke Okuno, Shintaro Izumi, Toshihiro Konishi, Song Dae-Woo, Masahiko Yoshimoto, Hiroshi Kawaguchi
    This paper presents a temperature compensation technique for a digitally controlled oscillator (DCO) using least means square (LMS) filtering. The proposed scheme contributes to reduction of the start-up settling time of all-digital phase-locked loop (ADPLL). The proposed method estimates the temperature using the output frequency of DCO because it is affected by temperature fluctuation. An optimal value of oscillation tuning word (OTW) for DCO can be estimated using the LMS algorithm because a linear relation exists between the output frequency of maximum OTW and the output frequency of other OTWs. These characteristics are confirmed using measurement results of the DCO, which is fabricated in 65-nm CMOS process. We modeled the ADPLL with the proposed temperature compensator in MATLAB using the measurement results of DCO. The simulation results show that the ADPLL with proposed temperature compensator achieves more than 53% settling time reduction and less than 10-MHz frequency error.
    IEEE, 2013, 2013 IEEE 11TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), pp.1 - 4, English
    [Refereed]
    International conference proceedings

  • Multiple-Cell-Upset Hardened 6T SRAM Using NMOS-Centered Layout
    S. Yoshimoto, K. Nii, H. Kawaguchi, M. Yoshimoto
    This paper presents a proposed NMOS-centered 6T SRAM cell layout that reduces a neutron-induced multiple-cell-upset (MCU) SER on a same wordline. We implemented an 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67-98% compared with a general macro that has PMOS-centered 6T SRAM cells.
    IEEE, 2013, 2013 IEEE INTERNATIONAL MEETING FOR FUTURE OF ELECTRON DEVICES, KANSAI (IMFEDK2013), pp. 98 - 99, English
    [Refereed]
    International conference proceedings

  • A 38 mu A Wearable Biosignal Monitoring System with Near Field Communication
    Yamashita, Ken, Izumi, Shintaro, Nakano, Masanao, Fujii, Takahide, Konishi, Toshihiro, Kawaguchi, Hiroshi, Kimura, Hiromitsu, Marumoto, Kyoji, Fuchikami, Takaaki, Fujimori, Yoshikazu, Nakajima, Hiroshi, Shiga, Toshikazu, Yoshimoto, Masahiko
    This paper presents a low-power wearable biosignal monitoring system. The proposed system can communicate with smartphones using Near Field Communication (NFC) to check vital signs easily at any time. It comprises a battery, electrodes, a triaxial accelerometer IC, an NFC tag IC, and a biosignal processor LSI. The proposed biosignal processor LSI, fabricated using a 130-nm CMOS process, comprises heart rate monitoring circuits, a 32-kbyte ferroelectric random access memory (FeRAM), an accelerometer interface, and an NFC interface. The proposed system consumes 38.1 mu A for logging application at 32-kHz operating frequency, with 3.0-V supply voltage.
    IEEE, 2013, 2013 IEEE 11TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), pp.1 - 4, English
    [Refereed]
    International conference proceedings

  • Takahide Fujii, Masanao Nakano, Ken Yamashita, Toshihiro Konishi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a robust method of Instantaneous Heart Rate (IHR) and R-peak detection from noisy electrocardiogram (ECG) signals. Generally, the IHR is calculated from the R-wave interval. Then, the R-waves are extracted from the ECG using a threshold. However, in wearable bio-signal monitoring systems, noise increases the incidence of misdetection and false detection of R-peaks. To prevent incorrect detection, we introduce a short-term autocorrelation (STAC) technique and a small-window autocorrelation (SWAC) technique, which leverages the similarity of QRS complex waveforms. Simulation results show that the proposed method improves the noise tolerance of R-peak detection.
    2013, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2013, 7330 - 3, English, International magazine
    [Refereed]
    Scientific journal

  • A 40-nm 8T SRAM with Selective Source Line Control of Read Bitlines and Address Preset Structure
    S. Yoshimoto, S. Miyano, M. Takamiya, H. Shinohara, H. Kawaguchi, M. Yoshimoto
    This paper presents a 40-nm 8T SRAM in which bitlines are partially discharged by a selective source line control (SSLC) for low-power operation. The proposed SSLC scheme reduces a read bitline voltage swing in an unselected column with a floating source line (SL) of dedicated read ports. The SL is controlled by an additional NMOS switch that is turned on in a selected column, but the switch is kept off in the remaining unselected columns. The proposed scheme is effective for power reduction in successive address readouts through a single column. Furthermore, this paper introduces an address preset structure. The preset address enables the SRAM to be read out with no access time penalty for preferred use of the SSLC scheme. We fabricated a 16-Kb 8T SRAM test chip in a 40-nm CMOS process and observed that the proposed SSLC scheme with the address preset structure saves 38.1% of the readout power on average.
    IEEE, 2013, 2013 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), pp.1 - 4, English
    [Refereed]
    International conference proceedings

  • Shintaro Izumi, Ken Yamashita, Masanao Nakano, Toshihiro Konishi, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto
    This report describes an electrocardiograph (ECG) processor for use with a wearable healthcare system. It comprises an analog front end, a 12-bit ADC, a robust Instantaneous Heart Rate (IHR) monitor, a 32-bit Cortex-M0 core, and 64 Kbyte Ferroelectric Random Access Memory (FeRAM). The IHR monitor uses a short-term autocorrelation (STAC) algorithm to improve the heart-rate detection accuracy despite its use in noisy conditions. The ECG processor chip consumes 13.7 μA for heart rate logging application. © 2013 IEEE.
    2013, European Solid-State Circuits Conference, 145 - 148, English
    [Refereed]
    International conference proceedings

  • A 40-NM 54-MW 3x-REAL-TIME VLSI PROCESSOR FOR 60-KWORD CONTINUOUS SPEECH RECOGNITION
    He, Guangji, Miyamoto, Yuki, Matsuda, Kumpei, Izumi, Shintaro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko
    This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). We implement parallel and pipelined architecture for GMM computation and Viterbi processing. It includes a 8-path Viterbi transition architecture to maximize the processing speed and adopts tri-gram language model to improve the recognition accuracy. A two-level cache architecture is implemented for the demo system. The test chip, fabricated in 40 nm CMOS technology, occupies 1.77 mm x 2.18 mm containing 2.98 M transistors for logic and 4.29 Mbit on-chip memory. The measured results show that our implementation achieves 25% required frequency reduction (62.5 MHz) and 26% power consumption reduction (54.8 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 3.02x and 2.25x times faster than real-time at 200 MHz using the bigram and trigram language models, respectively.
    IEEE, 2013, 2013 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), 147 - 152, English
    [Refereed]
    International conference proceedings

  • Low-power Hardware Implementation of Noise Tolerant Heart Rate Extractor for a Wearable Monitoring System
    Shintaro Izumi, Masanao Nakano, Ken Yamashita, Takahide Fujii, Hiroshi Kawaguchi, Masahiko Yoshimoto
    To prevent lifestyle diseases, wearable bio-signal monitoring systems for daily life monitoring have attracted attention. Wearable systems have strict size and weight constraints, which impose significant limitations of the battery capacity and the signal-to-noise ratio of bio-signals. The novelty of this work is the hardware implementation of a noise-tolerant heart rate extraction algorithm that can achieve low-power performance with high reliability. This report describes comparisons of the heart rate extraction algorithm performance and the dedicated hardware implementation of short-term autocorrelation ( STAC) method. The proposed heart rate extractor, implemented in 65-nm CMOS process using Verilog-HDL, consumes 1.65 mu A at 32.768-kHz operating frequency with 1.1 V supply voltage.
    IEEE, 2013, 2013 IEEE 13TH INTERNATIONAL CONFERENCE ON BIOINFORMATICS AND BIOENGINEERING (BIBE), pp.1 - 4, English
    [Refereed]
    International conference proceedings

  • A 0.38-V Operating STT-MRAM with Process Variation Tolerant Sense Amplifier
    Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii
    This paper exhibits a 65-nm 8-Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at a single supply voltage with a process-variation tolerant sense amplifier. The proposed sense amplifier comprises a boosted-gate nMOS and negative-resistance pMOSes as loads, which maximizes the readout margin in any process corner. The STT-MRAM achieves a cycle time of 1.9 mu s (=0.526 MHz) at 0.38 V. The operating power is 6.15 mu W at that voltage. The minimum energy per access is 3.89 pJ/bit when the supply voltage is 0.44 V. The proposed STT-MRAM operates at lower energy than SRAM when a utilization of a memory bandwidth is 14% or less.
    IEEE, 2013, PROCEEDINGS OF THE 2013 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 249 - 252, English
    [Refereed]
    International conference proceedings

  • A 2.4x-Real-Time VLSI Processor for 60-k Word Continuous Speech Recognition
    MIYAMOTO Yuuki, HE Guangji, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    This paper describes a low-power VLSI chip for 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). Our implementation includes a compression–decoding scheme to reduce the external memory bandwidth for Gaussian Mixture Model (GMM) computation and multi-path Viterbi transition units. We optimize the internal SRAM size using the max-approximation GMM calculation and adjusting the number of look-ahead frames. The measured results show that our implementation achieves 34.2% required frequency reduction (83.3 MHz) and reduces 48.5% power consumption (74.14 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 2.4× faster than real-time at 200 MHz and 1.1 V with power consumption of 168 mW.
    The Institute of Electronics, Information and Communication Engineers, Dec. 2012, Technical report of IEICE. ICD, 112(365) (365), 49 - 53, Japanese
    Scientific journal

  • Low-Power Ferroelectric 6T4C Shadow SRAM for Normally-Off Computing
    Nakagawa Tomoki, Yoshimoto Shusuke, Kitahara Yuki, Yanagida Koji, Umeki Yohei, Okumura Shunsuke, Izumi Shintaro, Kawaguchi Hiroshi, Yoshimoto Masahiko
    In recent years, sensor network has attracted much attention in agricultural, medical, and disaster-prevention area to collect on-field information. Each sensor node requires extremely low-power operation because its battery size is limited. In the sensor node chip, memory consumes large leakage power so a low-power memory technique is strongly required.

    This paper presents a novel low-power technique for a ferroelectric 6T4C shadow SRAM. The shadow SRAM works a high-speed SRAM in an active mode and a nonvolatile FeRAM in a sleep mode. The nonvolatility completely removes the leakage current from the memory. However, the ferroelectric capacitors increase the power consumption and decrease the cycle time of the SRAM. In this paper, the proposed technique is evaluated by SPICE simulation results.
    The Institute of Electronics, Information and Communication Engineers, Dec. 2012, Technical report of IEICE. ICD, 112(365) (365), 41 - 41, Japanese
    Scientific journal

  • Instantaneous Heart Rate Detection Using Short-Time Autocorrelation for Wearable Healthcare Systems
    YAMASHITA Ken, NAKANO Masanao, KONISHI Toshihiro, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    This report describes a robust method of Instantaneous Heart Rate (IHR) detection from noisy electrocardiogram (ECG) signals. Generally, the IHR is calculated from the interval of R-waves. Then, the R-waves are extracted from the ECG using a threshold. However, in wearable biosignal monitoring systems, various noises (e.g. muscle artifacts from myoelectric signals, electrode motion artifacts) increase incidences of misdetection and false detection because the power consumption and electrode distance of the wearable sensor are limited to reduce its size and weight. To prevent incorrect detection, we use a short-time autocorrelation technique. The proposed method uses similarity of the waveform of the QRS complex. Therefore, it has no threshold calculation Process and it is robust for noisy environment. By the proposed method, it is possible to reduce power consumption of Analog Front End and relax the performance requirements of the electrodes because IHR is calculated by digital signal processing.
    The Institute of Electronics, Information and Communication Engineers, Dec. 2012, Technical report of IEICE. ICD, 112(365) (365), 27 - 27, Japanese
    Scientific journal

  • FPGA Implementation of HOG-based Real-Time Object Detection Processor
    TAKAGI Kenta, MIZUNO Kosuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Histogram of Oriented Gradients (HOG) is widely accepted feature descriptor for object detection. HOG is robust against changes in illumination and texture. Thus, HOG is highly effective for pedestrian detection and other object detection. In recent years, object detection techniques have been introduced to advanced automobile products and increasingly valuable. Additionally, recent progress of general-purpose processors enables to implement algorithms that require heavy computations such as HOG-based object detection. However, these processors suffer from high power consumption and are therefore unsuitable for mobile systems under limited battery conditions. Therefore, we propose a HOG-based object detection processor. It features a simplified HOG algorithm with cell-based scanning and simultaneous Support Vector Machine (SVM) calculation, cell-based pipeline architecture and parallelized modules. To evaluate the effectiveness of our approach, the proposed architecture is implemented onto a FPGA prototyping board. Results show that the proposed architecture can generate HOG features and detect objects with 40 MHz for SVGA resolution video (800 × 600 pixels) at 72 frames per second (fps).
    The Institute of Electronics, Information and Communication Engineers, Dec. 2012, Technical report of IEICE. ICD, 112(365) (365), 61 - 61, Japanese
    Scientific journal

  • Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We propose a chip identification (ID) generating scheme with random variation of transistor characteristics in SRAM bitcells. In the proposed scheme, a unique fingerprint is generated by grounding both bitlines in write operations. Through minor modifications, this scheme can be implemented for existing SRAMs. It has high speed, and it can be implemented in a very small area overhead. The generated fingerprint mainly reflects threshold voltages of load transistors in the bitcells. We fabricated test chips in a 65-nm process and obtained 12,288 sets of unique 128-bit fingerprints, which are evaluated in this paper. The failure rate of the IDs is found to be 2.1 x 10(-12).
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Dec. 2012, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E95A(12) (12), 2226 - 2233, English
    [Refereed]
    Scientific journal

  • Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents a new 8T (8-transistor) SRAM cell layout mitigating multiple-bit upset (MBU) in a divided wordline structure. Because bitlines along unselected columns are not activated, the divided wordline structure eliminates a half-select problem and achieves low-power operation, which is often preferred for low-power/low-voltage applications. However, the conventional 81 SRAM with the divided wordline structure engenders MBUs because all bits in the same word are physically adjoining. Consequently, it is difficult to apply an error correction coding (ECC) technique to it. In this paper, we propose a new 81 cell layout pattern that separates internal latches in SRAM cells using both an n-well and a p-substrate. We saw that a SEU cross section of nMOS is 3.5-4.5 times higher than that of pMOS (SEU: single event upset; a cross section signifies a sensitive area to soft error effects). By using a soft-error simulator, iRoC TFIT, we confirmed that the proposed 81 cell has better neutron-induced MBU tolerance. The simulator includes soft-error measurement data in a commercial 65-nm process. The MBU in the proposed 81 SRAM is improved by 90.70% and the MBU soft error rate (SER) is decreased to 3.46 FIT at 0.9 V when ECC is implemented (FIT: failure in time). Additionally, we conducted Synopsys 3-0 TCAD simulation, which indicates that the linear energy transfer (LET) threshold in SEU is also improved by 66% in the proposed 81 SRAM by a common-mode effect.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Oct. 2012, IEICE TRANSACTIONS ON ELECTRONICS, E95C(10) (10), 1675 - 1681, English
    [Refereed]
    Scientific journal

  • Guangji He, Takanobu Sugahara, Yuki Miyamoto, Tsuyoshi Fujinaga, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We have developed a low-power VLSI chip for 60-kWord real-time continuous speech recognition based on a context-dependent hidden Markov model (HMM). Our implementation includes a cache architecture using locality of speech recognition, beam pruning using a dynamic threshold, two-stage language model searching, highly parallel Gaussian mixture model (GMM) computation based on the mixture level, a variable-frame look-ahead scheme, and elastic pipeline operation between the Viterbi transition and GMM processing. The accuracy degradation of the important parameters in Viterbi computation is strictly discussed. Results show that our implementation achieves 95% bandwidth reduction (70.86 MB/s) and 78% required frequency reduction (126.5 MHz) comparing to the referential Julius [1] system. The test chip, fabricated using 40 nm CMOS technology, contains 1.9 M transistors for logic and 7.8 Mbit on-chip memory. It dissipates 144 mW at 126.5 MHz and 1.1 V for 60-kWord real-time continuous speech recognition.
    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, Aug. 2012, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 59(8) (8), 1656 - 1666, English
    [Refereed]
    Scientific journal

  • Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Koji Nii, Masahiko Yoshimoto, Hiroshi Kawaguchi
    This paper presents measurement results of bit error rate (BER) and soft error rate (SER) improvement on 150-nm FD-SOI 7T/14T (7-transistor/14-transistor) SRAM test chips. The reliability of the 7T/14T SRAM can be dynamically changed by a control signal depending on an operating condition and application. The 14T dependable mode allocates one bit in a 14T cell and improves the BER in a read operation and SER in a retention state, simultaneously. We investigate its error rate mitigating mechanisms using Synopsys TCAD simulator. In our measurements, the minimum operating voltage was improved by 100 mV, the alpha-induced SER was suppressed by 80.0%, and the neutron-induced SER was decreased by 34.4% in the 14T dependable mode over the 7T normal mode.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Aug. 2012, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E95A(8) (8), 1359 - 1365, English
    [Refereed]
    Scientific journal

  • Trading off ECU Footprint for Reliability in X-by-Wire Application with Hybrid TMR Architecture
    Y. Nakata, S. Izumi, H. Kawaguchi, YOSHIMOTO MASAHIKO
    Jun. 2012, DAC International Workshop on System Level-Design of Automotive Electronics/Software (SLDAES),, English
    [Refereed]
    International conference proceedings

  • SRAMセルを用いたLow書込みによるチップID生成手法
    奥村俊介, 吉本秀輔, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO
    Apr. 2012, 信学技報, vol. 112(no. 15) (no. 15), pp. 97 - 102, Japanese
    Scientific journal

  • Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto
    As process technology is scaled down, a typical system on a chip (SoC) becomes denser. In scaled process technology, process variation becomes greater and increasingly affects the SoC circuits. Moreover, the process variation strongly affects network-on-chips (NoCs) that have a synchronous network across the chip. Therefore, its network frequency is degraded. We propose a process-variation-adaptive NoC with a variation-adaptive variable-cycle router (VAVCR). The proposed VAVCR can configure its cycle latency adaptively on a processor core basis, corresponding to the process variation. It can increase the network frequency, which is limited by the process variation in a conventional router. Furthermore, we propose a variable-cycle pipeline adaptive routing (VCPAR) method with VAVCR; the proposed VCPAR can reduce packet latency and has tolerance to network congestion. The total execution time reduction of the proposed VAVCR with VCPAR is 15.7%, on average, for five task graphs.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2012, IEICE TRANSACTIONS ON ELECTRONICS, E95C(4) (4), 523 - 533, English
    [Refereed]
    Scientific journal

  • Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents a novel disturb mitigation scheme which achieves low-energy operation for a deep sub-micron 8T SRAM macro. The classic write-back scheme with a dedicated read port overcame both half-select and read-disturb problems. Moreover, it improved the yield, particularly in the low-voltage range. The conventional scheme, however, consumed more power because of charging and discharging all write bitlines in a sub-block. Our proposed scheme reduces the power overhead of the write-back scheme using a floating write bitline technique and a low-swing bitline driver (LSBD). The floating bitline and the LSBD respectively consist of a precharge-less CMOS equalizer (transmission gate) and an nMOS write-back driver. The voltage on the floating write bitline is at an intermediate voltage between the ground and the supply voltage before a write cycle. The write target cells are written by normal CMOS drivers, whereas the write bitlines in half-selected columns are driven by the LSBDs in the write cycle, which suppresses the write bitline voltage to VDD - V-tn and therefore saves the active power in the half-selected columns (where V-tn is a threshold voltage of an nMOS). In addition, the proposed scheme reduces a leakage current from the write bitline because of the floating write bitline. The active leakage is reduced by 33% at the FF corner, 125 degrees C. The active energy in the write operation is reduced by 37% at the FF corner. In other process corners, more writing power reduction can be expected because it depends on the V-tn in the LSBD. We fabricated a 512-Kb 8T SRAM test chip that operates at a single 0.5-V supply voltage. The test chip with the proposed scheme respectively achieves 1.52-mu W/MHz writing energy and 72.8-mu W leakage power, which are 59.4% and 26.0% better than those of the conventional write-back scheme. The total energy is 12.9 mu W/MHz (12.9 pJ/access) at a supply voltage of 0.5 V and operating frequency of 6.25 MHz in a 50%-read/50%-write operation.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2012, IEICE TRANSACTIONS ON ELECTRONICS, E95C(4) (4), 572 - 578, English
    [Refereed]
    Scientific journal

  • Shunsuke Okumura, Hidehiro Fujiwara, Kosuke Yamaguchi, Shusuke Yoshimoto, Masahiko Yoshimoto, Hiroshi Kawaguchi
    We propose a novel substrate-bias control scheme for an FD-SOI SRAM that suppresses inter-die variability. The proposed circuits detect inter-die threshold-voltage variation automatically, and then maximize read/write margins of memory cells to supply the substrate bias. We confirmed that a 486-kb 61 SRAM operates at 0.42 V, in which an FS corner can be compared as much as 0.14 V or more.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2012, IEICE TRANSACTIONS ON ELECTRONICS, E95C(4) (4), 579 - 585, English
    [Refereed]
    Scientific journal

  • Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy
    Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper proposes a 7T SRAM that realizes a block-level instantaneous comparison feature. The proposed SRAM is useful for operation results comparison in dual modular redundancy (DMR). The data size that can be instantaneously compared is scalable using the proposed structure. The 1-Mb SRAM comprises 16-Kb blocks in which 8-Kb data can be compared in 130.0 ns. The proposed scheme reduces energy consumption in data comparison to 1/418, compared to that of a parallel cyclic redundancy check (CRC) circuit.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Mar. 2012, IEICE ELECTRONICS EXPRESS, 9(6) (6), 470 - 476, English
    [Refereed]
    Scientific journal

  • Nakata Yohei, Okumura Shunsuke, Kawaguchi Hiroshi, Yoshimoto Masahiko
    This paper presents a novel cache architecture using 7T/14T SRAM, which can improve its reliability with control lines dynamically. Our proposed 14T word-enhancing scheme can enhance its operating margin in word granularity by combining two words in a low-voltage mode. Furthermore, we propose a new testing method that maximizes the efficiency of the 14T word-enhancing scheme. In a 65-nm process, it can reduce the minimum operation voltage (Vmin) to 0.5V to a level that is 42% and 21% lower, respectively, than those of a conventional 6T SRAM and a cache word-disable scheme. Measurement results show that the 14T word-enhancing scheme can reduce Vmin of the 6T SRAM and 14T dependable modes by 25% and 19%, respectively. The respective dynamic power reductions are 89.2% and 73.9%. The respective total power reductions are 44.8% and 20.9%.
    Information and Media Technologies Editorial Board, 2012, IMT, 7(2) (2), 544 - 555, English

  • Kosuke Mizuno, Yosuke Terachi, Kenta Takagi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a Histogram of Oriented Gradients (HOG) feature extraction processor for HDTV resolution video (1920 × 1080 pixels). It features a simplified HOG algorithm with cell-based scanning and simultaneous Support Vector Machine (SVM) calculation, cell-based pipeline architecture, and parallelized modules. To evaluate the effectiveness of our approach, the proposed architecture is implemented onto a FPGA prototyping board. Results show that the proposed architecture can generate HOG features and detect objects with 40 MHz for SVGA resolution video (800 × 600 pixels) at 72 frames per second (fps). The proposed schemes are easily expandable to HDTV resolution video at 30 fps with 76.2 MHz if a highresolution camera and higher operating frequency are available. © 2012 IEEE.
    2012, IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, 197 - 202, English
    [Refereed]
    International conference proceedings

  • Nakano, Masanao, Konishi, Toshihiro, Izumi, Shintaro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko
    This report describes a robust method of Instantaneous Heart Rate (IHR) detection from noisy electrocardiogram (ECG) signals. Generally, the IHR is calculated from the interval of R-waves. Then, the R-waves are extracted from the ECG using a threshold. However, in wearable biosignal monitoring systems, various noises (e.g. muscle artifacts from myoelectric signals, electrode motion artifacts) increase incidences of misdetection and false detection because the power consumption and electrode distance of the wearable sensor are limited to reduce its size and weight. To prevent incorrect detection, we use a short-time autocorrelation technique. The proposed method uses similarity of the waveform of the QRS complex. Therefore, it has no threshold calculation Process and it is robust for noisy environment. Simulation results show that the proposed method improves the success rate of IHR detection by up to 37%.
    IEEE, 2012, 2012 ANNUAL INTERNATIONAL CONFERENCE OF THE IEEE ENGINEERING IN MEDICINE AND BIOLOGY SOCIETY (EMBC), 2012, 6703 - 6706, English, International magazine
    [Refereed]
    International conference proceedings

  • Shimpei Soda, Masahide Nakamura, Shinsuke Matsumoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We have been developing a hands-free voice controller for a home network system (HNS) by using microphone arrays. In our current implementation, however, all human-HNS interactions are performed by voice only. Hence, the interactions tend to be mechanical, dreary and uninformative. To achieve richer interactions, we try to introduce the virtual agent technology as a feedback interface of the HNS. In this paper, we implement the virtual agent as a Web service, by using MMDAgent Toolkit extensively. The agent is then integrated with the HNS and microphone arrays in a service-oriented fashion. Finally, we conduct a user experiment with three versions of virtual agents. In the experiment, we evaluate how the virtual agent can enrich the interactions. © 2012 IEEE.
    IEEE Computer Society, 2012, Proceedings - Asia-Pacific Software Engineering Conference, APSEC, 1, 342 - 345, English
    [Refereed]
    International conference proceedings

  • 読出しビット線リミット機構を備えた40-nm 256-Kb サブ10pJ/access動作8T SRAM
    吉本 秀輔, 寺田 正治, 梅木 洋平, 奥村 俊介, 川澄 篤, 鈴木 利一, 森脇 真一, 宮野 信治, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO
    This paper presents a novel read-bitline amplitude limiting (RBAL) scheme which suppresses dynamic energy dissipation caused by random variation. In addition, a discharge acceleration (DA) circuit is proposed to decrease delay overhead of RBAL. The proposed scheme improves the active energy dissipation in a read cycle by 22% at the center-center (CC) corner and 25℃. The maximum delay overhead is 32% at the fast-slow (FS) corner and -40℃. The circuits have been implemented using the 40-nm bulk CMOS process. The implemented 256-Kb 8T SRAM works fine with energy dissipation of sub-10 pJ / access from 0.5-0.7V.
    The Institute of Electronics, Information and Communication Engineers, 2012, 信学技報, vol. 112(no. 169) (no. 169), pp. 7 - 12, Japanese
    Scientific journal

  • 低電力ディスターブ緩和技術を備えた40nm 12.9pJ/access 8T SRAM
    吉本 秀輔, 寺田 正治, 奥村 俊介, 鈴木 利一, 宮野 信治, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO
    2012, 信学技報, vol. 112(no. 15) (no. 15), pp. 67 - 72, Japanese
    Scientific journal

  • 低エネルギ比較機能を有するDMR応用7T SRAM
    梅木 洋平, 奥村 俊介, 中田 洋平, 柳田 晃司, 鍵山 祐輝, 吉本 秀輔, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO
    This paper proposes a 7T SRAM that realizes a block-level instantaneous comparison feature. The proposed SRAM is useful for operation results comparison in dual modular redundancy (DMR). The data size that can be instantaneously compared is scalable using the proposed structure. The 1-Mb SRAM comprises 16-Kb blocks in which 8-Kb data can be compared in 130.0ns. The proposed scheme reduces energy consumption in data comparison to 1/418, compared to that of a parallel cyclic redundancy check (CRC) circuit.
    The Institute of Electronics, Information and Communication Engineers, 2012, 信学技報, vol. 112(no. 15) (no. 15), pp. 85 - 90, Japanese
    Scientific journal

  • プロセスばらつきを考慮した低電圧動作混合連想度キャッシュ構造
    鄭 晋旭, 中田 洋平, 奥村 俊介, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO
    2012, 信学技報, vol. 112(no. 170) (no. 170), pp. 1 - 6, Japanese
    Scientific journal

  • Takashi Matsuda, Shintaro Izumi, Yasuharu Sakai, Takashi Takeuchi, Hidehiro Fujiwara, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    One of the most challenging issues in wireless sensor networks is extension of the overall network lifetime. Data aggregation is one promising solution because it reduces the amount of network traffic by eliminating redundant data. In order to aggregate data, each sensor node must temporarily store received data, which requires a specific amount of memory. Most sensor nodes use static random access memory (SRAM) or flash memory for storage. SRAM can be implemented in a one-chip sensor node at low cost; however, SRAM requires standby energy, which consumes a lot of power, especially because the sensor node spends most of its time sleeping, i.e. its radio circuits are quiescent. This study proposes two types of divided SRAM: equal-size divided SRAM and equal-ratio divided SRAM. Simulations show that both proposed SRAM types offer reduced power consumption in various situations.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jan. 2012, IEICE TRANSACTIONS ON COMMUNICATIONS, E95B(1) (1), 178 - 188, English
    [Refereed]
    Scientific journal

  • Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents a novel cache architecture using 7T/14T SRAM, which can improve its reliability with control lines dynamically. Our proposed 14T word-enhancing scheme can enhance its operating margin in word granularity by combining two words in a low-voltage mode. Furthermore, we propose a new testing method that maximizes the efficiency of the 14T word-enhancing scheme. In a 65-nm process, it can reduce the minimum operation voltage (Vmin) to 0.5V to a level that is 42% and 21% lower, respectively, than those of a conventional 6T SRAM and a cache word-disable scheme. Measurement results show that the 14T word-enhancing scheme can reduce Vmin of the 6T SRAM and 14T dependable modes by 25% and 19%, respectively. The respective dynamic power reductions are 89.2% and 73.9%. The respective total power reductions are 44.8% and 20.9%. © 2012 Information Processing Society of Japan.
    2012, IPSJ Transactions on System LSI Design Methodology, 5, 32 - 43, English
    [Refereed]
    Scientific journal

  • Bit Error Rate Estimation in SRAM Considering Temperature Fluctuation
    Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, Shusuke Yoshimoto, Yohei Nakata, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    SRAM performance varies depending on the operating environment. This study specifically examines the bit error rate (BER) when considering temperature fluctuation. The SRAM performance is generally determined using a read margin because a half-select issue must be considered even in a write operation. As a metric of the SRAM's performance, we also adopt a static noise margin (SNM) with which we evaluate three methods to estimate the BER considering temperature fluctuation. Method 1 iterates calculations for the SNM many times with Monte Carlo simulation. BER is defined as the number of cells that have no margin. Method 2 includes the assumption that SNM forms a normal distribution. Its BER is defined as a probability distribution function. Method 3 includes the assumption that SNM is determined as either square but not the smaller one of the two squares. The BER estimations are compared with a test chip result implemented in a 65-nm CMOS technology: Method 2 has 11.10% and Method 3 has 4.09% difference (unfortunately, Method 1 has no data missing because of a lack of simulations). The shift of the minimum operating voltage between the low and high temperatures is 0.04 V at a 128-Kb capacity when the temperature fluctuates from 25 degrees C to 100 degrees C.
    IEEE, 2012, 2012 13TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), pp. 514-517, 516 - 519, English
    [Refereed]
    International conference proceedings

  • A 40-nm 256-Kb 0.6-V Operation Half-Select Resilient 8T SRAM with Sequential Writing Technique Enabling 367-mV VDDmin Reduction
    M. Terada, S. Yoshimoto, S. Okumura, T. Suzuki, S. Miyano, H. Kawaguchi, M. Yoshimoto
    This paper introduces a novel half-select resilient dual write wordline 8T (DW8T) SRAM with a sequential writing technique. The process scaling increases random variation that degrades SRAM operating margins, for which the proposed DW8T cell presents two features: half-VDD precharging write bitlines and dual write wordlines. The dual write wordlines are sequentially activated in a write cycle, and its combination with the half-VDD precharge suppresses the half-select problem. The DW8T SRAM with the sequential writing technique improve a half-select bit error rate by 71% at the disturb worst corner (FS, 125 degrees C) and by 79% at a typical corner (CC, 25 degrees C) over the conventional 8T, respectively. We implemented a 256-Kb DW8T SRAM and a half-VDD generator on a single chip in a 40-nm CMOS process. The measurement results of the seven samples show that the proposed DW8T SRAM achieves a VDDmin of 600 mV and improves the average VDDmin by 367 mV compared to the conventional 8T SRAM. The measured leakage power can be reduced by 25%.
    IEEE, 2012, 2012 13TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), pp. 487-490, 489 - 492, English
    [Refereed]
    International conference proceedings

  • NMOS-Inside 6T SRAM Layout Reducing Neutron-Induced Multiple Cell Upsets
    Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents a novel NMOS-inside 6T SRAM cell layout that reduces a neutron-induced MCU SER on a same wordline. We implemented a 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER The proposed 6T SRAM macro improves the horizontal MCU SER by 67-98% compared with a general macro that has PMOS-inside 6T SRAM cells.
    IEEE, 2012, 2012 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), pp. 5B.5.1 - 5, English
    [Refereed]
    International conference proceedings

  • A 51-dB SNDR DCO-Based TDC Using Two-Stage Second-Order Noise Shaping
    Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    This paper presents a two-stage second-order noise shaping time-to-digital converter (TDC) using a one-bit digitally-controlled oscillator (DCO). The clocks output from DCOs are counted and digitized as in a conventional gated ring oscillator (GRO) TDC. A time error is propagated to the second DCO, which provides second-order noise shaping. In the conventional GROTDC, internal oscillators must maintain their phase state. However, because of the leak current, the stored phase states are degraded or even lost. In our proposed architecture, the DCOs always oscillate and need not maintain their phase state. Therefore, our proposed TDC is more suitable in leaky recent process than a GROTDC is. Because no switched capacitor or opamp is used, the proposed TDC can be implemented in a small area and with low power. Mismatches in the oscillation frequency between the DCOs might occur. However, error detection and correction can be performed using a first-order least mean square (LMS) filter. In a standard 65-nm CMOS process, an SNDR of 51 dB is achievable at an input bandwidth of 3 MHz and a sampling rate of 65 MHz, where the power is 271 mu W.
    IEEE, 2012, 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), pp. 3170 - 3173, English
    [Refereed]
    International conference proceedings

  • Neutron-Induced Soft Error Rate Estimation for SRAM Using PHITS
    Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents a novel neutron-induced soft-error-rate (SER) estimation tool with a particle transport code: PHITS. The proposed tool can calculate the SER according to various data patterns and the layout of the memory cells in an SRAM. As layouts, two kinds of an NMOS-PMOS-NMOS 6T and an inside-out PMOS-NMOS-PMOS versions are considered. The proposed tool distinguishes a single-event-upset (SEU) SER, a horizontal multiple-cell-upset (MCU) SER, and a vertical MCU SER using an extracting function. The horizontal MCU SER in the inside-out version of the PMOS-NMOS-PMOS 6T SRAM cell layout was expected to be 26-41% less than that of the general NMOS-PMOS-NMOS 6T cell layout.
    IEEE, 2012, 2012 IEEE 18TH INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), 138 - 141, English
    [Refereed]
    International conference proceedings

  • Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
    In this paper, we present a novel cache scheme which efficiently reduces the minimum operating voltage (Vmin) despite manufacturing-induced defective SRAM cells. The proposed low-voltage scheme exploits the fact that locations of defective SRAM cells are usually non-uniformly scattered. It also leverages the reliable characteristics of 7T/14T SRAM and allows associativites in each index to be different. Our evaluation results show that the proposed cache can reduce Vmin of 64 KB 8-way set-associative cache by 80 mV within 7.81% capacity and 5.22% area overhead. © 2012 IEEE.
    2012, 2012 IEEE Faible Tension Faible Consommation, FTFC 2012, English
    [Refereed]
    International conference proceedings

  • A 62-dB SNDR Second-Order Gated Ring Oscillator TDC with Two-Stage Dynamic D-Type Flipflops as A Quantization Noise Propagator
    Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    This paper presents a second-order noise shaping time-to-digital converter (TDC) with two gated ring oscillators (GROs). The oscillating outputs from the GROs are counted and digitized. As a quantization noise propagator (QNP) between the two GROs, two-stage dynamic d-type flipflops (DDFFs) and a NOR gate are adopted. The proposed QNP does not propagate a time error caused by flipflop's metastability to the next GRO, and thus improves its linearity over the conventional masterslave d-type flipflop. In a standard 65-nm CMOS process, an SNDR of 62-dB is achievable at a sampling rate of 65MS/s.
    IEEE, 2012, 2012 IEEE 10TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), IEEE International New Circuit, 289 - 292, English
    [Refereed]
    International conference proceedings

  • Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    We present a small-area second-order all-digital time-to-digital converter (TDC) with two frequency shift oscillators (FSOs) comprising inverter chains and dynamic flipflops featuring low jitter. The proposed FSOs can maintain their phase states through continuous oscillation, unlike conventional gated ring oscillators (GROs) that are affected by transistor leakage. Our proposed FSOTDC is more robust and is eligible for all-digital TDC architectures in recent leaky processes. Low-jitter dynamic flipflops are adopted as a quantization noise propagator (QNP). A frequency mismatch occurring between the two FSOs can be canceled out using a least mean squares (LMS) filter so that second-order noise shaping is possible. In a standard 65-nm CMOS process, an SNDR of 61 dB is achievable at an input bandwidth of 500 kHz and a sampling rate of 16 MHz, where the respective area and power are 700 μm 2 and 281 μW. © 2012 IEEE.
    2012, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 190 - 191, English
    [Refereed]
    International conference proceedings

  • S. Yoshimoto, M. Terada, S. Okumura, T. Suzuki, S. Miyano, H. Kawaguchi, M. Yoshimoto
    This paper introduces a novel half-select resilient dual write wordline 8T (DW8T) SRAM with a sequential writing technique. The dual write wordlines are sequentially activated in a write cycle, and its combination with the half-VDD precharge suppresses the half-select problem. We implemented a 256-Kb DW8T SRAM and a half-VDD generator with a 40-nm CMOS process. The measurement results of the seven samples show that the proposed DW8T SRAM achieves a VDDmin of 600mV and improves the average VDDmin by 367mV compared to the conventional 8T SRAM. The measured leakage power can be reduced by 25%.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2012, IEICE ELECTRONICS EXPRESS, 9(12) (12), 1023 - 1029, English
    [Refereed]
    Scientific journal

  • Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents a novel read-bitline amplitude limiting (RBAL) scheme which suppresses dynamic energy dissipation caused by random variation. In addition, a discharge acceleration (DA) circuit is proposed to decrease delay overhead of RBAL. The proposed scheme improves the active energy dissipation in a read cycle by 22% at the center-center (CC) corner and 25°C. The maximum delay overhead is 32% at the fast-slow (FS) corner and -40°C. The circuits have been implemented using the 40-nm bulk CMOS process. The implemented 256-Kb 8T SRAM works fine with energy dissipation of sub-10 pJ / access from 0.5-0.7 V. © 2012 ACM.
    2012, Proceedings of the International Symposium on Low Power Electronics and Design, 85 - 90, English
    [Refereed]
    International conference proceedings

  • A 40-nm 168-mW 2.4x-Real-Time VLSI Processor for 60-kWord Continuous Speech Recognition
    Guangji He, Takanobu Sugahara, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). Our implementation includes a compression-decoding scheme to reduce the external memory bandwidth for Gaussian Mixture Model (GMM) computation and multi-path Viterbi transition units. We optimize the internal SRAM size using the max-approximation GMM calculation and adjusting the number of look-ahead frames. The test chip, fabricated in 40 nm CMOS technology, occupies 1.77 mm x 2.18 mm containing 2.52 M transistors for logic and 4.29 Mbit on-chip memory. The measured results show that our implementation achieves 34.2% required frequency reduction (83.3 MHz) and reduces 48.5% power consumption (74.14 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 2.4x faster than real-time at 200 MHz and 1.1 V with power consumption of 168 mW.
    IEEE, 2012, 2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), vol. 59(no. 8) (no. 8), pp.1656 - 1666, English
    [Refereed]
    International conference proceedings

  • Kosuke Mizuno, Yosuke Terachi, Kenta Takagi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a Histogram of Oriented Gradients (HOG) feature extraction processor for HDTV resolution video (1920 x 1080 pixels). It features a simplified HOG algorithm with cell-based scanning and simultaneous Support Vector Machine (SVM) calculation, cell-based pipeline architecture, and parallelized modules. To evaluate the effectiveness of our approach, the proposed architecture is implemented onto a FPGA prototyping board. Results show that the proposed architecture can generate HOG features and detect objects with 40 MHz for SVGA resolution video (800 x 600 pixels) at 72 frames per second (fps). The proposed schemes are easily expandable to HDTV resolution video at 30 fps with 76.2 MHz if a high-resolution camera and higher operating frequency are available.
    IEEE, 2012, 2012 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), 197 - 202, English
    [Refereed]
    International conference proceedings

  • A 40-nm 168-mW 2.4x-Real-Time VLSI Processor for 60-kWord Continuous Speech Recognition
    Guangji He, Takanobu Sugahara, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). Our implementation includes a compression-decoding scheme to reduce the external memory bandwidth for Gaussian Mixture Model (GMM) computation and multi-path Viterbi transition units. We optimize the internal SRAM size using the max-approximation GMM calculation and adjusting the number of look-ahead frames. The test chip, fabricated in 40 nm CMOS technology, occupies 1.77 mm x 2.18 mm containing 2.52 M transistors for logic and 4.29 Mbit on-chip memory. The measured results show that our implementation achieves 34.2% required frequency reduction (83.3 MHz) and reduces 48.5% power consumption (74.14 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 2.4x faster than real-time at 200 MHz and 1.1 V with power consumption of 168 mW.
    IEEE, 2012, 2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), pp.1 - 4, English
    [Refereed]
    International conference proceedings

  • Shimpei Soda, Masahide Nakamura, Shinsuke Matsumoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    The voice control is a promising user interface for the home network system (HNS). In our previous interface, a user had to be equipped with an actual microphone device, which imposed a burden on the user. This paper presents a hands-free voice interface using a microphone array network. The microphone array network enables voice quality enhancement, as well as sound source localization, by networking multiple microphone arrays. Attaching the arrays to the walls or ceiling, users can input voice operations to the HNS from anywhere in the room, without being aware of the microphone devices. We implement a prototype system with a 16ch microphone array, and evaluate the speech recognition rate and the accuracy of sound source localization in a real home network environment. A hands-free operation service and an automatic speech logging service are implemented.
    IEEE, 2012, 2012 THIRD INTERNATIONAL CONFERENCE ON NETWORKING AND COMPUTING (ICNC 2012), 195 - 200, English
    [Refereed]
    International conference proceedings

  • チップ間ばらつき及びチップ内ばらつきを抑制する基板バイアス制御回路を備えた0.42-V 576-Kb 0.15-um FD-SOI 7T/14T SRAM
    吉本 秀輔, 山口 幸介, 奥村 俊介, 吉本 雅彦, 川口 博
    We propose 7T/14T FD-SOI SRAM with a substrate bias control mechanism. The 14T configuration suppresses intra-die variation in a bit cell. The substrate bias control circuits detect a threshold voltage and automatically change it with the substrate bias. Thereby, the inter-die variation is suppressed. By combining these two schemes, we confirmed that a 576-kb SRAM test chip in a 0.15-μm FD-SOI works at 0.43 V.
    The Institute of Electronics, Information and Communication Engineers, Dec. 2011, 信学技報, vol. 111, no. 352, ICD2011-133(352) (352), 155 - 160, Japanese
    Scientific journal

  • Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Takashi Takeuchi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    We propose a transfer gate phase coupler for a low-power multi-phase oscillator (MPOSC). The phase coupler is an nMOS transfer gate, which does not waste charge to the ground and thus achieves low power. The proposed MPOSC can set the number of outputs to an arbitrary number. The test circuit in a 180-nm process and a 65-nm process exhibits 20 phases, including 90 degrees different angles. The designs in a 180-nm CMOS process and a 65-nm CMOS process were fabricated to confirm its process scalability; in the respective designs, we observed 36.6% and 38.3% improvements in a power-delay products, compared with the conventional MPOSCs using inverters and nMOS latches. In a 65-nm process, the measured DNL and 3 sigma period jitter are, respectively, less than +/- 1.22 degrees and 5.82 ps. The power is 284 mu W at 1.85 GHz.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Dec. 2011, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E94A(12) (12), 2701 - 2708, English
    [Refereed]
    Scientific journal

  • Shunsuke Okumura, Yuki Kagiyama, Yohei Nakata, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper proposes 7T SRAM which realizes block-level simultaneous copying feature. The proposed SRAM can be used for data transfer between local memories such as checkpoint data storage and transactional memory. The 1-Mb SRAM is comprised of 32-kb blocks, in which 16-kb data can be copied in 33.3 ns at 1.2 V. The proposed scheme reduces energy consumption in copying by 92.7% compared to the conventional read-modify-write manner. By applying the proposed scheme to transactional memory, the number of write back cycles is possibly reduced by 98.7% compared with the conventional memory system.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Dec. 2011, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E94A(12) (12), 2693 - 2700, English
    [Refereed]
    Scientific journal

  • A 40nm 144mW VLSI Processor for Realtime 60k Word Continuous Speech Recognition
    SUGAHARA Takanobu, HE Guangji, FUJINAGA Tsuyoshi, MIYAMOTO Yuki, NOGUCHI Hiroki, IZUMI Shintaro, KAWAGUCHi Hiroshi, YOSHIMOTO Masahiko
    We have developed a low power VLSI chip for 60k-word real-time continuous speech recognition based on HMM(Hidden Markov Model). Our implementation includes a cache architecture using the locality of speech recognition, beam pruning using dynamic threshold, two-stage language model searching highly parallel Gaussian Mixture Model (GMM) computation based on mixture level, Variable 50 frames look-ahead scheme and elastic pipeline operation between Viterbi transition and GMM processing. Results show that our implementation achieves 97.94% bandwidth reduction (70.86MB/s) and 78% required frequency reduction (126.5MHz) for 60k-word real-time continuous speech recognition. The test chip has been fabricated in 40nm CMOS technology and occupies 2.2mm X 2.5mm containing 1.9M transistors for logic and 7.8 Mbit on-chip memory. Measured data show 144mW power consumption at 126.5MHz and 1.1V.
    The Institute of Electronics, Information and Communication Engineers, Nov. 2011, Technical report of IEICE. ICD, 111(327) (327), 79 - 84, Japanese
    [Refereed]
    Scientific journal

  • Toshihiro Konishi, Shintaro Izumi, Koh Tsuruda, Hyeokjong Lee, Takashi Takeuchi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    Concomitantly with the progress of wireless communications, cognitive radio has attracted attention as a solution for depleted frequency bands. Cognitive radio is suitable for wireless sensor networks because it reduces collisions and thereby achieves energy-efficient communication. To make cognitive radio practical, we propose a low-power multi-resolution spectrum sensing (MRSS) architecture that has flexibility in sensing frequency bands. The conventional MRSS scheme consumes much power and can be adapted only slightly to process scaling because it comprises analog circuits. In contrast, the proposed architecture carries out signal processing in a digital domain and can detect occupied frequency bands at multiple resolutions and with low power. Our digital MRSS module can be implemented in 180-nm and 65-nm CMOS processes using Verilog-HDL. We confirmed that the processes respectively dissipate 9.97 mW and 3.45 mW
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Nov. 2011, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E94A(11) (11), 2287 - 2294, English
    [Refereed]
    Scientific journal

  • A 40-nm 0.5-V 20.1-uW/MHz 8T SRAM with Low-Energy Disturb Mitigation Scheme,
    Syusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
    Jun. 2011, Digest of Technical Papers 2011 Symposium on VLSI Circuits, pp. 72-73, 72 - 73, English
    [Refereed]
    Scientific journal

  • Hiroki Noguchi, Kazuo Miura, Tsuyoshi Fujinaga, Takanobu Sugahara, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We propose a low-memory-bandwidth, high-efficiency VLSI architecture for 60-k word real-time continuous speech recognition. Our architecture includes a cache architecture using the locality of speech recognition, beam pruning using a dynamic threshold, two-stage language model searching, a parallel Gaussian Mixture Model (GMM) architecture based on the mixture level and frame level, a parallel Viterbi architecture, and pipeline operation between Viterbi transition and GMM processing. Results show that our architecture achieves 88.24% required frequency reduction (66.74 MHz) and 84.04% memory bandwidth reduction (549.91 MB/s) for real-time 60-k word continuous speech recognition.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2011, IEICE TRANSACTIONS ON ELECTRONICS, E94C(4) (4), 458 - 467, English
    [Refereed]
    Scientific journal

  • Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Tsuyoshi Fujinaga, Shintaro Izumi, Yasuo Ariki, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a SIFT (Scale Invariant Feature Transform) descriptor generation engine which features a VLSI oriented SIFT algorithm, three-stage pipelined architecture and novel systolic array architectures for Gaussian filtering and key-point extraction. The ROI-based scheme has been employed for the VLSI oriented algorithm. The novel systolic array architecture drastically reduces the number of operation cycle and memory access. The cycle counts of Gaussian filtering module is reduced by 82%, compared with the SIMD architecture. The number of memory accesses of the Gaussian filtering module and the key-point extraction module are reduced by 99.8% and 66% respectively, compared with the results obtained assuming the SIMD architecture. The proposed schemes provide processing capability for HDTV resolution video (1920 x 1080 pixels) at 30 frames per second (fps). The test chip has been fabricated in 65 nm CMOS technology and occupies 4.2 x 4.2 mm(2) containing 1.1M gates and 1.38 Mbit on-chip memory. The measured data demonstrates 38.2 mW power consumption at 78 MHz and 1.2 V.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2011, IEICE TRANSACTIONS ON ELECTRONICS, E94C(4) (4), 448 - 457, English
    [Refereed]
    Scientific journal

  • Noguchi Hiroki, Takagi Tomoya, Kugata Koji, Izumi Shintaro, Yoshimoto Masahiko, Kawaguchi Hiroshi
    We propose a microphone array network that realizes ubiquitous sound acquisition. Several nodes with 16 microphones are connected to form a novel huge sound acquisition system, which carries out voice activity detection (VAD), sound source localization, and sound enhancement. The three operations are distributed among nodes. Using the distributed network, we produce a low-traffic data-intensive array network. To manage node power consumption, VAD is implemented. The system uses little power when speech is not active. For sound localization, a network-connected multiple signal classification (MUSIC) algorithm is used. The experimental result of the sound-source enhancement shows a signal-noise ratio (SNR) improvement of 7.75dB using 112 microphones. Network traffic is reduced by 99.11% when using 1,024 microphones.
    Information and Media Technologies Editorial Board, 2011, Information and Media Technologies, 6(2) (2), 307 - 318, English

  • Noguchi Hiroki, Iguchi Yusuke, Fujiwara Hidehiro, Okumura Shunsuke, Nii Koji, Kawaguchi Hiroshi, Yoshimoto Masahiko
    As process technology is scaled down, a large-capacity SRAM will be used. Its power must be lowered. The Vth variation of the deep-submicron process affects the SRAM operation and its power. This paper compares the macro area, readout power, and operating frequency among dual-port SRAMs: an 8T SRAM, 10T single-end SRAM, and 10T differential SRAM considering the multi-media applications. The 8T SRAM has the lowest transistor count, and is the most area efficient. However, the readout power becomes large and the access time increases because of peripheral circuits. The 10T single-end SRAM, in which a dedicated inverter and transmission gate are appended as a single-end read port, can reduce the readout power by 74%. The operating frequency is improved by 195%, over the 8T SRAM. However, the 10T differential SRAM can operate fastest (256% faster than the 8T SRAM) because its small differential voltage of 50mV achieves high-speed operation. In terms of the power efficiency, however, the readout current is affected by the Vth variation and the timing of sense cannot be optimized singularly among all memory cells in a 45-nm technology. The readout power remains 34% lower than that of the 8T SRAM (33% higher than the 10T single-end SRAM); even its operating voltage is the lowest of the three. The 10T single-end SRAM always consumes less readout power than the 8T or 10T differential SRAM.
    Information and Media Technologies Editorial Board, 2011, Information and Media Technologies, 6(2) (2), 296 - 306, English

  • Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    This paper presents a second-order ΔΣ analog to digital converter (ADC) operating in a time domain. In the proposed ADC architecture, a voltage-controlled delay unit (VCDU) converts an input analog voltage to a delay time. Then the number of clocks output from a gated ring oscillator (GRO) is counted up during the delay time. Because no switched capacitor or opamp is used, the proposed ADC can be implemented in a small area and at low power. For the same reason, it has process scalability: it can be in keeping with Moore's law. A time error is propagated to the second GRO by a multi-stage noise-shaping (MASH) topology, which provides second-order noise-shaping. In a standard 40-nm CMOS process, a SNDR of 45 dB is achievable at an input bandwidth of 3 MHz and a sampling rate of 100 MHz, where the power is 583.2 μW. Its area is 640 μm2. © 2011 IEEE.
    2011, Proceedings - IEEE International Symposium on Circuits and Systems, 518 - 521, English
    [Refereed]
    International conference proceedings

  • Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
    As process technology is scaled down, a large-capacity SRAM will be used. Its power must be lowered. The V th variation of the deep-submicron process affects the SRAM operation and its power. This paper compares the macro area, readout power, and operating frequency among dual-port SRAMs: an 8T SRAM, 10T single-end SRAM, and 10T differential SRAM considering the multi-media applications. The 8T SRAM has the lowest transistor count, and is the most area efficient. However, the readout power becomes large and the access time increases because of peripheral circuits. The 10T single-end SRAM, in which a dedicated inverter and transmission gate are appended as a singleend read port, can reduce the readout power by 74%. The operating frequency is improved by 195%, over the 8T SRAM. However, the 10T differential SRAM can operate fastest (256% faster than the 8T SRAM) because its small differential voltage of 50mV achieves high-speed operation. In terms of the power efficiency, however, the readout current is affected by the V th variation and the timing of sense cannot be optimized singularly among all memory cells in a 45-nm technology. The readout power remains 34% lower than that of the 8T SRAM (33% higher than the 10T single-end SRAM) even its operating voltage is the lowest of the three. The 10T single-end SRAM always consumes less readout power than the 8T or 10T differential SRAM. © 2011 Information Processing Society of Japan.
    2011, IPSJ Transactions on System LSI Design Methodology, 4, 80 - 90, English
    [Refereed]
    Scientific journal

  • 0.42-V 576-kb 0.15-um FD-SOI SRAM with 7T/14T Bit Cells and Substrate Bias Control Circuits for Intra-Die and Inter-Die Variability Compensation
    K. Yamaguchi, S. Okumura, M. Yoshimoto, H. Kawaguchi
    We propose 7T/14T FD-SOI SRAM with a substrate bias control mechanism. The 14T configuration suppresses intra-die variation in a bit cell. The substrate bias control circuits detect a threshold voltage and automatically change it with the substrate bias. Thereby, the inter-die variation is suppressed. By combining these two schemes, we confirmed that a 576-kb SRAM test chip in a 0.15-μm FD-SOI works at 0.43 V.
    The Institute of Electronics, Information and Communication Engineers, Jan. 2011, Proceedings of 7th Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EUROSOI), pp. 37-38(352) (352), 155 - 160, English
    [Refereed]
    Scientific journal

  • Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    We propose a microphone array network that realizes ubiquitous sound acquisition. Several nodes with 16 microphones are connected to form a novel huge sound acquisition system, which carries out voice activity detection (VAD), sound source localization, and sound enhancement. The three operations are distributed among nodes. Using the distributed network, we produce a low-traffic data-intensive array network. To manage node power consumption, VAD is implemented. The system uses little power when speech is not active. For sound localization, a network-connected multiple signal classification (MUSIC) algorithm is used. The experimental result of the sound-source enhancement shows a signal-noise ratio (SNR) improvement of 7.75dB using 112 microphones. Network traffic is reduced by 99.11% when using 1,024 microphones.
    Information Processing Society of Japan, 2011, Journal of Information Processing, 19, 129 - 140, English
    [Refereed]
    Scientific journal

  • 0.45-V Operating V-t-Variation Tolerant 9T/18T Dual-Port SRAM
    Hiroki Noguchi, Shunsuke Okumura, Tomoya Takagi, Koji Kugata, Masahiko Yoshimoto, Hiroshi Kawaguchi
    This paper proposes a dependable dual-port SRAM with 9T/18T bitcell structure. The proposed SRAM has two operating modes: a 9T normal mode and an 18T dependable mode. The 9T bitcell has an outside single-ended bitline as a dedicated read port along with a pair of conventional differential inside bitlines. Therefore, the 18T bitcell has two differential pairs of the outside bitlines and inside bitlines. For the dedicated read port, the 18T bitcell can exploit a differential sense amplifier operating at low voltage, but the 9T bitcell must have a single-ended readout inverter at high voltage. To achieve the 9T/18T SRAM architecture, an interleaved bitline scheme is incorporated for the dedicated read port. The 9T/18T dual-port SRAM can scale its speed, operating voltage, and power dynamically by combining two bitcells for one-bit information. We designed and fabricated the proposed SRAM using a 65-nm process. The measurement results show that the dependable read mode using the pair of the single-ended bitlines can reduce the operation voltage to 0.45 V at a frequency of 1 MHz because of the disturb-free read port, although the dependable read mode using the inside bitlines needs 0.54 V at the same frequency.
    IEEE, 2011, 2011 12TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), pp. 219-222, 225 - 228, English
    [Refereed]
    International conference proceedings

  • Bit Error and Soft Error Hardenable 7T/14T SRAM with 150-nm FD-SOI Process
    Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Kosuke Yamaguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    This paper presents measurement results of bit error rate (BER) and soft error rate (SER) improvement on 150-nm FD-SOI 7T/14T (7-transistor / 14-transistor) SRAM test chips. The reliability of the 7T/14T SRAM can be dynamically changed by a control signal depending on an operating condition and application. The 14T dependable mode allocates one bit in a 14T cell and improves the BER in a read operation and SER in a retention state, simultaneously. We investigate its error rate mitigating mechanisms using Synopsys TCAD simulator. In our measurements, the minimum operating voltage was improved by 100 mV, the alpha-induced SER was suppressed by 80.0%, and the neutron-induced SER was decreased by 34.4% in the 14T dependable mode over the 7T normal mode.
    IEEE, 2011, 2011 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), pp. 876-881, English
    [Refereed]
    International conference proceedings

  • Shimpei Soda, Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    Physical positions are quite useful to realize an intuitive interface for communication among mobile terminals. We propose the placement of a microphone array on mobile terminals and the use of a network as an intuitive interface. The mobile terminals can obtain their relative positions by emitting a sound, which facilitates estimation of the directions of arrival (DOAs) among them. We produced a prototype using a tablet PC, 16 microphones, and an FPGA board. Then, we implemented two applications, exploiting the positioning system to elucidate its wider possibilities. © 2011 IEEE.
    2011, 2011 Joint Workshop on Hands-free Speech Communication and Microphone Arrays, HSCMA'11, 155 - 156, English
    [Refereed]
    International conference proceedings

  • A 40-nm 640-mu m(2) 45-dB Opampless All-Digital Second-Order MASH Delta Sigma ADC
    Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    This paper presents a second-order Delta Sigma analog to digital converter (ADC) operating in a time domain. In the proposed ADC architecture, a voltage-controlled delay unit (VCDU) converts an input analog voltage to a delay time. Then the number of clocks output from a gated ring oscillator (GRO) is counted up during the delay time. Because no switched capacitor or opamp is used, the proposed ADC can be implemented in a small area and at low power. For the same reason, it has process scalability: it can be in keeping with Moore's law. A time error is propagated to the second GRO by a multi-stage noise-shaping (MASH) topology, which provides second-order noise-shaping. In a standard 40-nm CMOS process, a SNDR of 45 dB is achievable at an input bandwidth of 3 MHz and a sampling rate of 100 MHz, where the power is 583.2 mu W. Its area is 640 mu m(2).
    IEEE, 2011, 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), pp. 518-521, 518 - 521, English
    [Refereed]
    International conference proceedings

  • Yohei Nakata, Yasuhiro Ito, Yasuo Sugure, Shigeru Oho, Yusuke Takeuchi, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We propose a fault-injection system (FIS) that can inject faults such as read/write margin failures and soft errors into a SRAM environment. The fault case generator (FCG) generates time-series SRAM failures in 7T/14T or 6T SRAM, and the proposed device model and fault-injection flow are applicable for system-level verification. For evaluation, an abnormal termination rate in vehicle engine control was adopted. We confirmed that the vehicle engine control system with the 7T/14T SRAM improves system-level dependability compared with the conventional 6T SRAM. © 2011 IEEE.
    2011, Proceedings of the International Conference on Dependable Systems and Networks, pp. 91-96, 91 - 96, English
    [Refereed]
    International conference proceedings

  • Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure
    S. Yoshimoto, T. Amashita, D. Kozuwa, T. Takata, M. Yoshimura, Y. Matsunaga, H. Yasuura, H. Kawaguchi, M. Yoshimoto
    This paper presents a new 8T (8-transistor) SRAM cell layout mitigating multiple-bit upset (MBU) in a divided wordline structure. Because bitlines along unselected columns are not activated, the divided wordline structure eliminates a half-select problem and achieves low-power operation, which is often preferred for low-power / low-voltage applications. However, the conventional 8T SRAM with the divided wordline structure engenders MBUs because all bits in the same word are physically adjoining. Consequently, error correction coding (ECC) techniques are difficult to apply. This paper presents a new 8T cell layout pattern that separates internal latches in SRAM cells using both an n-well and a p-substrate. We investigated an SEU cross section of nMOS that is 3.5-4.5 times higher than that of pMOS. Using an iRoC TFIT simulator, we confirmed that the proposed 8T cell has better neutron-induced MBU tolerance. The MBU in the proposed 8T SRAM is improved by 90.70% and the MBU soft error rate (SER) is decreased to 3.46 FIT at 0.9 V when ECC is implemented. Additionally, we conducted Synopsys 3-D TCAD simulation, which indicates that the LET threshold (LETth) in single-event upset (SEU) is also improved by 66.47% in the proposed 8T SRAM by a common-mode effect.
    IEEE COMPUTER SOC, 2011, 2011 IEEE 17TH INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), pp.151-156, English
    [Refereed]
    International conference proceedings

  • Data Aggregation Protocol for Multiple Sound Sources Acquisition with Microphone Array Network
    Shintaro Izumi, Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shimpei Soda, Masahiko Yoshimoto, Hiroshi Kawaguchi
    In this paper, we propose a microphone array network that realizes ubiquitous sound acquisition for multiple sound sources. Several nodes with 16 microphones are connected to form a huge sound acquisition system, which carries out voice activity detection (VAD), sound source localization, and enhancement. The three operations are distributed among nodes with multi-hop data communication. Using the distributed network, we produce a low-traffic data-intensive array network. In the sound-source enhancement, we combine the delay-and-sum beam-forming algorithm with network data aggregation. The prototype of microphone array node is implemented in SUZAKU FPGA boards, which demonstrates a real-time multiple-sound-source enhancement operation.
    IEEE, 2011, 2011 20TH INTERNATIONAL CONFERENCE ON COMPUTER COMMUNICATIONS AND NETWORKS (ICCCN), English
    [Refereed]
    International conference proceedings

  • Yohei Nakata, Yukihiro Takeuchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    As process technology is scaled down, a typical system on a chip (SoC) becomes denser. In scaled process technology, process variation becomes greater and increasingly affects the SoC circuits. Process variation strongly affects Network-on-Chips (NoCs), which have a synchronous network across the chip: its network frequency is degraded. As described herein, we propose a process-variation-adaptive NoC with a variation-adaptive variable-cycle router (VAVCR). The proposed VAVCR can configure its cycle latency adaptively, corresponding to process variation. It can increase the network frequency, which is limited by the slowest network component in a conventional router. The total execution time reduction of the proposed VAVCR is 14.9%, on average, for five task graphs. © 2011 IEEE.
    2011, Proceedings - 2011 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011, pp. 801-804, 801 - 804, English
    [Refereed]
    International conference proceedings

  • Low-Power Block-Level Instantaneous Comparison 7T SRAM for Dual Modular Redundancy
    Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper proposes a 7T SRAM that realizes a block-level instantaneous comparison feature. The proposed SRAM is useful for operation results comparison in dual modular redundancy (DMR). The data size that can be instantaneously compared is scalable using the proposed structure. The 1-Mb SRAM comprises 16-kb blocks in which 8-kb data can be compared in 130.0ns. The proposed scheme reduces power consumption in data comparison by 92.3%, compared to that of a parallel cyclic redundancy check (CRC) circuit.
    IEEE, 2011, 2011 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), pp. 1-4, English
    [Refereed]
    International conference proceedings

  • Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We propose a chip identification (ID) generating scheme with random variation of transistor characteristics in SRAM bitcells. In the proposed scheme, a unique fingerprint is generated by grounding both bitlines in write operation. The generated fingerprint mainly reflects threshold voltages of load transistors in the bitcells. We fabricated test chips in a 65-nm process and obtained 384 sets of unique 128-bit fingerprints from 12 chips, which were evaluated in this paper. The fail rate of the ID was found to be 4.45 × 10-19 at a nominal supply voltage of 1.2 V and at room temperature. This scheme can be implemented for existing SRAMs through minor modifications. It has high speed, and is implemented in a very small area overhead. © 2011 IEEE.
    2011, European Solid-State Circuits Conference, pp. 527-530, 527 - 530, English
    [Refereed]
    International conference proceedings

  • Masanori Nishino, Hiroki Noguchi, Yusuke Shimai, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a low-power eight-core Mixed Integer Quadric Programming (MIQP) solver processor VLSI for real-time autonomous robot control. It features an eight-core architecture with operation-level and task-level parallel processing using speculative execution to solve a 75-variable MIQP problem within 100 ms. The VLSI, containing 12.2 M transistors and occupying 2.7 × 3.0 mm 2 area, was designed and fabricated using 40-nm CMOS technology. It consumes 568 mW with 135 MHz operation, allowing real-time, low-power capability for a 75-variable MIQP solver. © 2011 IEEE.
    2011, 2011 IEEE/SICE International Symposium on System Integration, SII 2011, pp. 469-472, 469 - 472, English
    [Refereed]
    International conference proceedings

  • Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents a dependable cache memory for which associativity can be reconfigured dynamically. The proposed associativity-reconfigurable cache consists of pairs of cache ways. Each pair has two modes: the normal mode and the dependable mode. The proposed cache can dynamically enhance its reliability in the dependable mode, thereby trading off its performance. The reliability of the proposed cache can be scaled by reconfiguring its associativity. Moreover, the configuration can be chosen based upon current operating conditions. Our chip measurement results show that the proposed dependable cache possesses the scalable characteristic of reliability. Moreover, it can decrease the minimum operating voltage by 115 mV. The cycle accurate simulation shows that designing the L1, L2 caches using the proposed scheme results in 4.93% IPC loss on average. Area estimation results show that the proposed cache adds area overhead of 1.91% and 5.57% in 32-KB and 256-KB caches, respectively. © 2011 IEEE.
    2011, 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011, pp. 524-527, 524 - 527, English
    [Refereed]
    International conference proceedings

  • Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure
    S. Yoshimoto, T. Amashita, D. Kozuwa, T. Takata, M. Yoshimura, Y. Matsunaga, H. Yasuura, H. Kawaguchi, M. Yoshimoto
    This paper presents a new 8T (8-transistor) SRAM cell layout mitigating multiple-bit upset (MBU) in a divided wordline structure. Because bitlines along unselected columns are not activated, the divided wordline structure eliminates a half-select problem and achieves low-power operation, which is often preferred for low-power / low-voltage applications. However, the conventional 8T SRAM with the divided wordline structure engenders MBUs because all bits in the same word are physically adjoining. Consequently, error correction coding (ECC) techniques are difficult to apply. This paper presents a new 8T cell layout pattern that separates internal latches in SRAM cells using both an n-well and a p-substrate. We investigated an SEU cross section of nMOS that is 3.5-4.5 times higher than that of pMOS. Using an iRoC TFIT simulator, we confirmed that the proposed 8T cell has better neutron-induced MBU tolerance. The MBU in the proposed 8T SRAM is improved by 90.70% and the MBU soft error rate (SER) is decreased to 3.46 FIT at 0.9 V when ECC is implemented. Additionally, we conducted Synopsys 3-D TCAD simulation, which indicates that the LET threshold (LETth) in single-event upset (SEU) is also improved by 66.47% in the proposed 8T SRAM by a common-mode effect.
    IEEE COMPUTER SOC, 2011, 2011 IEEE 17TH INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), Vol. E95-C(No. 10,) (No. 10,), pp. 1675 - 1681, English
    [Refereed]
    International conference proceedings

  • システムレベル故障注入技術を用いたディペ ンダブルプロセッサアーキテクチャの評価・ 検証
    Y. Nakata, ITO Hiroaki, SUGURE Yasuo, OHO Shigeru, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Nov. 2010, 電子情報通信学会技術研究報告, vol. 110, no. 317, VLD2010-74,, Japanese
    Scientific journal

  • The Area Criteria of 6T and 8T SRAM Cells,
    S. Yoshimoto, S. Okumura, H. Kawaguchi, M. Yoshimoto
    Nov. 2010, EEE/ACM Workshop on Variability Modeling and Characterization (VMC), p.4, English
    Scientific journal

  • ブロック一括コピー機能を有する7T SRAM
    S. Okumura, Y. Kagiyama, S. Yoshimoto, K. Yamaguchi, Y. Nakata, H. Kawaguchi, M. Yoshimoto
    Oct. 2010, 電子情報通信学会CEATEC JAPAN 2010 連携企画研究報告 (Digital Harmony を支えるプロ セッサとDSP,画像処理の最先 端), pp.49-54 (2010), Japanese
    Scientific journal

  • ネットワーク型マイクロホンアレイ間のデー タ集約による音声信号ビームフォーミング
    IZUMI Shintaro, NOGUCHI Hiroki, TAKAGI Tomoya, KUGATA Koji, SODA Shinpei, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi
    Oct. 2010, 電子情報通信学会CEATEC JAPAN 2010 連携企画研究報告 (Digital Harmony を支えるプロ セッサとDSP、画像処理の最先 端), pp.95-100 (2010)(217(IE2010 71-86)) (217(IE2010 71-86)), Japanese
    Scientific journal

  • Takashi Matsuda, Takashi Takeuchi, Takefumi Aonishi, Masumi Ichien, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    Network protocols for wireless sensor networks should be evaluated in terms of life time in a whole system. There exists power variation node due to the manufacturing variation. In this paper, we develop a power model, in which we consider threshold-voltage variation. We implement it to QualNet in order to evaluate the impact against a life time. The simulation results show that the conventional model has overestimated the life time longer than our model when nodes are randomly deployed. In addition, the network life time is extended by 19.3% compared with the conventional model by an optimum deployment.
    The Institute of Electronics, Information and Communication Engineers(IEICE), Mar. 2010, IEICE Electron. Express, Vol. 7, No. 3, pp.197-202(3) (3), 197 - 202, English
    [Refereed]
    Scientific journal

  • Shintaro Izumi, Takashi Takeuchi, Takashi Matsuda, Hyeokjong Lee, Toshihiro Konishi, Koh Tsuruda, Yasuharu Sakai, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    This paper presents an ultra-low-power single-chip sensor-node VLSI for wireless-sensor-network applications A communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system. through a vertical cooperative design among circuits. architecture, and communication protocols The sensor-node LSI features a synchronous media access control (MAC) protocol and integrates a transceiver. 18051 microcontroller. and dedicated MAC processor The test chip occupies 3 x 3 mm(2) in a 180-nm CMOS process. including 1 38 M transistors It dissipates 58 0 mu W under a network environment
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Mar. 2010, IEICE TRANSACTIONS ON ELECTRONICS, E93C(3) (3), 261 - 269, English
    [Refereed]
    Scientific journal

  • A 284-mu W 1.85-GHz 20-Phase Oscillator Using Transfer Gate Phase Couplers
    Hyeokjong Lee, Takashi Takeuchi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    We propose a transfer gate phase coupler for a low-power multi-phase oscillator (MPOSC). The phase coupler is an nMOS transfer gate, which does not waste charge to the ground and thus achieves low power. The proposed MPOSC can set the number of outputs to an arbitrary number. The test circuit in a 180-nm process and a 65-nm process exhibits 20 phases, including 90 different angles. In a 65-nm process, the measured peak DNL and 3 sigma period jitter are, respectively, less than +/- 1.2 degrees and 5.82 ps. The minimum I/Q angle error is 0.019 degrees. The power is 284 mu W at 1.85 GHz.
    IEEE, 2010, 2010 ASIA-PACIFIC MICROWAVE CONFERENCE, 594 - 597, English
    [Refereed]
    International conference proceedings

  • Intelligent Ubiquitous Sensor Network for Sound Acquisition
    Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    We propose a microphone array network that realizes ubiquitous sound acquisition. Nodes with 16 microphones are connected to form a large sound acquisition system that carries out voice activity detection (VAD), sound source localization and sound source separation. The three operations are distributed among nodes using network. Because the VAD is implemented to manage power consumption, the system consumes little power when speech is not active. The power of the VAD module is only 2.1 mW on an FPGA. The system can improve an SNR by 7.75 dB using 112 microphones.
    IEEE, 2010, 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 1414 - 1417, English
    [Refereed]
    International conference proceedings

  • MICROPHONE ARRAY NETWORK FOR UBIQUITOUS SOUND ACQUISITION
    Tomoya Takagi, Hiroki Noguchi, Koji Kugata, Masahiko Yoshimoto, Hiroshi Kawaguchi
    We propose a microphone array network that realizes ubiquitous sound acquisition. Nodes with 16 microphones are connected to form a huge sound acquisition system that carries out VAD, sound source localization and separation. The three operations are distributed among nodes. The VAD is implemented to manage power consumption. Consequently, the system consumes little power when speech is not active. The VAD module uses only 2.1 mW. The system can improve an SNR by 7.75 dB using 112 microphones.
    IEEE, 2010, 2010 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, pp. 1474-1477, 1474 - 1477, English
    [Refereed]
    International conference proceedings

  • Live Demonstration: Intelligent Ubiquitous Sensor Network for Sound Acquisition
    Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    We propose a microphone array network that realizes ubiquitous sound acquisition. Nodes with 16 microphones are connected to form a large sound acquisition system that carries out voice activity detection (VAD), sound source localization and sound source separation. The three operations are distributed among nodes using network. Because the VAD is implemented to manage power consumption, the system consumes little power when speech is not active. The power of the VAD module is only 2.1 mW on an FPGA. The system can improve an SNR by 7.75 dB using 112 microphones.
    IEEE, 2010, 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, p. 1413, 1413 - 1413, English
    [Refereed]
    International conference proceedings

  • Live Demonstration: Intelligent Ubiquitous Sensor Network for Sound Acquisition
    Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    We propose a microphone array network that realizes ubiquitous sound acquisition. Nodes with 16 microphones are connected to form a large sound acquisition system that carries out voice activity detection (VAD), sound source localization and sound source separation. The three operations are distributed among nodes using network. Because the VAD is implemented to manage power consumption, the system consumes little power when speech is not active. The power of the VAD module is only 2.1 mW on an FPGA. The system can improve an SNR by 7.75 dB using 112 microphones.
    IEEE, 2010, 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, pp. 1414-1417, 1413 - 1413, English
    [Refereed]
    International conference proceedings

  • Takashi Takeuchi, Shinji Mikami, Hyeokjong Lee, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    In this paper we propose a novel functional amplifier suitable for low-power wireless receivers in a wireless sensor network. This amplifier can change input threshold level as carrier sensing level, since it has a minimum input amplitude to be amplified. A simple rail-to-rail output is suitable for a subsequent digital interface. The target frequency is 433 MHz, and the maximum voltage gain is 11 dB. The standby power is 39.5 nW, and the active power is 352 mu W. The chip area is 82 x 24 mu m(2).
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jun. 2009, IEICE TRANSACTIONS ON ELECTRONICS, E92C(6) (6), 815 - 821, English
    [Refereed]
    Scientific journal

  • Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper proposes a novel dependable SRAM with 7T/14T memory cells, and introduces a new concept, "quality of a bit (QoB)" for it. The proposed SRAM has three modes: a normal mode, highspeed mode, and dependable mode, and dynamically scales its reliability, power and speed by combining two memory cells for one-bit information (i.e. 14T/bit). By carrying out Monte Carlo simulation in a 65-nm process technology, the minimum voltages in read and write operations are improved by 0.21 V and 0.26 V, respectively, with a bit error rate of 10(-8) kept. In addition, we confirm that the dependable mode achieves a lower bit error rate than the error correction code (ECC) and multi module redundancy (MMR). Furthermore, we propose a new memory array structure to avoid the half-selection problem in a write operation. The respective cell area overheads in the normal mode are 26% and 11% in the cases where additional transistors are pMOSes and nMOSes, compared to the conventional 6T memory cell.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2009, IEICE TRANSACTIONS ON ELECTRONICS, E92C(4) (4), 423 - 432, English
    [Refereed]
    Scientific journal

  • 低消費電力センサノードVLSIのための時刻同期型MACプロトコルの研究
    IZUMI Shintaro, MATSUDA Takashi, TAKEUCHI Takashi, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko
    Mar. 2009, 電子情報通信学会技術研究報告(信学技報), vol. 108, no. 457, NS2008-174,(457(NS2008 143-233)) (457(NS2008 143-233)), Japanese
    International conference proceedings

  • 7T/14TディペンダブルSRAMおよびそのセル配置構造
    FUJIWARA Hidehiro, OKUMURA Syunsuke, IGUCHI Yusuke, NOGUCHI Hiroki, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Mar. 2009, 電子情報通信学会総合大会, 0, Japanese
    International conference proceedings

  • Yoshinori Sakata, Kentaro Kawakami, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We propose an elastic pipeline architecture that can apply dynamic voltage scaling (DVS) to a dedicated hardware, and implement the elastic pipeline to a portable H.264/AVC decoder LSI with embedded frame buffer SRAM. A supply voltage and operating frequency are decreased by a feedback-type voltage/frequency control algorithm. In a portable H.264/AVC decoder, embedded SARM can be utilized as frame buffer since the frame buffer is not so large that an external DRAM is required. In the proposed pipeline architecture, the power in the embedded SRAM and even in a local bus connecting with the frame buffer SRAM can be controlled by dynamic voltage scaling (DVS). We carried out simulation in the 320 × 180 pixels baseline profile and 320 × 240 pixels mail profile. The total power reduction in 320 × 180 pixels and 320 × 240 pixels are 30 and 31%, respectively. © 2009 Springer Science+Business Media, LLC.
    2009, Lecture Notes in Electrical Engineering, 28(2) (2), 25 - 32, English
    [Refereed]
    International conference proceedings

  • Hiroshi Kawaguchi
    In upcoming ubiquitous electronics environment, abundant electronics systems will be deployed in a sensor, car, robot, home, town, and even in a farm. The ubiquitous electronics support our comfortable and safe life, and thus require low-power feature. High-performance silicon VLSIs such as microprocessors will still be the mainstream also in the future ubiquitous electronics environment, as the modern life is supported by "the micro electronics". That is, cost reduction and power saving by downsizing will be keys. However, the ubiquitous electronics are not achieved only by the micro electronics. Another technology such as organic electronics has been recently called "macro electronics", and will complement the silicon system. The macro electronics realize a new system as a fusion of the heterogeneous technologies. In this paper, we introduce some low-power control techniques for silicon and organic electronics. In particular, we focus on circuits with array structures like silicon static random access memory and organic sensors. © 2009 IEEE.
    2009, Proceedings of the IEEE International Conference on Control Applications, 326 - 333, English
    [Refereed]
    International conference proceedings

  • A 58-mu W Single-Chip Sensor Node Processor Using Synchronous MAC Protocol
    Takeuchi, Takashi, Izumi, Shintaro, Matsuda, Takashi, Lee, Hyeokjong, Otake, Yu, Konishi, Toshihiro, Tsuruda, Koh, Sakai, Yasuharu, Fujiwara, Hidehiro, Ohta, Chikara, Kawaguchi, Hiroshi, Yoshimoto, Masahiko
    We propose a single-chip ultralow-power sensor node processor with a synchronous media access control (MAC). It is comprised of a transceiver, i8051 micro processor, and dedicated MAC processor. The test chip occupies 3 x 3 mm(2) in a 180-nm CMOS process, including 1.38 M transistors. The power is 58.0 mu W under a network environment.
    JAPAN SOCIETY APPLIED PHYSICS, 2009, 2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 290 - 291, English
    [Refereed]
    International conference proceedings

  • Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We propose a novel dependable SRAM with 7T cells and their array structure that avoids a half-selection problem. In addition, we introduce a new concept, "quality of a bit (QoB)" for it. The dependable SRAM has three modes (normal mode, high-speed mode, and dependable mode), and dynamically scales its reliability and speed by combining two memory cells for one-bit information (i.e. 14T/bit). Monte Carlo simulation demonstrates that, in a 65-nm process technology, the minimum voltages in read and write operations are improved by 0.20V and 0.26V, respectively, with a bit error rate of 10(-8) kept. The cell area overhead is 11%, compared to the conventional 6T cell in the normal mode.
    IEEE COMPUTER SOC, 2009, 22ND INTERNATIONAL CONFERENCE ON VLSI DESIGN HELD JOINTLY WITH 8TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS, pp. 295-300, 295 - 300, English
    [Refereed]
    International conference proceedings

  • A 0.56-V 128kb 10T SRAM Using Column Line Assist (CLA) Scheme
    Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We present a small-area 10T SRAM cell without half selection problem. As well, the proposed 10T cell achieves a faster access time and low voltage operation. The cell area is reduced by 25%, and the cell current is increased by 21%, compared with the prior 10T cell. The minimum operating voltage is lowered by the column line assist (CLA) scheme that suppresses write margin degradation. By measurement, we confirmed that the proposed 128-kb SRAM works at 0.56 V.
    IEEE, 2009, ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2, 0, 659 - +, English
    [Refereed]
    International conference proceedings

  • Izumi Shintaro, Yoshimoto Masahiko, Takeuchi Takashi, Matsuda Takashi, Lee Hyeokjong, Konishi Toshihiro, Tsuruda Koh, Sakai Yasuharu, Kawaguchi Hiroshi, Ohta Chikara
    In this paper, we propose a single-chip ultra low-power sensor node processor with a synchronous media access control (MAC). It is comprised of a transceiver, i8051 micro processor, and dedicated MAC processor. The test chip occupies 3x3mm^2 in a 180-nm CMOS process, including 1.38M transistors. The power is 58.0μW under a network environment.
    The Institute of Image Information and Television Engineers, 2009, ITE Technical Report, 33(0) (0), 141 - 145, Japanese
    [Refereed]
    Scientific journal

  • A 60-dB Image Rejection Filter Using Delta-Sigma Modulation and Frequency Shifting
    Toshihiro Konishi, Koh Tsuruda, Shintaro Izumi, Hyeokjong Lee, Hidehiro Fujiwara, Takashi Takeuchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We propose a novel image rejection scheme for a low-IF (low intermediate frequency,) receiver. A Delta-Sigma modulator converts I/Q signals to digital values, and then they are digitally processed. The Delta-Sigma modulator is a second-order complex band-pass type; the proposed architecture is suitable for various multi-channel communications and/or cognitive radio. As the first step in the digital signal processing, a spectrum is shifted so that the desired signal band is centered at 0 Hz. Next, by LPFs (low-pass filters), an image signal and the quantization noise of the Delta-Sigma modulator are removed. These LPFs also function as a decimation filter; thus a dedicated decimation filter is not needed, and an extra area and power for it are saved. The test chip occupies 0.75 mm2 in a 180-nm mixed-signal process. The power is 6.0 mW at 1.8 V. The IRR (image rejection ratio) achieves 60 dB.
    IEEE, 2009, 2009 IEEE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUTERS AND SIGNAL PROCESSING, VOLS 1 AND 2, pp. 565-570, 565 - 570, English
    [Refereed]
    International conference proceedings

  • Parallelized Viterbi Processor for 5,000-Word Large-Vocabulary Real-Time Continuous Speech Recognition FPGA System
    Tsuyoshi Fujinaga, Kazuo Miura, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We propose a novel Viterbi processor for the large vocabulary real-time continuous speech recognition. This processor is built with multi Viterbi cores. Since each core can independently compute, these cores reduce the cycle times very efficiently. To verify the effect of utilizing multi cores, we implement a dual-core Viterbi processor in an FPGA and achieve 49% cycle-time reduction, compared to a single-core processor. Our proposed dual-core Viterbi processor achieves the 5,000-word real-time continuous speech recognition at 65.175 MHz. In addition, it is easy to implement scalable increases in the number of cores, which leads to achievement of the larger vocabulary.
    ISCA-INST SPEECH COMMUNICATION ASSOC, 2009, INTERSPEECH 2009: 10TH ANNUAL CONFERENCE OF THE INTERNATIONAL SPEECH COMMUNICATION ASSOCIATION 2009, VOLS 1-5, pp.1483-1486, 1495 - 1498, English
    [Refereed]
    International conference proceedings

  • AN ULTRA-LOW-POWER VAD HARDWARE IMPLEMENTATION FOR INTELLIGENT UBIQUITOUS SENSOR NETWORKS
    Hiroki Noguchi, Tomoya Takagi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    We propose a power management method using a digital voice activity detection (VAD) module for intelligent ubiquitous sensor systems. When this VAD module detects a speech signal, a main signal processing circuit is connected to a power source. When no speech signal is detected, most circuits except VAD are blocked off, thereby reducing stand-by power for the specialized sensor nodes used for speech signal processing. We implemented the VAD algorithm, using zero crossing of input signals to an FPGA, thereby achieving 2.10 mW operation. We synthesized this VAD module using CMOS 0.18-mu m process, achieving 3.49 mu W power consumption for operation at 1.8 V and 100 kHz.
    IEEE, 2009, SIPS: 2009 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS, pp. 214-219, 214 - 219, English
    [Refereed]
    International conference proceedings

  • Takashi Takeuchi, Shintaro Izumi, Takashi Matsuda, Hyeokjong Lee, Toshihiro Konishi, Koh Tsuruda, Yasuhiro Sakai, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    This paper presents an ultra-low-power single-chip sensor-node VLSI with a synchronous MAC protocol and divided data-buffer SRAM for wireless-sensor-network applications. One of the most challenging issues in wireless sensor networks is extension of the overall network lifetime. So a communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system, through a vertical cooperative design among circuits, architecture, and communication protocols. A transceiver, i8051 microcontroller, and dedicated MAC processor with divided SRAM are integrated in a single chip. The test chip occupies 3.0 x 1.7 mm(2) in a 180-nm CMOS process, including 0.63 M transistors. Divided data-buffer reduces 18.6% of average power and the LSI consumes 6.34 mu W under a network environment.
    IEEE, 2009, 2009 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2009), 202 - 207, English
    [Refereed]
    International conference proceedings

  • チップ間ばらつき 補正機能を有する基板バイアス制御を用いた0.42V動作486kb FD-SOI SRAM
    山口 幸介, 藤原 英弘, 竹内 隆, 大竹 優, 吉本 雅彦, 川口 博
    We propose a novel substrate-bias control scheme for FD-SOI SRAM that suppresses inter-die variability and achieves low-voltage operation. Substrate-bias control circuits automatically detect an inter-die threshold-voltage variation, and then maximize read/write margins of memory cells. We confirmed that a 486-kb SRAM operates at 0.42V, in which an FS/SF corners can be compensated as much as 0.14V or more.
    The Institute of Electronics, Information and Communication Engineers, Dec. 2008, 電子情 報通信学会技術研究報告(信学技報), vol. 108, no. 347, ICD2008-127(347) (347), 131 - 136, Japanese
    Scientific journal

  • Takashi Takeuchi, Yu Otake, Masumi Ichien, Akihiro Gion, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    We propose Isochronous-MAC (I-MAC) using the Long-Wave Standard Time Code (so called "wave clock"), and introduce cross-layer design for a low-power wireless sensor node with I-MAC. I-MAC has a periodic wakeup time synchronized with the actual time, and thus we take the wave clock. However, a frequency of a crystal oscillator varies along with temperature, which incurs a time difference among nodes. We present a time correction algorithm to address this problem, and shorten the time difference. Thereby, the preamble length in I-MAC can be minimized, which saves communication power. For further power reduction. a low-power crystal oscillator is also proposed. as a physical-layer design. We implemented I-MAC oil an off-the-shelf sensor node to estimate the power saving, and verified that the proposed cross-layer design reduces 81% of the total power, compared to Low Power Listening.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Nov. 2008, IEICE TRANSACTIONS ON COMMUNICATIONS, E91B(11) (11), 3480 - 3488, English
    [Refereed]
    Scientific journal

  • Shintaro Izumi, Takashi Takeuchi, Takashi Matsuda, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    Broadcasting is an elementary operation in wireless multihop networks. Flooding is a simple broadcast protocol but it frequently causes serious redundancy. contention and collisions. Probability based methods are promising because they can reduce broadcast messages without additional hardware and control packets. In this paper, the counter-based scheme which is one of the probability based methods is focused on as a broadcast protocol, and the RAD (Random Assessment Delay) Extension is proposed to improve the original counter-based scheme. The RAD Extension can be implemented without additional hardware, so that the strength of the counter-based scheme can be preserved. In addition, we propose the additional algorithm called Hop Count Aware RAD Extension to establish shorter path from the source node. Simulation results show that both of the RAD Extension and the Hop Count Aware RAD Extension reduce the number of retransmitting nodes by about 10% compared with the original scheme. Furthermore. the Hop Count Aware RAD Extension call establish almost the same path length as the counter-based scheme.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Nov. 2008, IEICE TRANSACTIONS ON COMMUNICATIONS, E91B(11) (11), 3489 - 3498, English
    [Refereed]
    Scientific journal

  • 全整数計画問題ソルバーのFPGA実装,
    TANI Junichi, NOGUCHI Hiroki, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Oct. 2008, 情報処理学会関西支部大会,, D-05, Japanese
    International conference proceedings

  • ワイヤレスセンサネットワークのためのデータ集約を考慮した部分起動メモリの電力削減効果に関する研究
    SAKAI Yasuharu, MATSUDA Takashi, IZUMI Shintaro, TAKEUCHI Takashi, FUJIWARA Hidehiro, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko
    Sep. 2008, 電子情報通信学会ソサイエティ大会, B-20-10, pp. 346, Japanese
    International conference proceedings

  • Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We propose a low-power two-port SRAM for real-time video processing that exploits statistical similarity in images. To-minimize the discharge power on a read bitline, a majority-logic circuit decides if input data should be inverted in a write cycle, so that "1"s are in the majority. In addition, for further power reduction, write-in data are reordered into digit groups from the most significant bit group to the least significant bit group. The measurement result of a 68-kbit video memory in a 90-nm process demonstrates that a 45% power saving is achieved on the read bitline. The speed and area overheads are 4% and 7%, respectively.
    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, Jun. 2008, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 16(6) (6), 620 - 627, English
    [Refereed]
    Scientific journal

  • 高信頼性モードと高速アクセスモードを有するディペンダブルSRAM
    OKUMURA Syunsuke, FUJIWARA Hidehiro, IGUCHI Yusuke, NOGUCHI Hiroki, MORITA Yasuhiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    We propose a novel dependable SRAM with 7T memory cell pair, and introduce a new concept, "quality of a bit (QoB)" for it. The proposed SRAM has three modes: a typical mode, high-speed mode, and dependable mode, in which the QoB is scalable. That is, the area, speed, reliability, and/or power of one-bit information can be controlled. In the typical mode, assignment of information is as usual as one memory cell has one bit. On the other hand, in the high-speed or dependable mode, one-bit information is stored in two memory cells, which boosts the speed or increases the reliability. In the high speed mode, the cell current is increased by 142%, and bitline discharge time is reduced by 66.3%. Furthermore, in dependable mode, Bit error rate (BER) in proposed SRAM is improved by 2.5×10^<-2>. Compared with the conventional 6T memory cell, the respective area overheads are 30% and 12%, in the nMOS and pMOS additional cases.
    The Institute of Electronics, Information and Communication Engineers, May 2008, 電子情報通信学会技術研究報告,, VLD2008-12, pp.31-36(23) (23), 31 - 36, Japanese
    International conference proceedings

  • サブ 100mW H.264 AVC MP@L4.1 HDTV 解像度対応整数画素精度動き検出プロセッサコア
    MIZUNO Kosuke, MIYAKOSHI Junichi, MURACHI Yuichiro, HAMAMOTO Masaki, IINUMA Takahiro, ISHIHARA Tomokazu, YIN Fang, LEE Jangchung, KAMINO Tetsuya, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    As digital terrestrial broadcasting prevails more, it is more important to develop techniques for compressing images of high resolution. This work focused on integer-pel motion estimation (IME) occupying more 90% workload in H.264/AVC encoder for HDTV resolution and aimed to realize a low power and high picture-quality IME processor.
    The Institute of Electronics, Information and Communication Engineers, May 2008, 電子情報通信学会技術研究報告, VLD2008-12, pp.25-30(23) (23), 25 - 30, Japanese
    International conference proceedings

  • Yuichiro Murachi, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We describe a sub 100-mW H.264 MP@L4.1 integerpel motion estimation processor core for low power video encoder. It supports macro block adaptive frame field (MBAFF) encoding and bidirectional prediction for a resolution of 1920 x 1080 pixels at 30fps. The proposed processor features a novel hierarchical algorithm, reconfigurable ring-connected systolic array architecture and segmentation-free, rectangle-access search window buffer. The hierarchical algorithm consists of a fine search and a coarse search. A complementary recursive cross search is newly introduced in the coarse search. The fine search is adaptively carried out, based on an image analysis result obtained by the coarse search. The proposed systolic array architecture minimizes the amount of transferred data, and lowers computation cycles for the coarse and fine searches. In addition, we propose a novel search window buffer SRAM that has instantaneous accessibility to a rectangular area with arbitrary location. The processor core has been designed with a 90 nm CMOS design rule. Core size is 2.5 x 2.5 mm(2). One core supports one-reference-frame and dissipates 48 mW at 1 V. Two core configuration consumes 96 mW for two-reference-frame search.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2008, IEICE TRANSACTIONS ON ELECTRONICS, E91C(4) (4), 465 - 478, English
    [Refereed]
    Scientific journal

  • Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We propose a low-power non-precharge-type two-port SRAM for video processing that exploits statistical similarity in images. To minimize the charge/discharge power on a read bitline, the proposed memory cell (MC) has ten transistors (10T), comprised of the conventional 6T MC, a readout inverter and a transmission gate for a read port. In addition, to incorporate three wordlines, we propose a shared wordline structure, with which the vertical cell size of the 10T MC is fitted to the same size as the conventional 8T MC. Since the readout inverter fully charges/discharges a read bitline, there is no precharge circuit on the read bitline. Thus, power is not consumed by precharging, but is consumed only when a readout datum is changed. This feature is suitable to video processing since image data have spatial correlation and similar data are read out in consecutive cycles. As well as the power reduction, the prechargeless structure shortens a cycle time by 38% compared with the conventional SRAM, because it does not require a precharge period. This, in turn, demonstrates that the proposed SRAM operates at a lower voltage, which achieves further power reduction. Compared to the conventional 8T SRAM, the proposed SRAM reduces a charge/discharge possibility to 19% (81% saving) on the bitlines. As the measurement result, we confirmed that the proposed 64-kb video memory in a 90-nm process achieves an 85% power saving on the read bitline, when considered as an H.264 reconstructed image memory. The area overhead is 14.4%.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2008, IEICE TRANSACTIONS ON ELECTRONICS, E91C(4) (4), 543 - 552, English
    [Refereed]
    Scientific journal

  • Kosuke Mizuno, Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes an H.264/AVC MP@L4.1 quarter-pel motion estimation processor core for a low power video encoder. It supports macro block adaptive frame field (MBAFF) encoding and bi-directional prediction for a resolution of 1920 × 1080 pixels at 30 fps which haven't been realized by conventional methods yet. The proposed processor consists of four modules for low power consumption: a module for an integer-pel motion estimation, a segmentation-free rectangle-access search window buffer, a module for quarter-pel motion estimation, and a module reducing candidate motion vectors. We propose an adaptive algorithm that reduces a workload and power in quarter-pel motion estimation. The algorithm and architecture for the candidate motion vectors reduction suppress a workload of the following process. The processor core has been designed in a 90 nm CMOS technology. The core size is 6.0 × 6.0 mm2. With this core, two reference frame can be handled, and 160.1 mW is consumed at 1.0 V. © 2008 IEEE.
    2008, Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, 1179 - 1182, English
    [Refereed]
    International conference proceedings

  • Yuichiro Murachi, Kosuke Mizuno, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a sub 100-mW H.264/AVC MP@L4.1 integer-pel motion estimation processor core for a low power video encoder. It supports macro block adaptive frame field (MBAFF) encoding and bi-directional prediction for a resolution of 1920 x 1080 pixels at 30 fps which haven't been realized by conventional methods[1][2]. The proposed processor core features a novel hierarchical algorithm, a reconfigurable ring-connected systolic array architecture, and a segmentation-free rectangle-access search window buffer. The processor core has been designed in a 90 nm CMOS technology, and its core size is 2.5 x 2.5 mm2. With one core, one reference frame can be handled, and 48 mW is consumed at 1 V. Two-core configuration dissipates 96 mW for two reference frames. ©2008 IEEE.
    2008, Proceedings - IEEE International Symposium on Circuits and Systems, 848 - 851, English
    [Refereed]
    International conference proceedings

  • Yuichiro Murachi, Yuki Fukuyama, Ryo Yamamoto, Junichi Miyakoshi, Hiroshi Kawaguchi, Hajime Ishihara, Masayuki Miyama, Yoshio Matsuda, Masahiko Yoshimoto
    This paper describes an optical-flow processor core for real-time video recognition. The processor is based on the Pyramidal Lucas and Kanade (PLK) algorithm. It features a smaller chip area, higher pixel rate, and higher accuracy than conventional optical-flow processors. Introduction of search range limitation and the Carman filter to the original PLK algorithm improve the optical-flow accuracy, and reduce the processor hardware cost. Furthermore, window interleaving and window overlap methods reduces the necessary clock frequency of the processor by 70%, allowing low-power characteristics. We first verified the PLK algorithm and architecture with a proto-typed FPGA implementation. Then, we designed a VLSI processor that can handle a VGA 30-fps image sequence clock frequency of 332 MHz. The core size and power consumption are estimated at 3.50 x 3.00 mm2 and 600 mW, respectively, in a 90-nm process technology. Copyright © 2008 The Institute of Electronics, Information and Communication Engineers.
    Institute of Electronics, Information and Communication, Engineers, IEICE, 2008, IEICE Transactions on Electronics, E91-C(4) (4), 457 - 464, English
    [Refereed]
    Scientific journal

  • Quality of a bit (QoB): A new concept in dependable SRAM
    Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We propose a novel dependable SRAM with 7T memory cells, and introduce a new concept, "quality of a bit (QoB)" for it. The proposed SRAM has three modes: a typical mode, high-speed mode, and dependable mode, in which the QoB is scalable. That is, the area, speed, reliability, and/or power of one-bit information can be controlled. In the typical mode, assignment of information is as usual as one memory cell has one bit. On the other hand, in the high-speed or dependable mode, one-bit information is stored in two memory cells, which boosts the speed or increases the reliability. By carrying out Monte Carlo simulation of dynamic cell stability in a 90-nm process technology, we confirmed the advantage of the proposed SRAM.
    IEEE COMPUTER SOC, 2008, ISQED 2008: PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, pp. 98-102, 98 - 102, English
    [Refereed]
    International conference proceedings

  • Impact of divided static random access memory considering data aggregation for wireless sensor networks
    Takashi Matsuda, Shintaro Izumi, Takashi Takeuchi, Hidehiro Fujiwara, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    The most challenging issue of sensor networks is extension of overall network system lifetimes. It is important for the extension of system lifetime to determine the routing considering data aggregation. Data aggregation can reduce network traffic by the elimination of the redundant data. Though data aggregation is effective, sensor node needs a certain amount of RAM to aggregate data. RAM has standby energy, and its power consumption is one of the major factors in sensor node. In this work, we investigate the relationship among RAM capacity, data aggregation and power consumption. Then, we propose to use divided operating SRAM. Proposal method can reduce energy of sensor node even if RAM capacity is large.
    IEEE, 2008, 2008 7TH ASIA-PACIFIC SYMPOSIUM ON INFORMATION AND TELECOMMUNICATION TECHNOLOGIES, pp. 130-134, 115 - +, English
    [Refereed]
    International conference proceedings

  • Hop Count Aware broadcast algorithm with Random Assessment Delay Extension for wireless sensor networks
    Shintaro Izumi, Takashi Matsuda, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    Broadcasting is an elementary operation in wireless multi-hop networks. Flooding is a simple broadcast protocol but it frequently causes serious redundancy, contention and collisions. Probability based methods are promising because they can reduce broadcast messages without additional hardwares and control packets. In this paper, the counter-based scheme which is one of the probability based methods is focused on as a broadcast protocol, and the RAD (Random Assessment Delay) Extension is proposed to improve the original counter-based scheme. The RAD Extension can be implemented without additional hardwares, so that the strength of the counter-based scheme can be preserved. In addition, we propose the additional algorithm called Hop Count Aware RAD Extension to establish shorter path from the source node. Simulation results show that both of the RAD Extension and the Hop Count Aware RAD Extension reduce the number of retransmitting nodes by about 10% compared with the original scheme. Furthermore, the Hop Count Aware RAD Extension can establish almost the same path length as the counter-based scheme.
    IEEE, 2008, 2008 7TH ASIA-PACIFIC SYMPOSIUM ON INFORMATION AND TELECOMMUNICATION TECHNOLOGIES, pp. 30-35, 207 - +, English
    [Refereed]
    International conference proceedings

  • A power-efficient SRAM core architecture with segmentation-free and rectangular accessibility for super-parallel video processing
    Yuichiro Murachi, Tetsuya Kamino, Junichi Miyakoshi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a unique SRAM architecture for super-parallel video processing. It features one cycle functional access of a rectangular image data (n x m pixels) with segmentation-free. To achieve this accessibility, a local word-line select scheme and a merged X-decoder method are newly introduced with elimination of extra X-decoder employed in usage of the conventional divided SRAM macro. The proposed SRAM has been adopted to a search window buffer for H.264 motion estimation processor for HDTV resolution video. As a result, a power and area of the search window buffer are reduced by 49 % and by 48 %, respectively. Furthermore, it is shown that the proposed SRAM is more efficient for super-HDTV resolution video which requires more parallelism.
    IEEE, 2008, 2008 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM, pp. 63-66, 63 - +, English
    [Refereed]
    International conference proceedings

  • Which is the best dual-port SRAM in 45-nm process technology? 8T, 10T single end, and 10T differential
    Hiroki Noguchi, Shunsuke Okumura, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper compares readout powers and operating frequencies among dual-port SRAMs: an 8T SRAM, 10T single-end SRAM, and 10T differential SRAM. The conventional 8T SRAM has the least transistor count, and is the most area efficient. However, the readout power becomes large and the cycle time increases due to peripheral circuits. The 10T single-end SRAM is our proposed SRAM, in which a dedicated inverter and transmission gate are appended as a single-end read port. The readout power of the 10T single-end SRAM is reduced by 75% and the operating frequency is increased by 95%, over the 8T SRAM. On the other hand the 10T differential SRAM can operate fastest, because its small differential voltage of 50 mV achieves the high-speed operation. In terms of the power efficiency, however, the sense amplifier and precharge circuits lead to the power overhead. As a result, the 10T single-end SRAM always consumes lowest readout power compared to the 8T and the 10T differential SRAM.
    IEEE, 2008, 2008 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS, pp.55-58,, 55 - 58, English
    [Refereed]
    International conference proceedings

  • A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding
    Yuichiro Murachi, Kosuke Mizuno, Junichi Miyakoshi, Masaki Harnarnoto, Takahiro Linurna, Tornokazu Ishibara, Fang Yin, Jangchung Lee, Tetsuya Karnino, Hiroshi Kawaguchi, Masahiko Yoshirnoto
    This paper describes a sub 100-mW H.264/AVC MP@L4.1 integer-pel motion estimation processor core for a low power video encoder. It supports macro block adaptive frame field (MBAFF) encoding and bi-directional prediction for a resolution of 1920 x 1080 pixels at 30 fps which haven't been realized by conventional methods[1][2]. The proposed processor core features a novel hierarchical algorithm, a reconfigurable ring-connected systolic array architecture, and a segmentation-free rectangle-access search window buffer. The processor core has been designed in a 90 nm CMOS technology, and its core size is 2.5 x 2.5 mm(2). With one core, one reference frame can be handled, and 48 mW is consumed at 1 V. Two-core configuration dissipates 96 mW for two reference frames.
    IEEE, 2008, PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 0, 848 - 851, English
    [Refereed]
    International conference proceedings

  • Tsuruda Koh, Izumi Shintaro, Lee Hyeokjong, Takeuchi Takashi, Kawaguchi Hiroshi, Yoshimoto Masahiko
    本論文ではコグニティブ無線向け可変帯域ディジタルBPF(Band-Pass Filter)を用いたベースバンドプロセッサを提案する.BPFにDA(Distributed Arithmetic)アルゴリズムを適応することで,内蔵するSRAMのデータを書き換えるだけでBPFの特性(チャネル中心周波数とバンド幅)を変化させることが可能となる.試作したベースバンドプロセッサではバンド幅を40kHzから240kHzまで10kHz単位で変化させることが可能である.CMOS 180nmプロセスで設計し,電源電圧1.8Vで消費電力は13.5mWであった.
    The Institute of Image Information and Television Engineers, 2008, ITE Technical Report, 32(0) (0), 137 - 141, Japanese
    International conference proceedings

  • An Inter-Die Variability Compensation Scheme for 0.42-V 486-kb FD-SOI SRAM using Substrate Control
    Hidehiro Fujiwara, Takashi Takeuchi, Yu Otake, Masahiko Yoshimoto, Hiroshi Kawaguchi
    We propose a novel substrate-bias control scheme for FD-SOI SRAM that suppresses inter-die variability and achieves low-voltage operation. Substrate-bias control circuits automatically detect an inter-die threshold-voltage variation, and then maximize read/write margins of memory cells. We confirmed that a 486-kb SRAM operates at 0.42 V, in which an FS/SF comers can be compensated as much as 0.14 V or more.
    IEEE, 2008, 2008 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, pp. 93-94, 93 - 94, English
    [Refereed]
    International conference proceedings

  • Memory Bandwidth Gaussian Mixture Model (GMM) Processor for 20,000-Word Real-Time Speech Recognition FPGA System
    Kazuo Miura, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We propose a GMM processor for large vocabulary real-time continuous speech recognition. This processor achieves low operating frequency and low memory bandwidth using parallelization and vector look-ahead schemes, which are suitable to FPGA implementation. We designed the proposed processor on a Celoxica RC250 FPGA board, and confirmed that the required frequency and memory bandwidth for real-time operation are reduced by 89.8% and 84.2%, respectively. The 20,000-word real-time GMM computation is made at a frequency of 30.4 MHz and memory bandwidth of 4 7 Mbps, on the prototype.
    IEEE, 2008, PROCEEDINGS OF THE 2008 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY, 0, 341 - 344, English
    [Refereed]
    International conference proceedings

  • A Flexible Baseband Processor with Multi-Resolution Spectrum-Sensing Functionality
    Koh Tsuruda, Shintaro Izumi, Hyeokjong Lee, Takashi Takeuchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    In this paper, we propose a reconfigurable baseband processor for a cognitive radio that has multi-resolution bandpass filters. By applying the distributed arithmetic algorithm to the reconfigurable baseband processor and rewriting SRAM data in it, a channel center frequency and bandwidth are reconfigurable. The filter bandwidth can be changed from 40 kHz to 240 kHz with a 10 kHz resolution on our prototype processor. The power is 13 mW at a supply voltage of 1.8 V in a 0.18-mu m CMOS process.
    IEEE, 2008, 2008 INTERNATIONAL SYMPOSIUM ON INFORMATION THEORY AND ITS APPLICATIONS, VOLS 1-3, pp. 1423-1428, 1422 - 1427, English
    [Refereed]
    International conference proceedings

  • Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Masahiko Yoshimoto, Hiroshi Kawaguchi
    We propose a microphone array network that realizes ubiquitous sound acquisition. Several nodes with 16 microphones are connected to form a novel huge sound acquisition system, which carries out voice activity detection (VAD), sound source localization, and separation. The three operations are distributed among nodes. Using the distributed network, we achieve a low-traffic data-intensive array network. To manage nodes' power consumption, VAD is implemented. Consequently, the system uses little power when speech is not active. For sound localization, a network-connected multiple signal classification (MUSIC) algorithm is used. The sound separation system can improve a signal-noise ratio (SNR) by 7.75 dB using 112 microphones. Network traffic is reduced by 99.11% when using 1024 microphones.
    IEEE, 2008, 2010 FOURTH INTERNATIONAL CONFERENCE ON SENSOR TECHNOLOGIES AND APPLICATIONS (SENSORCOMM), pp. 157-162, 157 - 162, English
    [Refereed]
    International conference proceedings

  • 超並列画像処理応用 任意位置任意サイズ矩形画素の1サイクルアクセスが可能なブロックアクセスメモリアーキテクチャ
    MURACHI Yuichiro, MIYAKOSHI Junichi, KAMINO Tetsuya, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    映像情報メディア学会, Dec. 2007, 電子情報通信学会技術研究報告,ICD2007-128, Vol.107,No.382,pp.47-52(63) (63), 47 - 52, Japanese
    International conference proceedings

  • Takashi Matsuda, Masumi Ichien, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    One challenging issue of sensor networks is extension of overall network system lifetimes. In periodic data gathering applications, the typical sensor node spends more time in the idle state than active state. Consequently, it is important to decrease power consumption during idle time. In this study, we propose a scheduling scheme based on the history of RTS/CTS exchange during the setup phase. Scheduling the transmission during transfer phase enables each node to turn off its RF circuit during idle time. By tracing ongoing RTS/CTS exchange during the steady phase, each node knows the progress of the data transfer process. Thereby, it can wait to receive packets for data aggregation. Simulation results show a 160-260% longer system lifetime with the proposed scheduling scheme compared to the existing approaches.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Dec. 2007, IEICE TRANSACTIONS ON COMMUNICATIONS, E90B(12) (12), 3410 - 3418, English
    [Refereed]
    Scientific journal

  • Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper compares areas between a 6T and 8T SRAM cells, in a dual-V-dd scheme and a dynamic voltage scaling (DVS) scheme. In the dual-V-dd scheme, we predict that the area of the 6T cell keep smaller than that of the 8T cell, over feature technology nodes all down to 32 nm. In contrast, in the DVS scheme, the 8T cell will becomes superior to the 6T cell after the 32-nm node, in terms of the area.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Dec. 2007, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E90A(12) (12), 2695 - 2702, English
    [Refereed]
    Scientific journal

  • Kohei Onizuka, Kenichi Inagaki, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai
    An on-chip buck converter which is implemented by stacking chips and suitable for on-chip distributed power supply systems is proposed. The operation of the converter with 3-D chip stacking is experimentally verified for the first time. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70 mA and a voltage conversion ratio of 0.7 with a switching frequency of 200 MHz and a 2 × 2 mm on-chip LC output filter. The active part and the passive LC output filter are implemented on separate chips fabricated in 0.35- μm CMOS and connected with metal bumps. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3% is also discussed. © 2007 IEEE.
    Nov. 2007, IEEE Journal of Solid-State Circuits, 42(11) (11), 2404 - 2410, English
    [Refereed]
    International conference proceedings

  • Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper shows that an 8T SRAM cell is superior to a 6T cell in terms of cell area in a future process. At a 65-nm node and later, the 6T cell comprised of the minimum-channel-length transistors cannot make the minimum area because of threshold-voltage variation. In contrast, the 8T cell can employ the optimized transistors and achieves the minimum area even if it is used as a single-port SRAM. In a 32-nm process, the 8T-cell area is smaller than the 6T cell by 14.6% at a supply voltage of 0.8 V. We also discuss the area and access time comparisons between the 6T-SRAM and 8T-SRAM macros.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Oct. 2007, IEICE TRANSACTIONS ON ELECTRONICS, E90C(10) (10), 1949 - 1956, English
    [Refereed]
    Scientific journal

  • An elastic pipeline architecture for dynamic voltage scaling and its application to low-power portable H.264/AVC decoder with embedded frame buffer SRAM
    SAKATA Yoshinori, KAWAKAMI Kentaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Sep. 2007, EUROPEAN COMPUTING CONFERENCE, pp.00-00, English
    [Refereed]
    International conference proceedings

  • DVS環境下での小面積・低電圧動作8T SRAMの設計
    MORITA Yasuhiro, FUJIWARA Hidehiro, NOGUCHI Hiroki, IGUCHI Yusuke, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Aug. 2007, 電子情報通信学会技術研究報告,ICD2007-95, Vol.107,No.195,pp.139-144, Japanese
    International conference proceedings

  • 電源電圧と周波数の動的制御によるH.264/AVC デコーダの低消費電力化
    SAKATA Yoshinori, 川上 健太郎, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    映像情報メディア学会, Jul. 2007, 電子情報通信学会技術研究報告,ICD2007-52, Vol.107,No.163,pp.89-94(34) (34), 89 - 94, Japanese
    International conference proceedings

  • 長波帯標準電波を用いた低電力センサーノードのための垂直統合設計
    OTAKE Yu, ICHIEN Masumi, TAKEUCHI Takashi, GION Akihiro, MIKAMI Shinji, FUJIWARA Hidehiro, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko
    Jul. 2007, 電子情報通信学会技術研究報告,ICD2007-49, Vol.107,No.163,pp.71-76, Japanese
    International conference proceedings

  • ワイヤレスセンサーネットワーク応用キャリアセンス機能を持つ433MHz帯、356-uW電圧増幅器
    LEE Hyeokjong, MIKAMI Shinji, TAKEUCHI Takashi, ICHIEN Masumi, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko
    Jul. 2007, 電子情報通信学会技術研究報告,ICD2007-50, Vol.107,No.163,pp.77-82, Japanese
    International conference proceedings

  • ビット線電力を74%削減する動画像処理応用 10T 非プリチャージ 2-port SRAMの設計
    OKUMURA Syunsuke, NOGUCHI Hiroki, IGUCHI Yusuke, FUJIWARA Hidehiro, MORITA Yasuhiro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Jul. 2007, 電子情報通信学会技術研究報告,ICD2007-53, Vol.107,No.163,pp.95-100, Japanese
    International conference proceedings

  • ビット線の電力を削減する実時間動画像処理応用2-port SRAM
    FUJIWARA Hidehiro, NII Koji, NOGUCHI Hiroki, MIYAKOSHI Junichi, MURACHI Yuichiro, MORITA Yasuhiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    We propose a low-power two-port SRAM for real-time video processing that exploits statistical similarity in images. To minimize discharge power on a read bitline in the precharge scheme, a majority-logic circuit decides if input data should be inverted in a write cycle, so that "1"s are in the majority. Write-in data are reordered into digit groups from the most significant bit group to the least significant bit group, and then a flag bit is appended to each group. If the number of "0"s in a group is more than that of "1"s, the input data are inverted by the majority logic. The majority-logic circuit reduces needless discharges on the read bitlines, and thus saves power in a read operation. The measurement result in a 68-kb SRAM fabricated in a 90-nm process demonstrates that thte 45% power saving on the read bitline is achieved as an H.264 reconstructed-image memory. The speed and area overhead are 4% and 7%, respectively.
    The Institute of Electronics, Information and Communication Engineers, Apr. 2007, 電子情報通信学会技術研究報告,ICD2007-7, Vol.107,No.1,pp.35-40(1) (1), 35 - 40, Japanese
    International conference proceedings

  • Wireless power transmission sheet with organic FETs and plastic MEMS switches
    M. Takamiya, T. Sekitani, Y. Miyamoto, Y. Noguchi, H. Kawaguchi, T. Someya, T. Sakurai
    Design innovations to overcome the shortcomings of a wireless power transmission sheet made with plastic MEMS switches and organic FETs (OFETs) for printable low-cost electronics are shown. The mixed circuits of MEMS switches and OFETs with two different frequencies reduce the number of coil sheets form 2 to 1. OFET level-shifters, with the current-source loads with enhancement/depletion mixed threshold voltages realized by controlling the back-gate voltage, bridge the operation voltage gap between silicon VLSIs (below 5 V) and OFETs/MEMS (above 40 V).
    2007, IDW '07 - Proceedings of the 14th International Display Workshops, 1, 95 - 98, English
    International conference proceedings

  • Hiroshi Kawaguchi
    2007, IEEE Transactions on Electron Devices
    Scientific journal

  • Hajime Ishihara, Masayuki Miyama, Yoshio Matsuda, Yuichiro Murachi, Yuki Fukuyama, Ryo Yamamoto, Junichi Miyakoshi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes an optical-flow processor core for real-time video recognition. The processor is based on the Pyramidal Lucas and Kanade algorithm. It has small chip area, a high pixel rate, and high accuracy compared to conventional optical-flow processors. Introduction of search range limitation and the Carman filter to the original algorithm improves the optical-flow accuracy and reduces the processor hardware cost. Furthermore, window interleaving and window overlap methods can reduce the necessary clock frequency of the processor by 70%. The proposed processor can handle a VGA 30-fps image sequence with 332 MHz clock frequency. The core size and power consumption in 90-nm process technology are estimated respectively as 3.50 × 3.00 mm 2 and 600 mW. ©2007 IEEE.
    IEEE Computer Society, 2007, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, 188 - 191, English
    [Refereed]
    International conference proceedings

  • Hiroshi Kawaguchi, Danardono Dwi Antono, Takayasu Sakurai
    Closed-form expressions for a crosstalk noise amplitude and worst-case delay in capacitively coupled two-line and three-line systems are derived assuming bus lines and other signal lines in a VLSI. Two modes are studied a case that adjacent lines are driven from the same direction, and the other case that adjacent lines are driven from the opposite direction. Beside, a junction capacitance of a driver MOSFET is considered. The closed-form expressions are useful for circuit designers in an early stage of a VLSI design to give insight to interconnection problems. The expressions are extensively compared and fitted to SPICE simulations. The relative and absolute errors in the crosstalk noise amplitude are within 63.8% and 0.098 E (where E is a supply voltage), respectively. The relative error in the worst-case delay is less than 8.1%. Copyright © 2007 The Institute of Electronics, Information and Communication Engineers.
    Institute of Electronics, Information and Communication, Engineers, IEICE, 2007, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E90-A(12) (12), 2669 - 2681, English
    [Refereed]
    Scientific journal

  • Kohei Onizuka, Makoto Takamiya, Hiroshi Kawaguchi, Takayasu Sakurai
    A design methodology to transmit power using a chip-to-chip wireless interface is proposed. The proposed power transmission system is based on magnetic coupling, and the power transmission of 5mW/mm2 was verified. The transmission efficiency trade-off with the transmitted power is also discussed. ©2007 IEEE.
    2007, Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT, 143 - 146, English
    [Refereed]
    International conference proceedings

  • Makoto Takamiya, Tsuyoshi Sekitani, Yoshio Miyamoto, Yoshiaki Noguchi, Hiroshi Kawaguchi, Takao Someya, Takayasu Sakurai
    Design innovations to overcome the shortcomings of a wireless power transmission sheet made with plastic MEMS switches and OFET for printable low-cost electronics are shown. The mixed circuits of MEMS switches and OFETs with two different frequencies reduce the number of coil sheets form 2 to 1. OFET level-shifters, with the current-source loads with enhancement/depletion mixed threshold voltages realized by controlling the back-gate voltage, bridge the operation voltage gap between silicon VLSIs (below 5 V) and OFETs/MEMS (above 40V). ©2007 IEEE.
    2007, Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT, 168 - 171, English
    [Refereed]
    International conference proceedings

  • David Levacq, Muhammad Yazid, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai
    A new low clock swing flip-flop (F/F) is proposed. The existing low clock-swing F/F's consume high power, introduce speed penalty due to contention currents or require large silicon area due to separate well for substrate biasing. By reducing contention currents, our proposal efficiently mitigates those issues. Measurements and simulations are carried out based on a 90 nm CMOS process, demonstrating reductions of active power by 71%, area by 36% and delay by 35% compared to previous proposals. It is shown that the combination of a low-clock swing distribution tree with the new F/F can save up to 60% of the total clock system power. © 2007 IEEE.
    2007, ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference, 190 - 193, English
    [Refereed]
    International conference proceedings

  • Makoto Takamiya, Tsuyoshi Sekitani, Yoshio Miyamoto, Yoshiaki Noguchi, Hiroshi Kawaguchi, Takao Someya, Takayasu Sakurai
    Design innovations that solve shortcomings of a wireless power transmission sheet are presented. The sheet is made with plastic MEMS switches and organic FET circuits. By using a level shifter with adaptive biasing in the organic circuit, the sheet can be directly driven using 5V digital input. It delivers power to multiple objects, frees the user from position adjustment, and reduces the number of coil arrays. © 2007 IEEE.
    2007, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 355 - 609, English
    [Refereed]
    International conference proceedings

  • Fayez Robert Saliba, Hiroshi Kawaguchi, Takayasu Sakurai
    We report an SRAM with a 90 reduction of active-leakage power achieved by controlling the supply voltage. In our design, the supply voltage of a selected row in the SRAM goes up to 1 V, while that in other memory cells that are not selected is kept at 0.3 V. This suppresses active leakage because of the drain-induced barrier lowering (DIBL) effect. To avoid unexpected flips in the memory cells, the wordline voltage is controlled so that it is always lower than the supply voltage in the proposed SRAM, with a self-alignment timing generator. The additional area overhead of the timing generator is 3.5. Copyright © 2007 The Institute of Electronics, Information and Communication Engineers.
    Institute of Electronics, Information and Communication, Engineers, IEICE, 2007, IEICE Transactions on Electronics, E90-C(4) (4), 743 - 748, English
    [Refereed]
    Scientific journal

  • Takashi Matsuda, Masumi Ichien, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    One challenging issue of sensor networks is extension of overall network system lifetimes. In periodic data gathering applications, the typical sensor node spends more time in the idle state than active state. Consequently, it is important to decrease power consumption during idle time. In this study, we propose a scheduling scheme based on the history of RTS/CTS exchange during the setup phase. Scheduling the transmission during transfer phase enables each node to turn off its RF circuit during idle time. By tracing ongoing RTS/CTS exchange during the steady phase, each node knows the progress of the data transfer process. Thereby, it can wait to receive packets for data aggregation. Simulation results show a 160-260% longer system lifetime with the proposed scheduling scheme compared to the existing approaches Copyright © 2007 The Institute of Electronics, Information and Communication Engineers.
    Institute of Electronics, Information and Communication, Engineers, IEICE, 2007, IEICE Transactions on Communications, E90-B(12) (12), 3410 - 3418, English
    [Refereed]
    Scientific journal

  • Power and memory bandwidth reduction of an H.264/AVC HDTV decoder LSI with elastic pipeline architecture
    Kentaro Kawakami, Mitsuhiko Kuroda, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We propose an elastic pipeline that can apply dynamic voltage scaling (DVS) to hardwired logic circuits. The proposed pipeline can also reduce a required local bus bandwidth. In order to demonstrate its feasibility, a hardwired H.264/AVC HDTV decoder is designed as a real-time application. The proposed architecture reduces a power to 56% in a 90-nm process technology, compared to the conventional clock-gating scheme or a local bus bandwidth to 37.2%.
    IEEE, 2007, PROCEEDINGS OF THE ASP-DAC 2007, pp.292-297, 292 - +, English
    [Refereed]
    International conference proceedings

  • Makoto Takamiya, Tsuyoshi Sekitani, Yusaku Kato, Hiroshi Kawaguchi, Takao Someya, Takayasu Sakurai
    An integrated system of organic FETs (OFETs) and plastic actuators is proposed, and it is applied to a Braille sheet display. Some circuit technologies are presented to enhance the speed and the lifetime for the Braille sheet display. An OFET SRAM is developed to hide the slow transition of the actuators. Developed five-transistor SRAM cell reduces the number of the bit lines by one-half and reduces the SRAM cell area by 20%. Pipelining the write-operation reduced the SRAM write-time by 69%. Threshold voltage control technology using a back gate increased the static noise margin of SRAM and compensated for the chemical degradation of the OFETs after 15 days. The oscillation frequency tuning range from -82% to +13% in a five-stage ring oscillator is also demonstrated with the threshold voltage control technology. The overdrive techniques for the driver OFETs reduced the transition time of the actuator from 34 s to 2 s. These developed circuit technologies achieved the practical 1.75-s operation to change all 144 Braille dots on Braille sheet display and will be essential for the future large area electronics made with OFETs.
    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, Jan. 2007, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 42(1) (1), 93 - 100, English
    [Refereed]
    Scientific journal

  • Shinji Mikami, Takashi Takeuchi, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    To extend an available period of wireless sensor networks, transmission power control is regarded as one of the promising schemes. In most of the previous studies on the transmission power control, it is assumed that a transmitter has power consumption of O(dn), where d and n denote a maximum communication distance and a pass loss factor. This assumption would substantially hold under the condition that the transmission efficiency is always constant at any transmission power (efficiency-fixed model). In practice, however, the transmission efficiency degrades as the transmission power is reduced. We analytically verify that an actual power amplifier with the efficiency degradation has a power consumption of 0(dr), where n/2.8 ≤ r ≤ n/2 (efficiency-degradation model). The efficiency-degradation model gives the negative impact against the transmission power control. © 2007 IEEE.
    2007, Proceedings - 2007 IEEE Radio and Wireless Symposium, RWS, pp.447-450, 447 - 450, English
    [Refereed]
    International conference proceedings

  • Shinji Mikami, Masumi Ichien, Takashi Takeuchi, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    We describe a low-power voltage amplifier that is suitable for RF (radio frequency) receivers in a WSN (wireless sensor network). Since a sensor node has a strict energy budget in a WSN, it often enters itself into a standby mode when no communication is required, and hence a standby power have to be suppressed as well as an active power in order to maximize a lifetime of a WSN. For this sake, it is effective to reduce an RF block's power in a sensor node because it is the major power-consuming block. We propose a simple rail-to-rail voltage amplifier with lowstandby-power and low-active-power capabilities that is suitable to a subsequent digital interface. The target frequency is set to 433 MHz, and the voltage gain achieves 26 dB. The standby and active powers are 24 nW and 356 μW, which are lower than the conventional inverter-type voltage amplifier by 86% and 46%, respectively. The proposed amplifier features a carrier sensing function in addition to the low-power operation since it has a minimum input amplitude to be amplified. By using this function, we can set a carrier sensing level as a threshold level, which is important to avoid collisions and interferences in a WSN that cause needless communications. © 2007 IEEE.
    2007, Proceedings - 2007 IEEE Radio and Wireless Symposium, RWS, pp.451-454, 451 - 454, English
    [Refereed]
    International conference proceedings

  • A 10T non-precharge two-port SRAM for 74% power reduction in video processing
    Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We propose a low-power non-precharge-type two-port SRAM for video processing. The proposed memory cell (MC) has ten transistors (10T), comprised of the conventional 6T MC, a readout inverter and a transmission gate for a read port. Since the readout inverter fully charges/discharges a read bitline, there is no precharge circuit on the read bitline. Thus, power is not consumed by precharging, but is consumed only when a readout datum is changed. This feature is suitable to video processing since image data have special correlation and similar data are read out in consecutive cycles. As well as the power reduction, the prechargeless structure shortens a cycle time by 38% compared with the conventional SRAM, because it does not require a precharge period. This, in turn, demonstrates that the proposed SRAM operates at a lower voltage, which achieves further power reduction. Compared to the conventional 8T SRAM, the proposed SRAM reduces a charge/discharge possibility to 19% (81% reduction) on the bitlines, and saves 74% of a readout power when considered as an H.264 reconstructed-image memory. The area overhead is 14.4% in a 90-nm process technology.
    IEEE COMPUTER SOC, 2007, IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS, pp.107-112, 107 - +, English
    [Refereed]
    International conference proceedings

  • An area-conscious low-voltage-oriented 8T-SRAM design under DVS environment
    Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper demonstrates that an 8T memory cell can be alternative design to a 6T cell in a future highly-integrated SRAM. in a 45-nm process and later with large threshold-voltage variation. The proposed voltage-control scheme that improves a write margin and read current, and the write-back scheme that stabilizes unselected cells are applied to the 8T SRAM. We verified that the low-voltage operation at 0.42 V in a 90-nm 64-Mb SRAM is possible under dynamic voltage scaling (DVS) environment.
    JAPAN SOCIETY APPLIED PHYSICS, 2007, 2007 Symposium on VLSI Circuits, Digest of Technical Papers, pp.256-257, 256 - 257, English
    [Refereed]
    International conference proceedings

  • Multipath routing using Isochronous medium access control with multi wakeup period for wireless sensor networks
    Takashi Matsuda, Takafumi Aonishi, Takashi Takeuchi, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    The cycled receiver MAC protocols reduce idle listening by periodically putting nodes into sleep state. Conventional cycled receiver protocols, however, have problem such as overhearing and high latency. In this study, we propose Isochronous MAC with multi wakeup period which can reduce the power consumption due to overhearing without delay increased. To exploit this benefit, we combine it with multipath routing. Simulation results show a 12% longer system lifetime and a 87% lower delay of our proposal scheme than that of the conventional scheme.
    IEEE, 2007, 2007 FOURTH INTERNATIONAL SYMPOSIUM ON WIRELESS COMMUNICATION SYSTEMS, VOLS 1 AND 2, pp.718-721, 796 - 799, English
    [Refereed]
    International conference proceedings

  • Shintaro Izumi, Takashi Matsuda, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    Broadcasting is an elementary operation in wireless multi-hop networks. Flooding is a simple broadcast protocol but it causes serious redundancy, contention and collisions. Probability based methods are promising because they can reduce broadcast messages at the cost of slight additional hardware and without any control. In this paper, the counter-based scheme which is one of the probability based methods is focused on as a broadcast protocol, and the RAD (random assessment delay) extension is proposed to improve the original. The RAD extension can be realized by the almost same hardware as the original, so that the strength of the counter-based scheme is kept. Simulation results showed that the RAD extension can reduce the number of retransmitting nodes by about 10 % compared with the original scheme. © 2007 IEEE.
    2007, 2007 International Conference on Sensor Technologies and Applications, SENSORCOMM 2007, Proceedings, pp.76-81, 76 - 81, English
    [Refereed]
    International conference proceedings

  • Yu Otake, Masumi Ichien, Takashi Takeuchi, Akihiro Gion, Shinji Mikami, Hidehiro Fujiwara, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    We propose Isochronous-MAC (I-MAC) using the Long-Wave Standard Time Code, and introduce cross-layer design for a low-power wireless sensor node with I-MAC. I-MAC has a periodic wakeup time synchronized with the actual time, and thus requires a precise timer. However, a frequency of a crystal oscillator varies along with temperature, from node to node. We utilize a time correction algorithm to shorten the time difference among nodes. Thereby, the preamble length in I-MAC can be minimized, which saves a communication power. For further power reduction, a low-power crystal oscillator is also proposed, as a physical-layer design. We implemented I-MAC on an off-the-shelf sensor node to estimate the power saving, and verified that I-MAC reduces 81% of the total power, compared to Low Power Listening. © 2007 IEEE.
    2007, 2007 International Conference on Sensor Technologies and Applications, SENSORCOMM 2007, Proceedings, pp.341-346, 341 - 346, English
    [Refereed]
    International conference proceedings

  • Danardono Dwi Antono, Kenichi Inagaki, Hiroshi Kawaguchi, Takayasu Sakurai
    A simple analytical model based on Delayed Quadratic (DQ) Transfer Function approximation is proposed for estimating waveforms of inductive single-line interconnects in VLSI's. An expression for overshoot voltage is derived by the model within 17% error for the line width less than 10 times the minimum line width and typical input signal. A delay expression is also proposed within 15% for the same condition. The strength of the inductive effect is shown to be expressed by a closed-form expression, A = 2(L(C-T +0.5C))(1/2)/(R-T(C-T +C-J)+RTC+RCT +0.4RC). By using the criteria, a scaling trend of inductive effects in VLSI's is discussed. It is shown that the inductive effect of single-line, minimum-width VLSI interconnect peaks off at 90 nm based on the ITRS predicted parameters.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Dec. 2006, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E89A(12) (12), 3569 - 3578, English
    [Refereed]
    Scientific journal

  • Junichi Miyakoshi, Yuichiro Murachi, Tetsuro Matsuno, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masayuki Miyama, Masahiko Yoshimoto
    We propose a sub-mW H.264 baseline-profile motion estimation processor for portable video applications. It features a VLSI-oriented block partitioning strategy and low-power SIMD/systolic-array datapath architecture, where the datapath can be switched between an SIMD and systolic array depending on processing flow. The processor supports all the seven kinds of block modes, and can handle three reference frames for a CIF (352 x 288) 30-fps to QCIF (176 x 144) 15-fps sequences with a quarter-pixel accuracy. It integrates 3.3 million transistors, and occupies 2.8 x 3.1 mm(2) in a 130-nm CMOS technology. The proposed processor achieves a power of 800 mu W in a QCIF 15-fps sequence with one reference picture.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Dec. 2006, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E89A(12) (12), 3623 - 3633, English
    [Refereed]
    Scientific journal

  • Kentaro Kawakami, Jun Takemura, Mitsuhiko Kuroda, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We propose an elastic pipeline that can apply dynamic voltage scaling (DVS) to hardwired logic circuits. In order to demonstrate its feasibility, a hardwired H.264/AVC HDTV decoder is designed as a real-time application. An entropy decoding process is divided into context-based adaptive binary arithmetic coding (CABAC) and syntax element decoding (SED), which has advantages of smoothing workload for CABAC and keeping efficiency of the elastic pipeline. An operating frequency and supply voltage are dynamically modulated every slot depending on workload of H.264 decoding to minimize power. We optimize the number of slots per frame to enhance power reduction. The proposed decoder achieves a power reduction of 50% in a 90-nm process technology, compared to the conventional clock-gating scheme.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Dec. 2006, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E89A(12) (12), 3642 - 3651, English
    [Refereed]
    Scientific journal

  • Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Kentaro Kawakami, Junichi Miyakoshi, Shinji Mikami, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We propose a voltage control scheme for 6T SRAM cells that makes a minimum operation voltage down to 0.3 V under DVS environment. A supply voltage to the memory cells and wordline drivers, bitline voltage, and body bias voltage of load pMOSFETs are controlled according to read and write operations, which secures operation margins even at a low operation voltage. A self-aligned timing control with a dummy wordline and its feedback is also introduced to guarantee stable operation in a wide range of the supply voltage. A measurement result of a 64-kb SRAM in a 90-nm process technology shows that a power reduction of 30% can be achieved at 100 MHz. In a 65-nm 64-Mb SRAM, a 74% power saving is expected at 1/6 of the maximum operating frequency. The performance penalty by the proposed scheme is less than 1% and area overhead-is 5.6%.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Dec. 2006, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E89A(12) (12), 3634 - 3641, English
    [Refereed]
    Scientific journal

  • Kohei Onizuka, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai
    A VD D-hopping accelerator for on-chip power supply circuits is proposed and the effectiveness of the accelerator circuit is experimentally verified. The quick dropper with the linear regulator enables nanosecond-order transient time in on-chip distributed power supply systems. The measured transition time is less than 5 ns with a load circuit equivalent to 25-k logic gates in 0.18-mu m CMOS. This is to be compared with the case without the accelerator of the order of mu s and thus the acceleration by two orders of magnitude is achieved. Extensions of the basic approach are also discussed including implementation of the quick dropper for a switching DC-DC converter, the control stability improvement, automatic timing generation, and the parasitic element effects of the power lines.
    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, Nov. 2006, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 41(11) (11), 2382 - 2389, English
    [Refereed]
    Scientific journal

  • Junichi Miyakoshi, Yuichiro Murachi, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto
    For super-parallel video processing, we proposed a power and area-efficient SRAM core architecture with a segmentation-free access, which means accessibility to arbitrary consecutive pixels, and horizontal/vertical access. To achieve these flexible accesses, a spirally-connected local-wordline select signal and multi-selection scheme in word-lines are proposed, so that extra X-decoders in the conventional multi-division SRAM can be eliminated. Consequently, the proposed SRAM reduces a power and area by 57-60% and 60%, respectively, when it is applied to a 128 parallel architecture. The proposed 160-kbit SRAM with 16-read ports (2-read port SRAM with eight-parallel architecture) is implemented to a search window buffer for an H.264 motion estimation processor core which dissipates 800 mu W for QCIF 15-fps in a 130-nm technology.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Nov. 2006, IEICE TRANSACTIONS ON ELECTRONICS, E89C(11) (11), 1629 - 1636, English
    [Refereed]
    Scientific journal

  • Isochronous MAC using Low Frequency Radio Wave Time Synchronization for Wireless Sensor Networks
    ICHIEN Mashumi, TAKEUCHI Takashi, MIKAMI Shinji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    This paper proposes Isochronous-MAC (I-MAC), which utilizes low-frequency radio waves time synchronization for radio controlled clocks, for sensor networks. Using I-MAC, based on the Low Power Listening (LPL), all sensor nodes wake and listen channel periodically and synchronously. Since a sender can easily predict wakeup time of an intended receiver, it can shorten the length of preamble to make the receiver prepare for reception of the following data packet. In the paper, we use an analytical model to investigate the impact of the data transmission frequency, the number of neighboring nodes, the wakeup period, the clock drift, and the time-synchronization frequency on the power consumption for consideration of the power overhead to perform the time synchronization. Those results demonstrate that I-MAC allows determination of any arbitrary wakeup period without much difficulty, whereas LPL requires a much more careful setting of the wakeup period because its optimum wakeup period is sensitive to the frequency of data transmission as well as to the number of neighboring nodes. Therefore, I-MAC has a great potential to reduce the power consumption in most situations compared with LPL, in spite of the overhead to perform time synchronization.
    The Institute of Electronics, Information and Communication Engineers, Oct. 2006, Proc. First International Conference on Communications Electronics (ICCE 2006), p.172-177(310) (310), 73 - 76, English
    [Refereed]
    International conference proceedings

  • Shinji Mikami, Takafumi Aonishi, Hironori Yoshino, Chikara Ohta, Hiroshi Kawaguchi, Masahiko Yoshimoto
    In most research work for sensor network routings, perfect aggregation has been assumed. Such an assumption might limit the application of the wireless sensor networks. We address the impact of aggregation efficiency on energy consumption in the context of GIT routing. Our questions are how the most efficient aggregation point changes according to aggregation efficiency and the extent to which energy consumption can decrease compared to the original GIT routing and opportunistic routing. To answer these questions, we analyze a two-source model, which yields results that lend insight into the impact of aggregation efficiency. Based on analytical results, we propose an improved GIT "aggregation efficiency-aware GIT," or AGIT. We also consider a suppression scheme for exploratory messages: "hop exploratory." Our simulation results show that the AGIT routing saves the energy consumption of the data transmission compared to the original GIT routing and opportunistic routing.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Oct. 2006, IEICE TRANSACTIONS ON COMMUNICATIONS, E89B(10) (10), 2741 - 2751, English
    [Refereed]
    Scientific journal

  • Hiroshi Kawaguchi, Shingo Iba, Yusaku Kato, Tsuyoshi Sekitani, Takao Someya, Takayasu Sakurai
    This paper describes a sheet-type scanner and its circuits. The three-dimensional-stacked sheets comprise of two organic-transistor sheets and one organic-photodiode sheet, which enable double-wordline and double-bitline structure. The operation was compared with the conventional single-wordline and single-bitline scheme, and confirmed by measurement. The double-wordline and double-bitline structure reduces the line delay and power by a factor of five and seven, respectively. A new dynamic decoder reduces active leakage current, to which the cut-and-paste customization can be applied.
    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, Oct. 2006, IEEE SENSORS JOURNAL, 6(5) (5), 1209 - 1217, English
    [Refereed]
    Scientific journal

  • しきい値電圧ばらつきを克服したDVS環境下における0.3V動作SRAMの開発
    NOGUCHI Hiroki, MORITA Yasuhiro, FUJIWARA Hidehiro, KAWAKAMI Kentaro, MIYAKOSHI Junichi, MIKAMI Shinji, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Aug. 2006, 電子情報通信学会技術研究報告, ICD2006-106Vol.106No.206pp.155, 155 - 160, Japanese
    International conference proceedings

  • AVC HDTVデコーダアーキテクチャ
    KAWAKAMI Kentaro, TAKEMURA Jun, KURODA Mitsuhiko, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    We propose an elastic pipeline that can apply dynamic voltage scaling (DVS) to hardwired logic circuits. In order to demonstrate its feasibility, a hardwired H.264/AVC HDTV decoder is designed as a real-time application. The designed decoder reduces 48% of execution cycles for H.264 HDTV decoding. In case of DVS is applied with this reduced cycles, the proposed decoder achieves a power reduction of 50% in a 90-nm process technology, compared to the conventional clock-gating scheme.
    The Institute of Electronics, Information and Communication Engineers, Jun. 2006, 電子情報通信学会技術研究報告, ICD-2006-45 Vol.106 No.92 pp.3(92) (92), 31 - 36, Japanese
    International conference proceedings

  • A Vth-Variation-Tolerant SRAM with 0.3-V Minimum Operation Voltage for Memory-Rich SoC under DVS Environment
    MORITA Yasuhiro, FUJIWARA Hidehiro, NOGUCHI Hiroki, KAWAKAMI Kentaro, MIYAKOSHI Junichi, MIKAMI Shinji, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Jun. 2006, 2006 Symposium on VLSI Circuits Digest of Technical Papers, pp.16-17, 13 - 14, English
    [Refereed]
    International conference proceedings

  • Koichi Ishida, Kouichi Kanda, Atit Tamtrakarn, Hiroshi Kawaguchi, Takayasu Sakurai
    The analog T-switch (AT-switch) scheme is introduced to suppress subthreshold-leakage problems in charge-based analog circuits such as switched capacitors and sample-and-hold circuits. A 0.5-V sigma-delta modulator is manufactured in a 0.15-μm FD-SOI process with low VTH of 0.1 V using the concept. The scheme is compared with another leakage-suppression scheme based on super cut-off CMOS (SCCMOS) and the conventional circuit which are also fabricated. The sigma-delta modulator based on AT-switch greatly improves 8.1-dB SNDR through reducing nonlinear leakage effects while the modulator based on SCCMOS improves the dynamic range rather than the SNDR by comparing with the conventional sigma-delta modulator © 2006 IEEE.
    Apr. 2006, IEEE Journal of Solid-State Circuits, 41(4) (4), 859 - 866, English
    [Refereed]
    International conference proceedings

  • 定期情報収集型センサネットワークのためのRTS/CTS交換に基づくデータ送信スケジューリング
    MATSUDA Takashi, ICHIEN Masumi, MIKAMI Shinji, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    One of challenging issues on the sensor networks is to extend lifetime of network system as a whole. In periodic data gathering applications, idle time occupies longer than transmission time in the state of a sensor node. Consequently, it is important to decrease wasteful power consumption during idle time. In this study, we propose a scheduling algorithm based on history of RTS/CTS exchange during setup phase. Scheduling the transmission during transfer phase enables each node to turn off its RF circuit during idle time. By tracing ongoing RTS/CTS exchange during data transfer phase, each node knows progress of data transfer process so that it can wait to receive packets for data aggregation. Simulation results show that system lifetime of our scheduling extends 220% longer than that of existing "power scheduling."
    The Institute of Electronics, Information and Communication Engineers, Apr. 2006, 電子情報通信学会技術研究報告, NS2006-7Vol.106No.14pp.25-28(14) (14), 25 - 28, Japanese
    International conference proceedings

  • 送信電力制御による効率劣化の影響
    MIKAMI Shinji, TAKEUCHI Takashi, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko
    ワイヤレスセンターネットワークの長寿命化において送信電力はその重要な1つの方法として考えられる。従来研究においては、消費電力はO(d^n)(ここでdは最大通信距離、nはパス損失係数)で変化すると仮定されてきた。しかし、この仮定は送信効率が常に一定の場合において成り立つものであり、実際には送信効率は変動すると考えられる。そこで本稿では、送信器の最終段であるパワーアンプ、インピーダンス整合回路、アンテナをモデル化し,インピーダンス整合理論ならびに,典型的なA、C級パワーアンの実回路シミュレーションにより、送信効率の劣化が及ぼす影響を検討した。その結果、送信効率が劣化する場合、送信器の消費電力がO(d^r)([numerilal formulu])により変化することを明らかにした。 In order to extend available period of wireless sensor networks, transmission power control is regarded as one of the promising schemes. In most of previous research about transmission power control, it is assumed that a transmitter has power consumption of O(d^n), where d and n denote maximum communication distance and pass loss factor. This assumption substantially holds under the condition that the transmitter efficiency is always constant (efficiency-fixed model). In practice, however, the transmitter efficiency can vary with antenna-output power. In this paper, we show a transmitter with its efficiency degradation has power consumption of O(d^r), where [numerilal formulu] (efficiency degradation model). To do so, we model the final stage of transmitter including antenna as an integrated circuit of PA (power amplifier), impedance matching circuit and antenna impedance, and then analyze the model in two ways. The first analysis is based on matching theorem. The second analysis treats of a typical and realistic circuit for class-A and C power amplifiers, and also verify the analytical results by circuit simulations.
    一般社団法人電子情報通信学会, Apr. 2006, 電子情報通信学会技術研究報告, NS2006-4Vol.106No.14pp.13-16(14) (14), 13 - 16, Japanese
    International conference proceedings

  • 製造ばらつきを考慮したセンサネットワークノード消費電力モデルの提案と評価
    TAKEUCHI Takashi, YOSHINO Hironori, ICHIEN Masumi, MATSUDA Takashi, MIKAMI Shinji, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    We introduced manufacturing variation into a power model for a wireless sensor network node. Network protocols for wireless sensor networks such as media access control and routing should be evaluated in terms of life time as a whole system. In fact, there exists variation in power node-by-node due to the manufacturing variation. In the previous research, however, this effect has not been investigated at all since it has been supposed that all nodes have the same power. In this paper, we develop a more exact power model for sensor nodes, which we name the threshold-voltage variation model, considering threshold-voltage variation in a manufacturing process. A microprocessor and RF part are considered as hardware blocks in the model, which is then implemented to QualNet in order to evaluate the impact on the life time. The simulation results show that the conventional model overestimates the life time longer than our model.
    The Institute of Electronics, Information and Communication Engineers, Apr. 2006, 電子情報通信学会技術研究報告, NS2006-6Vol.106No.14pp.21-24(14) (14), 21 - 24, Japanese
    International conference proceedings

  • センサネットワークのための長波帯標準電波時刻同期を用いた周期起動型MACの提案
    ICHIEN Masumi, TAKEUCHI Takashi, MIKAMI Shinji, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko
    This paper proposes Isochronous-MAC (I-MAC), which utilizes low-frequency radio waves time synchronization for radio controlled clocks, for sensor networks. Using I-MAC, based on the Low Power Listening (LPL), all sensor nodes wake and listen channel periodically and synchronously. Since a sender can easily predict wakeup time of an intended receiver, it can shorten the length of preamble to make the receiver prepare for reception of the following data packet. In the paper, we use an analytical model to investigate the impact of the data transmission frequency, the number of neighboring nodes, the wakeup period, the clock drift, and the time-synchronization frequency on the power consumption for consideration of the power overhead to perform the time synchronization. Those results demonstrate that I-MAC allows determination of any arbitrary wakeup period without much difficulty, whereas LPL requires a much more careful setting of the wakeup period because its optimum wakeup period is sensitive to the frequency of data transmission as well as to the number of neighboring nodes. Therefore, I-MAC has a great potential to reduce the power consumption in most situations compared with LPL, in spite of the overhead to perform time synchronization.
    The Institute of Electronics, Information and Communication Engineers, Apr. 2006, 電子情報通信学会技術研究報告, NS2006-8Vol.106No.14pp.29-32(14) (14), 29 - 32, Japanese
    International conference proceedings

  • センサネットワークのための集約率を考慮したGIT経路制御の評価
    AONISHI Takafumi, YOSHINO Hironori, MIKAMI Shinji, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    In most research work for sensor network routings, perfect aggregation has been assumed. Such an assumption might limit the application of the wireless sensor networks. We address the impact of aggregation efficiency on energy consumption in the context of GIT routing. Our question is the extent to which energy consumption can decrease compared to the original GIT. In this paper, we propose an improved GIT: "aggregation efficiency-aware routing", or AGIT. We also consider a suppression scheme for exploratory messages: "hop exploratory." Our simulation results show that the AGIT saves the energy consumption of the data transmission compared to the original GIT.
    The Institute of Electronics, Information and Communication Engineers, Apr. 2006, 電子情報通信学会技術研究報告, NS2006-9Vol.106No.14pp.33-36(14) (14), 33 - 36, Japanese
    International conference proceedings

  • KS Min, HD Choi, HY Choi, H Kawaguchi, T Sakurai
    As a candidate for the clock-gating scheme, Zigzag Super Cut-off CMOs (ZSCCMOS) has proposed to reduce not only the switching power but also the leakage power. Due to its fast wakeup nature, the ZSCCMOs can be best suited to the clock-gating scheme. The wakeup time of the ZSCCMOS is estimated to be 12 times faster than the conventional Super Cut-off CMOs (SCCMOS) in 70-nm process technology. From the measurement of wakeup time in 0.6-mu m technology, it is observed to be eight times faster than the conventional scheme. Layout area, power, and delay overhead of the ZSCCMOS are discussed and analyzed in this paper.
    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, Apr. 2006, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 14(4) (4), 430 - 435, English
    [Refereed]
    Scientific journal

  • An Architecture Study of Scalable Optical-Flow Processor for Real-Time Video Segmentation
    YAMAMOTO Ryo, FUKAYAMA Yuuki, KATAGIRI Tadayoshi, MIYAKOSHI Junichi, KURODA Yuki, MINEGISHI Noriyuki, MIYAMA Masayuki, KAWAGUCHI Hiroshi, IMAMURA Kosuke, HASHIMOTO Hideo, YOSHIMOTO Masahiko
    Apr. 2006, Proc. IEEE Symposium on Low-Power High-Speed Chips (COOL Chips IX), pp. 225-240, English
    [Refereed]
    International conference proceedings

  • DD Antono, K Inagaki, H Kawaguchi, T Sakurai
    This paper discusses propagation delay error, transient response, and power consumption distribution due to inductive effects in optimal buffered on-chip interconnects. Inductive effect is said to be important to consider in deep submicron (DSM) VLSI design. However, study shows that the effect decreases and can be neglected in next technology nodes for such conditions.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Mar. 2006, IEICE TRANSACTIONS ON ELECTRONICS, E89C(3) (3), 392 - 394, English
    [Refereed]
    Scientific journal

  • An Organic FET SRAM for Braille Sheet Display with Back Gate to Increase Static Noise Margin
    TAKAMIYA Makoto, SEKITANI Tsuyoshi, KATO Yusaku, KAWAGUCHI Hiroshi, SOMEYA Takao, SAKURAI Takayasu
    Feb. 2006, IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 276-277, 276 - 278
    [Refereed]
    International conference proceedings

  • Sakurai, T., Matsuzawa, A., Douseki, T., Matsuhashi, H., Tsuchiya, T., Omura, Y., Shimomura, H., Yonemaru, M., Fujii, K., Kameyama, A., Kawaguchi, H., Tsukahara, T., Kozaki, M., Kinoshita, M., Sawada, A., Matsuya, Y., Terada, J., Inagaki, Y., Fuse, T., Ohtomo, Y., Koizumi, H., Baba, S., Nishimura, K., Yoshida, Y., Hama, N., Mogami, T., Hiramoto, T., Uchida, K., Takagi, S.-I., Numata, T.
    Fully-Depleted SOI CMOS Circuits and Technology: For Ultralow-Power Applications, 2006, Fully-Depleted SOI CMOS Circuits and Technology: For Ultralow-Power Applications
    Scientific journal

  • Low power and flexible braille sheet display with organic FET's and plastic actuators
    Makoto Takamiya, Tsuyoshi Sekitani, Yusaku Kato, Hiroshi Kawaguchi, Takao Someya, Takayasu Sakurai
    Organic FETs (OFETs) are integrated with actuators, and a Braille sheet display is demonstrated. A newly developed back-gated OFETs SRAM and the circuits technology for the Braille sheet display to enhance speed, yield and lifetime are presented, which will be essential for future large-area electronics made with OFETs.
    IEEE, 2006, 2006 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS, 219 - +, English
    International conference proceedings

  • Tsuyoshi Sekitani, Makoto Takamiya, Yoshiaki Noguchi, Shintaro Nakano, Yusaku Kato, Kazuki Hizu, Hiroshi Kawaguchi, Takayasu Sakurai, Takao Someya
    We have successfully manufactured a large-area power transmission sheet by using printing technologies. The position of electronic objects on this sheet can be contactlessly sensed by electromagnetic coupling using an organic transistor active matrix. Power is selectively fed to the objects by an electromagnetic field using a plastic MEMS-switching matrix.
    2006, Technical Digest - International Electron Devices Meeting, IEDM, English
    [Refereed]
    International conference proceedings

  • Kohei Onizuka, Hiroshi Kawaguchi, Makoto Takamiya, Tadahiro Kuroda, Takayasu Sakurai
    A chip-to-chip inductive wireless power transmission system is proposed and the feasibility is experimentally demonstrated for the first time. The circuit realized 2.5mW power transmission at the output DC voltage of 0.5V using 700×700μm on-chip planar inductors for the transmitter and the receiver. Methods to optimize the circuit design about the maximum transmission power and the simulated optimization results are discussed. © 2006 IEEE.
    2006, Proceedings of the Custom Integrated Circuits Conference, 575 - 578, English
    [Refereed]
    International conference proceedings

  • Kohei Onizuka, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai
    An on-chip buck converter which is implemented by stacking chips and which is suitable for on-chip distributed power supply systems is proposed and the operation is experimentally verified for the first time. The manufactured converter achieves the maximum power efficiency of 62% for an output current of 70mA with a switching frequency of 200MHz with a 2×2mm on-chip LC output filter. The active part and the passive LC output filter are implemented on separate chips fabricated in 0.35-μm CMOS and connected with metal bumps. The optimization and improvement of the power efficiency and implementation structure are also discussed. © 2006 IEEE.
    2006, 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006, 127 - 130, English
    [Refereed]
    International conference proceedings

  • Hidetoshi Onodera, Makoto Ikeda, Tohru Ishihara, Tsuyoshi Isshiki, Koji Inoue, Kenichi Okada, Seiji Kajihara, Mineo Kaneko, Hiroshi Kawaguchi, Shinji Kimura, Morihiro Kuga, Atsushi Kurokawa, Takashi Sato, Toshiyuki Shibuya, Yoichi Shiraishi, Kazuyoshi Takagi, Atsushi Takahashi, Yoshinori Takeuchi, Nozomu Togawa, Hiroyuki Tomiyama, Yuichi Nakamura, Kiyoharu Hamaguchi, Yukiya Miura, Shin-Ichi Minato, Ryuichi Yamaguchi, Masaaki Yamada, Yasushi Yuminaka, Takayuki Watanabe, Masanori Hashimoto, Masayuki Miyazaki
    Institute of Electronics, Information and Communication, Engineers, IEICE, 2006, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E89-A(12) (12), 3377, English
    [Refereed]
    Scientific journal

  • T. Someya, T. Sekitani, S. Iba, Y. Kato, T. Sakurai, H. Kawaguchi
    It is believed that skin sensitivity will be important for future robots working in our daily life for home-care and entertainment purposes. However, relatively little progress has been made in the field of pressure recognition compared to the areas of sight and voice recognition, mainly because good artificial "electronic skin with a large area and mechanical flexibility is not yet available. The fabrication of a sensitive skin consisting of thousands of pressure sensors would require a flexible switching matrix that cannot be realized with present silicon-based electronics. Organic field-effect transistors can be used complimentary to such conventional electronics because organic circuits are inherently flexible and potentially ultra-low in cost even for large area. In this paper, we describe that integration of organic transistors and rubber pressure sensors provides an ideal solution to realize a practical artificial skin.
    2006, Molecular Crystals and Liquid Crystals, 444, 13 - 22, English
    [Refereed]
    International conference proceedings

  • Canh Quang Tran, Hiroshi Kawaguchi, Takayasu Sakurai
    A low-power FPGA design approach is proposed based on a fine-grain V(DD) control scheme called micro-V(DD)-hopping. Four configurable logic blocks (CLBs) are grouped into one block where V(DD) is shared. In the micro-V(DD)-hopping scheme, V(DD) in each block is changed between V(DDH) (high V(DD)) and V(DDL) (low V(DD)) spatially and temporally in order to achieve lower power without performance degraded. A low-power level shifter that has less contention is also proposed for low-swing inter-block signals. The FPGA incorporates the Zigzag power-gating scheme, in which special care has been taken to cope with a sneak leakage-path problem. A test chip was fabricated using a 0.35-μm CMOS technology, together with the conventional fixed-V(DD) FPGA for comparison. Measurement results show that dynamic power in the proposed scheme can be reduced by 86% when a frequency is half of the maximum one. Simulation using a 90-nm CMOS technology shows that leakage power can be reduced by 97%, when the proposed method is used. The area overhead of the proposed FPGA is 2%. Copyright © 2006 The Institute of Electronics, Information and Communication Engineers.
    Institute of Electronics, Information and Communication, Engineers, IEICE, 2006, IEICE Transactions on Electronics, E89-C(3) (3), 280 - 286, English
    [Refereed]
    Scientific journal

  • Isochronous MAC using long-wave standard time code for wireless sensor networks
    Masumi Ichien, Takashi Takeuchi, Shinji Mikami, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    This paper proposes Isochronous-MAC (I-MAC), which utilizes low-frequency radio waves time synchronization for sensor networks. Using INIAC, based on the Low Power Listening (LPL), all sensor nodes wake and listen channel periodically and synchronously. Since a sender can easily predict wakeup time of an intended receiver, it can shorten the length of preamble to make the receiver prepare for reception of the following data packet. This saves power consumption for the sender to rendezvous with the receiver. In the paper, we use an analytical model to investigate the impact of the data transmission frequency, the number of neighboring nodes, the wakeup period, the clock drift, and the time-synchronization frequency on the power consumption for consideration of the power overhead to perform the time synchronization. Those results demonstrate that I-MAC allows determination of any arbitrary wakeup period without much difficulty, whereas LPL requires a much more careful setting of the wakeup period because its optimum wakeup period is sensitive to the frequency of data transmission as well as to the number of neighboring nodes. Therefore, IMAC has a great potential to reduce the power consumption in most situations compared with LPL, in spite of the overhead to perform time synchronization.
    IEEE, 2006, 2006 FIRST INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND ELECTRONICS, 172 - +, English
    [Refereed]
    International conference proceedings

  • S Iba, Y Kato, T Sekitani, H Kawaguchi, T Sakurai, T Someya
    Inverter circuits have been made by connecting two high-quality pentacene field-effect transistors. A uniform and pinhole-free 900 nm thick polyimide gate-insulating layer was formed on a flexible polyimide film with gold gate electrodes and partially removed by using a CO2 laser drilling machine to make via holes and contact holes. Subsequent evaporation of the gold layer results in good electrical connection with a gold gate layer underneath the gate-insulating layer. By optimization of the settings of the CO2 laser drilling machine, contact resistance can be reduced to as low as 3 Omega for 180 mu m square electrodes. No degradation of the transport properties of the organic transistors was observed after the laser-drilling process. This study demonstrates the feasibility of using the laser drilling process for implementation of organic transistors in integrated circuits on flexible polymer films.
    SPRINGER HEIDELBERG, Jan. 2006, ANALYTICAL AND BIOANALYTICAL CHEMISTRY, 384(2) (2), 374 - 377, English
    [Refereed]
    Scientific journal

  • Shinji Mikami, Tetsuro Matsuno, Masayuki Miyama, Hiroshi Kawaguchi, Masahiko Yoshimoto, Hiroaki Ono
    This paper describes design and verification of a wireless-interface SoC (system-on-a-chip) for a wireless battery-less mouse with short-range data-communication capability. The SoC comprises an RF transmitter and microcontroller. The SoC, which is powered by an electric generator that exploits gyration energy by dragging the mouse, was fabricated using a TSMC 0.18-um CMOS process. The features of the SoC are the adoption of a simple FSK modulation scheme, single-end configuration on the RF transmitter, and specific microcontroller design for mouse operation. We verified that the RF transmitter can make data communication within a 1-m range at 2.17 mW, and the microcontroller consumes 0.03 mW at 1 MHz, which exhibits that the total power consumption is 2.2 mW. This is sufficiently low for the SoC to operate with energy harvesting.
    Institute of Electrical Engineers of Japan, 2006, IEEJ Transactions on Electronics, Information and Systems, 126(5) (5), 565 - 570, English
    [Refereed]
    Scientific journal

  • Impact of aggregation efficiency on GIT routing for wireless sensor networks
    Takafumi Aonishi, Takashi Matsuda, Shinji Mikami, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    In most research work for sensor network routings, perfect aggregation has been assumed. Such an assumption might limit the application of the wireless sensor networks. We address the impact of aggregation efficiency on energy consumption in the context of GIT routing. Our questions are how the most efficient aggregation point changes according to aggregation efficiency and the extent to which energy consumption can decrease compared to the original GIT routing and opportunistic routing. To answer these questions, we analyze a two-source model, which yields results that lend insight into the impact of aggregation efficiency. Based on analytical results, we propose an improved GIP "aggregation efficiency-aware GIT", or AGIT We also consider a suppression scheme for exploratory messages: "hop exploratory," Our simulation results show that the AGIT routing saves the energy consumption of the data transmission compared to the original GIT routing and opportunistic routing.
    IEEE COMPUTER SOC, 2006, 2006 INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING WORKSHOPS, PROCEEDINGS, pp.00-00, 151 - +, English
    [Refereed]
    International conference proceedings

  • A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering
    Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We propose a low-power two-port SRAM suitable for real-time video processing. In order to minimize discharge power on a read bitline, a majority-logic decides if input data are inverted in a write cycle, so that "1"s are in the majority. In video data, since more significant bits of adjacent pixel data are fortunately lopsided to either "0" or "1" with higher probability, the data bits in the pixels are reordered in each digit group to exploit the majority logic. The speed and area overheads are 4% and 11% in a 90-nm process technology, respectively. The proposed SRAM achieves 53% power reduction on the bitlines, and saves 43% of a total power when considered as an H.264 reconstructed-image memory.
    ASSOC COMPUTING MACHINERY, 2006, ISLPED '06: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, pp.61-66, 61 - 66, English
    [Refereed]
    International conference proceedings

  • A power-variation model for sensor node and the impact against life time of wireless sensor networks
    Takashi Matsuda, Takashi Takeuchi, Hironori Yoshino, Masumi Ichien, Shinji Mikami, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    We introduce manufacturing variation into a power model for a wireless sensor network node. Network protocols for the wireless sensor networks such as media access control and routing should be evaluated in terms of life time in a whole system. In fact, there exists power variation node by node due to the manufacturing variation. In the previous researches, however, this effect has not been investigated at all since it has been supposed that all nodes have a same power. In this paper, we develop a power model for a sensor node, in which we consider threshold-voltage variation derived from a manufacturing process. We take both a microprocessor and an RF part into account for the model, and implement it to QualNet in order to evaluate the impact against a life time of a wireless sensor network. The simulation results show that the conventional model has overestimated the life time longer than our model when nodes are randomly deployed. In contrast, if we make an optimum deployment of nodes by exploiting the power variation, the network life time is extended by 12.7% compared to the case of the conventional model.
    IEEE, 2006, 2006 FIRST INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND ELECTRONICS, pp.106-111, 106 - +, English
    [Refereed]
    International conference proceedings

  • A power- and area-efficient SRAM core architecturt for super-parallel video processing
    Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto, Tetsuro Matsuno
    super-parallel video processing, we proposed a power- and area-efficient SRAM core architecture with a segmentation-free access, which means accessibility to arbitrary consecutive pixels, and horizontal/vertical access. To achieve these flexible accesses, a spirally-connected local-wordline select signal and multi-selection scheme in wordlines are proposed, so that extra X-decoders in the conventional muld-division SRAM can be eliminated. Consequently, the proposed SRAM reduces an area and power by 69% and 59%, respectively, when it is applied to a 128 parallel architecture. The proposed 160-kbit SRAM with 16-read ports (eight-division and 2-read port SRAM) is implemented to a search window buffer for an H.264 motion estimation processor core which dissipates 800 mu W for QCIF 15-fps in a 130-nm technology.
    IFIP-INT FEDERATION INFORMATION PROCESSING, 2006, IFIP VLSI-SOC 2006: IFIP WG 10.5 INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION & SYSTEM-ON-CHIP, pp.192-197, 192 - +, English
    [Refereed]
    International conference proceedings

  • Takahiro Iinuma, Junichi Miyakoshi, Yuichiro Murachi, Tetsuro Matsuno, Masaki Hamamoto, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto, Masayuki Miyama
    This paper describes an 800-μW H.264 baseline-profile motion estimation processor for portable video applications. It features a VLSI-oriented block partitioning strategy, a reconfigurable SEMD/systolic-array datapath architecture and a power-efficient novel SRAM circuit with a segmentation-free and horizontal/vertical accessibility. The proposed architecture can reconfigure datapath to either an SIMD or systolic array depending on processing flow. The segmentation-free access means concurrent accessibility to arbitrary consecutive pixels. The processor supports all the seven kinds of block modes, and can handle three reference frames for a VGA (640 × 480) 30-fps to QCIF (176 × 144) 15-fps sequences with a quarter-pixel accuracy. It integrates 3.3 million transistors, and occupies 2.8 × 3.1 mm2 in a 130-nm CMOS technology. The proposed processor achieves a power of 800 μW for QCIF 15-fps with one reference picture. © 2006 IEEE.
    2006, 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006, pp.99-102, 99 - 102, English
    [Refereed]
    International conference proceedings

  • T Someya, Y Kato, S Iba, Y Noguchi, T Sekitani, H Kawaguchi, T Sakurai
    A large-area, flexible, and lightweight sheet image scanner has been successfully manufactured on a plastic film by integrating high-quality organic transistors and organic photodetectors. The effective sensing area of the integrated device is 5 x 5 cm(2); the resolution, 36 dots per inch (dpi); and the total number of sensor cells, 5184. The pentacene transistors with top contact geometry have a channel length of 18 mu m and mobility of 0.7 cm(2)/Vs. Organic photodetectors composed of copper phthalocyanine and 3,4,9,10-peryiene-tetracarboxylic-diimide distinguish between black and white parts on paper based on the difference in their reflectivity. Since this new area-type image-capturing device does not require any optics or mechanical scanning devices, the present sheet image scanners are mechanically flexible, lightweight, shock resistant, and potentially inexpensive to manufacture; therefore, they are suitable for human-friendly mobile electronics.
    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, Nov. 2005, IEEE TRANSACTIONS ON ELECTRON DEVICES, 52(11) (11), 2502 - 2511, English
    [Refereed]
    Scientific journal

  • センサネットワークのための集約率を考慮したGIT経路制御の評価
    AONISHI Takafumi, YOSHINO Hironori, MIKAMI Shinji, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    In most research work for sensor network routings, perfect aggregation has been assumed. Such an assumption might limit the application of the wireless sensor networks. We address the impact of aggregation efficiency on energy consumption in the context of GIT routing. Our question is the extent to which energy consumption can decrease compared to the original GIT. In this paper, we propose an improved GIT : "aggregation efficiency-aware routing", or AGIT. We also consider two suppression schemes for exploratory messages : "minimum exploratory" and "hop exploratory." Our simulation results show that the AGIT saves the energy consumption of the data transmission compared to the original GIT.
    The Institute of Electronics, Information and Communication Engineers, Oct. 2005, 電子情報通信学会技術研究報告;NS2005-108, Vol.105; No.357; pp.37-40(357) (357), 37 - 40, Japanese
    International conference proceedings

  • ワイヤレスセンサノードのための送信電力制御におけるインピーダンス不整合の影響
    MIKAMI Shinji, TAKEUCHI Takashi, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Sep. 2005, 2005年電子情報通信学会ソサイエティ大会;B-5-148, p.148, Japanese
    International conference proceedings

  • (Invited) Recent Progress of Organic Transistor Integrated Circuits for Large-Area Sensor Applications
    SOMEYA Takao, SAKURAI Takayasu, SEKITANI Tsuyoshi, KAWAGUCHI Hiroshi, IBA Shingo, KATO Yusaku, NOGUCHI Yoshiaki
    Sep. 2005, Proceedings of International Conference on Solid State Devices and Materials (SSDM), pp. 380-381
    [Refereed]
    International conference proceedings

  • T Someya, Y Kato, T Sekitani, S Iba, Y Noguchi, Y Murase, H Kawaguchi, T Sakurai
    Skin-like sensitivity, or the capability to recognize tactile information, will be an essential feature of future generations of robots, enabling them to operate in unstructured environments. Recently developed large-area pressure sensors made with organic transistors have been proposed for electronic artificial skin (E-skin) applications. These sensors are bendable down to a 2-mm radius, a size that is sufficiently small for the fabrication of human-sized robot fingers. Natural human skin, however, is far more complex than the transistor-based imitations demonstrated so far. It performs other functions, including thermal sensing. Furthermore, without conformability, the application of E-skin on three-dimensional surfaces is impossible. In this work, we have successfully developed conformable, flexible, large-area networks of thermal and pressure sensors based on an organic semiconductor. A plastic film with organic transistor-based electronic circuits is processed to form a net-shaped structure, which allows the E-skin films to be extended by 25%. The net-shaped pressure sensor matrix was attached to the surface of an egg, and pressure images were successfully obtained in this configuration. Then, a similar network of thermal sensors was developed with organic semiconductors. Next, the possible implementation of both pressure and thermal sensors on the surfaces is presented, and, by means of laminated sensor networks, the distributions of pressure and temperature are simultaneously obtained.
    NATL ACAD SCIENCES, Aug. 2005, PROCEEDINGS OF THE NATIONAL ACADEMY OF SCIENCES OF THE UNITED STATES OF AMERICA, 102(35) (35), 12321 - 12325, English
    [Refereed]
    Scientific journal

  • S Iba, T Sekitani, Y Kato, T Someya, H Kawaguchi, M Takamiya, T Sakurai, S Takagi
    We fabricated pentacene field-effect transistors with planar-type double-gate structures, where the top- and bottom-gate electrodes can independently apply voltage biases to channel layers. The threshold voltage of organic transistors is changed systematically in a wide range from -16 to -43 V when the voltage bias of the top-gate electrode is changed from 0 to +60 V. The mobility in the linear regime is almost constant (0.2 cm(2)/V s) at various voltage biases of the top-gate electrode and the on/off ratio is 10(6). (c) 2005 American Institute of Physics.
    AMER INST PHYSICS, Jul. 2005, APPLIED PHYSICS LETTERS, 87(2) (2), English
    [Refereed]
    Scientific journal

  • Keisuke Toyama, Satoshi Misaka, Kazuo Aisaka, Toshiyuki Aritsuka, Kunio Uchiyama, Koichiro Ishibashi, Hiroshi Kawaguchi, Takayasu Sakurai
    Frequency-voltage cooperative power control (FVC) is a powerful method to reduce the CPU power consumption of a program during execution, because it utilizes the information on the software workload dynamically. In this paper, we first show through a mathematical analysis the design rule to determine the necessary frequencies and its effect. Then we show experimental results of implementing an FVC with a feedback algorithm on MPEG-4 video and MP3 audio decoders with two sets of frequency and voltage. The FVC gave a 72% reduction in CPU power consumption during execution. In addition, we show a "Cool-Start" method that begins the FVC at a lower frequency and improves the power reduction effect. © 2005 Wiley Periodicals, Inc.
    Jun. 2005, Systems and Computers in Japan, 36(6) (6), 39 - 48, English
    [Refereed]
    Scientific journal

  • Time Revising Robust Frequency-Voltage Cooperative Power Reduction for Multi-tasking Multimedia Applications
    MISAKA Satoshi, KAWAGUCHI Hiroshi, SAKURAI Takayasu
    Apr. 2005, IEEE International Symposium on Low-Power and High-Speed Chips (COOL Chips), pp. 165-180
    [Refereed]
    International conference proceedings

  • Hiroshi Kawaguchi, Youngsoo Shin, Takayasu Sakurai
    This paper presents a cooperative dynamic power management method and its implementation. The implementation consists of design of a real-time OS, applications including MPEG-4, and development of a supporting hardware platform with an off-the-shelf processor. We describe several factors that are important in the implementation and discuss its efficiency through experiment. The experimental results with the prototype system shows that 74% power saving is possible in multi-task multimedia environment.
    Feb. 2005, IEEE Transactions on Multimedia, 7(1) (1), 67 - 74, English
    [Refereed]
    Scientific journal

  • Sheet image scanner with organic transistor integrated circuits
    T. Someya, T. Sakurai, T. Sekitani, H. Kawaguchi, Y. Kato, S. Iba
    A sheet image scanner has been fabricated by integrating high-quality organic transistors with organic photodetectors. Because the sheet scanner requires no mechanical components, it is mechanically flexible, light to transport, shock-resistant and potentially inexpensive to manufacture.
    2005, IDW/AD'05 - Proceedings of the 12th International Display Workshops in Conjunction with Asia Display 2005, (2) (2), 1037 - 1040, English
    International conference proceedings

  • Canh Q. Tran, Hiroshi Kawaguchi, Takayasu Sakurai
    A leakage current reduction scheme based on ZSCCMOS (zigzag super cutoff CMOS) is proposed for a LUT (look-up table ) using input forcing and an overdriven power gates. A fabricated chip demonstrates that the leakage current of the LUT can be reduced by more than 2 orders of magnitude. The wake-up time of the proposed LUT is 10 times as short as that of the LUT using SCCMOS (super cutoff CMOS). The area and delay overheads are 15% and 8%, respectively. © 2005 IEEE.
    2005, Proceedings - IEEE International Symposium on Circuits and Systems, 4701 - 4704, English
    [Refereed]
    International conference proceedings

  • K. Ishida, K. Kanda, A. Tamtrakarn, H. Kawaguchi, T. Sakurai
    A subthreshold-leakage suppressed switched capacitor (SC) circuit based on super cut-off CMOS (SCCMOS) scheme is introduced. This scheme realizes low-voltage SC circuits using low threshold voltage (VTH) transistors which are superior in drivability and are compatible with digital circuits. The SC circuit cannot be operated under 0.5V with high-VTH devices but on the other hand, SC circuits with low-VTH transistors suffer from charge loss even in analog operations. A 0.5-V sigma-delta modulator with the proposed scheme is successfully manufactured and measured by using 0.15-μm FD-SOI process with 0.1-V VTHN transistors. © 2005 IEEE.
    2005, Proceedings - IEEE International Symposium on Circuits and Systems, 3119 - 3122, English
    [Refereed]
    International conference proceedings

  • Kyeong-Sik Min, Kouichi Kanda, Hiroshi Kawaguchi, Kenichi Inagaki, Fayez Robert Saliba, Hoon-Dae Choi, Hyun-Young Choi, Daejeong Kim, Dong Myong Kim, Takayasu Sakurai
    A new Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) scheme is proposed to suppress leakage current by two orders of magnitude in the SRAM's for sub-70 nm process technology with sub-1-V V(DD) [10]. This two-order leakage reduction is caused from the cooperation of reverse body-to-source biasing and Drain Induced Barrier Lowering (DIBL) effects. In addition, metal shields are proposed to be inserted between the cell nodes and the bit lines not to allow the cell nodes to be flipped by the external bit-line coupling noise in this paper. A test chip has been fabricated to verify the effectiveness of the RRDSV scheme with the metal shields by using 0.18-μm CMOS process. The retention voltages of SRAM's with the metal shields are measured to be improved by as much as 40-60 mV without losing the stored data compared to the SRAM's without the shields. Copyright © 2005 The Institute of Electronics, Information and Communication Engineers.
    Institute of Electronics, Information and Communication, Engineers, IEICE, 2005, IEICE Transactions on Electronics, E88-C(4) (4), 760 - 767, English
    [Refereed]
    Scientific journal

  • Hiroshi Kawaguchi, Takao Someya, Tsuyoshi Sekitani, Takayasu Sakurai
    The concept of cut-and-paste customization is introduced for the first time in designing integrated circuits based on mechanically flexible organic field-effect transistors, and is applied to electronic artificial skin. The electronic artificial skin comprise of three separate integrated circuits that are a pressure-sensor array, row decoders, and column selectors to read out pressure information over a large area. All of three integrated circuits are scalable in size because the pressure-sensor array is a simple repetition of sensor cells and the row and column decoders adopt wired-NAND circuits, which enables the cut-and-paste customization in size. The physical cut-and-paste procedure is employed by cutting a part of the integrated circuits and pasting it to another integrated circuit with a connecting plastic tape. The integrated circuits are designed with a standard SPICE simulator and layout design tool, and the operation is confirmed by measurement.
    Jan. 2005, IEEE Journal of Solid-State Circuits, 40(1) (1), 177 - 185, English
    [Refereed]
    International conference proceedings

  • Subthreshold-leakage suppressed switched capacitor circuit based on super cut-off CMOS (SCCMOS)
    K Ishida, K Kanda, A Tamtrakarn, H Kawaguchi, T Sakurai
    A subthreshold-leakage suppressed switched capacitor (SC) circuit based on super cut-off CMOS (SCCMOS) scheme is introduced. This scheme realizes low-voltage SC circuits using low threshold voltage (V(TH)) transistors which are superior in drivability and are compatible with digital circuits. The SC circuit cannot be operated under 0.5V with high-V(TH) devices but on the other hand, SC circuits with low-V(TH) transistors suffer from charge loss even in analog operations. A 0.5-V sigma-delta modulator with the proposed scheme is successfully manufactured and measured by using 0.15-mu m FD-SOI process with 0.1-V V(THN) transistors.
    IEEE, 2005, 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, pp. 3119-3122, 3119 - 3122, English
    [Refereed]
    International conference proceedings

  • More than two orders of magnitude leakage current reduction in look-up table for FPGA's
    CQ Tran, H Kawaguchi, T Sakurai
    A leakage current reduction scheme based on ZSCCMOS (Zigzag super cutoff CMOS) is proposed for a LUT (look-up table) using input forcing and an overdriven power gates. A fabricated chip demonstrates that the leakage current of the LUT can be reduced by more than 2 orders of magnitude. The wake-up time of the proposed LUT is 10 times as short as that of the LUT using SCCMOS (super cutoff CMOS). The area and delay overheads am 15% and 8%, respectively.
    IEEE, 2005, 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, pp. 4701-4704, 4701 - 4704, English
    [Refereed]
    International conference proceedings

  • Low-power high-speed level shifter design for block-level dynamic voltage scaling environment
    CQ Tran, H Kawaguchi, T Sakurai
    Two novel level shifters that are suitable for block-level dynamic voltage scaling environment (namely, V-DD-hopping) are proposed. In order to achieve reduction in power consumption and delay, the first proposed level shifter which is called Contention Mitigated Level Shifter (CMLS) uses a contention-reduction technique. The simulation results with 65-nm CMOS model show 24% reduction in power and 50% decrease in delay with 4% area increase compared with the conventional level shifter. The second proposed level shifter which is called Bypassing Enabled Level Shifter (BELS) implements a bypass function and it is fabricated using 035pm CMOS technology. The measurement results show that the power and delay of the proposed BELS are reduced by 50% and 65%, respectively with 60% area overhead over the conventional level shifter.
    IEEE, 2005, 2005 International Conference on Integrated Circuit Design and Technology, pp. 229-232, 229 - 232, English
    [Refereed]
    International conference proceedings

  • Recent advances in applications of organic integrated circuits for large-area electronics
    T Someya, T Sakurai, T Sekitani, H Kawaguchi, S Iba, Y Kato
    IEEE, 2005, 2005 International Conference on Integrated Circuit Design and Technology, pp. 57-58, 57 - 58, English
    [Refereed]
    International conference proceedings

  • Managing leakage in charge-based analog circuits with low-V-TH transistors by analog T-switch (AT-switch) and super cut-off CMOS
    K Ishida, K Kanda, A Tamtrakarn, H Kawaguchi, T Sakurai
    Analog T-switch scheme is introduced to suppress subthreshold-leakage problems in charge-based analog circuits such as switched capacitor and sample and hold circuits. A 0.5-V sigma-delta modulator is manufactured in a 0.15-mu m FD-SOI process with low V-TH of 0.1V using the concept. The scheme is compared with another leakage suppressed scheme based on Super Cut-off CMOS (SCCMOS) and the conventional circuit which are also fabricated. The sigma-delta modulator based on analog T-switch realizes 6-bit resolution through reducing non-linear leakage effects while the conventional circuit and the scheme based on SCCMOS can achieve 4-bit and 5-bit resolution, respectively.
    JAPAN SOCIETY APPLIED PHYSICS, 2005, 2005 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 122-125, 122 - 125, English
    [Refereed]
    International conference proceedings

  • Experimental verification of row-by-row variable V-DD scheme reducing 95% active leakage power of SRAM's
    FR Saliba, H Kawaguchi, T Sakurai
    Low-power SRAM has become a critical component in recent VLSI systems. This paper reports an SRAM reducing 95% of active leakage power. The SRAM is successfully implemented and reliably measured for the first time, with self-aligned timing generation to avoid malfunction during V-DD transition. The cycle time overhead is 9%, and the area overhead is 3.5%.
    JAPAN SOCIETY APPLIED PHYSICS, 2005, 2005 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 162-165, 162 - 165, English
    [Refereed]
    International conference proceedings

  • Pocket scanner using organic transistors and detectors
    T Someya, T Sakurai, T Sekitani, H Kawaguchi, Y Kato, S Iba
    A pocket scanner has been manufactured by integrating high-quality organic transistors with organic photodetectors. Because the pocket scanner requires no mechanical components, it is mechanically flexible, light to transport, shock-resistant and potentially inexpensive to manufacture.
    IEEE, 2005, 2005 IEEE LEOS Annual Meeting Conference Proceedings (LEOS), pp. 59-60, 59 - 60, English
    [Refereed]
    International conference proceedings

  • 95% Leakage-reduced FPGA using zigzag power-gating, dual-V(TH)/V(DD) and micro-VDD-hopping
    Canh Q. Tran, Hiroshi Kawaguchi, Takayasu Sakurai
    Low-power FPGA architecture is proposed based on fine-grained V(DD) control scheme called micro-V(DD)-hopping. Four Configurable Logic Blocks (CLB) are grouped into one block where V(DD) is shared. In the micro-V(DD)-hopping scheme, V(DD) of each block is varied between the higher V(DD) (V(DDH)) and the lower V(DD) (V(DDL)) spatially and temporally to achieve lower power, while keeping performance undegraded. A level shifter that has less contention is proposed. The FPGA also incorporates Zigzag power-gating scheme, special care has been taken to cope with sneak leakage path problem. The proposed FPGA is fabricated using 035 mu m CMOS technology together with the conventional fixed-V(DD) FPGA. Measurement shows that the dynamic power can be reduced by 86% when the required speed is half of the highest speed. Simulation using 90nm CMOS technology shows that a leakage power reduction of 95% can be achieved, when the proposed method is used. Area overhead of the proposed FPGAs 2%.
    IEEE, 2005, 2005 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS, pp. 149-152, 149 - 152, English
    [Refereed]
    International conference proceedings

  • A flexible, lightweight Braille sheet display with plastic actuators driven by an organic field-effect transistor active matrix
    Y Kato, S Iba, T Sekitani, Y Noguchi, K Hizu, XZ Wang, K Takenoshita, Y Takamatsu, S Nakano, K Fukuda, K Nakamura, T Yamaue, M Doi, K Asaka, H Kawaguchi, M Takamiya, T Sakurai, T Someya
    A flexible, shock-resistant, and lightweight Braille sheet display has been successfully manufactured on a plastic film by integrating a plastic sheet actuator array with a high-quality organic transistor active matrix. This is the first demonstration, to the best of our knowledge, to integrate plastic MEMS (microelectromechanical systems) actuators with organic transistor active matrices, which opens up new versatile possibilities for flexible, large-area electronic applications including tactile displays.
    IEEE, 2005, IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST, pp. 105-108, 105 - 108, English
    [Refereed]
    International conference proceedings

  • 95% Leakage-reduced FPGA using zigzag power-gating, dual-V(TH)/V(DD) and micro-VDD-hopping
    Canh Q. Tran, Hiroshi Kawaguchi, Takayasu Sakurai
    Low-power FPGA architecture is proposed based on fine-grained V(DD) control scheme called micro-V(DD)-hopping. Four Configurable Logic Blocks (CLB) are grouped into one block where V(DD) is shared. In the micro-V(DD)-hopping scheme, V(DD) of each block is varied between the higher V(DD) (V(DDH)) and the lower V(DD) (V(DDL)) spatially and temporally to achieve lower power, while keeping performance undegraded. A level shifter that has less contention is proposed. The FPGA also incorporates Zigzag power-gating scheme, special care has been taken to cope with sneak leakage path problem. The proposed FPGA is fabricated using 035 mu m CMOS technology together with the conventional fixed-V(DD) FPGA. Measurement shows that the dynamic power can be reduced by 86% when the required speed is half of the highest speed. Simulation using 90nm CMOS technology shows that a leakage power reduction of 95% can be achieved, when the proposed method is used. Area overhead of the proposed FPGAs 2%.
    IEEE, 2005, 2005 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS, vol. E89-C, no. 3, pp. 280-286, 149 - 152, English
    [Refereed]
    International conference proceedings

  • Managing leakage in charge-based analog circuits with low-V-TH transistors by analog T-switch (AT-switch) and super cut-off CMOS
    K Ishida, K Kanda, A Tamtrakarn, H Kawaguchi, T Sakurai
    Analog T-switch scheme is introduced to suppress subthreshold-leakage problems in charge-based analog circuits such as switched capacitor and sample and hold circuits. A 0.5-V sigma-delta modulator is manufactured in a 0.15-mu m FD-SOI process with low V-TH of 0.1V using the concept. The scheme is compared with another leakage suppressed scheme based on Super Cut-off CMOS (SCCMOS) and the conventional circuit which are also fabricated. The sigma-delta modulator based on analog T-switch realizes 6-bit resolution through reducing non-linear leakage effects while the conventional circuit and the scheme based on SCCMOS can achieve 4-bit and 5-bit resolution, respectively.
    JAPAN SOCIETY APPLIED PHYSICS, 2005, 2005 Symposium on VLSI Circuits, Digest of Technical Papers, vol.41:no. 4:pp. 859-867, 122 - 125, English
    [Refereed]
    International conference proceedings

  • Takao Someya, Tsuyoshi Sekitani, Shingo Iba, Yusaku Kato, Hiroshi Kawaguchi, Takayasu Sakurai
    It is now widely accepted that skin sensitivity will be very important for future robots used by humans in daily life for housekeeping and entertainment purposes. Despite this fact, relatively little progress has been made in the field of pressure recognition compared to the areas of sight and voice recognition, mainly because good artificial "electronic skin" with a large area and mechanical flexibility is not yet available. The fabrication of a sensitive skin consisting of thousands of pressure sensors would require a flexible switching matrix that cannot be realized with present silicon-based electronics. Organic field-effect transistors can substitute for such conventional electronics because organic circuits are inherently flexible and potentially ultralow in cost even for a large area. Thus, integration of organic transistors and rubber pressure sensors, both of which can be produced by low-cost processing technology such as large-area printing technology, will provide an ideal solution to realize a practical artificial skin, whose feasibility has been demonstrated in this paper. Pressure images have been taken by flexible active matrix drivers with organic transistors whose mobility reaches as high as 1.4 cm2/V·s. The device is electrically functional even when it is wrapped around a cylindrical bar with a 2-mm radius.
    Jul. 2004, Proceedings of the National Academy of Sciences of the United States of America, 101(27) (27), 9966 - 9970, English
    [Refereed]
    Scientific journal

  • Yusaku Kato, Shingo Iba, Ryohei Teramoto, Tsuyoshi Sekitani, Takao Someya, Hiroshi Kawaguchi, Takayasu Sakurai
    The fabrication of high-quality pentacene field-effect transistors on polyethylenenaphthalate (PEN) films with polyimide gate dielectric layers was investigated. It was observed from atomic force microscopy measurements that the surface roughness of the gate dielectric layer was 0.2 nm, while of the base film was 1 nm. The on/off ratio and mobility of the transistors with pentacene channel layers, which were deposited on 990 nm polyimide gate dielectric layers, were 106 and 0.3 cm2/V s respectively. It was also observed that the mobility of the transistors was enhanced up to 1 cm 2/V s by decreasing the thickness of the polyimide gate dielectric layers to 540 nm.
    May 2004, Applied Physics Letters, 84(19) (19), 3789 - 3791, English
    [Refereed]
    Scientific journal

  • A large-area, flexible, and lightweight sheet image scanner integrated with organic field-effect transistors and organic photodiodes
    Takao Someya, Shingo Iba, Yusaku Kato, Tsuyoshi Sekitani, Yoshiaki Noguchi, Yousuke Murase, Hiroshi Kawaguchi, Takayasu Sakurai
    A large-area, flexible, and lightweight sheet image scanner has been successfully manufactured on a plastic film, for the first time, integrating high-quality organic transistors and organic photodetectors. Since this area-type image-capturing device does not require any optics or any mechanical scanning devices, it is innovatively light to carry, shock-resistant and potentially inexpensive to manufacture. © 2004 IEEE.
    2004, Technical Digest - International Electron Devices Meeting, IEDM, 365 - 368, English
    International conference proceedings

  • Hiroshi Kawaguchi
    2004, Materials Research Society Symposium - Proceedings
    Scientific journal

  • 0.5V, 400MHz, VDD-hopping processor with zero VTH FD-SOI technology
    Hiroshi Kawaguchi, Kouichi Kanda, Koichi Nose, Sadaaki Hattori, Danardono Dwi Antono, Daisuke Yamada, Takayuki Miyazaki, Kenichi Inagaki, Toshiro Hiramoto, Takayasu Sakurai
    A 0.5V, 400MHz, 3.5mW, 16b RISC processor with a 0.25μm, dual VT, fully-depleted SOI technology is presented. Zero VT is used in logic for high speed while memories and register files adopt a higher VDD and VT to suppress leakage. Experimental results show that VDD-hopping is effective in leakage dominant environments.
    2003, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 101 - 481, English
    International conference proceedings

  • Row-by-row dynamic source-line voltage control (RRDSV) scheme for two orders of magnitude leakage current reduction of sub-1-V-V-DD SRAM's
    KS Min, K Kanda, T Sakurai
    A new Row-by-Row Dynamic Source-line Voltage control (RRDSV) scheme is proposed to reduce the active leakage as well as the stand-by leakage in SRAM. By dynamically controlling the source-line voltage of cells row by row, the cell leakage through inactive cells can be reduced by two orders of magnitude. Moreover, the bit-line leakage through pass transistors can be completely cut off. This leakage reduction is caused from the cooperation of reverse body-to-source biasing and Drain Induced Barrier Lowering (DIBL) effects. A test chip has been fabricated using 0.18-mum triple-well CMOS technology to verify the data retention capability of this RRDSV scheme. The minimum retention voltage in the RRDSV is measured to be reduced by more than 60mV, when shielding metal is inserted to protect the memory cell nodes from bit-line coupling noise. It can reduce the leakage by another 50% in addition to the reduction by two orders of magnitude.
    ASSOC COMPUTING MACHINERY, 2003, ISLPED'03: PROCEEDINGS OF THE 2003 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, vol. E88-C, no. 4, pp. 760-767, 66 - 71, English
    [Refereed]
    International conference proceedings

  • Koichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi, Seongsoo Lee, Takayasu Sakurai
    In order to suppress the power consumption in low-voltage processors, a threshold voltage hopping (VTH-hopping) scheme is proposed where the threshold voltage is dynamically controlled through software depending on a workload. V TH-hopping is shown to reduce the power to 18% of the fixed low-threshold voltage circuits in 0.5-V supply voltage regime for multimedia applications. A positive back-gate bias scheme with V TH-hopping is presented for the high-performance and low-voltage processors. In order to verify the effectiveness of V TH-hopping, a small-scale RISC processor with V TH-hopping capability and the positive back-gate bias scheme is fabricated in a 0.6-μm CMOS technology. MPEG4 encoding is simulated based on the measured data. The result shows that 86 % power saving can be achieved by using V TH-hopping compared with the fixed positive back-gate bias scheme.
    Mar. 2002, IEEE Journal of Solid-State Circuits, 37(3) (3), 413 - 419, English
    [Refereed]
    Scientific journal

  • A controller LSI for realizing V-DD-hopping scheme with off-the-shelf processors and its application to MPEG4 system
    Hiroshi Kawaguchi
    2002, IEICE Transactions on Electronics
    Scientific journal

  • Kawaguchi, H., Zhang, G., Lee, S., Shin, Y., Sakurai, T.
    2002, IEICE Transactions on Electronics, E85-C(2) (2)
    Scientific journal

  • Kouichi Kanda, Takayuki Miyazaki, Mitt Kyeong Sik, Hiroshi Kawaguchi, Takayasu Sakurai
    A novel SRAM scheme is proposed that can reduce the active leakage power by two orders of magnitude. In low voltage region less than IV, the VTH, VTH, is lowered to less than 0.2V and leakage power of memory cells becomes a dominant issue. By dynamically dropping the supply voltage of un-accessed cells row by row, the cell leakage can be reduced exponentially through the Drain Induced Barrier Lowering (DIBL) effect. Additionally, to lower the leakage from bit-line through transfer gates of memory cells, un-accessed word line is applied negative voltage together with reduced swing write technique. The bASIC advantage is verified by measurement and the effectiveness in future generations is discussed by simulations.
    Institute of Electrical and Electronics Engineers Inc., 2002, Proceedings of the Annual IEEE International ASIC Conference and Exhibit, 2002-, 381 - 385, English
    [Refereed]
    International conference proceedings

  • Kouichi Kanda, Kouichi Nose, Hiroshi Kawaguchi, Takayasu Sakurai
    In Sub-1-V CMOS designs, especially around 0.5-V CMOS designs, on-state drain current of MOSFETs shows positive temperature dependence, being different from the negative temperature dependence in the conventional voltage designs. Combined with low threshold voltage less than 0.2 V, the possibility of temperature instability increases. This paper describes possible temperature instabilities in the low-voltage regime by using circuit simulation environments incorporating temperature change in time and experiments using MOSFETs and the 32-bit adder circuit in quarter-micrometer CMOS technology with a low threshold voltage of 0.25 V.
    Oct. 2001, IEEE Journal of Solid-State Circuits, 36(10) (10), 1559 - 1564, English
    [Refereed]
    Scientific journal

  • Optimum device parameters and scalability of variable threshold voltage complementary MOS (VTCMOS)
    T Hiramoto, M Takamiya, H Koura, T Inukai, H Gomyo, H Kawaguchi, T Sakurai
    The optimum device parameters of variable threshold voltage complementary metal oxide semiconductor (VTCMOS) have been investigated by means of device simulation and its scalability has been discussed. The optimum body effect factor depends on the relationship between the substrate bias and the supply voltage. It is shown that the VTCMOS scheme aiming at extremely low stand-by power will fail as the device size and the supply voltage are scaled. The advantage of VTCMOS will be its high speed, and the VTCMOS will be essential in high-speed circuits operating at a low supply voltage in combination with another low stand-by power scheme such as the insertion of leak cut-off switches.
    INST PURE APPLIED PHYSICS, Apr. 2001, JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 40(4B) (4B), 2854 - 2858, English
    [Refereed]
    Scientific journal

  • Hiroshi Kawaguchi
    2001, International Archives of Allergy and Immunology
    Scientific journal

  • Hiroshi Kawaguchi, Gang Zhang, Seongsoo Lee, Takayasu Sakurai
    An LSI is fabricated and measured to demonstrate the feasibility of the V/sub DD/-hopping scheme in a system level. In the scheme, supply voltage, V/sub DD/, is dynamically controlled through software depending on workload. The V/sub DD/-hopping scheme is shown to reduce the power to less than 1/4 compared with the conventional fixed-V/sub DD/ scheme. The power saving is achieved without degrading the real-time feature of an MPEG4 system. © 2001 IEEE.
    2001, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings, 4, 918 - 921, English
    [Refereed]
    International conference proceedings

  • Hiroshi Kawaguchi, Koichi Nose, Takayasu Sakurai
    A super cut-off CMOS (SCCMOS) scheme is proposed and demonstrated by measurement to achieve high-speed and low stand-by current CMOS VLSIs in sub-1-V supply voltage regime. By overdriving the gate of a cut-off MOSFET, the SCCMOS suppresses leakage current below 1 pA per logic gate in a stand-by mode while high-speed operation in an active mode is possible with low-threshold voltage of 0.1-0.2 V. The SCCMOS pushes the low-voltage operation limit 0.2 V further down compared with conventional schemes while maintaining the same stand-by current level.
    IEEE, Oct. 2000, IEEE Journal of Solid-State Circuits, 35(10) (10), 1498 - 1501, English
    [Refereed]
    Scientific journal


  • Boosted gate MOS (BGMOS): Device/circuit cooperation scheme to achieve leakage-free giga-scale integration
    T Inukai, M Takamiya, K Nose, H Kawaguchi, T Hiramoto, T Sakurai
    This paper proposes a new device and circuit scheme that drastically suppresses the stand-by leakage current for the deep sub-0.1 mu m era while maintaining the circuit speed. Applying boosted gate voltage on the low leakage switches with higher V-th and thicker T-ox, extremely low stand-by power for battery type application is achieved, while degradation of circuit performance and an increase of area overhead are sufficiently suppressed. The combination with a negative gate voltage scheme and the application of the boosted voltage scheme to SRAMs are also discussed.
    IEEE, 2000, PROCEEDINGS OF THE IEEE 2000 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 409 - 412, English
    [Refereed]
    International conference proceedings

  • Vitamin D receptor gene polymorphism in sarcoidosis
    Hiroshi Kawaguchi
    1999, American Journal of Respiratory and Critical Care Medicine
    Scientific journal

  • Hiroshi Kawaguchi, Takayasu Sakurai
    A reduced clock-swingflip-flop (RCSFF) is proposed, which is composed of a reduced swing clock driver and a special flip-flop which embodies the leak current cutoff mechanism. The RCSFF can reduce the clock system power of a VLSI down to one-third compared to the conventional flip-flop. This power improvement is achieved through the reduced clock swing down to 1 V. The area and the delay of the RCSFF can also be reduced by a factor of about 20% compared to the conventional flipflop. The RCSFF can also reduce the RC delay of a long RC interconnect to one-half.
    John Wiley and Sons Inc., Jan. 1999, High-Performance System Design: Circuits and Logic, 349 - 353, English
    [Refereed]
    In book

  • Hiroshi Kawaguchi, Takayasu Sakurai
    A reduced clock-swing flip-flop (RCSFF) is proposed, which is composed of a reduced swing clock driver and a special flip-flop which embodies the leak current cutoff mechanism. The RCSFF can reduce the clock system power of a VLSI down to one-third compared to the conventional flip-flop. This power improvement is achieved through the reduced clock swing down to 1 V. The area and the delay of the RCSFF can also be reduced by a factor of about 20% compared to the conventional flipflop. The RCSFF can also reduce the RC delay of a long RC interconnect to one-half.
    May 1998, IEEE Journal of Solid-State Circuits, 33(5) (5), 807 - 811, English
    [Refereed]
    Scientific journal

  • Hiroshi Kawaguchi
    1998, PROCEEDINGS OF THE ASP-DAC - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE WITH EDA TECHNO FAIR
    Scientific journal

■ MISC
  • マイクロ波ドップラーセンサを用いた非接触生体認証—Heartbeat-based Non-contact Biometric Authentication Using Microwave Doppler Sensor
    高橋 宏太, 和泉 慎太郎, 川口 博
    [東京] : Institute of Electrical Engineers of Japan, Nov. 2023, 「センサ・マイクロマシンと応用システム」シンポジウム論文集 電気学会センサ・マイクロマシン部門 [編], 40, 5p, Japanese

  • Contactless respiration monitoring using spatial ultrasound Doppler sensor
    都甲尚志, 河合晃聖, 石井徹, 和泉慎太郎, 川口博
    2023, 電子情報通信学会大会講演論文集(CD-ROM), 2023

  • Ray-tracing ultrasonic simulation method for bathroom surveillance
    BIN KAMARULZAMAN M. Shahrul Amir, 濱邉理久, 安田祐人, 大原遼太郎, 佐藤駿, 和泉慎太郎, 川口博
    2023, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 40th

  • 3D person location estimation using spatial ultrasound and VAE in the bathroom
    佐藤駿, 安田祐人, 大原遼太郎, 濱邉理玖, 玄田貴之, 今中翔哉, 和泉慎太郎, 川口博
    2023, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 40th

  • Bathroom acoustic event detection using machine learning
    森浩貴, 玄田貴之, 佐藤駿, 大原遼太郎, SHAHRUL Muhammad, 安田裕人, 河合晃聖, 濱邉理玖, 和泉慎太郎, 川口博
    2023, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 40th

  • Road traffic monitoring by machine learning using ultrasonic and audible sound
    濱邉理玖, 大原遼太郎, 安田祐人, 佐藤駿, 川口博, 和泉慎太郎
    2023, 電子情報通信学会大会講演論文集(CD-ROM), 2023

  • Feature Extraction from Body Surface Potential using Variational Autoencoder
    吉野早耶, 和泉慎太郎, 川口博
    2023, 電子情報通信学会大会講演論文集(CD-ROM), 2023

  • 1W/8R20T SRAMコードブックメモリによる深層学習プロセッサの主記憶帯域削減
    大原遼太郎, 加太雅也, 大地正和, 大地正和, 安田祐人, 大地正和, 濱邉理玖, 和泉慎太郎, 川口博
    2023, 電子情報通信学会技術研究報告(Web), 123(143(SDM2023 35-53)) (143(SDM2023 35-53))

  • 空間超音波を用いた非接触バイタルモニタリング—Non-contact vital monitoring using spatial ultrasound
    河合 晃聖, 和泉 慎太郎, 川口 博, 近藤 勲, 小椋 朗広
    Institute of Electrical Engineers of Japan, Nov. 2022, 「センサ・マイクロマシンと応用システム」シンポジウム論文集 電気学会センサ・マイクロマシン部門 [編], 39, 3p, Japanese

  • マルチモーダルセンシングによる脊髄損傷患者の下肢伸展挙上の解析—Analysis of SLR in spinal cord injury patients using multimodal sensing
    吉倉 崚人, 和泉 慎太郎, 杉本 達也, 川口 博
    Institute of Electrical Engineers of Japan, Nov. 2022, 「センサ・マイクロマシンと応用システム」シンポジウム論文集 電気学会センサ・マイクロマシン部門 [編], 39, 4p, Japanese

  • Ryo Takamatsu, Shogo Amano, Shintaro Izumi, Hiroshi Ohta, Toshikazu Nezu, Yuki Noda, Teppei Araki, Takafumi Uemura, Tsuyoshi Sekitani, Hiroshi Kawaguchi
    IEEE, Nov. 2022, 2022 IEEE Sensors, 39, 3p - 4, Japanese

  • Outdoor 3D object reconstruction method using spatial ultrasound and VAE
    佐藤駿, 安田祐人, 大原遼太郎, 濱邉理玖, 石井徹, 和泉慎太郎, 川口博
    2022, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 39th

  • Low Power Noise Reduction Technology for ECG Sensors Using Dry Electrodes
    元辻有貴, 和泉慎太郎, 川口博
    2022, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 39th

  • Thermal Stimulation Device Using Matrix Drive Circuitry
    江森俊哉, 和泉慎太郎, 和泉慎太郎, 伊庭野健造, 伊庭野健造, 伊藤雄一, 伊藤雄一, 佐藤克成, 佐藤克成, 菅原徹, 菅原徹, 川口博
    2022, 日本機械学会ロボティクス・メカトロニクス講演会講演論文集(CD-ROM), 2022

  • マイクロ波ドップラーセンサを用いた心拍計測における個人差の評価
    真鍋歩夢, 和泉慎太郎, 落合拓光, 川口博
    2021, 電子情報通信学会技術研究報告(Web), 121(24(WBS2021 1-21)) (24(WBS2021 1-21))

  • 大型船舶エンジンの燃料効率改善を目的とした回転体位相計測センサの開発
    小銭瞭介, 原田正康, 吉川裕木子, 石井徹, 和泉慎太郎, 川口博, 上村祥平, 荒木要, 松田真理子
    2021, マリンエンジニアリング学術講演会講演論文集, 91st

  • A Consideration of Heart Rate Measurement Technology with Doppler sensor
    落合拓光, 和泉慎太郎, 矢野裕二, 川口博, 吉本雅彦
    2020, 電子情報通信学会大会講演論文集(CD-ROM), 2020

  • A Study of Machine Learning Architecture for Wearable Bio-signal Sensor
    渡辺大輔, 矢野祐二, 和泉慎太郎, 川口博, 吉本雅彦
    2020, 電子情報通信学会大会講演論文集(CD-ROM), 2020

  • Low Power circuit for Electro-Cardiogram Measurement Using Body Temperature Power Generation
    藤井将裕, 和泉慎太郎, 矢野裕二, 川口博, 吉本雅彦
    2020, 電子情報通信学会大会講演論文集(CD-ROM), 2020

  • 加速度センサとひずみセンサを用いた咳嗽検出手法の検討
    渡辺大輔, 和泉慎太郎, 大歳丈博, 永野達也, 西村善博, 吉本雅彦, 川口博
    2020, 電子情報通信学会技術研究報告(Web), 120(219(MICT2020 7-20)) (219(MICT2020 7-20))

  • Heart Rate Interval Error Compensation Method Using Multiple-Photoplethysmography
    親富彩花, 和泉慎太郎, 矢野裕二, 川口博, 吉本雅彦
    2020, 電子情報通信学会大会講演論文集(CD-ROM), 2020

  • A Low-Power Photoplethysmography Sensor Using Current Integration Circuit
    笹井 香菜, 和泉 慎太郎, 渡辺 健斗, 矢野 祐二, 川口 博, 吉本 雅彦
    Institute of Electrical Engineers of Japan, 19 Nov. 2019, 「センサ・マイクロマシンと応用システム」シンポジウム論文集 電気学会センサ・マイクロマシン部門 [編], 36, 4p, Japanese

  • 光電式容積脈波法を用いた脈拍測定の低消費電力化手法
    渡辺健斗, 和泉慎太郎, 矢野祐二, 川口博, 吉本雅彦
    2019, 電子情報通信学会技術研究報告, 118(383(MICT2018 59-67)(Web)) (383(MICT2018 59-67)(Web))

  • ウェアラブル生体情報センサのための学習推論アルゴリズムの検討
    渡辺大輔, 矢野祐二, 和泉慎太郎, 川口博, 吉本雅彦
    2019, 電子情報通信学会技術研究報告, 119(263(MICT2019 23-37)(Web)) (263(MICT2019 23-37)(Web))

  • ARモデルを用いた心拍変動解析のための低消費電力アーキテクチャの検討
    吉田聖也, 和泉慎太郎, 矢野裕二, 川口博, 吉本雅彦
    2019, 電子情報通信学会大会講演論文集(CD-ROM), 2019

  • メモリ容量と帯域幅削減のための分散深層学習ハードウェア
    川口博, 森陽紀, 陽川哲也, 和泉慎太郎, 井上淳樹
    2018, 電気関係学会関西連合大会講演論文集(CD-ROM), 2018

  • Chemical Reaction Actuator and Wireless Power Feeding for Swallowable Sensing Device
    中村 亮太, 和泉 慎太郎, 川口 博, 吉本 雅彦, 太田 英敏
    Institute of Electrical Engineers of Japan, 31 Oct. 2017, 「センサ・マイクロマシンと応用システム」シンポジウム論文集 電気学会センサ・マイクロマシン部門 [編], 34, 1 - 5, Japanese

  • マイクロ波ドップラーセンサを用いた車両走行中の心拍計測手法
    松永大地, 和泉慎太郎, 川口博, 吉本雅彦
    2017, 電子情報通信学会大会講演論文集(CD-ROM), 2017

  • ノイズフィードバック技術を用いたウェアラブル向け容量結合型心電センサ
    永里佑樹, 和泉慎太郎, 川口博, 吉本雅彦
    2017, 電子情報通信学会大会講演論文集(CD-ROM), 2017

  • ウェアラブルデバイスのための圧電素子を用いたマルチモーダルな心血管情報の計測
    岡野孝昭, 和泉慎太郎, 勝浦巧, 川口博, 吉本雅彦
    2017, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 34th

  • ヘルスケアデバイスと材料
    川口博, 和泉慎太郎, 吉本雅彦
    2016, 日本化学会春季年会講演予稿集(CD-ROM), 96th

  • 加速度センサを用いた低消費電力運動強度推定アルゴリズム
    塚原美緒, 中西基文, 和泉慎太郎, 中井陽三郎, 川口博, 吉本雅彦
    2016, 電気学会電子・情報・システム部門大会講演論文集(CD-ROM), 2016

  • 和泉 慎太郎, 川口 博, 吉本 雅彦
    一般社団法人 電気学会, 2016, 電気学会論文誌. E, センサ・マイクロマシン部門誌, 136(3) (3), NL3_2 - NL3_2, Japanese

  • IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

    Monitoring of daily life using a wearable sensor is useful to prevent lifestyle diseases. This paper presents an electrocardiograph (ECG) monitoring SoC using a non-volatile MCU and a noise-tolerant instantaneous heartbeat detector.

    The Japan Society of Applied Physics, 2016, Oyo Buturi, 85(4) (4), 301 - 305, Japanese
    [Refereed][Invited]
    Introduction scientific journal

  • Haptic Stimulus Actuator using Piezoelectric Pump for Wearable Devices
    児玉 泰佑, 和泉 慎太郎, 正木 何奈, 川口 博, 吉本 雅彦, 前中 一介
    Institute of Electrical Engineers of Japan, 28 Oct. 2015, 「センサ・マイクロマシンと応用システム」シンポジウム論文集 電気学会センサ・マイクロマシン部門 [編], 32, 1 - 5, Japanese

  • Non-contact and Noise Tolerant Heart Rate Monitoring using Microwave Doppler Sensor and Range Imagery
    松永 大地, 和泉 慎太郎, 奥野 圭祐, 川口 博, 吉本 雅彦
    Institute of Electrical Engineers of Japan, 28 Oct. 2015, 「センサ・マイクロマシンと応用システム」シンポジウム論文集 電気学会センサ・マイクロマシン部門 [編], 32, 1 - 5, Japanese

  • Dependable Memory Design for Robust VLSI System
    吉本 秀輔, 川口 博, 吉本 雅彦
    [電子情報通信学会], 03 Aug. 2015, 回路とシステムワークショップ論文集 Workshop on Circuits and Systems, 28, 276 - 281, Japanese

  • A Noise-Tolerant ECG Sensing Method for Wearable Healthcare Systems
    TANAKA Yoshito, KAWAMOTO Yuta, NAKAI Youzaburo, OKUNO Keisuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    The Institute of Electronics, Information and Communication Engineers, 24 Nov. 2014, IEICE technical report. Computer systems, 114(346) (346), 47 - 47, Japanese

  • A Normally-off Wearable Monitoring SoC using Non-volatile MCU
    Matsunaga Daichi, NAKAI Yozaburo, KAWAMOTO Yuta, NAKAGAWA Tomoki, OKUNO Keisuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    The Institute of Electronics, Information and Communication Engineers, 24 Nov. 2014, IEICE technical report. Computer systems, 114(346) (346), 49 - 49, Japanese

  • A 0.38-V Operating STT-MRAM with Process Variation Tolerant Sense Amplifier
    UMEKI Yohei, YANAGIDA Koji, YOSHIMOTO Shusuke, IZUMI Shintaro, YOSHIMOTO Masahiko, Kawaguchi Hiroshi, TSUNODA Koji, SUGII Toshihiro
    This paper exhibits a 65-nm 8-Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at a single supply voltage with a process-variation tolerant sense amplifier. The proposed sense amplifier comprises a boosted-gate nMOS and negative-resistance pMOSes as loads, which maximizes the readout margin in any process corner. The STT-MRAM achieves a cycle time of 1.9μs (=0.526MHz) at 0.38V. The operating power is 6.15μW at that voltage. The minimum energy per access is 3.89pJ/bit when the supply voltage is 0.44V. The proposed STT-MRAM operates at lower energy than SRAM when a utilization of a memory bandwidth is 14% or less.
    The Institute of Electronics, Information and Communication Engineers, 17 Apr. 2014, Technical report of IEICE. ICD, 114(13) (13), 47 - 51, Japanese

  • STT-MRAM Architecture for Improving Throughput
    Mori Haruki, Yanagida Koji, Umeki Yohei, Yoshimoto Shusuke, Izumi Shintaro, Yoshimoto Masahiko, Kawaguchi Hiroshi, Tsunoda Koji, Sugii Toshihiro
    The Institute of Electronics, Information and Communication Engineers, 21 Jan. 2014, Technical report of IEICE. ICD, 113(419) (419), 27 - 27, Japanese

  • High-Speed Ferroelectric 6T4C Shadow SRAM for Normally-Off Computing
    NAKAGAWA Tomoki, YOSHIMOTO Shusuke, KITAHARA Yuki, YANAGIDA Koji, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    The Institute of Electronics, Information and Communication Engineers, 21 Jan. 2014, Technical report of IEICE. ICD, 113(419) (419), 39 - 39, Japanese

  • Electrocardiogram analytical technique for wearable living body sensors wearable biomedical sensor
    NAKAI Yozaburo, IZUMI Shintaro, NAKANO Masanao, YAMASHITA Ken, FUJII Takahide, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    The Institute of Electronics, Information and Communication Engineers, 21 Jan. 2014, Technical report of IEICE. ICD, 113(419) (419), 61 - 61, Japanese

  • 低消費電力貼り付け型センサのためのテンプレートマッチングを用いたロバスト心拍抽出手法の開発
    中井陽三郎, 和泉慎太郎, 中野将尚, 山下顕, 藤井貴英, 川口博, 吉本雅彦
    2014, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 31st

  • 5.5 A Reconfigurable Architecture for Dependable Cache(5. Time-Dependent Degradation in Device Characteristics,Dependable VLSI System)
    YOSHIMOTO Masahiko, NAKATA Yohei, KIMI Yuta, Jung Jinwook, KAWAGUCHI Hiroshi
    Reliability Engineering Association of Japan (REAJ), 01 Dec. 2013, The journal of Reliability Engineering Association of Japan, 35(8) (8), 462 - 462, Japanese

  • Normally-Off Computing: 4. Normally-off Computing Techniques for Wearable Healthcare Systems
    藤森 敬和, 和泉 慎太郎, 川口 博, 志賀 利一, 吉本 雅彦
    本稿ではウェアラブルな貼り付け型生体情報計測センサにおける課題と,生体信号計測のためのノーマリーオフコンピューティング手法について解説する.また,本研究で試作した貼り付け型生体情報計測センサLSIを紹介する.常時計測可能な貼り付け型生体情報計測センサノードを実現するためには,センサのサイズと重量を可能な限り削減する必要がある.貼り付け型センサノードを構成する要素の内,重量に対して最も支配的な要素はバッテリであり,ノーマリーオフコンピューティングによってセンサLSIの消費電力を極限まで削減することを目指している.
    情報処理学会 ; 1960-, 15 Jun. 2013, 情報処理, 54(7) (7), 677 - 682, Japanese

  • KAWAGUCHI Hiroshi, YOSHIMOTO Shusuke, OKUMURA Shunsuke, Amashita TAKURO, IZUMI Shintaro, YOSHIMOTO Masahiko
    Reliability Engineering Association of Japan, 2013, The Journal of Reliability Engineering Association of Japan, 35(8) (8), 432 - 432, Japanese

  • Introducing Multiple Microphone Arrays for Enhancing Smart Home Voice Control
    Shimpei Soda, Masahide Nakamura, Shinsuke Matsumoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We have previously developed a voice control system for a home network system (HNS), using a microphone array technology. Although the microphone array achieved a convenient hands-free controller, a single array had limitations on coverage of sound collection and speech recognition rate. In this paper, we try to overcome the limitations by increasing the number of the microphone arrays. Specifically, we construct a microphone array network using four separate arrays, and enhance algorithms of sound source localization (SSL) and sound source separation (SSS) on the network. We also conduct an experimental evaluation, where precision of SSL and speech recognition rate are evaluated in a real HNS test-bed. As a result, it is shown that the usage of multiple arrays significantly improves the coverage and speech recognition ratio, compared with the previous system.
    The Institute of Electronics, Information and Communication Engineers, Jan. 2013, 電子情報通信学会技術研究報告, 112(388) (388), 19 - 24, English

  • A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme
    YOSHIMOTO Shusuke, TERADA Masaharu, OKUMURA Shunsuke, SUZUKI Toshikazu, MIYANO Shinji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    This paper presents a novel disturb mitigation scheme which achieves low-power and low-voltage operation for a deep sub-micron SRAM macro. The classic write-back scheme overcame a half-select problem and improved a yield; however, the conventional scheme consumed more power due to charging and discharging all write bitlines (WBLs) in a sub block. Our proposed scheme consists of a floating bitline technique and a low-swing bitline driver (LSBD). This scheme decreases active leakage and active power by 33% and 37% at the FF corner, respectively. In other process corners, more active power reduction can be expected. We fabricated a 512-Kb 8T SRAM test chip that operates at a single 0.5-V supply voltage. The proposed scheme achieves 1.52-μW/MHz active energy in a write cycle and 72.8-MW leakage power, which are 59.4% and 26.0% better than the conventional write-back scheme. The total energy is 12.9 μW/MHz at 0.5 V in a 50%-read / 50%-write operation.
    The Institute of Electronics, Information and Communication Engineers, 16 Apr. 2012, Technical report of IEICE. ICD, 112(15) (15), 73 - 78, Japanese

  • C-12-4 A Block-Basis On-Line Built-In Self-Test Architecture for Dependable SRAM
    Fujikawa Asuka, Yoshikawa Masahiro, Okumura Shunsuke, Nakata Yohei, Kagiyama Yuki, Kawaguchi Hiroshi, Yoshimoto Masahiko
    The Institute of Electronics, Information and Communication Engineers, 06 Mar. 2012, Proceedings of the IEICE General Conference, 2012(2) (2), 76 - 76, Japanese

  • C-12-1 A 40-nm 0.6-V Operation Half-Select Resilient 8T SRAM with Sequential Writing Technique
    Umeki Youhei, Terada Masaharu, Yoshimoto Shusuke, Kawaguchi Hiroshi, Yoshimoto Masahiko
    The Institute of Electronics, Information and Communication Engineers, 06 Mar. 2012, Proceedings of the IEICE General Conference, 2012(2) (2), 73 - 73, Japanese

  • C-12-3 Bit Error Rate Estimation SRAM Considering Temperature Fluctuation
    Kitahara Yuki, Kagiyama Yuki, Okumura Shunsuke, Yanagida Koji, Yoshimoto Shusuke, Nakata Yohei, Izumi Shintaro, Kawaguchi Hiroshi, Yoshimoto Masahiko
    The Institute of Electronics, Information and Communication Engineers, 06 Mar. 2012, Proceedings of the IEICE General Conference, 2012(2) (2), 75 - 75, Japanese

  • マイクアレイネットワークを用いたホームネットワークサービス向けハンズフリー音声インタフェース
    SODA Shimpei, NAKAMURA Masahide, MATSUMOTO Shinsuke, MATSUBARA Noriyuki, KUGATA Kouji, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Mar. 2012, 電子情報通信学会技術研究報告, Vol. 111, No. 481, pp.73-78(481(SS2011 57-82)) (481(SS2011 57-82)), Japanese
    Report scientific journal

  • Associativity-Variable Cache to Adaptively Expand Operating Voltage Margin
    JUNG Jinwook, NAKATA Yohei, OKUMURA Shunsuke, KAWAGUCHI Hiroshi, Yoshimoto Masahiko
    This paper presents a dependable cache memory for which associativity can be reconfigured dynamically. The proposed associativity-reconfigurable cache consists of pairs of cache ways. The proposed cache can dynamically enhance its reliability in the dependable mode, thereby trading off its performance. The reliability of the proposed cache can be scaled by reconfiguring its associativity. Moreover, the configuration can be chosen based upon current operating conditions. Our chip measurement results show that the proposed dependable cache possesses the scalable characteristic of reliability. Moreover, it can decrease the minimum operating voltage by 115 mV. The cycle accurate simulation shows that designing the L1, L2 caches using the proposed scheme results in 4.93% IPC loss on average. Area estimation results show that the proposed cache adds area overhead of 1.91% and 5.57% in 32-KB and 256-KB caches, respectively.
    The Institute of Electronics, Information and Communication Engineers, 19 Jan. 2012, Technical report of IEICE. ICD, 111(388) (388), 55 - 60, Japanese

  • A 75-Variable MIQP Solver Processor for Real-Time Robot Control
    NISHINO Masanori, NOGUCHI Hiroki, SHIMAI Yusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    This paper describes a low-power eight-core Mixed Integer Quadric Programming (MIQP) solver processor VLSI for real-time autonomous robot control. It features an eight-core architecture with operation-level and task-level parallel processing using speculative execution to solve a 75-variable MIQP problem within 100 ms. The VLSI, containing 12.2 M transistors and occupying 2.7×3.0 mm2 area, was designed and fabricated using 40-nm CMOS technology. It consumes 568 mW with 135 MHz operation, allowing real-time, low-power capability for a 75-variable MIQP solver.
    The Institute of Electronics, Information and Communication Engineers, 19 Jan. 2012, Technical report of IEICE. ICD, 111(388) (388), 103 - 107, Japanese

  • A 75-Variable MIQP Solver Processor for Real-Time Robot Control
    西野 允雅, 野口 紘希, 嶋井 優介, 和泉 慎太郎, 川口 博, 吉本 雅彦
    本研究では,自律ロボット制御のための実時間混合整数2次計画(MIQP)問題ソルバープロセッサVLSIを提案する.実時間でのMIQP問題求解のために,演算レベルとタスクレベルにおける2つの並列化手法を提案し,8コアによる並列処理アーキテクチャを実現した.40nmCMOSプロセスを用いて提案プロセッサの試作を行い,動作周波数135MHz,消費電力568mWにおいて75変数MIQP問題を100ms以内に求解できることを確認した.This paper describes a low-power eight-core Mixed Integer Quadric Programming (MIQP) solver processor VLSI for real-time autonomous robot control. It features an eight-core architecture with operation-level and task-level parallel processing using speculative execution to solve a 75-variable MIQP problem within 100 ms. The VLSI, containing 12.2 M transistors and occupying 2.7 × 3.0 mm2 area, was designed and fabricated using 40-nm CMOS technology. It consumes 568 mW with 135 MHz operation, allowing real-time, low-power capability for a 75-variable MIQP solver.
    12 Jan. 2012, 研究報告計算機アーキテクチャ(ARC), 2012(19) (19), 1 - 5, Japanese

  • Associativity-Variable Cache to Adaptively Expand Operating Voltage Margin
    鄭 晋旭, 中田 洋平, 奥村 俊介, 川口 博, 吉本 雅彦
    本論文では、低電圧動作時における最適なキャッシュの構成が得られる連想度可変キャッシュを提案する。連想度可変キャッシュは 2 つのキャッシュウェイをペアで構成した構造を持ち、メモリセルとして 7T/14T SRAM を使用する。それにより、連想度を可変にすることが可能となり、動作環境に応じて連想度を適切に選ぶことでキャッシュの動作マージンを拡大する。すなわち、動作環境に適したキャッシュの構成を取ることで低電圧動作時の信頼性改善が可能である。実チップの測定に基づく評価の結果、4.93% の IPC 劣化で最低動作電圧が 115mV 改善できることを確認した。また、面積評価の結果、32KB キャッシュの場合 1.91%、256KB キャッシュの場合 5.57% の面積オーバヘッドがあることを確認した。This paper presents a dependable cache memory for which associativity can be reconfigured dynamically. The proposed associativity-reconfigurable cache consists of pairs of cache ways. The proposed cache can dynamically enhance its reliability in the dependable mode, thereby trading off its performance. The reliability of the proposed cache can be scaled by reconfiguring its associativity. Moreover, the configuration can be chosen based upon current operating conditions. Our chip measurement results show that the proposed dependable cache possesses the scalable characteristic of reliability. Moreover, it can decrease the minimum operating voltage by 115 mV. The cycle accurate simulation shows that designing the L1, L2 caches using the proposed scheme results in 4.93% IPC loss on average. Area estimation results show that the proposed cache adds area overhead of 1.91% and 5.57% in 32-KB and 256-KB caches, respectively.
    12 Jan. 2012, 研究報告計算機アーキテクチャ(ARC), 2012(11) (11), 1 - 6, Japanese

  • Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure
    UMEKI Youhei, YOSHIMOTO Shusuke, AMASHITA Takurou, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    This paper presents a new 8T (8-transistor) SRAM cell layout mitigating multiple-bit upset (MBU) in a divided wordline structure. Because bitlines along unselected columns are not activated, the divided wordline structure eliminates a half-select problem and achieves low-power operation, which is often preferred for low-power / low-voltage applications. However, the conventional 8T SRAM with the divided wordline structure engenders MBUs because all bits in the same word are physically adjoining. Consequently, error correction coding (ECC) techniques are difficult to apply. This paper presents a new 8T cell layout pattern that separates internal latches in SRAM cells using both an n-well and a p-substrate. We investigated an SEU cross section of nMOS that is 3.5-4.5 times higher than that of pMOS. Using an iRoC TFIT simulator, we confirmed that the proposed 8T cell has better neutron-induced MBU tolerance. The MBU in the proposed 8T SRAM is improved by 90.70% and the MBU soft error rate (SER) is decreased to 3.46 FIT at 0.9 V when ECC is implemented. Additionally, we conducted Synopsys 3-D TCAD simulation, which indicates that the LET threshold (LETth) in single-event upset (SEU) is also improved by 66.47% in the proposed 8T SRAM by a common-mode effect.
    The Institute of Electronics, Information and Communication Engineers, 15 Dec. 2011, Technical report of IEICE. ICD, 111(352) (352), 161 - 166, Japanese

  • A 284-uW 1.85-GHz 20-Phase Oscillator Using Transfer Gate Phase Couplers
    OKUNO Keisuke, KONISHI Toshihiro, LEE Hyeokiong, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    We propose a transfer gate phase coupler for a low-power multi-phase oscillator (MPOSC). The phase coupler is an nMOS transfer gate, which does not waste charge to the ground and thus achieves low power. The proposed MPOSC can set the number of outputs to an arbitrary number. The test circuit in a 180-nm process and a 65-nm process exhibits 20 phases, including 90° different angles. The designs in a 180-nm CMOS process and a 65-nm CMOS process were fabricated to confirm its process scalability; in the respective designs, we observed 36.6% and 38.3% improvements in a power-delay products, compared with the conventional MPOSCs using inverters and nMOS latches. In a 65-nm process, the measured DNL and 3a periodjitter are, respectively, less than ±1.22° and 5.82 ps. The power is 284μW at 1.85 GHz.
    The Institute of Electronics, Information and Communication Engineers, 08 Dec. 2011, Technical report of IEICE. ICD, 111(352) (352), 149 - 154, Japanese

  • Dependability evaluation of processor using the dependable SRAM by system-level fault injection
    TAKEUCHI Yusuke, NAKATA Yohei, ITO Yasuhiro, SUGURE Yasuo, OHO Shigeru, OKUMURA Shunsuke, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    We propose a fault-injection system (FIS) that can inject faults such as read/write margin failures and soft errors into a SRAM environment. The fault case generator (FCG) generates time-series SRAM failures in 7T/14T or 6T SRAM, and the proposed device model and fault injection flow are applicable for system-level verification. For evaluation, an abnormal termination rate in vehicle engine control was adopted. We confirmed that the vehicle engine control system with the 7T/14T SRAM improves system-level dependability compared with the conventional 6T SRAM.
    The Institute of Electronics, Information and Communication Engineers, 14 Oct. 2011, IEICE technical report. Computer systems, 111(255) (255), 1 - 6, Japanese

  • A Feasibility Study of Home Services Using a Microphone Array Network
    SODA Shimpei, MATSUMOTO Shinsuke, NAKAMURA Masahide, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    The home network system (HNS), which provides value-added services by orchestrating networked home appliances, equipments and sensors, attracts great attention to realize the next-generation smart home. Implementing the location-aware services within the the HNS context is one of greatest challenges, where the appropriate services are performed based according to the location of the inhabitants. We have been studying the technologies of sound source localization and sound source separation using networked multiple microphone arrays. In this paper, we conduct a feasibility study of applying the microphone array network to the location-aware services within the HNS. Specifically, we first present three kinds of home services using illustrative examples. We then enumerate three kinds of requirements (accuracy requirement, installation requirement, user requirement), which are essential for implementing the location-aware home services using the microphone array network. In a preliminary experiment, we evaluate the accuracy requirement using an actual microphone array. Moreover, we conduct a directivity shape simulation assuming multiple arrays.
    The Institute of Electronics, Information and Communication Engineers, 14 Oct. 2011, IEICE technical report. Computer systems, 111(255) (255), 61 - 66, Japanese
    Report scientific journal

  • 局所特徴量抽出アルゴリズムのハードウェアコストと精度のトレードオフ解析
    水野孝祐, 寺地陽祐, 黒田光彦, 川口博, 吉本雅彦
    20 Jul. 2011, 画像の認識・理解シンポジウム(MIRU2011)論文集, 2011, 117 - 124, Japanese

  • Data-Intensive Sound Acquisition System with Large-scale Microphone Array
    Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    We propose a microphone array network that realizes ubiquitous sound acquisition. Several nodes with 16 microphones are connected to form a novel huge sound acquisition system, which carries out voice activity detection (VAD), sound source localization, and sound enhancement. The three operations are distributed among nodes. Using the distributed network, we produce a low-traffic data-intensive array network. To manage node power consumption, VAD is implemented. The system uses little power when speech is not active. For sound localization, a network-connected multiple signal classification (MUSIC) algorithm is used. The experimental result of the sound-source enhancement shows a signal-noise ratio (SNR) improvement of 7.75dB using 112 microphones. Network traffic is reduced by 99.11% when using 1,024 microphones.We propose a microphone array network that realizes ubiquitous sound acquisition. Several nodes with 16 microphones are connected to form a novel huge sound acquisition system, which carries out voice activity detection (VAD), sound source localization, and sound enhancement. The three operations are distributed among nodes. Using the distributed network, we produce a low-traffic data-intensive array network. To manage node power consumption, VAD is implemented. The system uses little power when speech is not active. For sound localization, a network-connected multiple signal classification (MUSIC) algorithm is used. The experimental result of the sound-source enhancement shows a signal-noise ratio (SNR) improvement of 7.75dB using 112 microphones. Network traffic is reduced by 99.11% when using 1,024 microphones.
    15 Mar. 2011, 情報処理学会論文誌, 52(3) (3), 1102 - 1113, English

  • Multiple-Bit- Upset Tolerant 8T SRAM Cell Layout with Divided Wordline Structure
    S. Yoshimoto, T. Amashita, D. Kozuwa, T. Takata, M. Yoshimura, Y. Matsunaga, H. Yasuura, H. Kawaguchi, M. Yoshimoto
    Mar. 2011, Proceedings of Silicon Errors in Logic - System Effects (SELSE), pp. 106 -111, English
    [Refereed]
    Others

  • Block-Basis On-Line BIST Architecture for Embedded SRAM Using Wordline and Bitcell Voltage Optimal Control
    Masahiro Yoshikawa, Shunsuke Okumura, Yohei Nakata, Yuki Kagiyama, Hiroshi Kawaguchi, Masahiko Yoshimoto
    A system on a chip (SOC) is becoming smaller and denser. Shrinking transistor size facilitates the integration of functionality on the chip operating at low supply voltage, although this trend lowers the silicon chip reliability. Nevertheless, it is necessary to maintain complete functionality during a long duration, even under changing environments such as temperature fluctuation and/or device wearout: Bias temperature instability must be considered as a time-varying parameter as well. Consequently, techniques that can maintain chip reliability with self-diagnosis and self-repair capabilities are required. In this paper, we propose a dependable SRAM with a built-in self-test that can diagnose and repair itself using wordline and bitcell voltage control. The proposed SRAM comprises memory blocks; each block has independent supply voltages for the wordlines and bitcells. This diagnosis and repair scheme is especially effective for faults that occur in the field. The self-testing capability is available on-line. It is completely transparent to a user, who can use the SRAM with no modification or speed degradation in the memory access protocol. A 1-Mb (64-Kb x 16 blocks) SRAM with the BIST was fabricated with a 65-nm CMOS process and verified. The area overhead is 2.8%.
    IEEE, 2011, 2011 12TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), pp. 322- 325, 322 - 325, English
    [Refereed]
    Others

  • Fault-Inject ion using Virtualized Environment for Validating Automotive Systems
    伊藤 康宏, 中田 洋平, 川口 博
    情報処理学会, Dec. 2010, 情報処理学会研究報告, 2010(4) (4), 5p, Japanese

  • Fault-Injection using Virtualized Environment for Validating Automotive Systems
    ITO Yasuhiro, NAKATA Yohei, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, SUGURE Yasuo, OHO Shigeru
    Fault Injection System: a system level co-simulation environment with fault-injection in memory access was developed. It accepted a fault scenario that includes when and where memory failures occur, and imposed SRAM access failure. A virtual bus-bridge model added in a memory bus of target system disguised SRAM access failure by intervening memory transactions Consequently, it was possible to maintain the tartget system noninvasive from modification. This approach was adopted to a validation of vehicle engine control, as a result a ignition failure occured by SRAM fault was observed
    The Institute of Electronics, Information and Communication Engineers, 22 Nov. 2010, IEICE technical report, 110(316) (316), 119 - 123, Japanese

  • An Investigation of Variation-Aware NoC Architecture
    NAKATA Yohei, TAKEUCHI Yukihiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    プロセステクノロジの微細化に伴い,LSI 設計におけるプロセスばらつきによる閾値電圧ばらつきの影響が増加している. 微細プロセスにおける NoC (Network-on-Chip) プロセッサは多くのプロセッサコアによって構成され,プロセスばらつきの影響によって個々のコアの特性が異なるという特徴を持つ.本項では NoC プロセッサにおけるプロセスばらつきの影響を考慮し,影響を抑制可能であるアーキテクチャについて検討を行う.As process technology advances, its minimum feature size decreases, which enables manufacturing with higher density and lower costs. However, technology scaling increases the threshold-voltage (Vth) variation of MOS transistors. NoC processor in an advanced process technology has many cores which have different characteristics individually. This paper shows an investigation of Variation-Aware NoC (Network-on-Chip) Architecture which enables to suppress the effect of process variation.
    情報処理学会, 11 Oct. 2010, 研究報告計算機アーキテクチャ(ARC), 2010(5) (5), 1 - 5, Japanese

  • A 58-uW Sensor Node LSI with Synchronous MAC Protocol
    S. Izumi, T. Takeuchi, T. Matsuda, H. Lee, T. Konishi, K. Tsuruda, Y. Sakai, C. Ohta, H. Kawaguchi, M. Yoshimoto
    Sep. 2010, Proceedings of Asia-aPacific Radio Science Conference (AP-RASC), English
    [Refereed]
    Others

  • 分散処理を用いた超低消費電力ネットワーク型マイクロホンアレーの研究
    祖田心平, 久賀田耕史, 高木智也, 和泉慎太郎, 野口紘希, 吉本雅彦, 川口博
    2010, 日本音響学会研究発表会講演論文集(CD-ROM), 2010

  • Parallel-Processing VLSI Architecture for Mixed Integer Linear Programming
    Hiroki Noguchi, Junichi Tani, Yusuke Shimai, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes parallel processor architecture for a mixed integer linear programming (MILP) solver to realize motion planning and hybrid system control in robot applications. It features pipeline architecture with an MILP-specific configuration and two-port SRAM. Based on the architecture, both FPGA and VLSI implementations have been done to solve sample problems including 16 variables. The FPGA implementation can reduce the power consumption to 13 W: an 85.4% reduction compared to a 3.0-GHz processor (Pentium 4; Intel Corp.). The VLSI solver further reduces the power to 6.4 W using 0.18-mu m CMOS technology.
    IEEE, 2010, 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, pp. 2362-2365, 2362 - 2365, English
    [Refereed]
    Others

  • Yukihiro Takeuchi, Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto
    Although valuable, the high-quality video compression format H.264/AVC workload complicates real-time encoding. This paper describes scalable parallel processing for H.264/AVC. Macroblock (MB)-level decomposition is more scalable than conventional methods for increasing the number of multiple threads. Moreover, it presents memory bandwidth advantages. This parallel algorithm can be improved using a motion estimation algorithm that distributes the workload among threads. Complementary recursive cross search (CRCS) is used to achieve efficient video encoding using MB-level decomposition. With and without B-frames for HDTV, MB-level decomposition with CRCS can respectively increase the frame rate of the conventional method by 2.4 and 4.6 times. Furthermore, the method suppresses memory accesses despite higher processing efficiency. Results show that MB-level decomposition with CRCS is suitable for computing in the many-core processor era. © 2010 IEEE.
    2010, Proceedings of 2010 International Conference on Intelligent Control and Information Processing, ICICIP 2010, pp. 163-170(2) (2), 163 - 170, English
    [Refereed]
    Others

  • Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes an FPGA implementation which features a hardware-oriented Scale Invariant Feature Transform (SIFT) algorithm, a scalable architecture with high-speed mode and high-accuracy mode, and highly parallel datapath modules. The proposed FPGA implementation can generate a SIFT descriptor vector with 50 MHz for VGA resolution video (640 × 480 pixels) at 56 frames per second (fps). Our proposed implementation made the operating frequency and memory bandwidth a half or less than that of the conventional FPGA implementation and as a result, we achieved a system that can provide low power consumption. © 2010 IEEE.
    2010, Proceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010, pp608-611, 608 - 611, English
    [Refereed]
    Others

  • Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents a novel cache architecture using 7T/14T hybrid SRAM, which can dynamically improve its reliability with control lines. Our proposed 14T word-enhancing scheme can enhance its operating margin in word granularity by combining two words in a low-voltage mode. The proposed scheme is suitable for dynamic voltage and frequency scaling (DVFS). In a 65-nm process, it can reduce the minimum operation voltage (Vmin) to 0.5 V, which is 42% and 21% lower, respectively, than the conventional 6T SRAM and the cache word-disable scheme. The respective power reductions are 90% and 65%. Copyright 2010 ACM.
    2010, Proceedings of the International Symposium on Low Power Electronics and Design, pp. 219-224, 219 - 224, English
    [Refereed]
    Others

  • A 34.7-mW Quad-Core MIQP Solver Processor for Robot Control
    Hiroki Noguchi, Junichi Tani, Yusuke Shimai, Masanori Nishino, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We propose a quad-core mixed integer quadric programming (MIQP) solver processor. The MIQP solver is applicable to hybrid control systems including real-time control robotics. Using multi-core architecture, fixed-point calculations, and branch-and-bound method with high-dispersion performance while processing a 50-variable problem, our design achieves 34.7-mW operation at a frequency of 52 MHz in measurement results, although a core 2 duo PC requires 3.16 GHz to solve it as rapidly.
    IEEE, 2010, IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010, English
    [Refereed]
    Others

  • 7T SRAM Enabling Low-Energy Simultaneous Block Copy
    Shunsuke Okumura, Shusuke Yoshimoto, Kosuke Yamaguchi, Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper proposes 7T SRAM which realizes block-level simultaneous copying feature. The proposed SRAM can be used for data transfer between local memories such as checkpoint data storage and transactional memory. The 1-Mb SRAM is comprised of 32-kb blocks, in which 16-kb data can be copied in 33.3 ns at 1.2V. The proposed scheme reduces energy consumption in copying by 92.7% compared to the conventional read-modify-write manner.
    IEEE, 2010, IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010, Dig. Tech. Papers, English
    [Refereed]
    Others

  • A 58-μW Single-Chip Sensor Node Processor Using Synchronous MAC Protocol
    IZUMI Shintaro, TAKEUCHI Takashi, MATSUDA Takashi, LEE Hyeokjong, KONISHI Toshihiro, TSURUDA Koh, SAKAI Yasuharu, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko
    In this paper, we propose a single-chip ultra low-power sensor node processor with a synchronous media access control (MAC). It is comprised of a transceiver, i8051 micro processor, and dedicated MAC processor. The test chip occupies 3x3mm^2 in a 180-nm CMOS process, including 1.38M transistors. The power is 58.0μW under a network environment.
    The Institute of Electronics, Information and Communication Engineers, 24 Sep. 2009, IEICE technical report, 109(214) (214), 141 - 145, Japanese

  • Yusuke Shimai, Junichi Tani, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We propose a high-speed mixed integer quadratic programming (MIQP) solver on an FPGA. The MIQP solver can be applied to various optimizing applications including real-time robot control. In order to rapidly solve the MIQP problem, we implement reusing a first solution (first point), pipeline architecture, and multi-core architecture on the single FPGA. By making use of them, we confirmed that 79.5% of the cycle times are reduced, compared with straightforward sequential processing. The operating frequency is 67 MHz, although a core 2 duo PC requires 3.16 GHz in processing the same size problem. The power consumption of the MIQP solver is 4.2 W. © 2009 IEEE.
    2009, Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09, pp. 447-450, 447 - 450, English
    Others

  • Variable bandwidth digital bandpass filter for cognitive radio
    TSURUDA Koh, IZUMI Shintaro, LEE Hyeokjong, TAKEUCHI Takashi, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    本論文ではコグニティブ無線向け可変帯域ディジタルBPF(Band-Pass Filter)を用いたベースバンドプロセッサを提案する.BPFにDA(Distributed Arithmetic)アルゴリズムを適応することで,内蔵するSRAMのデータを書き換えるだけでBPFの特性(チャネル中心周波数とバンド幅)を変化させることが可能となる.試作したベースバンドプロセッサではバンド幅を40kHzから240kHzまで10kHz単位で変化させることが可能である.CMOS 180nmプロセスで設計し,電源電圧1.8Vで消費電力は13.5mWであった.
    The Institute of Electronics, Information and Communication Engineers, 15 Oct. 2008, IEICE technical report, 108(253) (253), 137 - 141, Japanese

  • Shintaro Izumi, Koh Tsuruda, Takashi Takeuchi, Hyeokjong Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto
    Concomitantly with the progress of wireless communications, cognitive radio has attracted attention as a solution for depleted frequency bands. Cognitive radio is suitable for wireless sensor networks because it reduces collisions and thereby achieves energy-efficient communication. To make cognitive radio practical, we propose a low-power multi-resolution spectrum sensing (MRSS) architecture that has flexibility in sensing frequency bands. The conventional MRSS scheme consumes much power and can be adapted only slightly to process scaling because it comprises analog circuits. In contrast, the proposed architecture carries out signal processing in a digital domain and can detect occupied frequency bands at multiple resolutions and with low power. Our digital MRSS module can be implemented in 180-nm and 65-nm CMOS processes using Verilog-HDL. We confirmed that the processes respectively dissipate 9.97 mW and 3.45 mW.
    IEEE, 2008, 2010 FOURTH INTERNATIONAL CONFERENCE ON SENSOR TECHNOLOGIES AND APPLICATIONS (SENSORCOMM), pp. 39-44, 39 - 44, English
    [Refereed]
    Others

  • A VGA 30-fps Real-Time Optical-Flow Processor Core for Video Recognition
    ISHIHARA Hajime, MIYAMA Masayuki, MURACHI Yuichiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, MATSUDA Yoshio
    This paper proposes an optical-flow processor for real-time video recognition. This processor is based on the Pyramidal Lucas and Kanade (PLK) algorithm and has smaller chip size, higher resolution and higher accuracy than conventional ones. Introduction of search range limitation and Carman filter to the original algorithm improves accuracy by 0.59°and reduces the processor hardware cost by 96%. Furthermore, the window interleaving and window overlap methods can reduce the necessary clock frequency of the processor by 70%. The proposed processor can handle a VGA 30-fps image sequence with 332MHz clock frequency. The core size and power consumption in 90-nm process technology are estimated as 3.5×3.0mm^2 and 600mW, respectively.
    The Institute of Electronics, Information and Communication Engineers, 06 Dec. 2007, IEICE technical report, 107(382) (382), 65 - 70, Japanese

  • Circuits Technologies for Wireless Power Transmission Sheet with Organic FETs and Plastic MEMS Switches
    KAWAGUCHI Hiroshi, TAKAMIYA Makoto, SEKITANI Tsuyoshi, MIYAMOTO Yoshio, NOGUCHI Yoshiaki, SOMEYA Takao, SAKURAI Takayasu
    Design innovations to overcome the shortcomings of a wireless power transmission sheet made with plastic MEMS switches and OFET for printable low-cost electronics are shown. The mixed circuits of MEMS switches and OFETs with two different frequencies reduce the number of coil sheets form 2 to 1. OFET level-shifters, with the current-source loads with enhancement/depletion mixed threshold voltages realized by controlling the back-gate voltage, bridge the operation voltage gap between silicon VLSIs(below 5V) and OFETs/MEMS(above 40V).
    The Institute of Electronics, Information and Communication Engineers, 19 Jul. 2007, IEICE technical report, 107(163) (163), 153 - 158, Japanese

  • Circuits technologies for wireless power transmission sheet with organic FETs and plastic MEMS switches
    川口 博, 高宮 真, 関谷 毅
    映像情報メディア学会, Jul. 2007, ITE technical report, 31(34) (34), 153 - 158, Japanese

  • A Real-Time Optical-Flow Processor and its Evaluation System Using an FPGA Board
    ISHIHARA Hajime, MIYAMA Masayuki, YAMAMOTO Ryo, FUKUYAMA Yuki, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, MATSUDA Yoshio
    This paper proposes an optical-flow processor architecture for real-time video recognition based on the Pyramidal Lucas & Kanade (PLK) algorithm. This processor is implemented on an FPGA to verify function and performance of the processor. The FPGA processor is able to handle a QCIF-30 image sequence. A real-time evaluation system including the FPGA processor is also constructed. The evaluation system can capture image, calculate its optical flow, and display the optical flow on the image in real-time.
    The Institute of Electronics, Information and Communication Engineers, 08 Jun. 2007, IEICE technical report, 107(94) (94), 1 - 6, Japanese

  • A-3-11 A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing
    Iguchi Yusuke, Noguchi H., Fujiwara H., Morita Y., Nii K., Kawaguchi H., Yoshimoto M.
    The Institute of Electronics, Information and Communication Engineers, 07 Mar. 2007, Proceedings of the IEICE General Conference, 2007, 101 - 101, Japanese

  • A-21-26 Improvement of Counter-based Broadcasting for Wireless Sensor Networks using Timer Control
    IZUMI S., MATSUDA T., MIKAMI S., KAWAGUCHI H., OHTA C., YOSHIMOTO M.
    The Institute of Electronics, Information and Communication Engineers, 07 Mar. 2007, Proceedings of the IEICE General Conference, 2007, 417 - 417, Japanese

  • C-12-42 A Two-port SRAM for Real-Time Video Processor Saving 53% of Bitline Power with Majority Logic and Data-Bit Reordering
    Fujiwara Hidehiro, Nii K., Miyakoshi J., Murachi Y., Noguchi H., Morita Y., Kawaguchi H., Yoshimoto M.
    The Institute of Electronics, Information and Communication Engineers, 07 Sep. 2006, Proceedings of the Society Conference of IEICE, 2006(2) (2), 103 - 103, Japanese

  • Dynamic Voltage Scaling in an Elastic Pipeline and Its Application to an H.264/AVC HDTV Video Decoder LSI
    KAWAKAMI Kentaro, TAKEMURA Jun, KURODA Mitsuhiko, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    We propose an elastic pipeline that can apply dynamic voltage scaling (DVS) to hardwired logic circuits. In order to demonstrate its feasibility, a hardwired H.264/AVC HDTV decoder is designed as a real-time application. The designed decoder reduces 48% of execution cycles for H.264 HDTV decoding. In case of DVS is applied with this reduced cycles, the proposed decoder achieves a power reduction of 50% in a 90-nm process technology, compared to the conventional clock-gating scheme.
    Information Processing Society of Japan (IPSJ), 08 Jun. 2006, IPSJ SIG Notes, 2006(62) (62), 31 - 36, Japanese

  • 有機トランジスタとプラスチックアクチュエータを集積化したフレキシブルな点字ディスプレイ向けの回路技術
    KAWAGUCHI Hiroshi, TAKAMIYA Makoto, SEKITANI Takeshi, KATO Yusaku, SOMEYA Takao, SAKURAI Takayasu
    Organic FETs (OFETs) are integrated with actuators, and a Braille sheet display is demonstrated. A newly developed back-gated OFETs SRAM and the circuits technology for the Braille sheet display to enhance speed, yield and lifetime are presented, which will be essential for future large-area electronics made with OFETs.
    The Institute of Electronics, Information and Communication Engineers, May 2006, 電子情報通信学会技術研究報告, ICD2006-22、1-6ページ(71) (71), 1 - 6, Japanese
    [Refereed]
    Others

  • BS-10-5 Long-lived network by considering production tolerance or sensor node
    Yoshino Hironori, Aonishi Takafumi, Ichien Masumi, Matsuda Takashi, Ohta Chikara, Kawaguchi Hiroshi, Yoshimoto Masahiko
    The Institute of Electronics, Information and Communication Engineers, 08 Mar. 2006, Proceedings of the IEICE General Conference, 2006(2) (2), "S - 72"-"S-73", Japanese

  • Low Leakage-power FPGA Design using Zigzag Power-gating, Dual V_/V_
    and Micro-V_
    -Hopping
    TRAN Canh Quang, KAWAGUCHI Hiroshi, SAKURAI Takayasu
    映像情報メディア学会, 26 Jan. 2006, ITE technical report, 30(8) (8), 19 - 24, Japanese

  • Low Leakage-power FPGA Design using Zigzag Power-gating, Dual V_/V_
    and Micro-V_
    -Hopping
    TRAN Canh Quang, KAWAGUCHI Hiroshi, SAKURAI Takayasu
    Low-power FPGA architecture is proposed based on fine-grained V_
    control scheme called micro-V_
    -hopping. Four Configurable Logic Blocks (CLB) are grouped into one block where V_
    is shared. In the micro-V_
    -hopping scheme, V_
    of each block is varied between the higher V_
    (V_) and the lower V_
    (V_) spatially and temporally to achieve lower power without performance degraded. A level shifter that has less contention is proposed. The FPGA also incorporates Zigzag power-gating scheme, special care has been taken to cope with sneak leakage path problem. To reduce power dissipated by interconnect, low swing interconnect is adopted. The proposed FPGA is fabricated using 0.35μm CMOS technology together with the conventional fixed-V_
    FPGA. Measurement shows that the dynamic power can be reduced by 86% when the required speed is half of the maximum achievable speed. Simulation using 90nm CMOS technology shows that a leakage power reduction of 95% can be achieved, when the proposed method is used. Area overhead of the proposed FPGA is 2%.
    The Institute of Electronics, Information and Communication Engineers, 19 Jan. 2006, Technical report of IEICE. ICD, 105(569) (569), 19 - 24, Japanese

  • Low-Power High-Speed Reduced-Clock-Swing Flip-Flops Based on Contention Reduction Techniques
    YAZID Muhammad, KAWAGUCHI Hiroshi, SAKURAI Takayasu
    VLSIの消費電力の多くの部分を消費しているクロックシステムの低消費電力化は重要な課題である。本論文では、低クロック電圧振幅を用いて低電力化するために必須である、低クロック振幅対応のフリップフロップ回路を提案する。従来と違い、基板バイアスに頼らず、contentionを減少させるメカニズムを導入することにより、低クロック振幅での遅延と消費電力が、それぞれ、従来比30%、20%小さいことがシミュレーションにより示された。
    The Institute of Electronics, Information and Communication Engineers, 16 Dec. 2005, IEICE technical report, 105(476) (476), 19 - 24, English

  • A Sheet-Type Scanner Based on a 3D Stacked Organic-Transistor Circuit with Double Word-line and Double Bit-line Structure
    KAWAGUCHI Hiroshi, IBA Shingo, KATO Yusaku, SEKITANI Tsuyoshi, SOMEYA Takao, SAKURAI Takayasu
    Double word-line and bit-line structure in an organic FET-based sheet-type scanner is described. This structure reduces the line delay by a fact or of 5, and the power by a factor of 7. To realize the structure in a pixel array, 3D stacked organic FETs are manufactured. The active leakage is reduced by a dynamic serially connected decoder.
    The Institute of Electronics, Information and Communication Engineers, 19 May 2005, Technical report of IEICE. ICD, 105(95) (95), 19 - 21, Japanese

  • Integration of organic transistors and organic photodiodes : Applications to sheet image scanners
    IBA Shingo, KATO Yusaku, SEKITANI Tsuyoshi, KAWAGUCHI Hiroshi, SAKURAI Takayasu, SOMEYA Takao
    映像情報メディア学会, 03 Mar. 2005, ITE technical report, 29(18) (18), 19 - 22, Japanese

  • 有機エレクトロニクス 有機材料採用の曲げられるスキャナ回路技術で市販品並みの高速動作
    染谷 隆夫, 桜井 貴康, 川口 博
    電子ペーパーや有機ELパネル,太陽電池,人工皮膚など,有機半導体を利用した曲げられるエレクトロニクス素子の研究開発が活発だ。この分野に新たなデバイスが加わった。東京大学が開発したシート型スキャナである。
    日経BP社, 28 Feb. 2005, 日経エレクトロニクス, (894) (894), 123 - 132, Japanese

  • Integration of organic transistors and organic photodiodes : Applications to sheet image scanners
    IBA Shingo, KATO Yusaku, SEKITANI Tsuyoshi, KAWAGUCHI Hiroshi, SAKURAI Takayasu, SOMEYA Takao
    We have manufactured a large-area, flexible, and lightweight sheet image scanner on plastic films, for the first time, integrating high-quality organic transistors and organic photodetectors. The present image-capturing device with organic transistors are shock-resistant and potentially very inexpensive since they requires no optics or moving parts, and therefore suitable for mobile electronics.
    The Institute of Electronics, Information and Communication Engineers, 24 Feb. 2005, Technical report of IEICE. OME, 104(688) (688), 19 - 22, Japanese

  • Cut-and-Paste Organic FET Customized ICs for Application to Artificial Skin
    SOMEYA Takao, KAWAGUCHI Hiroshi, SAKURAI Takayasu
    The Concept of cut-and-paste customization is introduced for the first time in designing integrated circuits based on organic field effect transistors. The customized integrated circuits are manufactured by comprising a pressure-sensor array, row decoders, and column selectors to read out pressure information over large area. The pressure-sensor array formed on a plastic film and pressure-sensitive conductive rubber are mechanically flexible, and therefore suitable for electronic artificial skin application. The physical cut-and-paste procedure is employed to make scalable circuits, which are manufactured by cutting a part of the circuits and pasting it to another circuit with a connecting plastic tape. The integrated circuits are designed with a standard SPICE simulator and layout design tool, and the operation is confirmed by measurement.
    The Institute of Electronics, Information and Communication Engineers, 14 May 2004, ISSCC Dig. of Tech. Papers, Feb. 2004, 104(67) (67), 37 - 40, Japanese

  • Large-area, flexible sensors for electronic artificial skins : A new class of applications of organic transistors
    SOMEYA Takao, SAKURAI Takayasu, KAWAGUCHI Hiroshi, SEKITANI Tsuyoshi
    応用物理学会, 10 May 2004, 應用物理, 73(5) (5), 610 - 614, Japanese

  • Frequency-Voltage Cooperative CPU Poser Control : A Design Rule and Its Application by Feedback Prediction
    TOYAMA Keisuke, MISAKA Satoshi, AISAKA Kazuo, ARITSUKA Toshiyuki, UCHIYAMA Kunio, ISHIBASHI Koichiro, KAWAGUCHI Hiroshi, SAKURAI Takayasu
    周波数-電圧協調型電力制御(FV制御)は,ソフトウェアの負荷情報を利用してハードウェアの動作条件を動的に制御するため,プログラム動作時のCPUの消費電力を低減する効果が大きい.本論文では,このFV制御の方式と効果を解析的に導いて,必要となる周波数決定のルールを得,フィードバック型のアルゴリズムを提案してそれによるFV制御の実装について示した.2種の周波数と電圧によってMPEG-4及びMP3デコーダに適用し,動作時のCPU消費電力の72%を削減している.更に,FV制御の開始時を低周波数とするCool-Start方式で電力削減効果が向上することを示した.
    The Institute of Electronics, Information and Communication Engineers, 01 Apr. 2004, The Transactions of the Institute of Electronics,Information and Communication Engineers., 87(4) (4), 452 - 461, Japanese

  • Statistical Leakage Current Reduction by Self - Timed Cut - Off Scheme for High Leakage Environments
    XU Yingxue, CHOI Jin-Hyeok, MIYAZAKI Takayuki, KAWAGUCHI Hiroshi, SAKURAI Takayasu
    This paper describes a statistical leakage current reduction scheme that can reduce leakage current even if the chip is in an active mode. The scheme utilizes a self-timed cut-off switch that puts a given block into a sleep mode if the block is not used for a certain number of cycles. The effectiveness of the proposed scheme is verified by an 8-bit RISC microprocessor using Verilog HDL, and demonstrated by a 64bit carry look-ahead adder fabricated with dual-V SOI technology.
    Information Processing Society of Japan (IPSJ), 23 Oct. 2003, 情報処理学会研究報告システムLSI設計技術(SLDM), 2003(105) (105), 157 - 162, Japanese

  • Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's
    ROBERT SALIBA Fayez, MIN Kyeong-Sik, KAWAGUCHI Hiroshi, KANDA Kouichi, SAKURAI Takayasu
    A new Row-by-Row Dynamic Source-line Voltage control (RRDSV) scheme is proposed to reduce the active leakage as well as the stand-by leakage in SRAM. By dynamically controlling the source-line voltage of cells row by row, the cell leakage through inactive cells can be reduced by two orders of magnitude. Moreover, the bit-line leakage through pass transistors can be completely cut off. This leakage reduction is caused from the cooperation of reverse body-to-source biasing and Drain Induced Barrier Lowering (DIBL) effects. A test chip has been fabricated using 0.18-um triple-well CMOS technology to verify the data retention capability of this RRDSV scheme. The minimum retention voltage in the RRDSV is measured to be reduced by more than 60mV, when shielding metal is inserted to protect the memory cell nodes from bit-line coupling noise. It can reduce the leakage by another 50% in addition to the reduction by two orders of magnitude.
    The Institute of Electronics, Information and Communication Engineers, 17 Oct. 2003, Technical report of IEICE. DSP, 103(380) (380), 71 - 76, English

  • Statistical Leakage Current Reduction by Self-Timed Cut-Off Scheme for High Leakage Environments
    XU Yingxue, CHOI Jin-Hyeok, MIYAZAKI Takayuki, KAWAGUCHI Hiroshi, SAKURAI Takayasu
    This paper describes a statistical leakage current reduction scheme that can reduce leakage current even if the chip is in an active mode. The scheme utilizes a self-timed cut-off switch that puts a given block into a sleep mode if the block is not used for a certain number of cycles. The effectiveness of the proposed scheme is verified by an 8-bit RISC microprocessor using Verilog HDL, and demonstrated by a 64bit carry look-ahead adder fabricated with dual-V_ SOI technology.
    The Institute of Electronics, Information and Communication Engineers, 17 Oct. 2003, Technical report of IEICE. DSP, 103(380) (380), 65 - 70, English

  • A-3-11 Fast Block-Wise V_
    -Hopping Scheme
    Xu Ying xue, Miyazaki Takayuki, Kawaguchi Hiroshi, Sakurai Takayasu
    The Institute of Electronics, Information and Communication Engineers, 10 Sep. 2003, Proceedings of the Society Conference of IEICE, 2003, 61 - 61, English

  • A Low Leakage Power Digital Circuit Scheme for Digital Appliance : Zigzag SCCMOS Scheme
    MIYAZAKI Takayuki, MIN Kyeong-Sik, KAWAGUCHI Hiroshi, SAKURAI Takayasu
    Zigzag Super Cut-off CMOS is proposed as clock-gating replacement in deep sub-micron era. The proposed scheme is applicable in V_
    less than 1-V, since it uses only low threshold voltage transistor in power switches. By inserting the power switches in zigzag, the serially connected transistors in power switch of Super Cut-off CMOS is avoided without any overstresses. Wake-up time of less than 1/3 the clock cycle and three-orders-of-magnitude leakage current reduction are confirmed. A method for switching the higher-man-V_
    and lower-than-VSs voltage is proposed. Furthermore, it is shown that the proposed scheme is applicable to a selector circuit.
    The Institute of Electronics, Information and Communication Engineers, 17 Jul. 2003, Technical report of IEICE. ICD, 103(216) (216), 1 - 6, Japanese

  • A O.5V, 400MHz, V_
    -Hopping Processor with Zero-V_ FD-SOI Technology
    KAWAGUCHI Hiroshi, KANDA Kouichi, NOSE Koichi, HATTORI Sadaaki, ANTONO Danardono Dwi, YAMADA Daisuke, MIYAZAKI Takayuki, INAGAKI Kenichi, HIRAMOTO Toshiro, SAKURAI Takayasu
    A 0.5V, 400MHz, V_
    -Hopping processor with zero-V_ FD-SOI was designed and evaluated. The logic blocks use zero-V_ cells for high speed and the memory and register file use high V_
    , high V_ cells to suppress leakage current. The test chip consumes 3.5mW at 0.5V V_
    . Software cooperation scheme namely V_
    -Hopping was shown to be effective in reducing power in leakage dominant era.
    The Institute of Electronics, Information and Communication Engineers, 22 May 2003, Technical report of IEICE. ICD, 103(89) (89), 55 - 58, Japanese

  • 1.27Gb/s/pin, 3mW/pin Wireless Superconnect (WSC) Interface Scheme
    KANDA Kouichi, ANTONO Danardono Dwi, ISHIDA Koichi, KAWAGUCHI Hiroshi, KURODA Tadahiro, SAKURAI Takayasu
    A low-power high-speed chip-to-chip interface scheme is described having a density of 625pins/mm^2. The interface utilizes capacitively coupled contactless minipads, return-to-V_
    /2 signaling and sense amplifying flip-flops. The measured test chip fabricated in 0.35μm CMOS delivers up to 1.27Gb/s/pin at 3mW/pin.
    The Institute of Electronics, Information and Communication Engineers, 21 May 2003, Technical report of IEICE. ICD, 103(88) (88), 19 - 22, Japanese

  • Design Rule and its Algorithm for Frequency-Voltage Cooperative Power Control
    AISAKA Kazuo, ARITSUKA Toshiyuki, MISAKA Satoshi, TOYAMA Keisuke, UCHIYAMA Kunio, ISHIBASHI Koichiro, KAWAGUCHI Hiroshi, SAKURAI Takayasu
    Frequency-voltage cooperative power control (FVC) is considered a powerful method to reduce the power consumption because of its dynamic feature. The authors first give a minute evaluation with the two-to-one frequency rule already proposed, under the restriction of operation voltage limit. Then we give an design algorithm for an FVC system which includes the decision criteria for the number of(F, V) sets to be prepared in the FVC system.
    The Institute of Electronics, Information and Communication Engineers, 16 Aug. 2002, Technical report of IEICE. ICD, 102(274) (274), 49 - 52, Japanese

  • Design Rule and its Algorithm for Frequency-Voltage Cooperative Power Control
    AISAKA Kazuo, ARITSUKA Toshiyuki, MISAKA Satoshi, TOYAMA Keisuke, UCHIYAMA Kunio, ISHIBASHI Koichiro, KAWAGUCHI Hiroshi, SAKURAI Takayasu
    Frequency-voltage cooperative power control (FVC) is considered a powerful method to reduce the power consumption because of its dynamic feature. The authors first give a minute evaluation with the two-to-one frequency rule already proposed, under the restriction of operation voltage limit. Then we give an design algorithm for an FVC system which includes the decision criteria for the number of (F, V) sets to be prepared in the FVC system.
    The Institute of Electronics, Information and Communication Engineers, 16 Aug. 2002, Technical report of IEICE. SDM, 102(272) (272), 49 - 52, Japanese

  • Design Rule for Frequency-Voltage Cooperative Power Control and Its Application to an MPEG-4 Decoder
    AISAKA Kazuo, ARITSUKA Toshiyuki, MISAKA Satoshi, TOYAMA Keisuke, UCHIYAMA Kunio, ISHIBASHI Koichiro, KAWAGUCHI Hiroshi, SAKURAI Takayasu
    Frequency-voltage cooperative power control (FVC) is considered a powerful method to reduce the power consumption of a program, because it utilizes the information of software loads dynamically. The authors first show through a mathematical analysis that a two-to-one rule is sufficient to prepare the frequency sets with a FVC system. Then we show an experimental result that FVC feedback control on an MPEG-4 video decoder can reduce the power to one-fourth.
    The Institute of Electronics, Information and Communication Engineers, 18 Jul. 2002, Technical report of IEICE. ICD, 102(234) (234), 13 - 16, Japanese

  • Coupling-driven bus design for low-power application-specific systems
    YAMADA Daisuke, SHIN Youngsoo, KAWAGUCHI Hiroshi, SAKURAI Takayasu
    In modern embedded systems including communication and multimedia applications, large fraction of power is consumed during memory access. Thus, buses should be designed and optimized to consume reasonable power while delivering sufficient performance. In this paper, we address a bus ordering problem for low-power application-specific systems. A heuristic algorithm is proposed to determine the order in a way that effective lateral component of capacitance is reduced, thereby reducing the power consumed by buses. Experimental results for various examples indicate that the average power saving from 30% to 46.7% depending on capacitance components can be obtained without any circuit overhead.
    The Institute of Electronics, Information and Communication Engineers, 17 Aug. 2001, Technical report of IEICE. ICD, 101(266) (266), 1 - 8, Japanese

  • Cooperative Voltage Scaling (CVS) and V_
    -Hopping among OS, Applications and Hardware for Low-Power Real-Time Embedded Systems
    KAWAGUCHI Hiroshi, ZHANG Gang, LEE Seongsoo, SHIN Youngsoo, SAKURAI Takayasu
    Power-efficient design of real-time embedded systems becomes more important as system functionality is increasingly realized by software. This paper presents a cooperative power-optimization scheme among an operation system, application programs and hardware. This scheme is shown to reduce the power to less than 1/4 compared to the conventional rate-monotonic scheduling with fixed supply voltage. The power saving is achieved without degrading the real-time features.
    The Institute of Electronics, Information and Communication Engineers, 18 May 2001, Technical report of IEICE. ICD, 101(85) (85), 59 - 65, Japanese

  • V_-hopping Scheme in Low-Voltage and Low-Power Processors
    NOSE Koichi, HIRABAYASHI Masayuki, KAWAGUCHI Hiroshi, LEE Seongsoo, SAKURAI Takayasu
    A threshold voltage hopping (V_-hopping) scheme is proposed where V_ is dynamically controlled through software depending on a workload. V_-hopping is shown to reduce the power to 18% of the fixed low-V_ circuits in 0.5V supply voltage regime for multimedia applications. A positive back-gate bias scheme within V_-hopping is presented for the high-performance and low-voltage processors. The measurement result shows about 90% power reduction is possible by using V_-hopping.
    The Institute of Electronics, Information and Communication Engineers, 18 May 2001, Technical report of IEICE. ICD, 101(85) (85), 67 - 73, Japanese

  • Abnormal Leakage Suppression (ALS) scheme for low standby current SRAMs
    KANDA Kouichi, MINH Nguyen Duc, KAWAGUCHI Hiroshi, SAKURAI Takayasu
    Abnormal Leakage Suppression (ALS) scheme is proposed to repair standby current errors in SRAMs. By introducing Leakage sensors, shift registers and fuses, the ALS senses 1μA of abnormal leakage, isolates the memory cell from V_
    lines and thus suppresses abnoamal leakage current. A 64Kbit test SRAM is fabricated and the effectiveness is demonstrated. The area overhead is 7%.
    The Institute of Electronics, Information and Communication Engineers, 05 Apr. 2001, Technical report of IEICE. ICD, 101(1) (1), 21 - 25, Japanese

  • Boosted Gate MOS (BGMOS) : Leakage-Free Circuits by Device/Circuit Cooperation Scheme
    INUKAI T., TAKAMIYA M., NOSE K., KAWAGUCHI H., SAKURAI T., HIRAMOTO T.
    An increase of stand-by power is one of the most important issues in future LSI devices. In this paper, a new device/circuit cooperation scheme, Boosted Gate MOS(BGMOS), is proposed to achieve leakage free circuits. In the proposed scheme, CMOS circuits consist of MOSFETs with low V_ and ultra-thin oxide to obtain hign speed and low voltage operation. On the other hand, low leakage devices with hign V_ and thick oxide are inserted in series with CMOS circuits and driven by higher gate voltage to achieve extremely low stand-by power while maintaining small area penalty. The application of the proposed scheme to other components such as SRAMs is also discussed.
    The Institute of Electronics, Information and Communication Engineers, 18 Aug. 2000, IEICE technical report. Electron devices, 100(266) (266), 1 - 8, Japanese

  • A CMOS Scheme for 0.5V Supply Voltage with Pico-Ampere Standby Current
    KAWAGUCHI Hiroshi, NOSE Kouichi, SAKURAI Takayasu
    If a VLSI should be operated in 0.5V〜0.8V VDD range for low-power consumption, the threshold voltage of MOSFET's VTH, should be well below 0.5V to turn the MOSFET's on.The low VTH like 0.1V〜0.2V, however, causes 10nA order subthreshold leakage current per logic gate in a standby mode, which leads to 10mA order standby current for one million gate VLSI's.In this paper, super cut-off CMOS(SCCMOS) circuit is proposed to overcome this situation.With the SCCMOS, an operation is possible under 0.5V〜0.8V VDD with 0.1V〜0.2V VTH and at the same time pA order standby current per logic gate can be achieved.
    The Institute of Electronics, Information and Communication Engineers, 23 Jul. 1998, Technical report of IEICE. ICD, 98(195) (195), 45 - 49, English

  • A CMOS Scheme for 0.5V Supply Voltage with Pico-Ampere Standby Current
    KAWAGUCHI Hiroshi, NOSE Kouichi, SAKURAI Takayasu
    If a VLSI should be operated in 0.5V-0.8V VDD range for low-power consumption, the threshold voltage of MOSFET's, VTH, should be well below 0.5V to turn the MOSFET's on. The low VTH like 0.1V-0.2V, however, causes 10nA order subthreshold leakage current perlogic gate in a standby mode, which leads to 10mA order standby current for one million gate VLSI's. In this paper, super cut-off CMOS(SCCMOS)circuit is proposed to overcome this situation. With the SCCMOS, an operation is possible under 0.5V-0.8V VDD with 0.1V-0.2V VTH and at the same time pA order standby current per logic gate can be achieved.
    The Institute of Electronics, Information and Communication Engineers, 23 Jul. 1998, Technical report of IEICE. SDM, 98(193) (193), 45 - 49, English

  • Dynamic Leakage Cut-off Scheme for Low-Voltage SRAM's
    KAWAGUCHI Hiroshi, ITAKA Yasuhito, SAKURAI Takayasu
    A 0.5V SRAM circuit scheme is proposed and fabricated which speeds up the conventional low-voltage SRAM by a factor of 2.5 without applying excessive voltage to gate oxide and with maintaining the subthreshold leakage current in a tolerable level. N-and P-well bias voltage are dynamically changed to V_
    and V_ respectively for selected memory cells, while the well bias of the dormant memory cells are kept 2V_
    and -V_
    .
    The Institute of Electronics, Information and Communication Engineers, 19 Jun. 1998, IEICE technical report. Electron devices, 98(117) (117), 1 - 4, Japanese

■ Lectures, oral presentations, etc.
  • 光電式容積脈波法による脈拍測定の低消費電力化手法
    WATANABE Kento, IZUMI Shintaro, YANO Yuji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    ヘルスケア・医療情報通信技術研究会(MICT), Jan. 2019, Japanese, 電子情報通信学会, 東京都千代田区明治大学駿河台キャンパス, Domestic conference
    Oral presentation

  • ウェアラブルデバイスのための心拍変動モニタリングにおけるサンプリングレート低減手法
    NISHIKAWA Yuki, IZUMI Shintaro, YANO Yuji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    第35回「センサ・マイクロマシンと応用システム」シンポジウム, Oct. 2018, Japanese, 電気学会 センサ・マイクロマシン部門, 北海道札幌市 札幌市民交流プラザ, Domestic conference
    Poster presentation

  • ウェアラブルデバイスのための圧電素子を用いたマルチモーダルな心血管情報の計測
    OKANO Takaaki, IZUMI Shintaro, KATSUURA Takumi, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    第34回「センサ・マイクロマシンと応用システム」シンポジウム,01am2-PS-135,広島,2017年11月1日, Nov. 2017, Japanese, Domestic conference
    Oral presentation

  • 消化管内への留置を目的とした飲み込み型デバイスの検討
    NAKAMURA Ryota, IZUMI Shintaro, KAWAGUCHI Hiroshi, OHTA Hidetoshi, YOSHIMOTO Masahiko
    第34回「センサ・マイクロマシンと応用システム」シンポジウム,31pm3-PS-46,広島,2017年10月31日, Oct. 2017, Japanese, Domestic conference
    Oral presentation

  • ノイズフィードバック技術を用いたウェアラブル向け容量結合型心電センサ
    NAGASATO Yuki, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    IEICEソサイエティ大会, 2017年9月12-15日,東京, Sep. 2017, Japanese, Domestic conference
    Oral presentation

  • 選択的ソース線駆動方式を用いた画像処理プロセッサ向け低消費電力28nm FD-SOI 8TデュアルポートSRAM
    MORI Haruki, NAKAGAWA Tomoki, KITAHARA Yuki, KAWAMOTO Yuta, TAKAGI Kenta, YOSHIMOTO Shusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    LSIとシステムのワークショップ2017 ポスターセッション, 東京, 2017年5月, May 2017, Japanese, Domestic conference
    Oral presentation

  • マイクロ波ドップラーセンサを用いた車両走行中の心拍計測手法
    MATSUNAGA DAICHI, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO
    電子情報通信学会総合大会,B-20-10, 名古屋, 2017年3月22日., Mar. 2017, Japanese, 名古屋, Domestic conference
    Oral presentation

  • プロセスばらつき耐性を有する低電圧動作STT-MRAM向けカウンターベース読出し回路
    UMEKI YOHEI, YANAGIDA KOUJI, YOSHIMOTO SHUSUKE, IZUMI SHINTARO, YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, TSUNODA KOJI, SUGII TOSHIHIRO
    LSIとシステムのワークショップ2016, May 2016, Japanese, Domestic conference
    Poster presentation

  • 消化管内に留置可能な飲み込み型生体センサー
    IZUMI Shintaro, NAKAMURA Ryota, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    電子情報通信学会総合大会, Mar. 2016, Japanese, 福岡, Domestic conference
    Oral presentation

  • ヘルスケアデバイスから見た材料科学への期待
    KAWAGUCHI Hiroshi
    日本化学会第96春季年会, Mar. 2016, Japanese, 京都, Domestic conference
    [Invited]
    Invited oral presentation

  • Process variation tolerant counter base read circuit for low-voltage operating STT-MRAM
    UMEKI Yohei, YANAGIDA Koji, KUROTSU Hiroaki, KITAHARA Hiroto, MORI Haruki, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, YOSHIMOTO Shusuke, TSUNODA Koji, SUGII Toshihiro
    DATE EMS Workshop, Mar. 2016, English, Dresden,Germany, International conference
    Poster presentation

  • Analysis of Soft Error Propagation considering Masking Effects on Re-convergent Path
    KIMI Yuta, MATSUKAWA Go, YOSHIDA Shuhei, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    IEEE Asian Test Symposium (ATS), Nov. 2015, English, International conference
    Oral presentation

  • A 298-fJ/writecycle 650-fJ/readcycle 8T Three-Port SRAM in 28-nm FD-SOI Process Technology for Image Processor
    MORI Haruki, NAKAGAWA Tomoki, KITAHARA Yuki, KAWAMOTO Yuta, TAKAGI Kenta, YOSHIMOTO Shusuke, IZUMI Shintaro, Nii Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    IEEE Custom Integrated Circuits Conference (CICC), Sep. 2015, English, International conference
    Oral presentation

  • 時間デジタル変換器を用いたIOサイズ8bitAD変換器
    OKUNO Keisuke, 小西恵大, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi
    LSIとシステムのワークショップ2015 ポスターセッション, May 2015, Japanese, 小倉, Domestic conference
    Poster presentation

  • ウェアラブル心電図計測SoC
    TANAKA Yoshito, NAKAI Yozaburo, KAWAMOTO Yuta, OKUNO Keisuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, KIMURA Hiromitsu, MURAMOTO Kyoji, FUCHIKAMI Takaaki, FUJIMORI Yoshikazu, YOSHIMOTO Masahiko
    LSIとシステムのワークショップ2015, May 2015, Japanese, 小倉, Domestic conference
    Poster presentation

  • 6T4C型低消費電力不揮発メモリ
    KITAHARA Hiroto, NAKAGAWA Tomoki, IZUMI Shintaro, TANAGIDA Kouji, KITAHARA Yuki, YOSHIMOTO Shusuke, UMEKI Yohei, MORI Haruki, KAWAGUCHI Hiroshi, KIMURA Hiromitsu, MURAMOTO Kyoji, FUCHIKAMI Takaaki, FUJIMORI Yoshikazu, YOSHIMOTO Masahiko
    LSIとシステムのワークショップ2015, May 2015, Japanese, 小倉, Domestic conference
    Poster presentation

  • 温度補償回路を用いた高速セットリングADPLL
    奥野 圭祐, 正木 何奈, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO
    第37回アナログRF研究会, Dec. 2014, Japanese, Domestic conference
    Oral presentation

  • 低消費電力貼り付け型センサのためのテンプレートマッチングを用いたロバスト心拍抽出手法の開発
    中井 陽三郎, IZUMI SHINTARO, 中野 将尚, 山下 顕, 藤井 貴英, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO
    第31回「センサ・マイクロマシンと応用システム」シンポジウム, Oct. 2014, Japanese, Domestic conference
    Oral presentation

  • 動作環境変動に応じて動的に動作マージンを拡大する自律制御キャッシュ
    KIMI YUTA, NAKATA YOHEI, OKUMURA SYUNSUKE, JUNG Jinwook, 澤田 卓也, 利川 托, NAGATA MAKOTO, 中野 博文, 藪内 誠, 藤原 英弘, 新居 浩二, 河合 浩行, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO
    LSIとシステムのワークショップ2014 ポスターセッション, May 2014, Japanese, 小倉, Domestic conference
    Poster presentation

  • 磁性変化型メモリの書き込み高速化メモリアーキテクチャ
    森 陽紀, 柳田 晃司, 梅木 洋平, 吉本秀輔, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO, 角田 浩司, 杉井 寿博
    LSIとシステムのワークショップ2014 ポスターセッション, May 2014, Japanese, 電子情報通信学会集積回路研究専門委員会, 小倉, Domestic conference
    Poster presentation

  • 温度補償回路を用いた高速セットリングADPLL
    正木 何奈, 奥野 圭祐, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO
    LSIとシステムのワークショップ2014 ポスターセッション, May 2014, Japanese, 電子情報通信学会集積回路研究専門委員会, 小倉, Domestic conference
    Poster presentation

  • 一括コピー・比較が可能なSRAMを用いた低遅延デュアルコアロックステップアーキテクチャ
    吉田 周平, 松川 豪, 中田 洋平, 木美 雄太, 勝 康夫, 下澤 晶史, 於保 茂, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO
    LSIとシステムのワークショップ2014 ポスターセッション, May 2014, Japanese, 電子情報通信学会集積回路研究専門委員会, 小倉, Domestic conference
    Poster presentation

  • 38μAウェアラブル生体情報計測プロセッサ
    中井 陽三郎, IZUMI SHINTARO, 山下 顕, 中野 将尚, 藤井 貴英, 小西 恵大, KAWAGUCHI HIROSHI, 木村 啓明, 丸元 共治, 渕上 貴昭, 藤森 敬和, 中嶋 宏, 志賀 利一, YOSHIMOTO MASAHIKO
    LSIとシステムのワークショップ2014 ポスターセッション, May 2014, Japanese, Domestic conference
    Poster presentation

  • ロバストな瞬時心拍抽出機能を有する低消費電力ウェアラブルヘルスケアシステム
    IZUMI Shintaro, NAKANO Masanao, YAMASHITA Ken, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    第14回計測自動制御学会システムインテグレーション部門講演会SI2013, Dec. 2013, Japanese, 神戸市, Domestic conference
    [Invited]
    Invited oral presentation

  • 読出しビット線振幅制限機構及び読み出し加速回路を備えた8T SRAM
    UMEKI Yohei, YOSHIMOTO Shusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference
    Poster presentation

  • 車載ECUのSRAMへの故障注入による自動車制御システムの挙動評価
    FUJIKAWA Asuka, TAKEUCHI Yusuke, NAKATA Yohei, 伊藤 康宏, 勝 康夫, 於保 茂, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference
    Poster presentation

  • 核反応シミュレータを用いたソフトエラー率導出ツール及び耐マルチビットエラー6T SRAM
    YOSHIMOTO Shusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference
    Poster presentation

  • ラウドコンピュータを用いたディペンダブルプロセッサの大規模故障注入評価
    MATSUKAWA Go, NAKATA Yohei, 伊藤 康宏, TAKEUTCI Yusuke, 勝 康夫, 於保 茂, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference
    Poster presentation

  • ゼロデータを利用したSTT-RAMキャッシュの低エネルギー化設計
    KIMI Yuta, JUNG Jinwook, NAKATA Yohei, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi
    LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference
    Poster presentation

  • HDTV解像度対応 実時間HOG特徴量抽出と複数物体検出を実現する43mWデュアルコアプロセッサ
    TKAGI Kenta, MIZUNO Kosuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference
    Poster presentation

  • 65nm 700-μm2 61-dB 低ジッター2次ΔΣT-D変換器
    OKUNO Keisuke, KONISHI Toshihiro, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi
    LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference
    Poster presentation

  • ウェアラブルヘルスケアシステムのための 短時間自己相関を用いた瞬時心拍検出手法
    中野将尚, 小西恵大, 和泉慎太郎, 川口博, YOSHIMOTO MASAHIKO
    電気学会センサ・マイクロマシン部門大会, Oct. 2012, Japanese, 北九州, Domestic conference
    Public symposium

  • 低電圧動作マージン拡大機能を有する連想度可変キャッシュ
    鄭晋旭, 中田洋平, 奥村俊介, 川口博, YOSHIMOTO MASAHIKO
    LSIとシステムのワークショップ 2012, May 2012, Japanese, 北九州, Domestic conference
    Poster presentation

  • プロセスばらつきを考慮したNoCアーキテクチャ
    中田洋平, 川口博, YOSHIMOTO MASAHIKO
    LSIとシステムのワークショップ 2012, May 2012, Japanese, 北九州, Domestic conference
    Poster presentation

  • 6万語彙実時間連続音声認識のための40nm, 144mW音声認識専用プロセッサの開発
    何光霽, 菅原隆伸, 藤永剛史, 宮本優貴, 野口紘希, 和泉慎太郎, 川口博, YOSHIMOTO MASAHIKO
    LSIとシステムのワークショップ 2012, May 2012, Japanese, 北九州, Domestic conference
    Poster presentation

  • 40nm 640μm2 7.2bit プロセススケーラブル・オペアンプレス時間演算型AD変換器
    小西恵大, 奥野圭祐, 和泉慎太郎, 吉本雅彦, KAWAGUCHI HIROSHI
    LSIとシステムのワークショップ 2012, May 2012, Japanese, 北九州, Domestic conference
    Poster presentation

  • 0.5V 12.9pJ/accessを実現する低電力ライトバック技術を備えた40nm 8T SRAM
    吉本秀輔, 寺田正治, 奥村俊介, 鈴木利一, 宮野信治, 川口博, YOSHIMOTO MASAHIKO
    LSIとシステムのワークショップ 2012, May 2012, Chinese, 北九州, Domestic conference
    Poster presentation

  • 温度変化を考慮したSRAMのBER導出手法の検討
    KITAHARA Yuki, KAGIYAMA Yuki, OKUMURA Shunsuke, YANAGIDA Koji, YOSHIMOTO Syusuke, NAKATA Yohei, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    電子情報通信学会総合大会, Mar. 2012, Japanese, 電子情報通信学会, 岡山市, Domestic conference
    Oral presentation

  • マイクアレイネットワークを用いたホームネットワークサービス向けハンズフリー音声インタフェース
    SODA_Shinpei, NAKAMURA_Masahide, MAtSUMOTO_Shinsuke, MATSUBARA_Noriyuki, KUGATA_Koji, 和泉 慎太郎_IZUMI_Shintaro, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko
    電子情報通信学会研究会, Mar. 2012, Japanese, 電子情報通信学会集積回路研究専門委員会, 那覇市, Domestic conference
    Oral presentation

  • ディペンダブルSRAMのためのオンライン故障診断技術の開発
    FUJIKAWA Asuka, YOSHIKAWA Masahiro, OKUMURA Shunsuke, NAKATA Yohei, KAGIYAMA Yuki, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    電子情報通信学会総合大会, Mar. 2012, Japanese, 電子情報通信学会, 岡山市, Domestic conference
    Oral presentation

  • 0.6V動作可能なハーフセレクト耐性を向上させる差動書込み技術を用いた40-nm 8T SRAM
    UMEKI_Yohei, TERADA_Masaharu, YOSHIMOTO_Syusuke, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko
    電子情報通信学会総合大会, Mar. 2012, Japanese, 電子情報通信学会, 岡山市, Domestic conference
    Oral presentation

  • 低電圧動作におけるマージン拡大機能を有する連想度可変キャッシュ
    JUNG_JinWook, NAKATA_Yohei, OKUMURA_Shunsuke, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko
    電子情報通信学会研究会, Jan. 2012, Japanese, 電子情報通信学会集積回路研究専門委員会, 東京, Domestic conference
    Oral presentation

  • 実時間ロボット制御のための75変数MIQP問題ソルバープロセッサ
    NISHINO Masanori, NOGUCHI Hiroki, SHIMAI Yusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    電子情報通信学会研究会, Jan. 2012, Japanese, 電子情報通信学会集積回路研究専門委員会, 東京, Domestic conference
    Oral presentation

  • 低電力20相出力発振回路
    OKUNO_Keisuke, KONISHI_Toshihiro, LEE_Hyeokjong, 和泉 慎太郎_IZUMI_Shintaro, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko
    電子情報通信学会研究会, Dec. 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 大阪, Domestic conference
    Oral presentation

  • マルチビットアップセット耐性及びシングルビットアップセット耐性を備えた8T SRAM セルレイアウト
    UMEKI_Yohei, YOSHIMOTO_Syusuke, AMASHITA_Takro, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko
    電子情報通信学会研究会, Dec. 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 大阪, Domestic conference
    Oral presentation

  • チップ間ばらつき及びチップ内ばらつきを抑制する基板バイアス制御回路を備えた0.42-V 576-Kb 0.15-um FD-SOI 7T/14T SRAM
    YOSHIMOTO Syusuke, YAMAGUCHI Kosuke, OKUMURA Shunsuke, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi
    電子情報通信学会研究会 (2011), Dec. 2011, Japanese, Domestic conference
    Poster presentation

  • 6万語彙実時間連続音声認識のための40nm,144mW音声認識専用プロセッサの開発
    SUGAHARA_Takanobu, HE_Guangji, FUJINAGA_Tsuyoshi, MIYAMOTO_Yuki, NOGUCHI_Hiroki, 和泉 慎太郎_IZUMI_Shintaro, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko
    デザインガイア2011, Nov. 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 宮崎市, Domestic conference
    Oral presentation

  • 故障注入技術を用いたディペンダブルSRAMを搭載するプロセッサの信頼性評価・検証
    TAKEUCHI_Yusuke, NAKATA_Yohei, ITO_Yasuhiro, SUGURE_Yasuo, OHO_Shigeru, OKUMURA_Shunsuke, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko
    コンピュータシステム研究会, Oct. 2011, Japanese, 電子情報通信学会, 神戸市, Domestic conference
    Oral presentation

  • マイクアレイネットワークを用いた宅内サービス実現可能性の検討
    SODA_Shinpei, NAKAMURA_Masahide, MAtSUMOTO_Shinsuke, MATSUBARA_Noriyuki, KUGATA_Koji, 和泉 慎太郎_IZUMI_Shintaro, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko
    コンピュータシステム研究会, Oct. 2011, Japanese, 電子情報通信学会, 神戸市, Domestic conference
    Oral presentation

  • 低電力20相出力発振回路
    OKUNO_Keisuke, KONISHI_Toshihiro, 和泉 慎太郎_IZUMI_Shintaro, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko
    LSIとシステムのワークショップ 2011, May 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference
    Poster presentation

  • 次世代知能ロボット制御のための混合整数2次計画問題(MIQP)ソルバーコアプロセッサ
    NISHINO Masanori, NOGUCHI Hiroki, TANI Junichi, SHIMAI Yusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    LSIとシステムのワークショップ 2011, May 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference
    Poster presentation

  • マルチビットアップセット耐性を備えた8T SRAMセルレイアウト
    AMASHITA_Takro, YOSHIMOTO_Syusuke, KOZUWA_Daisuke, TAKATA_Taiga, YOSHIMURA_Masayoshi, MATSUNAGA_Yusuke, YASUURA_Hiroto, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko
    LSIとシステムのワークショップ 2011, May 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference
    Poster presentation

  • ブロックデータ一括コピー機能を有する7T SRAM
    KAGIYAMA_Yuki, OKUMURA_Shunsuke, YOSHIMOTO_Syusuke, NAKATA_Yohei, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko
    LSIとシステムのワークショップ 2011, May 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference
    Poster presentation

  • フルHDTV実時間動画像認識のための低消費電力SIFT特徴量抽出プロセッサ
    TERACHI_Yosuke, MIZUNO_Kosuke, HE_Guangji, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko
    LSIとシステムのワークショップ 2011, May 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference
    Poster presentation

  • ビットエラー耐性及びソフトエラー耐性を備えたFD-SOI 7T/14T SRAM
    吉本 秀輔, 天下 卓郎, 奥村 俊介, 山口 幸介, 吉本 雅彦, 川口 博
    LSIとシステムのワークショップ 2011, May 2011, Japanese, 北九州市, Domestic conference
    Poster presentation

  • システムレベル故障注入技術によるディペンダブルメモリを搭載したプロセッサの評価・検証
    TAKEUCHI_Yusuke, NAKATA_Yohei, ITO_Yasuhiro, SUGURE_Yasuo, OHO_Shigeru, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko
    LSIとシステムのワークショップ 2011, May 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference
    Poster presentation

  • 18TデュアルポートSRAM
    YANAGIDA Koji, NOGUCHI Hiroki, OKUMURA Shunsuke, TAKAGI Tomoya, KUGATA Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    LSIとシステムのワークショップ 2011, May 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference
    Poster presentation

  • 7T/14T SRAMの細粒度制御による低電圧動作キャッシュアーキテクチャ
    JUNG JinWook, NAKATA Yohei, OKUMURA Shunsuke, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    LSIとシステムのワークショップ 2011, May 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference
    Poster presentation

  • 18TデュアルポートSRAM
    YANAGIDA Koji, NOGUCHI Hiroki, OKUMURA Shunsuke, TAKAGI Tomoya, KUGATA Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    電子情報通信学会研究会, Apr. 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 神戸市, Domestic conference
    Poster presentation

  • プロセスばらつきを考慮したNoCアーキテクチャの検討
    中田 洋平, 竹内 幸大, 川口 博, 吉本 雅彦
    情報処理学会研究報告 計算機アーキテクチャ(ARC), Oct. 2010, Japanese, Domestic conference
    Others

  • 分散処理を用いた超低消費電力 ネットワーク型マイクロホンアレーの研究
    祖田 心平, 久賀田 耕史, 高木 智也, 和泉 慎太郎, 野口 紘希, 吉本 雅彦, 川口 博
    日本音響学会2010年秋季研究発表会, Sep. 2010, Japanese, 関西大学, Domestic conference
    Poster presentation

  • マルチコアプロセッサにおけるH.264/AVC符号化処理の並列度とメモリアクセスに関する高効率実装
    中田 洋平, 竹内 幸大, 川口 博, 吉本 雅彦
    DAシンポジウム2010, Sep. 2010, Japanese, 豊橋市, Domestic conference
    Poster presentation

  • 高精度音源定位および音源分離機能を有する低消費電力ユビキタス・センサネットの開発
    TAKAGI Tomoya, 川口 博, 吉本 雅彦
    STARCフォーラム/シンポジウム2009, Aug. 2010, Japanese, Domestic conference
    Poster presentation

  • ネットワーク分散処理を用いた超低消費電力音声信号処理プロセッサ
    久賀田 耕史, 野口 紘希, 高木 智也, 祖田 心平, 吉本 雅彦, 川口 博
    STARC フォーラム/シンポジウム2010, Aug. 2010, Japanese, 横浜市, Domestic conference
    Poster presentation

  • 分散処理型ユビキ タスセンサネットワークのための超低消費電力音声処理プロセッサ
    高木 智也, 野口 紘希, 久賀田 耕史, 吉本 雅彦, 川口 博
    LSIとシステムのワークショップ 2010, May 2010, Japanese, 北九州市, Domestic conference
    Poster presentation

  • 知能ロボットのためのマルチコアMIQPソルバープロセッサのFPGA実装
    嶋井 優介, 谷 純一, 野口 紘輝, H. Kawaguchi, M. Yoshimoto
    LSIとシステムのワークショップ 2010, May 2010, Japanese, 北九州, Domestic conference
    Poster presentation

  • 大語彙連続音声認識のための並列Viterbiプロセッサアーキテクチャ
    藤永 剛史, 三浦 和夫, 野口 紘輝, 川口 博, M. Yoshimoto
    LSIとシステムのワークショップ 2010, May 2010, Japanese, 北九州, Domestic conference
    Poster presentation

  • ワイヤレスセンサネットワークのためのΔ-Σ変調とデジタルアシストを用いたイメージ信号除去に関する研究
    小西 恵大, 李 赫鍾, 和泉 慎太郎, 竹内 隆, H. Kawaguchi, 吉本 雅彦
    LSIとシステムのワークショップ 2010, May 2010, Japanese, 北九州市, Domestic conference
    Poster presentation

  • 7T/14T SRAMを内部メモリに用いたマルチコアプロセッサアーキテクチャ
    中田 洋平, 川口 博, 吉本 雅彦
    LSIとシステムのワークショップ 2010, May 2010, Japanese, 北九州市, Domestic conference
    Poster presentation

  • "時刻同期型MACプロトコルを用いる6.4μWシングルチップセンサーノードLSI,
    和泉 慎太郎, 李 赫鍾, 小西 恵大, 岡 顕久, 松田 隆志, 竹内 隆, 太田 能, 川口 博, 吉本 雅彦
    LSIとシステムのワークショップ 2010, May 2010, Japanese, 北九州市, Domestic conference
    Poster presentation

  • 時刻同期型MACプロトコルを用いる58-uWワンチップセンサノードプロセッサ
    和泉 慎太郎, 竹内 隆, 松田 隆志, 李 赫鍾, 小西 恵大, 鶴田 嵩, 酒井 康晴, 川口 博, 太田 能, 吉本 雅彦
    電子情報通信学会技術研究報告, Oct. 2009, Japanese, 電子情報通信学会, Domestic conference
    Poster presentation

  • 高精度音源定位および音源分離機能を有する低消費電力ユビキタス・センサネットの開発
    高木 智也, 川口 博
    STARCフォーラム/シンポジウム2009 学生ポスターセッション, Aug. 2009, Japanese, 株式会社 半導体理工学研究センター(STARC), 新横浜国際ホテル, Domestic conference
    Poster presentation

  • 7T/14T SRAMを内部メモリに用いたマルチコアプロセッサアーキテクチャの検討
    中田 洋平, 川口 博, 吉本 雅彦
    DAシンポジウム2009, Aug. 2009, Japanese, 情報処理学会 システムLSI設計技術研究会, 石川, Domestic conference
    Poster presentation

  • 全整数計画問題のソルバーのFPGA実装
    谷 純一, 野口 紘希, 嶋井 優介, 川口 博, 吉本 雅彦
    LSIとシステムのワークショップ2009 ポスターセッション, May 2009, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, Domestic conference
    Poster presentation

  • 時間同期型MACプロトコルの垂直統合設計によるセンサノードVLSIの低消費電力化
    和泉 慎太郎, 松田 隆志, 竹内 隆, 川口 博, 太田 能, 吉本 雅彦
    LSIとシステムのワークショップ2009 ポスターセッション, May 2009, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, Domestic conference
    Poster presentation

  • 高信頼性モードを有する7T/14TディペンダブルSRAM,
    奥村 俊介, 藤原 英弘, 井口 友輔, 野口 紘希, 川口 博, 吉本 雅彦
    LSIとシステムのワークショップ2009 ポスターセッション, May 2009, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, Domestic conference
    Poster presentation

  • リアルタイム20,000語彙連続音声認識のためのGMMプロセッサのFPGA実装
    三浦 和夫, 野口 紘希, 藤永 剛史, 川口 博, 吉本 雅彦
    LSIとシステムのワークショップ2009 ポスターセッション, May 2009, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, Domestic conference
    Poster presentation

  • マイクロホンアレイ・センサネットワークによるインテリジェント・ユビキタス音声処理システムと,その低消費電力LSIの提案,
    高木 智也, 野口 紘希, 吉本 雅彦, 川口 博
    LSIとシステムのワークショップ2009 ポスターセッション, May 2009, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, Domestic conference
    Poster presentation

  • チップ間ばらつき補正機能を有する基板バイアス制御を用いた0.42V動作486-kb FD-SOI SRAM,
    山口 幸介, 藤原 英弘, 竹内 隆, 大竹 優, 吉本 雅彦, 川口 博
    LSIとシステムのワークショップ2009 ポスターセッション, May 2009, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, Domestic conference
    Poster presentation

  • カラム線制御回路を用いた0.56V動作128-kb10T小面積SRAM,
    吉本 秀輔, 井口 友輔, 奥村 俊介, 藤原 英弘, 野口 紘希, 新居 浩二, 川口 博, 吉本 雅彦
    LSIとシステムのワークショップ2009 ポスターセッション, May 2009, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, Domestic conference
    Poster presentation

  • 低電圧・低消費電力SRAM
    川口 博
    IEEE Solid-State Circuits Society Kansai Chapter Technical Seminar, Dec. 2008, Japanese, Domestic conference
    Invited oral presentation

  • 発話推定を用いたインテリジェント認識システムの低消費 電力化技術
    野口 紘希, 川口 博
    半導体理工学研究センター(STARC)フォーラム/シンポジウム学生ポ スターセッション, Jul. 2008, Japanese, パシフィコ横浜, Domestic conference
    Poster presentation

  • 発話推定を用いたインテリジェント認識システムの低消費電力化技術
    NOGUCHI Hiroki, KAWAGUCHI Hiroshi
    STARCフォーラム/シンポジウム2008 学生ポスターセッション, Jul. 2008, Japanese, 半導体理工学研究センター, 横浜, Domestic conference
    Poster presentation

  • 動的電源電圧/周波数制御によるフレームバッファSRAM内蔵型H.264 AVCデコーダの低消費電力化
    SAKATA Yoshinori, NAKATA Youhei, KAWAKAMI Kentaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    第11回システムLSIワークショップ ポスタセッション, Nov. 2007, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, Domestic conference
    Poster presentation

  • 長波帯標準電波を用いた低電力センサノードのための垂直統合設計
    OTAKE Yu, ICHIEN Masumi, TAKEUCHI Takashi, GION Akihiro, MIKAMI Shinji, FUJIWARA Hidehiro, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko
    第11回システムLSIワークショップ ポスタセッション, Nov. 2007, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, Domestic conference
    Poster presentation

  • 超並列画像処理プロセッサ応用任意位置任意サイズ矩形データの1サイクルアクセスが可能なメモリアーキテクチャ
    KAMINO Tetsuya, MIYAKOSHI Junichi, MURACHI Yuichiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    第11回システムLSIワークショップ ポスタセッション, Nov. 2007, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, Domestic conference
    Poster presentation

  • サブ100mW H.264 MP@L4.1 HDTV解像度対応 整数画素精度動き検出プロセッサコア
    MIZUNO Kosuke, MIYAKOSHI Junichi, MURACHI Yuichiro, HAMAMOTO Masaki, IINUMA Takahiro, ISHIHARA Tomokazu, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    第11回システムLSIワークショップ ポスタセッション, Nov. 2007, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, Domestic conference
    Poster presentation

  • VGA 30fps実時間動画像認識応用オプティカルフロープロセッサコア
    MURACHI Yuichiro, FUKUYAMA Yuki, YAMAMOTO Ryo, MIYAKOSHI Junichi, KAWAGUCHI Hiroshi, ISHIHARA Hajime, MIYAMA Masayuki, MATSUDA Yoshio, 吉本 雅彦
    第11回システムLSIワークショップ ポスタセッション, Nov. 2007, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, Domestic conference
    Poster presentation

  • H.264 MP@L4.1エンコーダLSIのためのHDTV解像度対応適応的階層探索動き検出アルゴリズム
    印 芳, MURACHI Yuichiro, HAMAMOTO Masaki, IINUMA Takahiro, ISHIHARA Tomokazu, 李 将充, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    第11回システムLSIワークショップ ポスタセッション, Nov. 2007, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, Domestic conference
    Poster presentation

  • DVS環境下での小面積・低電圧動作8T SRAMの設計-32nm世代以降で8Tセルが小面積・低電圧動作を同時に実現
    MORITA Yasuhiro, FUJIWARA Hidehiro, NOGUCHI Hiroki, IGUCHI Yusuke, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    第11回システムLSIワークショップ ポスタセッション, Nov. 2007, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, Domestic conference
    Poster presentation

  • ビット線電力を削減する;動画像処理応用 10T 非プリチャージ 2-port SRAM
    IGUCHI Yusuke, NOGUCHI Hiroki, OKUMURA Syunsuke, FUJIWARA Hidehiro, MORITA Yasuhiro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    VDEC LSIデザイナーフォーラム2007(若手の会)ポスターセッション, Sep. 2007, Japanese, 東京大学大規模集積システム設計教育研究センター, 北海道, Domestic conference
    Poster presentation

  • ワイヤレスセンサネットワークのためのタイマ制御によるカウンターベースブロードキャスティング方式の改良
    IZUMI Shintaro, MATSUDA Takashi, MIKAMI Shinji, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko
    2007年電子情報通信学会総合大会, Mar. 2007, Japanese, 電子情報通信学会, 名古屋, Domestic conference
    Oral presentation

  • ビット線電力を8割削減する動画像処理応用 10T非プリチャージ2-port SRAM
    IGUCHI Yusuke, NOGUCHI Hiroki, FUJIWARA Hidehiro, MORITA Yasuhiro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    2007年電子情報通信学会総合大会, Mar. 2007, Japanese, 電子情報通信学会, 名古屋, Domestic conference
    Oral presentation

  • Design Solutions for a Multi-Object Wireless Power Transmission Sheet Based on Plastic Switches
    TAKAMIYA Makoto, SEKITANI Takeshi, MIYAMOTO Yoshio, NOGUCHI Yoshiaki, KAWAGUCHI Hiroshi, SAKURAI Takayasu, SOMEYA Takao
    IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), Feb. 2007, English, IEEE, San Francisco, USA, International conference
    Oral presentation

  • A Large-area Flexible Wireless Power Transmission Sheet Using Printed Plastic MEMS Switches and Organic Field-effect Transistors
    SEKITANI Takeshi, TAKAMIYA Makoto, NOGUCHI Yoshiaki, S. NAKANO, KATO Yusaku, K. HIZU, KAWAGUCHI Hiroshi, SAKURAI Takayasu, SOMEYA Takao
    IEEE International Electron Devices Meeting Digest of Technical Papers (IEDM), Dec. 2006, English, IEEE, San Francisco, USA, International conference
    Oral presentation

  • (Invited) Flexible Braille Sheet Display with Organic FETs and Plastic Actuators
    TAKAMIYA Makoto, SEKITANI Takeshi, KATO Yusaku, KAWAGUCHI Hiroshi, SOMEYA Takao, SAKURAI Takayasu
    International Display Workshops (IDW), Dec. 2006, English, Ootsu city JAPAN, International conference
    [Invited]
    Invited oral presentation

  • 超並列画像処理のための、任意位置・水平垂直連続複数画素を同時アクセスできるメモリアーキテクチャ
    ISHIHARA Tomokazu, MIYAKOSHI Junichi, MURACHI Yuichiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    第10回システムLSIワークショップ ポスタセッション, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference
    Poster presentation

  • 消費電力を50%削減する動的電圧/周波数スケーリング型H.264 Main Profile@Level 4ビデオデコーダLSI
    KAWAKAMI Kentaro, KURODA Mitsuhiko, SAKATA Yoshinori, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    第10回システムLSIワークショップ ポスタセッション, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference
    Poster presentation

  • 実時間動画像認識応用スケーラブルオプティカルフロープロセッサ
    FUKUYAMA Yuuki, YAMAMOTO Ryo, MIYAKOSHI Junichi, KATAGIRI Tadayoshi, MINEGISHI Noriyuki, KAWAGUCHI Hiroshi, MIYAMA Masayuki, IMAMURA Kosuke, HASHIMOTO Hideo, YOSHIMOTO Masahiko
    第10回システムLSIワークショップ ポスタセッション, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference
    Poster presentation

  • ワイヤレスセンサーネットワーク応用キャリアセンス機能を持つ433MHz帯、356-uW電圧増幅器
    OTAKE Yu, MIKAMI Shinji, TAKEUCHI Takashi, ICHIEN Masumi, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko
    第10回システムLSIワークショップ ポスタセッション, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference
    Poster presentation

  • ワイヤレスセンサーネットワークにおける送信電力制御による送信効率劣化が消費電力モデルに与えるネガティブインパクト
    MIKAMI Shinji, TAKEUCHI Takashi, OTAKE Yu, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko
    第10回システムLSIワークショップ ポスタセッション, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference
    Poster presentation

  • ビット線電力を53%削減できる実時間動画像処理応用2ポートSRAM
    FUJIWARA Hidehiro, NII Koji, MIYAKOSHI Junichi, MURACHI Yuichiro, MORITA Yasuhiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    第10回システムLSIワークショップ ポスタセッション, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference
    Poster presentation

  • しきい値電圧ばらつきを克服したDVS環境下における0.3V動作SRAMの開発
    NOGUCHI Hiroki, MORITA Yasuhiro, FUJIWARA Hidehiro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    第10回システムLSIワークショップ ポスタセッション, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference
    Poster presentation

  • Stacked-Chip Implementation of On-Chip Buck Converter for Power-Aware Distributed Power Supply Systems
    ONIZUKA Kohei, KAWAGUCHI Hiroshi, TAKAMIYA Makoto, SAKURAI Takayasu
    IEEE Asian Solid-State Circuits Conference Proceedings of Technical Papers (A-SSCC), Nov. 2006, English, IEEE, Hangzhou, China, International conference
    Oral presentation

  • 800-μW H.264 Baseline-Profile対応動き検出プロセッサIP
    IINUMA Takahiro, MIYAKOSHI Junichi, MURACHI Yuichiro, MATSUNO Tetsuro, HAMANOTO Masaki, ISHIHARA Tomokazu, KAWAGUCHI Hiroshi, MIYAMA Masayuki, YOSHIMOTO Masahiko
    第10回システムLSIワークショップ ポスタセッション, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference
    Poster presentation

  • Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications
    ONIZUKA Kohei, KAWAGUCHI Hiroshi, TAKAMIYA Makoto, T. KURODA, SAKURAI Takayasu
    Proceedings of IEEE Custom Integrated Circuits Conference (CICC), Sep. 2006, English, IEEE, San Jose, USA, International conference
    Oral presentation

  • (Invited) Low Power and Flexible Braille Sheet Display with Organic FET's and Plastic Actuators
    TAKAMIYA Makoto, SEKITANI Takeshi, KATO Yusaku, KAWAGUCHI Hiroshi, SOMEYA Takao, SAKURAI Takayasu
    Proceedings of IEEE International Conference on IC Design and Technology (ICICDT), May 2006, English, Italy, International conference
    Oral presentation

  • 動的電圧制御環境下における0.3-V 動作64-kb SRAM
    MORITA Yasuhiro, FUJIWARA Hidehiro, NOGUCHI Hiroki, KAWAKAMI Kentaro, MIYAKOSHI Junichi, MIKAMI Shinji, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    2006年電子情報通信学会総合大会;AS-2-2, Mar. 2006, Japanese, 電子情報通信学会, 東京都, Domestic conference
    Oral presentation

  • 動的電圧制御環境下における0.3-V 動作64-kb SRAM
    森田 泰弘, 藤原 英弘, 野口 紘希, 川上 健太郎, 宮越 純一, 三上 真司, 新居 浩二, 川口 博, 吉本 雅彦
    電子情報通信学会総合大会, Mar. 2006, Japanese, 東京, Domestic conference
    Oral presentation

  • センサノードの製造バラツキを考慮したネットワーク可用時間改善の一検討
    YOSHINO Hironori, AONISHI Takafumi, ICHIEN Masumi, MATSUDA Takashi, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    2006年電子情報通信学会総合大会;BS-10-5, Mar. 2006, Japanese, 電子情報通信学会, 東京都, Domestic conference
    Oral presentation

  • Long-lived network by considering production trelance of sensor node
    YOSHINO Hironori, AONISHI Takafumi, ICHIEN Masumi, MATSUDA Takashi, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    電子情報通信学会総合大会, Mar. 2006, Japanese, Tokyo, Domestic conference
    Oral presentation

  • Evaluation of GIT Routing Considering Aggregation Ratio in Sensor Networks
    AONISHI Takafumi, YOSHINO Hironori, MIKAMI Shinji, OHTA Chikara, KAWAGUCHI Hiroshi, YOHIMOTO Masahiko
    電子情報通信学会技術研究報告, Oct. 2005, Japanese, 新潟, Domestic conference
    Oral presentation

  • Impact on impedance mismatch of output power control for wireless sensor nodes
    MIKAMI Shinji, TAKEUCHI Takashi, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    電子情報通信学会ソサイエティ大会, Sep. 2005, Japanese, 北海道大学, Domestic conference
    Oral presentation

  • 二重ワード線と二重ビット線を用いた3次元積層シート型スキャナ
    川口 博, 伊庭 信吾, 加藤 祐作, 関谷 毅, 染谷 隆夫, 桜井 貴康
    電子情報通信学会技術研究報告, May 2005, Japanese, 神戸, Domestic conference
    Oral presentation

■ Affiliated Academic Society
  • ACM

  • IEEE

■ Research Themes
  • 川口 博
    科学研究費補助金/基盤研究(B), Apr. 2018 - Mar. 2021, Principal investigator
    Competitive research funding

  • 省電力AIエンジンと異種エンジン統合クラウドによる人工知能プラットフォーム
    川口 博
    国立研究開発法人産業技術総合研究所, IoT推進のための横断技術開発プロジェクト, 2017, Principal investigator
    Competitive research funding

  • 省電力AIエンジンと異種エンジン統合クラウドによる人工知能プラットフォーム
    川口 博
    IoT推進のための横断技術開発プロジェクト, 2016, Principal investigator
    Competitive research funding

  • 川口 博
    科学研究費補助金/基盤研究(B), 2008, Principal investigator
    Competitive research funding

  • A research on silicon nano-devices for single-electron, quantum, CMOS integrated circuits operating at room temperature
    HIRAMOTO Toshiro, SAKURAI Takayasu, SARAYA Takuya
    Japan Society for the Promotion of Science, Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (A), The University of Tokyo, 2004 - 2007
    This research aims at a new concept of integrate circuit in which new functional devices utilizing single-electron/quantum effect and conventional CMOS devices are merged operating at room temperature. At first, the fabrication process of single-electron transistors was developed. The world largest peak-to-valley current ratios of Coulomb blockade oscillations and negative differential conductance at room temperature were successfully obtained. Furthermore, the precise control of the peak position of the Coulomb blockade oscillations was achieved for the first time in single-hole transistors which have very small quantum dots. The unique characteristics originate from large quantum energy spacing in the quantum dot. Next, the integration of single-electron transistors operating at room temperature was pursued. The process conditions were finely tuned and finally, the single-electron transistors operating at room temperature were successfully integrated for the first time. Moreover, analog pattern matching circuits were fabricated by integrating single-electron transistors and their operations were demonstrated at room temperature.

  • 有機トランジスタ駆動による点字ディスプレイの試作研究
    染谷 隆夫, 桜井 貴康, 関谷 毅, 川口 博
    日本学術振興会, 科学研究費助成事業, 萌芽研究, 東京大学, 2005 - 2006
    本研究は、有機トランジスタの駆動回路を用いた点字ディスプレイを試作することを目的としている。点字の表示部には導電性高分子のアクチュエータを活用し、オール・プラスティックの点字ディスプレイを実現することをねらいとしている。 今年度は、柔らかいアクチュエータと電気回路が同時にプラスティック・フィルム上に集積可能であることを世界に先駆けて示し、有機トランジスタで超薄型の点字ディスプレイを試作して、その動作原理実験に成功した。点字ディスプレイのプロトタイプは、実効表示面積が4x4平方センチメートル、1文字は合計6点(2x3)からなり、全部で24文字分の点字で構成される。有機トランジスタは、ポリエチレンナフタレート(PEN)もしくはポリイミドといったプラスティック・フィルムの上に製造されている。表示部の厚みは1mm、重さは5gである。 有機トランジスタ駆動回路の軽量性、可とう性、耐衝撃性を利用して、携帯性に優れる点字ディスプレイを実現し、目の不自由な方が電車で単庫本を広げて読むように手軽に読書ができる技術として供することをねらいとする。

  • 吉本 雅彦
    科学研究費補助金/基盤研究(A), 2006
    Competitive research funding

  • 太田 能
    科学研究費補助金/基盤研究(C), 2006
    Competitive research funding

  • 川口 博
    科学研究費補助金/若手研究(B), 2005, Principal investigator
    Competitive research funding

■ Industrial Property Rights
  • 低電圧動作キャッシュメモリ
    YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 中田 洋平, 奥村 俊介, 鄭 晋旭
    特願2012-267445, 06 Dec. 2012, 大学長, 特許6024897, 21 Oct. 2016
    Patent right

  • 半導体メモリおよびプログラム(韓国)
    YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 藤原 英弘, 奥村 俊介
    10-2010-7016180, 07 Jan. 2009, TLO, 10-1569540, 10 Nov. 2015
    Patent right

  • メモリセルアレイを用いたIDチップ
    YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 奥村 俊介
    特願2010-219910, 29 Sep. 2010, 大学長, 特許5499365, 20 Mar. 2014
    Patent right

  • データ一括比較処理回路、データ一括比較処理方法およびデータ一括比較プログラム
    YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 奥村 俊介
    特願2010-219902, 29 Sep. 2010, 大学長, 特許5488920, 07 Mar. 2014
    Patent right

  • キャッシュメモリとそのモード切替方法
    YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 中田 洋平
    特願2009-189603, 18 Aug. 2009, 大学長, 特許5397843, 01 Nov. 2013
    Patent right

  • 共有キャッシュメモリとそのキャッシュ間のデータ転送方法
    YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 藤原 英弘, 奥村 俊介
    特願2009-082997, 30 Mar. 2009, 大学長, 特許5311309, 12 Jul. 2013
    Patent right

  • 半導体メモリのハーフセレクト防止セル配置
    YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 藤原 英弘, 奥村 俊介
    特願2009-000012, 04 Jan. 2009, 大学長, 特許5298373, 28 Jun. 2013
    Patent right

  • 画像処理用メモリ
    YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 宮越 純一, 村地勇一郎
    特願2007-298743, 18 Nov. 2007, 大学長, 特許5261694, 10 May 2013
    Patent right

  • 半導体メモリのメモリセル間のデータコピー方法
    YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 藤原 英弘, 奥村 俊介
    特願2009-082996, 30 Mar. 2009, 大学長, 特許5256534, 02 May 2013
    Patent right

  • 半導体メモリおよびプログラム
    YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 藤原 英弘, 奥村 俊介
    特願2009-548936, 07 Jan. 2009, TLO, 特許5196449, 15 Feb. 2013
    Patent right

  • 不良メモリセルの予知診断アーキテクチャーと予知診断方法
    YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 藤原 英弘, 奥村 俊介
    特願2009-082998, 30 Mar. 2009, 大学長, 特許5187852, 01 Feb. 2013
    Patent right

  • 半導体記憶装置
    YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 藤原 英弘, 森田 泰弘
    特願2006-061644, 07 Mar. 2006, TLO, 特許5119489, 02 Nov. 2012
    Patent right

  • 半導体メモリおよびプログラム SEMICONDUCTOR MEMORY AND PROGRAM
    YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 藤原 英弘, 奥村 俊介
    US12,809,684, 07 Jan. 2009, TLO, 8,238,140, 07 Aug. 2012
    Patent right

  • 画像処理装置
    YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 宮越 純一, 村地 勇一郎, 濱本 真生, 飯沼 隆弘, 石原 朋和
    特願2007-298142, 16 Nov. 2007, 大学長, 特許5020029, 22 Jun. 2012
    Patent right

  • センサネットワークにおける無線トランシーバー用電圧増幅器
    YOSHIMOTO MASAHIKO, OHTA CHIKARA, KAWAGUCHI HIROSHI, 三上 真司
    特願2007-035223, 15 Feb. 2007, 大学長, 特許5019362, 22 Jun. 2012
    Patent right

  • センサネットワークシステム及びメディアアクセス制御方法
    YOSHIMOTO MASAHIKO, OHTA CHIKARA, KAWAGUCHI HIROSHI, 一圓 真澄
    特願2006-279761, 13 Oct. 2006, 大学長, 特許4919204, 10 Feb. 2012
    Patent right

  • データ送信スケジューリング方法およびそれを用いたセンサネットワークシステム
    YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, OHTA CHIKARA, 三上 真司
    特願2006-279760, 13 Oct. 2006, 大学長, 特許4863069, 18 Nov. 2011
    Patent right

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