IZUMI Shintaro

Graduate School of Science, Technology and Innovation / Department of Science, Technology and InnovationAssociate Professor

Research Areas

  • Life sciences / Biomedical engineering

Award

  • Jan. 2024 IEEE 42nd International Conference on Consumer Electronics, Best Student Poster Award, Wearable Perspiration Characteristic Sensor Using Bi-Directional Driver Circuit
    R. Takamatsu, S. Izumi, H. Kawaguchi

  • Nov. 2023 電気学会 第40回「センサ・マイクロマシンと応用システム」シンポジウム, 優秀ポスター発表賞, マイクロ波ドップラーセンサを用いた非接触生体認証
    高橋 宏太, 和泉 慎太郎, 川口 博

  • Oct. 2020 看護理工学学会, 看護理工学学会奨励賞, 情報通信機器を活用した総合周産期母子医療センター 夜勤シフトにおける助産師の滞在場所と滞在時間の分析
    西川 美樹, 齋藤 いずみ, 大滝 千文, 和泉 慎太郎

  • Sep. 2019 電子情報通信学会ヘルスケア・医療情報通信技術研究専門委員会, ヘルスケア・医療情報通信技術研究賞 優秀研究賞, 光電式容積脈波法を用いた脈拍測定の低消費電力化手法
    渡辺 健斗, 和泉 慎太郎, 矢野 祐二, 川口 博, 吉本 雅彦

  • Jun. 2019 看護理工学会, 研究奨励賞, 産科混合病棟における看護職の滞在場所と滞在時間
    齋藤 いずみ, 和泉 慎太郎, 大滝 千文, 岩佐 由美, 大澤 佳代

  • May 2019 電子情報通信学会, LSIとシステムのワークショップ2019 優秀ポスター賞, 有機トランジスタと薄膜抵抗を集積したシート型計装アンプの開発と生体センサへの応用
    杉山 真弘, 植村 隆文, 近藤 雅哉, 秋山 実邦子, 難波 直子, 井上 由美, 吉本 秀輔, 和泉 慎太郎, 関谷 毅

  • 2018 電子情報通信学会, 電子情報通信学会ELEX Best Paper Award, A low power, VLSI object recognition processorusing Sparse FIND Feature for 60fps HDTV resolution video
    Matsukawa Go, Kodamda Taisuke, Nishizumi Yuri, Kajihara Koichi, Nakanishi Chikako, IZUMI Shintaro, KAWAGUCHI Hiroshi, Goto Toshio, Kato Takeo, YOSHIMOTO Masahiko
    Official journal

  • Sep. 2017 IEEE International Workshop on Machine Learning for Signal Processing (MLSP), Sep. 2017., Best Student Paper Award, A Layer-Block-Wise Pipeline For Memory And Bandwidth Reduction In Distributed Deep Learning
    MORI Haruki, YOUKAWA Tetsuya, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, INOUE Atsuki
    International society

  • Dec. 2016 IEEE International Conference on Electronics, Circuits, and Systems (ICECS), IEEE ICECS 2016 Best Paper Award, Dec. 2016, An Low-Energy 8T Dual-Port SRAM for Image Processor with Selective Sourceline Drive Scheme in 28-nm FD-SOI Process Technology
    MORI Haruki, NAKAGAWA Tomoki, KITAHARA Yuki, KAWAMOTO Yuta, TAKAGI Kenta, YOSHIMOTO Shusuke, IZUMI Shintaro, YOSHIMOTO Masahiko
    International society

  • May 2016 電子情報通信学会集積回路研究専門委員会, LSIとシステムのワークショップ2016 優秀ポスター賞(学生部門), プロセスばらつき耐性を有する低電圧動作STT-MRAM向けカウンターベース読出し回路
    UMEKI Yohei, YANAGIDA Kouji, YOSHIMOTO Shusuke, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, TSUNODA Koji, SUGII Toshihiro
    Japan society

  • May 2014 電子情報通信学会集積回路研究専門委員会, 優秀ポスター賞, 38μAウェアラブル生体情報計測プロセッサ
    中井 陽三郎, IZUMI SHINTARO, 山下 顕, 中野 将尚, 藤井 貴英, 小西 恵大, KAWAGUCHI HIROSHI, 木村 啓明, 丸元 共治, 渕上 貴昭, 藤森 敬和, 中嶋 宏, 志賀 利一, YOSHIMOTO MASAHIKO
    Japan society

Paper

  • Hiroki Sato, Tatsuya Nagano, Shintaro Izumi, Jun Yamada, Daisuke Hazama, Naoko Katsurada, Masatsugu Yamamoto, Motoko Tachihara, Yoshihiro Nishimura, Kazuyuki Kobayashi
    The respiratory rate is an important factor for assessing patient status and detecting changes in the severity of illness. Real-time determination of the respiratory rate will enable early responses to changes in the patient condition. Several methods of wearable devices have enabled remote respiratory rate monitoring. However, gaps persist in large-scale validation, patient-specific calibration, standardization and their usefulness in clinical practice has not been fully elucidated. The aim of this study was to evaluate the accuracy of 2 wearable stretch sensors, C-STRECH® which is used in clinical practice and a novel stretchable capacitor in measuring the respiratory rate. The respiratory rate of 20 healthy subjects was measured by a spirometer with the stretch sensor applied to 1 of 5 locations (umbilicus, lateral abdomen, epigastrium, lateral chest, or chest) of their body at rest while they were in a sitting or supine position before or after exercise. The sensors detected the largest amplitudes at the epigastrium and umbilicus compared to other sites of measurement for the sitting and supine positions, respectively. At rest, the respiratory rate of the sensors had an error of 0.06 to 2.39 breaths/minute, whereas after exercise, an error of 1.57 to 3.72 breaths/minute was observed compared to the spirometer. The sensors were able to detect the respiratory rate of healthy volunteers in the sitting and supine positions, but there was a need for improvement in detection after exercise.
    Jul. 2024, Medicine, 103(29) (29), e38818, English, International magazine
    Scientific journal

  • Tatsuya Sugimoto, Nobuhito Taniguchi, Ryoto Yoshikura, Hiroshi Kawaguchi, Shintaro Izumi
    This study aimed to evaluate walking independence in acute-care hospital patients using neural networks based on acceleration and angular velocity from two walking tests. Forty patients underwent the 10-m walk test and the Timed Up-and-Go test at normal speed, with or without a cane. Physiotherapists divided the patients into two groups: 24 patients who were monitored or independent while walking with a cane or without aids in the ward, and 16 patients who were not. To classify these groups, the Transformer model analyzes the left gait cycle data from eight inertial sensors. The accuracy using all the sensor data was 0.836. When sensor data from the right ankle, right wrist, and left wrist were excluded, the accuracy decreased the most. When analyzing the data from these three sensors alone, the accuracy was 0.795. Further reducing the number of sensors to only the right ankle and wrist resulted in an accuracy of 0.736. This study demonstrates the potential of a neural network-based analysis of inertial sensor data for clinically assessing a patient's level of walking independence.
    May 2024, Bioengineering (Basel, Switzerland), 11(6) (6), English, International magazine
    Scientific journal

  • Tatsuya Sugimoto, Ryoto Yoshikura, Toshiyuki Maezawa, Kojiro Mekata, Yuya Ueda, Hiroshi Kawaguchi, Shintaro Izumi
    The purpose of this study was to compare the acceleration and surface electromyography (EMG) of the lower extremity and trunk muscles during straight-leg raising (SLR) in patients with incomplete cervical cord injury according to their levels of walking independence. Twenty-four patients were measured acceleration and EMG during SLR held for 10 s. Data were analyzed separately for the dominant and nondominant sides and compared between the nonindependent (NI) and independent (ID) groups based on their levels of walking independence. Frequency analysis of the EMG showed that the high-frequency (HF) band of the contralateral biceps femoris (BF) in the ID group and bands below the medium-frequency (MF) of the BF and the HF and MF bands of the rectus abdominis in the NI group were significantly higher during dominant and nondominant SLR. During the nondominant SLR, the low-frequency band of the internal oblique and the MF band of the external oblique were significantly higher in the NI group. The ID group mobilized muscle fiber type 2 of the BF, whereas the NI group mobilized type 1 of the BF and types 2 and 1 of the trunk muscles to stabilize the pelvis. This result was more pronounced during the nondominant SLR.
    Feb. 2024, Scientific reports, 14(1) (1), 4363 - 4363, English, International magazine
    Scientific journal

  • Rei Kawabata, Kou Li, Teppei Araki, Mihoko Akiyama, Kaho Sugimachi, Nozomi Matsuoka, Norika Takahashi, Daiki Sakai, Yuto Matsuzaki, Ryo Koshimizu, Minami Yamamoto, Leo Takai, Ryoga Odawara, Takaaki Abe, Shintaro Izumi, Naoko Kurihira, Takafumi Uemura, Yukio Kawano, Tsuyoshi Sekitani
    Abstract Flexible imagers are currently under intensive development as versatile optical sensor arrays, designed to capture images of surfaces and internals, irrespective of their shape. A significant challenge in developing flexible imagers is extending their detection capabilities to encompass a broad spectrum of infrared light, particularly terahertz (THz) light at room temperature. This advancement is crucial for thermal and biochemical applications. In this study, a flexible infrared imager is designed using uncooled carbon nanotube (CNT) sensors and organic circuits. The CNT sensors, fabricated on ultrathin 2.4 µm substrates, demonstrate enhanced sensitivity across a wide infrared range, spanning from near‐infrared to THz wavelengths. Moreover, they retain their characteristics under bending and crumpling. The design incorporates light‐shielded organic transistors and circuits, functioning reliably under light irradiation, and amplifies THz detection signals by a factor of 10. The integration of both CNT sensors and shielded organic transistors into an 8 × 8 active‐sensor matrix within the imager enables sequential infrared imaging and nondestructive assessment for heat sources and in‐liquid chemicals through wireless communication systems. The proposed imager, offering unique functionality, shows promise for applications in biochemical analysis and soft robotics.
    Wiley, Jan. 2024, Advanced Materials, 36(15) (15), e2309864, English, International magazine
    Scientific journal

  • Ryotaro Ohara, Yuto Yasuda, Riku Hamabe, Shun Sato, Ishii Toru, Shintaro Izumi, Hiroshi Kawaguchi
    2024, IEEE Open Journal of Ultrasonics, Ferroelectrics, and Frequency Control
    Scientific journal

  • Ryotaro Ohara, Shintaro Izumi, Shoya Imanaka, Tetsuo Yamamura, Ishii Toru, Hiroshi Kawaguchi
    2024, IEEE Access
    Scientific journal

  • Ryotaro Ohara, Atsushi Fukunaga, Masakazu Taichi, Masaya Kabuto, Riku Hamabe, Masato Ikegawa, Shintaro Izumi, Hiroshi Kawaguchi 0001
    We investigated the improvement achieved in the performance of a deep-learning inference processor by changing its cache memory from SRAM to spin-orbit torque magnetoresistive random-access memory (SOT-MRAM). The implementation of SOT-MRAM doubled the capacity in the same area compared to SRAM. It is also expected to reduce the main memory transfer without changing the chip area, thereby reducing the energy. As a case study, we simulated how much the performance could be improved by replacing SRAM with MRAM in a deep learning processor. The NVIDIA deep-learning accelerator (NVDLA) was used as a motif processor, and SegNet and U-Net were used as the target networks for the segmentation task. The image size was set to 512 × 1024 pixels. We evaluated the performance of the NVDLA with a 512-KB buffer and cache memory sizes of 1, 2, 4, and 8 MB for its on-chip memory, replacing these two memories with MRAM implementations. As a result, when both the buffer and cache were replaced with SOT-MRAM, the energy consumption and speed could be reduced by 18.6% and 17.9%, respectively. In addition, the performance per unit area was improved by more than 36.4%. Replacing SRAM with spin-transfer torque MRAM is not suitable for inference devices, because the latency is significantly worse as a result of its slow write operation.
    2024, IPSJ Trans. Syst. LSI Des. Methodol., 17, 7 - 15
    Scientific journal

  • Ryo Takamatsu, Shintaro Izumi, Hiroshi Kawaguchi 0001
    The number of patients with heat stroke has been increasing, and it is one of the social problems. Heat stroke frequently occurs indoors and often goes unnoticed, particularly at home. Therefore, our goal is to prevent heat stroke by developing a wearable sensor that can measure the volume and salinity of perspiration. In the proposed sensor, textile-based electrodes with conductive adhesive are applied to the fiber material. Because perspiration lowers the impedance between the textile-based electrodes, perspiration can be estimated from the impedance change. However, both the volume and salinity of perspiration contribute to these impedance changes, making it challenging to distinguish between these effects. To address this challenge, we utilized the impedance characteristics of water and salinity. A bidirectional driver circuit for impedance estimation was proposed and implemented. The measurement results indicate that the proposed method can measure the volume and salinity of perspiration from the impedance changes in the electrode.
    2024, ICCE, 1 - 6
    International conference proceedings

  • Shun Sato, Ryotaro Ohara, M. Shahrul Amir Kamarulzaman, Yuto Yasuda, Shintaro Izumi, Hiroshi Kawaguchi 0001
    Bathrooms can be slippery, increasing the risk of falling. In addition, because people enter the bathroom alone, it is difficult to detect accidents immediately when they occur. Therefore, a system is required to quickly detect accidents and call for assistance. In this study, the location and the posture of the bather are important attributes. We propose a method to estimate the location of a bather using ultrasound correlation values as input to a deep neural network and to estimate the bather's posture. Therefore, the mean absolute error achieved 11.7 cm for location estimation, and accuracy achieved 95.3% for posture estimation in the experiment involving an individual moving throughout the bathroom.
    2024, ICCE, 1 - 5
    International conference proceedings

  • Yusaku Goto, Shintaro Izumi, Ryotaro Ohara, Teppei Araki, Sho Murase, Hiroshi Kawaguchi 0001
    The early detection and treatment of cardiovascular diseases hold significant importance; an electrocardiogram (ECG) is the most widely employed tool for assessing the functional status of the heart. Traditional standard 12-lead and Holter electrocardiographs used in medical facilities are characterized by their substantial size and possess drawbacks, including the necessity for professional assistance during application and removal, as well as limitations on patient mobility during monitoring. Consumer-oriented devices employed within the home environment such as wristwatch and patch electrocardiographs encounter issues related to measurement accuracy. Consequently, a demand arises for a system capable of conveniently and accurately measuring and monitoring cardiac activity within a home setting. This study presents a 15-channel wearable body surface potential sensor using a flexible electrode sheet. In addition, we introduce a machine-learning approach for estimating the waveform of a standard 12-lead ECG based on measurements obtained from the proposed sensor device that integrates a wireless measurement circuit.
    2024, ICCE, 1 - 5
    International conference proceedings

  • Teppei Araki, Kou Li, Daichi Suzuki, Takaaki Abe, Rei Kawabata, Takafumi Uemura, Shintaro Izumi, Shuichi Tsuruta, Nao Terasaki, Yukio Kawano, Tsuyoshi Sekitani
    The integration of flexible electronics with optics can help realize a powerful tool that facilitates the creation of a smart society wherein internal evaluations can be easily performed nondestructively from the surface of various objects that is used or encountered in daily lives. Here, organic-material-based stretchable optical sensors and imagers that possess both bending capability and rubber-like elasticity are reviewed. The latest trends in nondestructive evaluation equipment that enable simple on-site evaluations of health conditions and abnormalities are discussed without subjecting the targeted living bodies and various objects to mechanical stress. Real-time performance under real-life conditions is becoming increasingly important for creating smart societies interwoven with optical technologies. In particular, the terahertz (THz)-wave region offers a substance- and state-specific fingerprint spectrum that enables instantaneous analyses. However, to make THz sensors accessible, the following issues must be addressed: broadband and high-sensitivity at room temperature, stretchability to follow the surface movements of targets, and digital transformation compatibility. The materials, electronics packaging, and remote imaging systems used to overcome these issues are discussed in detail. Ultimately, stretchable optical sensors and imagers with highly sensitive and broadband THz sensors can facilitate the multifaceted on-site evaluation of solids, liquids, and gases.
    Jul. 2023, Advanced materials (Deerfield Beach, Fla.), 36(20) (20), e2304048, English, International magazine
    Scientific journal

  • Shun Sato, Yuto Yasuda, Ryotaro Ohara, Riku Hamabe, Takayuki Genda, Shoya Imanaka, Shintaro Izumi, Hiroshi Kawaguchi
    In bathrooms, a fall can lead to severe injuries or even drowning. While taking preventive measures against such accidents is crucial, it's equally important to swiftly detect and request rescue when they occur. In such scenarios, knowing the exact location of the person in the bathroom becomes critical. However, concerns related to privacy and costs make the use of cameras and lidar impractical. To address these issues, we propose a method for estimating the 3D location of a person within the bathroom using ultrasound correlation values as input for a deep neural network. To validate our approach, we conduct experiments using two sensors in this study. The results are promising, as we achieved a mean square error of just 10.48 cm.
    2023, IEEE International Ultrasonics Symposium, IUS
    International conference proceedings

  • Kousei Kawai, Ryotaro Ohara, Shun Sato, Toru Ishii, Shintaro Izumi, Hiroshi Kawaguchi
    Respiration is an important vital sign to detect abnormalities in the respiratory organ. However, conventional respiration sensors require contact with the human body, which poses challenges in terms of ease of use and infection control. In this study, we proposed a noncontact method for measuring respiration using ultrasound. We applied the proposed method to a seated subject wearing clothes and evaluated the accuracy of the respiration measurement. The results showed that the RMSEs of the respiration interval under the conditions of 20 cm, 30 cm, and 50 cm were 61.08 ms, 84.89 ms, and 110.98 ms, respectively.
    2023, IEEE International Ultrasonics Symposium, IUS
    International conference proceedings

  • Saki Wada, Kengo Nishimoto, Yoshio Inasawa, Shintaro Izumi
    The constant monitoring of biological data such as heart rate, heartbeat interval, and respiration rate enables the estimation of physical and psychological conditions. In our previous study, we adopted radio-wave sensors as non-contact and non-invasive sensors and developed a non-contact heart rate sensor that uses a small loop antenna in the very-high-frequency band with low radiation efficiency. In this study, we extracted peaks from heart rate waveforms obtained from 9 participants with a small card-sized (60 mm × 90 mm) heartbeat sensor module and demonstrated that the heartbeats interval can be obtained with high accuracy with an average acquisition error of R-R interval of 123 ms.
    2023, BSN, 1 - 4
    International conference proceedings

  • Tatsuya Sugimoto, Ryoto Yoshikura, Hiroshi Kawaguchi 0001, Shintaro Izumi
    This study aimed to assess ambulation in hospitalized patients undergoing rehabilitation and determine the timing of independence using the Timed Up and Go (TUG) test as an evaluation method. The objective of this study was to categorize hospitalized patients based on their TUG completion time and level of walking independence, and to compare their movement patterns as measured by inertial sensors across the groups. The study included hospitalized patients undergoing rehabilitation who were already independent in walking with a walker. The patients performed the TUG test by walking as quickly as possible without assistance or with a cane. Inertial sensors were attached to both lower legs and the lumbar region, and the acceleration and angular velocity of the lumbar region were analyzed. A total of 21 patients were included in the analysis: 9 patients in the Independent Fast (IF) group, who were independent in walking without aids or with a cane and had a TUG time of less than 13.5 seconds; 6 patients in the Independent Slow (IS) group, who were independent in walking but had a TUG time greater than 13.5 seconds; and 6 patients in the Monitored Slow (MS) group, who required monitoring during walking and had a TUG time greater than 13.5 seconds. The IF group demonstrated significantly lower total TUG time and total number of steps compared to the other two groups, and the IS group had significantly lower values than the MS group. For the sit-To-stand phase, the mean pitch angle of the IF group was significantly higher than that of the other two groups. For the second turn phase, the maximum, mean, and range of yaw angle were significantly higher in the IF group compared to the MS group. The autocorrelation coefficient of acceleration for the anterior-posterior axis for the first walk phase was significantly higher in the IF group compared to the other two groups. These results may indicate recovery, as the IS group exhibited slower TUG times but had movement patterns closer to those of the IF group. Consequently, this highlights the potential of inertial sensors as an objective tool for assessing walking independence.
    2023, BSN, 1 - 4
    International conference proceedings

  • Ryotaro Ohara, Masaya Kabuto, Masakazu Taichi, Atsushi Fukunaga, Yuto Yasuda, Riku Hamabe, Shintaro Izumi, Hiroshi Kawaguchi
    This study introduces a 1W8R 20T multiport memory for codebook quantization in deep-learning processors. We manufactured the memory in a 40 nm process and achieved memory read-access time at 2.75 ns and 2.7-pj/byte power consumption. In addition, we used NVDLA, which was NVIDIA's deep-learning processor, as a motif and simulated it based on the power obtained from the actual proposed memory. The obtained power and area reduction results are 20.24% and 26.24%, respectively.
    2023, AICAS, 1 - 5
    International conference proceedings

  • Rei Kawabata, Teppei Araki, Mihoko Akiyama, Takafumi Uemura, Tianxu Wu, Hirotaka Koga, Yusuke Okabe, Yuki Noda, Shuichi Tsuruta, Shintaro Izumi, Masaya Nogi, Katsuaki Suganuma, Tsuyoshi Sekitani
    Wearable devices with excellent mechanical stretchability, comparable to that of human skin, are highly desirable for preventing discomfort and dermatitis. Composite material systems that use metal particles and elastomers are promising for realizing intrinsic stretchable electrodes with high conductivity and enhancing mechanical flexibility of wearable devices. However, it is challenging to achieve stable device performance under mechanical deformation using stretchable electrodes. In this study, stretchable electrodes with enhanced conductivity and stretchability are developed and integrated with organic transistors to fabricate a stretchable printed circuit board (PCB) that acts as a voltage amplifier under large strains. The stretchable electrodes are composed of silver microparticles, a small quantity of silver nanowires (AgNWs), and an elastomer matrix, which demonstrated a conductivity of 8.5 × 103 S cm−1 at a curing temperature of 100 °C. The observed conductivity was 3.6 times higher than that of electrodes without AgNWs. Owing to the addition of AgNWs, the durability strain in cyclic stretching increased from 10% to 75%; the increment can be attributed to the suppression of microcrack propagation. Moreover, the proposed stretchable PCB was applied to fabricate a voltage amplifier, which enabled stable amplification by 14 times under 0% and 75% strain owing to a mechanical rigid-soft patterning designed into the substrate according to the rigidness of the mounted components. The stabilization technologies in the proposed stretchable PCB can contribute to the development of wearable devices for long-term usage to assist the early detection of diseases.
    Dec. 2022, Flexible and Printed Electronics, 7(4) (4)
    Scientific journal

  • Ryotaro Ohara, Yuto Yasuda, Riku Hamabe, Ishii Toru, Shintaro Izumi, Hiroshi Kawaguchi
    IEEE, Oct. 2022, 2022 IEEE International Ultrasonics Symposium (IUS)

  • Ishii Toru, Yuto Yasuda, Shun Sato, Shintaro Izumi, Hiroshi Kawaguchi
    In this paper, we present a 3-D ultrasonic measurement technique that uses direct sequence spread spectrum (DSSS) with simultaneous multiple code-division multiple access (CDMA) signals. This technique can be applied in precise indoor locating systems. By placing three microphones close to one another separated by distances on the order of the ultrasound wavelength and imposing the constraint that one transducer and two from the three microphones form three triangles in the space (i.e., the triangle constraint) for 3-D ultrasonic DSSS trilateration measurement, millimeter 3-D positioning precision is achieved. The experimental results for a positioning system comprising a set of three microphones and four ultrasound transducers, each of them transmitting its respective 256-bit DSSS code, demonstrate that the proposed system can measure the spatial 3-D location of the receiver with a standard deviation of less than 1.21 mm. The proposed technique is suitable for potential future indoor positioning system (IPS) applications that require sub-centimeter 3-D positioning.
    Institute of Electrical and Electronics Engineers ({IEEE}), Aug. 2022, IEEE Sensors Journal, 22(16) (16), 16202 - 16211
    Scientific journal

  • Teppei Araki, Shusuke Yoshimoto, Takafumi Uemura, Aiko Miyazaki, Naoko Kurihira, Yuko Kasai, Yoshiko Harada, Toshikazu Nezu, Hirokazu Iida, Junko Sandbrook, Shintaro Izumi, Tsuyoshi Sekitani
    The growing demand for efficient home healthcare applications for brain disorder diagnostics and treatment has inspired the development of wearable devices for monitoring brain activity. However, flexible probes that have improved biocompatibility for wearable devices are markedly affected by noise due to contact interface issues. In this study, a stretchable (≤1500% strain) and transparent (over 85% transmittance) biocompatible electrode that steadily adheres to skin is developed to fabricate an imperceptible sheet-type device that wirelessly records electroencephalograms (EEGs). The multifunctional characteristic of the electrode results from the double-network structure in an elastomer/conductive additive blend on a metal-nanowire-based track, which contributed to EEG monitoring with ultralow noise (≈0.14 µV noise floor) and sleep-stage classification. Furthermore, the optical transparency enabled camera-based photoplethysmography to detect pulse waves and blood oxygen saturation without interfering with the light path, which is a crucial factor in realizing a remote healthcare system.
    Wiley, Jul. 2022, Advanced Materials Technologies, 7(11) (11), 2200362 - 2200362
    Scientific journal

  • Hisaya Kato, Yoshiro Maezawa, Dai Nishijima, Eisuke Iwamoto, June Takeda, Takashi Kanamori, Masaya Yamaga, Tatsuzo Mishina, Yusuke Takeda, Shintaro Izumi, Yutaro Hino, Hiroyuki Nishi, Jun Ishiko, Masahiro Takeuchi, Hiyori Kaneko, Masaya Koshizaka, Naoya Mimura, Masafumi Kuzuya, Emiko Sakaida, Minoru Takemoto, Yuichi Shiraishi, Satoru Miyano, Seishi Ogawa, Atsushi Iwama, Masashi Sanada, Koutaro Yokote
    Werner syndrome (WS) is a progeroid syndrome caused by mutations in the WRN gene, which encodes the RecQ type DNA helicase for the unwinding of unusual DNA structures and is implicated in DNA replication, DNA repair, and telomere maintenance. patients with WS are prone to develop malignant neoplasms, including hematological malignancies. However, the pathogenesis of WS-associated hematological malignancies remains uncharacterized. Here we investigated the somatic gene mutations in WS-associated myelodysplastic syndrome/acute myeloid leukemia (MDS/AML). Whole-exome sequencing (WES) of 4 patients with WS with MDS/AML revealed that all patients had somatic mutations in TP53 but no other recurrent mutations in MDS/AML. TP53 mutations were identified at low allele frequencies at more than one year before the MDS/AML stage. All 4 patients had complex chromosomal abnormalities including those that involved TP53. Targeted sequencing of nine patients with WS without apparent blood abnormalities did not detect recurrent mutations in MDS/AML except for a PPM1D mutation. These results suggest that patients with WS are apt to acquire TP53 mutations and/or chromosomal abnormalities involving TP53, rather than other MDS/AML-related mutations. TP53 mutations are frequently associated with prior exposure to chemotherapy; however, all four patients with WS with TP53 mutations/deletions had not received any prior chemotherapy, suggesting a pathogenic link between WRN mutations and p53 insufficiency. These results indicate that WS hematopoietic stem cells with WRN insufficiency acquire competitive fitness by inactivating p53, which may cause complex chromosomal abnormalities and the subsequent development of myeloid malignancies. These findings promote our understanding of the pathogenesis of myeloid malignancies associated with progeria.
    May 2022, Experimental hematology, 109, 11 - 17, English, International magazine
    Scientific journal

  • Ayaka Shintomi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    The purpose of this study is to evaluate the effectiveness of heartbeat error and compensation methods on heart rate variability (HRV) with mobile and wearable sensor devices. The HRV analysis extracts multiple indices related to the heart and autonomic nervous system from beat-to-beat intervals. These HRV analysis indices are affected by the heartbeat interval mismatch, which is caused by sampling error from measurement hardware and inherent errors from the state of human body. Although the sampling rate reduction is a common method to reduce power consumption on wearable devices, it degrades the accuracy of the heartbeat interval. Furthermore, wearable devices often use photoplethysmography (PPG) instead of electrocardiogram (ECG) to measure heart rate. However, there are inherent errors between PPG and ECG, because the PPG is affected by blood pressure fluctuations, vascular stiffness, and body movements. This paper evaluates the impact of these errors on HRV analysis using dataset including both ECG and PPG from 28 subjects. The evaluation results showed that the error compensation method improved the accuracy of HRV analysis in time domain, frequency domain and non-linear analysis. Furthermore, the error compensation by the algorithm was found to be effective for both PPG and ECG.
    Institution of Engineering and Technology ({IET}), Feb. 2022, Healthcare Technology Letters, 9(1-2) (1-2), 9 - 15, English, International magazine
    Scientific journal

  • Yuichiro Yasuda, Tatsuya Nagano, Shintaro Izumi, Mina Yasuda, Kosuke Tsuruno, Kazunori Tobino, Kyosuke Nakata, Kayoko Okamura, Teruaki Nishiuma, Kiyonobu Takatsuki, Yasuhiro Funada, Hisashi Ohnishi, Masatsugu Yamamoto, Yoshihiro Nishimura, Kazuyuki Kobayashi
    Figure 4 of the published article contained an error. The correct figure is shown below(Figure Presented.).
    SPRINGER HEIDELBERG, Jan. 2022, Sleep & breathing = Schlaf & Atmung, 26(3) (3), 1503 - 1503, English, International magazine
    Scientific journal

  • Ryoto Yoshikura, Shintaro Izumi, Tatsuya Sugimoto, Hiroshi Kawaguchi
    In the world, approximately 250,000-500,000 new cases of spinal cord injury occur each year, and they require chronic treatment due to the intractable nature of the injuries. The mainstream method for evaluating trunk function in spinal cord injury patients is based on subjective evaluation by physical therapists. Because this evaluation is based on the experience of the physical therapist, the detailed evaluation method of trunk function is largely dependent on the skill of the physical therapist. Therefore, an objective and quantitative method of evaluating trunk function is necessary. This study focuses on the straight leg raising (SLR) test during rehabilitation. By measuring SLR using multimodal sensing and convolutional neural network (CNN), the severity of the patient's condition can be quantitatively assessed.
    IEEE, 2022, 2022 IEEE Sensors, 2022-October, 1 - 4
    International conference proceedings

  • Saki Wada, Kengo Nishimoto, Yoshio Inasawa, Shintaro Izumi
    IEEE, 2022, 2022 IEEE Sensors, 1 - 4
    International conference proceedings

  • Shintaro Izumi, Sho Murase, Itsumi Fukuda, Kenta Taki, Kazunori Toyama, Tadashi Inuzuka, Hideki Mochizuki, Hiroshi Kawaguchi
    IEEE, 2022, 2022 IEEE Sensors, 1 - 4
    International conference proceedings

  • Masayasu Harada, Shintaro Izumi, Ryosuke Kozeni, Yukiko Yoshikawa, Toru Ishii, Hiroshi Kawaguchi, Shohei Uemura, Kaname Araki
    IEEE, 2022, 19th IEEE Annual Consumer Communications & Networking Conference(CCNC), 181 - 186
    International conference proceedings


  • Asuka Yoshizaki, Tatsuya Nagano, Shintaro Izumi, Teruaki Nishiuma, Kyosuke Nakata, Masatsugu Yamamoto, Yuichiro Yasuda, Daisuke Hazama, Kanoko Umezawa, Naoko Katsurada, Motoko Tachihara, Yoshihiro Nishimura, Kazuyuki Kobayashi
    BACKGROUND: Nocturnal desaturation is common in patients with chronic obstructive pulmonary disease (COPD) and impacts disease exacerbation and prognosis. In our previous study, we developed a diagnostic algorithm to classify nocturnal desaturation from SpO2 waveform patterns based on data from patients receiving home oxygen therapy. In this study, we aimed to investigate nocturnal desaturation in patients with COPD based on SpO2 waveform patterns and the associations between the waveforms and clinical data. METHODS: We investigated patients diagnosed with COPD and measured SpO2 and nasal airflow with a type 4 portable long-term recordable pulse oximeter. Then, we classified the SpO2 waveforms with the algorithm and compared the clinical data. RESULTS: One hundred fifty-three patients (136 male and 17 female) were analysed. One hundred twenty-eight of the 153 (83.7%) patients had nocturnal desaturation, with an intermittent pattern (70.6%), sustained pattern (13.1%) and periodic pattern (68.0%). Intriguingly, desaturation with an intermittent pattern was associated with the apnoea-hypopnea index obtained with the portable monitor, and desaturation with a sustained pattern was associated with the cumulative percentage of time at a SpO2 below 90%. CONCLUSIONS: We found that nocturnal desaturation was frequently observed in patients with COPD and could be classified into 3 types of waveform patterns.
    BMC, Oct. 2021, Respiratory research, 22(1) (1), 276 - 276, English, International magazine
    Scientific journal

  • Yuichiro Yasuda, Tatsuya Nagano, Shintaro Izumi, Mina Yasuda, Kosuke Tsuruno, Kazunori Tobino, Kyosuke Nakata, Kayoko Okamura, Teruaki Nishiuma, Kiyonobu Takatsuki, Yasuhiro Funada, Hisashi Ohnishi, Masatsugu Yamamoto, Yoshihiro Nishimura, Kazuyuki Kobayashi
    PURPOSE: Sleep-disordered breathing is recognized as a comorbidity in patients with idiopathic pulmonary fibrosis (IPF). Among them, nocturnal hypoxemia has been reported to be associated with poor prognosis and disease progression. We developed a diagnostic algorithm to classify nocturnal desaturation from percutaneous oxygen saturation (SpO2) waveform patterns: sustained pattern, periodic pattern, and intermittent pattern. We then investigated the prevalence of nocturnal desaturation and the association between the waveform patterns of nocturnal desaturation and clinical findings of patients with IPF. METHODS: We prospectively enrolled patients with IPF from seven general hospitals between April 2017 and March 2020 and measured nocturnal SpO2 and nasal airflow by using a home sleep apnea test. An algorithm was used to classify the types of nocturnal desaturation. We evaluated the association between sleep or clinical parameters and each waveform pattern of nocturnal desaturation. RESULTS: Among 60 patients (47 men) who met the eligibility criteria, there were 3 cases with the sustained pattern, 49 cases with the periodic pattern, and 41 cases with the intermittent pattern. Lowest SpO2 during sleep and total sleep time spent with SpO2 < 90% were associated with the sustained pattern, and apnea-hypopnea index was associated with the intermittent pattern. CONCLUSION: We demonstrated the prevalence of each waveform and association between each waveform and sleep parameters in patients with IPF. This classification algorithm may be useful to predict the degree of hypoxemia or the complication of obstructive sleep apnea.
    SPRINGER HEIDELBERG, Aug. 2021, Sleep & breathing = Schlaf & Atmung, 26(3) (3), 1079 - 1086, English, International magazine
    Scientific journal

  • Takehiro Otoshi, Tatsuya Nagano, Shintaro Izumi, Daisuke Hazama, Naoko Katsurada, Masatsugu Yamamoto, Motoko Tachihara, Kazuyuki Kobayashi, Yoshihiro Nishimura
    Objective evaluations of cough frequency are considered important for assessing the clinical state of patients with respiratory diseases. However, cough monitors with audio recordings are rarely used in clinical settings. Issues regarding privacy and background noise with audio recordings are barriers to the wide use of these monitors; to solve these problems, we developed a novel automatic cough frequency monitoring system combining a triaxial accelerator and a stretchable strain sensor. Eleven healthy adult volunteers and 10 adult patients with cough were enrolled. The participants wore two devices for 30 min for the cough measurements. An accelerator was attached to the epigastric region, and a stretchable strain sensor was worn around their neck. When the subjects coughed, these devices displayed specific waveforms. The data from all the participants were categorized into a training dataset and a test dataset. Using a variational autoencoder, a machine learning algorithm with deep learning, the components of the test dataset were automatically judged as being a "cough unit" or "non-cough unit". The sensitivity and specificity in detecting coughs were 92% and 96%, respectively. Our cough monitoring system has the potential to be widely used in clinical settings without any concerns regarding privacy or background noise.
    May 2021, Scientific reports, 11(1) (1), 9973 - 9973, English, International magazine
    Scientific journal

  • 西川 美樹, 齋藤 いずみ, 大滝 千文, 大澤 佳代, 和泉 慎太郎
    日本では,分娩の約8割がほかの診療科が混合する病棟で行われており,分娩と他科死亡患者の看護が重複するといった実態が明らかにされてきた.また,産科単独病棟でもその68.2%がハイリスク化しており出産環境の安全性の低下が危惧されている.よって本研究は24時間体制でハイリスクの母体救命救急に対応している産科単独病棟の看護の実態を可視化することで周産期医療体制の在り方を検討することを目標とした.ビーコンとスマートフォンを活用し,助産師の滞在場所と滞在時間を明らかにした.通常業務以外の突発的な事象が生じると母児の救命に向けて分娩エリアに半数以上の助産師が配置されていたが,「病室」「新生児室」の滞在時間を減らさずにクライアントに必要なケアを提供していた.そこにはチームメンバー間の協働による成果と,調査施設が周産期のケアに専念できる産科単独病棟であったことが関与していたと考えられる.(著者抄録)
    看護理工学会, 2021, 看護理工学会誌, 9, 21 - 33, English

  • Arata Ishii, Shokichi Tsukamoto, Tatsuzo Mishina, Shintaro Izumi, Yurie Nagai, Miki Yamazaki, Yutaro Hino, Kensuke Kayamori, Nagisa Oshima-Hasegawa, Tomoya Muto, Shio Mitsukawa, Yusuke Takeda, Naoya Mimura, Chikako Ohwada, Chiaki Nakaseko, Jun-Ichiro Ikeda, Emiko Sakaida
    A 45-year-old woman was diagnosed with myelodysplastic syndrome (MDS) with trisomy 8 and Behçet-like disease (BLD) with multiple colorectal ulcers. Nonspecific inflammatory cells were infiltrated in the intestinal mucosa, whereas fluorescence in situ hybridization (FISH) analysis revealed only sporadic trisomy 8-positive cells. She presented massive lower gastrointestinal bleeding early after bone marrow transplantation but achieved long-term remission of both MDS and BLD. This is the first report of massive gastrointestinal bleeding after transplantation for MDS with BLD. Based on FISH analysis, dysregulation of systemic inflammation may be involved in BLD rather than direct invasion by trisomy 8-positive MDS clones.
    2021, Leukemia research reports, 16, 100278 - 100278, English, International magazine
    Scientific journal

  • Asuka Yoshizaki, Tatsuya Nagano, Shintaro Izumi, Yasuhiro Funada, Kyosuke Nakata, Teruaki Nishiuma, Kiyonobu Takatsuki, Hisashi Ohnishi, Nobuko Hazeki, Yuichiro Yasuda, Ryota Dokuni, Masatsugu Yamamoto, Kazuyuki Kobayashi, Yoshihiro Nishimura
    Objective Nocturnal desaturation is common in patients with chronic respiratory disease and often worsens the prognosis. Therefore, it should be diagnosed accurately and appropriately treated. The aim of this study was to clarify the diversity of nocturnal desaturation. Methods We prospectively enrolled 58 outpatients diagnosed with chronic respiratory disease receiving home oxygen therapy and measured nocturnal SpO2 using a portable oximeter. We classified nocturnal desaturation (3% decrease in SpO2 from baseline) into three patterns: periodic pattern (desaturation duration of <655 seconds), sustained pattern (desaturation duration of ≥655 seconds), and intermittent pattern (desaturation and recovery of SpO2 repeated with a cycle of several minutes). Results Nocturnal hypoxemia (SpO2≤88% for more than 5 minutes) was found in 23.8% of patients. The percentage of patients with chronic obstructive pulmonary disease (COPD) was significantly higher in the nocturnal hypoxemia group than in the non-hypoxemia group (80% vs. 40.6%, p=0.03). Desaturation with a periodic pattern was found in 81% of patients, desaturation with a sustained pattern was found in 40.5% of patients, and desaturation with an intermittent pattern was found in 59.5% of patients. In patients with COPD, desaturation with a periodic pattern was found in 85.7%, desaturation with a sustained pattern was found in 47.6%, and desaturation with an intermittent pattern was found in 57.1%. Conclusion The SpO2 waveform of nocturnal hypoxemia was able to be classified into three patterns. Suitable treatment for each pattern might improve the prognosis of these patients.
    JAPAN SOC INTERNAL MEDICINE, 2021, Internal medicine (Tokyo, Japan), 60(19) (19), 3071 - 3079, English, Domestic magazine
    Scientific journal

  • Yukiko Yoshikawa, Yuto Yasuda, Toru Ishii, Shintaro Izumi, Hiroshi Kawaguchi
    IEEE, 2021, IEEE International Instrumentation and Measurement Technology Conference(I2MTC), 38th, 1 - 6

  • ISHII Toru, Yukiko Yoshikawa, Shintaro Izumi, Hiroshi Kawaguchi
    2021, IEEE Transactions on Instrumentation and Measurement, 70, 1 - 8
    Scientific journal

  • Ashuya Takemoto, Teppei Araki, Takafumi Uemura, Yuki Noda, Shusuke Yoshimoto, Shintaro Izumi, Shuichi Tsuruta, Tsuyoshi Sekitani
    Wiley, Aug. 2020, Advanced Intelligent Systems, 2(11) (11), 2000093 - 2000093
    Scientific journal

  • Kento Watanabe, Shintaro Izumi, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This study presents a method for improving the heartbeat interval accuracy of photoplethysmographic (PPG) sensors at ultra-low sampling rates. Although sampling rate reduction can extend battery life, it increases the sampling error and degrades the accuracy of the extracted heartbeat interval. To overcome these drawbacks, a sampling-error compensation method is proposed in this study. The sampling error is reduced by using linear interpolation and autocorrelation based on the waveform similarity of heartbeats in PPG. Furthermore, this study introduces two-line approximation and first derivative PPG (FDPPG) to improve the waveform similarity at ultra-low sampling rates. The proposed method was evaluated using measured PPG and reference electrocardiogram (ECG) of seven subjects. The results reveal that the mean absolute error (MAE) of 4.11 ms was achieved for the heartbeat intervals at a sampling rate of 10 Hz, compared with 1-kHz ECG sampling. The heartbeat interval error was also evaluated based on a heart rate variability (HRV) analysis. Furthermore, the mean absolute percentage error (MAPE) of the low-frequency/high-frequency (LF/HF) components obtained from the 10-Hz PPG is shown to decrease from 38.3% to 3.3%. This error is small enough for practical HRV analysis.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jun. 2020, IEICE TRANSACTIONS ON COMMUNICATIONS, E103B(6) (6), 645 - 652, English
    Scientific journal

  • Reiya Kawamoto, Masakazu Taichi, Masaya Kabuto, Daisuke Watanabe, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Go Matsukawa, Toshio Goto, Motoshi Kojima
    Institute of Electrical and Electronics Engineers ({IEEE}), May 2020, IEEE Journal of Selected Topics in Signal Processing, 14(4) (4), 634 - 645
    Scientific journal

  • Teppei Araki, Takafumi Uemura, Shusuke Yoshimoto, Ashuya Takemoto, Yuki Noda, Shintaro Izumi, Tsuyoshi Sekitani
    Mechanically and visually imperceptible sensor sheets integrated with lightweight wireless loggers are employed in ultimate flexible hybrid electronics (FHE) to reduce vital stress/nervousness and monitor natural biosignal responses. The key technologies and applications for conceptual sensor system fabrication are reported, as exemplified by the use of a stretchable sensor sheet completely conforming to an individual's body surface to realize a low-noise wireless monitoring system (<1 µV) that can be attached to the human forehead for recording electroencephalograms. The above system can discriminate between Alzheimer's disease and the healthy state, thus offering a rapid in-home brain diagnosis possibility. Moreover, the introduction of metal nanowires to improve the transparency of the biocompatible sensor sheet allows one to wirelessly acquire electrocorticograms of nonhuman primates and simultaneously offers optogenetic stimulation such as toward-the-brain-machine interface under free movement. Also discussed are effective methods of improving electrical reliability, biocompatibility, miniaturization, etc., for metal nanowire based tracks and exploring the use of an organic amplifier as an important component to realize a flexible active probe with a high signal-to-noise ratio. Overall, ultimate FHE technologies are demonstrated to achieve efficient closed-loop systems for healthcare management, medical diagnostics, and preclinical studies in neuroscience and neuroengineering.
    WILEY-V C H VERLAG GMBH, Apr. 2020, Advanced materials (Deerfield Beach, Fla.), 32(15) (15), e1902684, English, International magazine
    [Refereed]
    Scientific journal

  • Toru Ishii, Yukiko Yoshikawa, Shintaro Izumi, Hiroshi Kawaguchi
    We present a Doppler effect compensation technique that can be applied to high-precision ultrasonic distance measurement using the direct sequence spread spectrum (DSSS). In this study, first, the theory of Doppler compensation technique is explained, and then the experimental results using the M-sequence coded ultrasonic signals are discussed. The evaluation results show that the proposed method can measure distance of target moving at 2 m/s in the range of 0.1-1.6 m, with an efficiency of more than 95%, and with a standard deviation of less than 8 mm by using either a 128-bit or a 32-bit long DSSS code.
    IEEE, 2020, 2020 IEEE International Instrumentation and Measurement Technology Conference(I2MTC), 1 - 6
    International conference proceedings

  • Yurie Nagai, Shokichi Tsukamoto, Yutaro Hino, Yusuke Isshiki, Miki Yamazaki, Shintaro Izumi, Tatsuzo Mishina, Nagisa Oshima-Hasegawa, Shio Mitsukawa, Yusuke Takeda, Naoya Mimura, Chikako Ohwada, Masahiro Takeuchi, Tohru Iseki, Chiaki Nakaseko, Emiko Sakaida
    Jan. 2020, Leukemia & lymphoma, 61(1) (1), 221 - 224, English, International magazine

  • Daisuke Watanabe, Yuji Yano, Shintaro Izumi, Hiroshi Kawaguchi, Kiyoshi Takeuchi, Toshiro Hiramoto, Shoichi Iwai, Masami Murakata, Masahiko Yoshimoto
    IEEE, 2020, 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems(AICAS), 305 - 309
    [Refereed]
    International conference proceedings

  • Reiya Kawamoto, Masakazu Taichi, Masaya Kabuto, Daisuke Watanabe, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    IEEE, 2020, 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems(AICAS), 203 - 207
    [Refereed]
    International conference proceedings

  • Otaki Chifumi, Saito Izumi, Izumi Shintaro, Osawa Kayo
    [Introduction] The number of mixed obstetric wards, which combine obstetric and non-obstetric patients, is increasing in Japan. The nurses and midwives working in these wards are concerned with their work process and sharing of roles. [Purpose] This study aimed to clarify how nurses and midwives work and share roles by measuring the location and duration of their work-related movements in mixed obstetric wards with critical patients. [Methods] We conducted a prospective observational study of nurses and midwives working in a mixed obstetric ward and measured times in various tasks according to a time-motion design using a smartphone and a beacon. [Results] The mean bedside time for nurses and midwives per patient in a general patient room did not differ significantly between days with and without critical patients in the ward (p=0.092). When critical patients were hospitalized, the nurses and midwives spent less time at the nurses' station. [Conclusion] Nurses' stay time per patient in general rooms was stable regardless of admission of critical patients. This staffing, which defined the role of nurses and midwives working in a mixed obstetric ward, secured nursing time for critical, general, and obstetric patients despite the mixed ward.
    The Society for Nursing Science and Engineering, 2020, Journal of Nursing Science and Engineering, 7(0) (0), 130 - 140, English
    [Refereed]

  • Kento Watanabe, Shintaro Izumi, Kana Sasai, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This study designs a low-power photoplethysmography (PPG) sensor based on the error compensation method for heartbeat interval acquisition. To perform heartbeat monitoring in daily life, it is necessary to obtain long-term and accurate heartbeat interval data with low power consumption, because of the limited size and battery capacity of the PPG sensor. Effective reduction in the power consumption of the sensor requires the duty-cycled LEDs and lowering pulse repetition frequency (PRF), i.e., decreasing the sampling rate. However, these methods reduce the accuracy of the heartbeat interval measurement because of signal-to-noise ratio (SNR) degradation and sampling errors. We propose an algorithm for heartbeat interval error compensation and incorporate a low-noise readout circuit to improve SNR. The readout circuit uses current integration to achieve low duty-cycle LED driving. A correlated double sampling (CDS) is introduced to minimize the random noise arising from the switching operation of the integration circuit. An error compensation method based on the PPG waveform similarity is also introduced using the autocorrelation and linear interpolation. The measurement results obtained from nine subjects show that a total current consumption of 28.2A is achieved with a 20-Hz PRF and 0.3 LED duty cycle. The proposed design effectively reduces the mean absolute error (MAE) of the heartbeat interval to an average of 6.2 ms.
    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, Dec. 2019, IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, 13(6) (6), 1552 - 1562, English, International magazine
    [Refereed]
    Scientific journal

  • Kana Sasai, Shintaro Izumi, Kento Watanabe, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a low-power photoplethysmography (PPG) sensor circuit using a current integration circuit. PPG sensors are widely used in modern healthcare products for monitoring cardiovascular information. However, the PPG circuits generally have a large power consumption because the LED driver consumes considerable energy to obtain the required amount of reflected light from the human body. A simple way to reduce the power requirements of PPG circuits is to lower the duty cycle of the LED through intermittent operation of the LED. However, this causes accuracy degradation because the target signal is susceptible to interference from various noises. To reduce the power consumption while maintaining accuracy, the correlated double sampling (CDS) method that we introduced in our previous work was used. In our previous work, wherein the PPG was placed on fingertips, the heartbeat error was 5 ms. This paper presents a signal-to-noise ratio improvement method for CDS by using a PPG sensor with current integration circuits. This enables SNR improvement and measurements to be taken from any part of the body. In the proposed method, the target PPG signal is extracted by canceling noise and DC components using two sensors. The proposed circuit was evaluated using actual measurements and the total consumption current was 26.9 μA. The root mean square error of the heartbeat interval was 4.27 ms, even though the sensor was worn on the wrist during the experiment.
    Institute of Electrical and Electronics Engineers Inc., Oct. 2019, Proceedings of IEEE Sensors, 2019-, English
    International conference proceedings

  • Seiya Yoshida, Shintaro Izumi, Koichi Kajihara, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents an energy-efficient spectral analysis method for the Internet of Things (IoT). The objective of this paper is to reduce the energy consumption of edge devices. The proposed method uses an autoregressive (AR) model for spectral analysis instead of the discrete Fourier transform, and its calculation process is distributed to the edge device and a base station by considering the energy consumption tradeoff of the data processing and the data communication. In this paper, the Yule-Walker method is employed for the AR coefficient calculation. The calculation process of Yule-Walker method can be divided into two parts: an autocorrelation calculation and an AR coefficient calculation. The autocorrelation calculation is implemented in the edge devices, and its dedicated hardware is designed using Verilog HDL. Meanwhile, the AR coefficient is calculated in the base station and is used for the spectral analysis. According to this distributed processing approach, the energy consumption of the edge device can be reduced compared with conventional DFT approaches using the fast Fourier transform (FFT). The system level energy consumption is evaluated assuming the IoT edge device, which has a wireless transceiver using Bluetooth low energy. The evaluation results show that the proposed method can reduce 79% of the edge device energy consumption for spectral analysis in a practical application.
    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, Oct. 2019, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 66(10) (10), 3896 - 3905, English
    [Refereed]
    Scientific journal

  • Shintaro Izumi, Tatsuya Nagano, Asuka Yoshizaki, Yoshihiro Nishimura
    This paper describes an automatic classification algorithm for nocturnal hypoxemia in patients receiving home oxygen therapy (HOT). Nocturnal hypoxemia is a well-known complication in patients with chronic respiratory disease, and the number of patients receiving HOT has increased in recent years. Many studies have reported that 40% of patients receiving HOT have sleep-related oxygen desaturation. To deal with this situation, a nocturnal pulse oximetry is used to measure oxygen saturation (SpO2) and control the flow rate of highly concentrated oxygen. However, in some cases, the flow rate is not controlled properly and the same flow rate is adopted both during the day and night. There are several types of nocturnal hypoxemia, and it is difficult to classify these types only according to a subjective assessment of a medical doctor. Furthermore, it is difficult to continuously monitor the measurement results of pulse oximetry, although a flexible treatment depending on the state of hypoxemia is desired. To overcome these difficulties, an automatic classification method for SpO2 measured by the nocturnal pulse oximetry is proposed in this paper. The proposed method uses the time domain waveform and the frequency characteristics of SpO2. The classification performance of the method is evaluated by using 48 measured SpO2 values from patients receiving the HOT. The classification results are validated with decisions of ten chest physicians.
    IEEE, Jul. 2019, Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual International Conference, 2019, 3662 - 3665, English, International magazine
    [Refereed]
    Scientific journal

  • Masahiko Yoshimoto, Shintaro Izumi
    This paper surveys advances in biomedical processor SoC technology for healthcare application and reviews state-of-the-art architecture and circuits used in SoC integration. Particularly, this paper categorizes and describes techniques for improving power efficiency in communication, computation, and sensing. Additionally, it surveys accuracy enhancement techniques for bio-signal measurement and recognition. Finally, we have discussed the potential new directions for development as well as research.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2019, IEICE TRANSACTIONS ON ELECTRONICS, E102C(4) (4), 245 - 259, English
    [Refereed]
    Scientific journal

  • Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents a low-energy 64-Kb eighttransistor (8T) one-read/one-write dual-port image memory with a 28-nm fully depleted SOI (FD-SOI) process technology. Our proposed SRAM adopts a selective sourceline drive (SSD) scheme and a consecutive data write technique for improving active energy efficiency at low voltage. The novel SSD scheme controls sourceline voltage and eliminates leakage energy at unselected columns in read operations. We fabricated a 64-Kb 8T dual-port SRAM in the 28-nm FD-SOI process technology. The 81 SRAM cell size is 0.291 x 1.457 mu m(2). The test chip exhibits 0A8-V operation at an access time of 135 ns. The energy minimum point is at a supply voltage of 0.56 V and an access time of 35 ns, where 265.0 fJ/cycle in write operations and 389.6 fJ/cycle in read operations are achieved. These factors are, respectively, 30% and 26% smaller than those of the 8T dual-port SRAM with the conventional scheme.
    Institute of Electrical and Electronics Engineers ({IEEE}), Apr. 2019, IEEE Transactions on Circuits and Systems I: Regular Papers, 66(4) (4), 1442 - 1453, English
    [Refereed]
    Scientific journal

  • Yuji Yano, Seiya Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Tetsuya Hirose, Masaya Miyahara, Teruki Someya, Kenichi Okada, Ippei Akita, Yoshihiko Kurui, Hideyuki Tomizawa, Masahiko Yoshimoto
    IEEE, 2019, IEEE Asian Solid-State Circuits Conference(A-SSCC), 267 - 270
    [Refereed]
    International conference proceedings

  • Seiya Yoshida, Shintaro Izumi, Yuki Nishikawa, Kento Watanabe, Kana Sasai, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents an error compensation method for heartbeat intervals measured by a photoplethysmography (PPG) sensor. The objective of this work is to improve the accuracy of heart rate variability analysis (HRVA) using PPG, because a peak-to-peak interval (PPI) of the PPG has an error when compared with R to R interval (RRI) of electrocardiograph (ECG). This error is caused by several factors such as blood pressure fluctuation, body motion artifact, and body position. The proposed method predicts RRI using multiple regression analysis with time series of PPIs. The predicted RRI using the proposed method can also reduce the error of frequency characteristics, which are used for HRVA. Evaluation results with three subjects show that the proposed method achieved about 30% mean absolute error (MAE) reduction for predicted RRI and 17% mean absolute percentage error (MAPE) of LF/HF index of HRV analysis.
    IEEE, 2019, 2019 IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE (BIOCAS 2019), 1 - 4, English
    [Refereed]
    International conference proceedings

  • Araki, Teppei, den Toonder, Jaap M. J., Suganuma, Katsuaki, Uemura, Takafumi, Noda, Yuki, Yoshimoto, Shusuke, Izumi, Shintaro, Sekitani, Tsuyoshi
    The roll-to-roll process is synonymous with newspaper production. If a similar high-throughput process is developed to fabricate electronics over large areas, it would revolutionize the printed electronics manufacturing process. Rapid fabrication of electrode, including patterning and nanoscale welding, is a necessary integration technique to reduce the duration of the process, but faces difficulties in being realized using conventional methods. This paper discusses material factors that affect printability, in the context of developing a promising fabrication technique called laser induced forward transfer (LIFT); LIFT is non-contact printing technique applied previously to realize simultaneous pattern deposition and nanowelding of Ag nanowire (AgNW)-based electrodes. A photodegradable polymer, which is a key component in the printing process to render droplet acceleration, is investigated with regards to its mechanical and optical properties. Furthermore, the printing process of the AgNW-based electrode is visualized, resulting in deeper understanding of LIFT. Knowledge of these factors will contribute to rapid and precise patterning of AgNW-based electrodes with high stretchability and transparency toward flexible optoelectronics devices.
    TECHNICAL ASSOC PHOTOPOLYMERS,JAPAN, 2019, JOURNAL OF PHOTOPOLYMER SCIENCE AND TECHNOLOGY, 32(3) (3), 429 - 434, English
    [Refereed]
    Scientific journal

  • Misaki Inaoka, Shintaro Izumi, Shusuke Yoshimoto, Toshikazu Nezu, Yuki Noda, Teppei Araki, Takafumi Uemura, Tsuyoshi Sekitani
    A test equipment that can evaluate the contact resistance and amount of noise of biosignal sensors is proposed in this study. Biosignals such as EEG are easily masked by the noise derived from contact resistance, because of their feebleness. To realize a low-noise measurement, the contact resistance and the amount of noise of biosignal sensors need to be investigated accurately prior to measuring the biosignal. A pseudo-skin made of conductive rubber was employed in this study to evaluate the performance of the sensors objectively and efficiently, similar to actual working conditions. The proposed device is composed of the pseudo-skin, signal-generating circuits to imitate EEG signals and pseudo hum noise on a minute scale, and a coil to emit the pseudo hum noise into the test space. The contact resistance of the pseudoskin can be compared to that of human foreheads. The experimental results indicated that the standard deviation of the contact resistance of the pseudo-skin is 1.70, which is smaller than that of the human foreheads, which is 6.64. This result demonstrated that the pseudo-skin is suitable for contact resistance evaluation of the biosignal sensors. In addition, the correlation between contact resistance and the amount of noise was evaluated to assess the validity of the system. The amount of noise obtained was 597.37 mu Vrms, 1063.09 mu Vrms, and 1694.04 mu Vrms for the conductive gels with contact resistances of 32.65 k Omega, 85.17 k Omega, and 405 k Omega, respectively. An increase in the amount of noise with the increasing contact resistance was observed from the results. Further improvement of the device and an intensive study of the evaluation method of noise are required in future, in order to establish an efficient evaluation method for biosignal sensors.
    IEEE, 2019, 2019 13TH INTERNATIONAL SYMPOSIUM ON MEDICAL INFORMATION AND COMMUNICATION TECHNOLOGY (ISMICT), 1 - 4, English
    [Refereed]
    International conference proceedings

  • Shintaro Izumi, Takaaki Okano, Daichi Matsunaga, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a non-contact and noise-tolerant heart rate monitoring system using a 24-GHz microwave Doppler sensor. The microwave Doppler sensor placed at some distance from the user's chest detects the small vibrations of the body surface due to the heartbeats. The objective of this work is to detect the instantaneous heart rate (IHR) using this non-contact system in a car, because the possible application of the proposed system is a driver health monitoring based on heart rate variability analysis. IHR can contribute to preventing heart-triggered disasters and to detect mental stress state. However, the Doppler sensor system is very sensitive and it can be easily contaminated by motion artifacts and road noise especially while driving. To address this problem, time-frequency analysis using the parametric method and template matching method are employed. Measurement results show that the Doppler sensor, which is pasted on the clothing surface, can successfully extract the heart rate through clothes. The proposed method achieves 13.1-ms RMS error in IHR measurements conducted on 11 subjects in a car on an ordinary road.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2019, IEICE Trans. Commun., 102-B(6) (6), 1088 - 1096, English
    [Refereed]
    Scientific journal

  • YAMADA Kazuki, MORI Haruki, YOUKAWA Tetsuya, MIYAUCHI Yuki, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi

    This paper describes short-term pre-training (STPT) algorism to adaptively select an optimum learning rate (LR). The proposed STPT algorism is beneficial for quick model prototyping in data-parallel deep learning. It adaptively finds an appropriate LR from multiple LR sets by STPT, which means the multiple LRs are evaluated within the beginning few iterations in an epoch. The STPT short cuts the tuning process of LRs that is requested in conventional training procedure as hyper-parameter tuning, even if the unknown models are considered. Therefore, the proposed STPT reduces computational time and increases throughput to find the best LR for network training. This algorism reduces the computational time by 87.5% than the conventional method when the eight-LR sets are evaluated using eight-parallel workers. We verified the accuracy improvement by 4.8 % compared with the conventional one with a reference LR of 0.1; there are no accuracy deterioration is observed. In this algorism, better training convergence is shown and expresses the advantage in terms of training time especially for the unknown models than other cases such as fixed LR.

    The Japanese Society for Artificial Intelligence, 2019, Proceedings of the Annual Conference of JSAI, 2019(0) (0), 2H3J202 - 2H3J202, Japanese

  • 西河有貴, 和泉慎太郎, 矢野祐二, 川口博, 吉本雅彦
    This report describes a sampling rate reduction method for heart rate variability monitoring with a wearable device. This work was conducted to realize low-power measurement of biological signals necessary for heart rate variability (HRV) analysis. Continuous operation of the wearable device is an important factor for daily life monitoring. Therefore, the active time of the measuring circuit must be minimized. To reduce the required sampling rate, we propose a sampling error reduction method using interpolation and correlation of the heartbeat waveform. The proposed method is evaluated using measured electrocardiograms from five subjects. Evaluation results demonstrate that the sampling rate can be reduced to 32 Hz with 1 ms RMS error in heartbeat interval and 1.04% LF/HF degradation in HRV analysis.
    Institute of Electrical Engineers of Japan, Oct. 2018, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 35, 5p - 5, Japanese

  • Motofumi Nakanishi, Shintaro Izumi, Sho Nagayoshi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Toshikazu Shiga, Takafumi Ando, Satoshi Nakae, Chiyoko Usui, Tomoko Aoyama, Shigeho Tanaka
    BACKGROUND: Herein, an algorithm that can be used in wearable health monitoring devices to estimate metabolic equivalents (METs) based on physical activity intensity data, particularly for certain activities in daily life that make MET estimation difficult. RESULTS: Energy expenditure data were obtained from 42 volunteers using indirect calorimetry, triaxial accelerations and heart rates. The proposed algorithm used the percentage of heart rate reserve (%HRR) and the acceleration signal from the wearable device to divide the data into a middle-intensity group and a high-intensity group (HIG). The two groups were defined in terms of estimated METs. Evaluation results revealed that the classification accuracy for both groups was higher than 91%. To further facilitate MET estimation, five multiple-regression models using different features were evaluated via leave-one-out cross-validation. Using this approach, all models showed significant improvements in mean absolute percentage error (MAPE) of METs in the HIG, which included stair ascent, and the maximum reduction in MAPE for HIG was 24% compared to the previous model (HJA-750), which demonstrated a 70.7% improvement ratio. The most suitable model for our purpose that utilized heart rate and filtered synthetic acceleration was selected and its estimation error trend was confirmed. CONCLUSION: For HIG, the MAPE recalculated by the most suitable model was 10.5%. The improvement ratio was 71.6% as compared to the previous model (HJA-750C). This result was almost identical to that obtained from leave-one-out cross-validation. This proposed algorithm revealed an improvement in estimation accuracy for activities in daily life; in particular, the results included estimated values associated with stair ascent, which has been a difficult activity to evaluate so far.
    BMC, Jul. 2018, Biomedical engineering online, 17(1) (1), 100 - 100, English, International magazine
    [Refereed]
    Scientific journal

  • Kento Watanabe, Shintaro Izumi, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents a low-power Photoplethysmography (PPG) sensing method. The PPG is commonly used in recent wearable devices to detect cardiovascular information including heartbeat. The heartbeat is useful for physical activity and stress monitoring. However, the PPG circuit consumes large power because it consists of LED and photodiode. To reduce its power consumption without accuracy degradation, a cooperative design of circuits and algorithms is proposed in this work. A straightforward way to reduce the power is intermittent driving of LED, but there is a disadvantage that the signal is contaminated by a noise while circuit switching. To overcome this problem, we introduce correlated double sampling (CDS) method, which samples an integration circuit output twice with short intervals after the LED turns on and uses the difference of these voltage. Furthermore, an up-conversion method using linear interpolation, and an error correction using autocorrelation are introduced. The proposed PPG sensor, which consists of the LED, the photodiode, the current integration circuit, a CMOS switch, an A/D converter, and an MCU, is prototyped. It is evaluated by actual measurement with 22-year-old subject. The measurement results show that 22-μA total current consumption is achieved with 5-ms mean absolute error.
    Jul. 2018, Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual International Conference, 2018, 5566 - 5569, English, International magazine
    [Refereed]
    Scientific journal

  • マイクロ波ドップラーセンサを用いた非接触生体認証
    OKANO Takaaki, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    電子情報通信学会, Mar. 2018, 信学技報, vol. 117, no. 511, MICT2017-54, pp. 17-20, 2018年3月, 117(511) (511), 17 - 20, Japanese

  • Shintaro Izumi, Kenji Kimura, Yusuke Takeda, Shokichi Tsukamoto, Miki Yamazaki, Tatsuzo Mishina, Yurie Nagai, Koji Takaishi, Yuhei Nagao, Nagisa Oshima-Hasegawa, Shio Mitsukawa, Naoya Mimura, Masahiro Takeuchi, Chikako Ohwada, Tohru Iseki, Satoshi Ota, Chiaki Nakaseko, Emiko Sakaida
    A 60-year-old man with chronic hepatitis C was referred to our hospital with significantly elevated total protein and serum IgM (9,500 mg/dl) levels identified via a routine checkup. Blood examination revealed increased serum IgM-monoclonal protein and serum-soluble IL-2 receptor (sIL2R) levels. Computed tomography and fluorodeoxyglucose positron emission tomography revealed pulmonary masses, abnormal soft tissue masses surrounding the bilateral kidneys, and thickened mucous membrane of the bladder with high fluorodeoxyglucose uptake. Pathological examination of the pulmonary mass revealed infiltration of medium-sized lymphocytes and plasma cells. Immunohistochemical analysis revealed tumor cells positive for CD138 and IgM, with a low positive rate of Ki-67 expression. Notably, the tumor cell-surrounding lymphocytes were positive for CD20. Although the patient was initially regarded as having Waldenström's macroglobulinemia owing to the significantly increased serum IgM levels, based on positive IgH-MALT1 translocation and negative MYD88 L265P mutation findings, he was further diagnosed with extranodal marginal zone lymphoma of mucosa-associated lymphoid tissue (MALT lymphoma). Complete remission was achieved following six cycles of rituximab + CHOP therapy. This study data suggest that analysis of the MYD88 L265P mutation in tumor cells is suitable for accurately diagnosing hematopoietic malignancies with increased IgM monoclonal protein.
    2018, [Rinsho ketsueki] The Japanese journal of clinical hematology, 59(12) (12), 2600 - 2605, Japanese, Domestic magazine
    Scientific journal

  • Go Matsukawa, Taisuke Kodama, Yuri Nishizumi, Koichi Kajihara, Chikako Nakanishi, Shintaro Izumi, Hiroshi Kawaguchi, Toshio Goto, Takeo Kato, Masahiko Yoshimoto
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2018, IEICE Electron. Express, 15(12) (12), 20188003 - 20188003, English
    [Refereed]
    Scientific journal

  • Motofumi Nakanishi, Shintaro Izumi, Mio Tsukahara, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Masahiko Yoshimoto
    This paper presents an algorithm for a physical activity (PA) classification and metabolic equivalents (METs) monitoring and its System-on-a-Chip (SoC) implementation to realize both power reduction and high estimation accuracy. Long-term PA monitoring is an effective means of preventing lifestyle-related diseases. Low power consumption and long battery life are key features supporting the wider dissemination of the monitoring system. As described herein, an adaptive sampling method is implemented for longer battery life by minimizing the active rate of acceleration without decreasing accuracy. Furthermore, advanced PA classification using both the heart rate and acceleration is introduced. The proposed algorithms are evaluated by experimentation with eight subjects in actual conditions. Evaluation results show that the root mean square error with respect to the result of processing with fixed sampling rate is less than 0.22 [METs], and the mean absolute error is less than 0.06 [METs]. Furthermore, to minimize the system-level power dissipation, a dedicated SoC is implemented using 130-nm CMOS process with FeRAM. A nonvolatile CPU using non-volatile memory and a flip-flop is used to reduce the stand-by power. The proposed algorithm, which is implemented using dedicated hardware, reduces the active rate of the CPU and accelerometer. The current consumption of the SoC is less than 3-mu A. And the evaluation system using the test chip achieves 74% system-level power reduction. The total current consumption including that of the accelerometer is 11.3-mu A on average.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2018, IEICE Trans. Electron., 101-C(4) (4), 233 - 242, English
    [Refereed]
    Scientific journal

  • Koichi Kajihara, Shintaro Izumi, Seiya Yoshida, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We present a hardware implementation of Burg's method, which is used for autoregressive (AR) model estimation. The AR model is a linear predictive modeling technique. It assumes that the current value of a signal can be described by a finite linear aggregate of the previous values. The AR model can be used for spectral analysis as an alternative to the Fourier transform. This approach is a parametric method, and it can yield higher resolutions than nonparametric methods in cases when the signal length is short. Although Burg's method requires a large computational capacity, especially with higher model orders, a fast Burg's method has been proposed for improving this draw back. In this study, we evaluate the influence of the order and the data length of Burg's method on the computational capacity. The hardware implementation method of the fast Burg's method including a two-stage pipeline architecture and a parallelization technique for autocorrelation calculations is proposed. The proposed method is implemented using Verilog HDL and its energy consumption is estimated with the 65-nm CMOS process. The evaluation result shows that the proposed method achieves an energy consumption of 21.6-361.4 nJ for the spectral estimation with a data length of 128-2048 points when the model order is 5.
    IEEE, 2018, PROCEEDINGS OF THE 2018 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), 199 - 204, English
    [Refereed]
    International conference proceedings

  • Tetsuya Youkawa, Haruki Mori, Yuki Miyauchi, Kazuki Yamada, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    This paper presents a proposal of a data-parallel stochastic gradient descent (SGD) using delayed weight update. A large-scale neural network appears to solve advanced problems, but its processing time increases concomitantly with the network scale. For conventional data parallelism, workers must wait for data communication to and from a server during weight updating. Using the proposed data-parallel method, the network weight has a delay. It is therefore stale. Nevertheless, it gives faster convergence time by hiding the latency of the weight communication for the server. The server concurrently carries out the weight communication and weight update while workers calculate their gradients. The experimentally obtained results demonstrate that, in the proposed data parallel method, the final accuracy converges within degradation of 1.5% compared with the conventional method in both VGG and ResNet At maximum, the convergence speedup factor theoretically reaches double that of conventional data parallelism.
    IEEE, 2018, 2018 IEEE GLOBAL CONFERENCE ON SIGNAL AND INFORMATION PROCESSING (GLOBALSIP 2018), 663 - 667, English
    [Refereed]
    International conference proceedings

  • Layer Skip Learning using LARS variables for 39% Faster Conversion Time and Lower Bandwidth
    Miyauchi, Yuki, Mori, Haruki, Youkawa, Tetsuya, Yamada, Kazuki, Izumi, Shintaro, Yoshimoto, Masahiko, Kawaguchi, Hiroshi, Inoue, Atsuki
    In this paper, a method for the improvement of the relationship between calculation time and recognition accuracy in deep learning is proposed. A major problem with respect to deep learning is that a large calculation time is required for higher recognition accuracy. Because of this problem, the implementation of deep learning in hardware and its application to real problems are limited. In this study, layer-wise adaptive rate scaling (LARS) variables are adopted to evaluate the necessity of the learning of each layer. When the variable of a certain convolution layer exceeds the threshold value, the learning for that layer is considered unnecessary; thus, the layer is skipped. When a layer recognized as the layer that does not require learning, only the lower layers below than that layer are learned in the next epoch. By adaptively skipping the layer, the calculation time is reduced. Furthermore, the recognition accuracy is improved. Consequently, the proposed methods accelerate the calculation time in VGG-F to achieve the highest accuracy for the top1 and top5 test accuracy by a speed up factor of 2.14, and 2.25, respectively. Moreover, the respective topl and top5 test accuracy was improved by 3.0 %, and 2.8% which obtained as the final accuracy. In addition, the operation process was reduced by approximately 39.0 %, and required bandwidth was reduced by 38.9 %, when compared with the case of conventional full layer learning.
    IEEE, 2018, 2018 25TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 673 - 676, English
    [Refereed]
    International conference proceedings

  • Haruki Mori, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents low-power and low-energy 8T dual-port SRAM with a novel MSB-based (most-significant-bit-based) inversion logic for an image processor such a deep learning processor. Our proposed SRAM is suitable for real-time and low-power image processing, in which data have statistical correlation and data bit reordering are exploited. The proposed MSB-based inversion logic eliminates an additional flag bit in a majority logic; the MSB digit in an input datum judges whether or not to invert the datum. Thus, the area overhead of 12.5 % for the 8-bit conventional majority logic is dramatically saved. The area overhead of the proposed SRAM is merely 0.6% for the MSB-based inversion logic. We verified that, with the proposed technique, 14.76 % of total energy can be saved in a 28-nm 64-kb FD-SOI SRAM when a set of images are read out. Furthermore, the saving factor is extended to 17.31 % when image processing in the VGG-F convolutional neural network (CNN) is considered, where 304.81 fJ/cycle in the read operation is achieved.
    IEEE, 2018, 2018 25TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 161 - 164, English
    [Refereed]
    International conference proceedings

  • Takaaki Okano, Shintaro Izumi, Takumi Katsuura, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This article describes a multimodal cardiovascular information measurement method using a wearable device composed of piezoelectric transducers. Cardiovascular diseases are increasing with the aging population, and they constitute a significant portion of the causes of death and long-term care. In recent years, daily-life monitoring using wearable sensor devices has attracted particular attention for the prevention and early detection of cardiovascular diseases. However, recent wearable devices can only measure limited cardiovascular information such as the heart rate. In contrast, the proposed method can simultaneously measure heart rate variability, pulse wave propagation velocity, and blood flow velocity using only a piezoelectric transducer array.
    Institute of Electrical Engineers of Japan, Oct. 2017, J. Signal Process. Syst., 34(9) (9), 1 - 6, Japanese
    [Refereed]

  • Takaaki Okano, Shintaro Izumi, Takumi Katsuura, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This report describes a multimodal cardiovascular information measurement method using a wearable sensor device. With the progress of aging populations worldwide, cardiovascular diseases are increasing. Such diseases account for a large share of causes of death and constitute the main cause of long-term care. Along with the miniaturization and longer life of measuring instruments in recent years, constant monitoring of biological information using a wearable biosensor has attracted attention for the prevention and early detection of cardiovascular diseases. However, today's wearable devices can only measure limited cardiovascular information such as the heart rate. Therefore, we propose a method that can simultaneously measure heart rate variation, pulse wave propagation velocity, and blood flow velocity with a single device equipped with a piezoelectric transducer array.
    Institute of Electrical Engineers of Japan, Oct. 2017, J. Signal Process. Syst., 34(9) (9), 1 - 6, Japanese

  • Non-Contact Biometric Identification and Authentication Using Microwave Doppler Sensor
    OKANO Takaaki, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Oct. 2017, The 13th IEEE BioMedical Circuits and Systems Conference(BioCAS), pp.392-395, Oct. 2017., 392 - 395, English
    [Refereed]
    International conference proceedings

  • Ryota Nakamura, Shintaro Izumi, Hiroshi Kawaguchi, Hidetoshi Ohta, Masahiko Yoshimoto
    This paper presents a swallowable sensor device that can be ingested orally, later passing to the stomach, where the device can indwell for long periods. Using wireless communication, it can be egested at any time after it is triggered. This device can indwell using a silicone balloon in the gastrointestinal tract. A chemical reaction inflates the balloon inside the stomach. Then it is deflated to egest the sensor device using an actuator with electrolysis of water. Energy for the actuator with electrolysis can be fed wirelessly. Near field communication and a flexible antenna are used for power feeding and wireless data communication. Because of the flexible balloon and the flexible antenna, the device size can be minimized without performance degradation.
    IEEE, Jul. 2017, Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual International Conference, 2017, 3040 - 3043, English, International magazine
    [Refereed]
    Scientific journal

  • A contact-less heart rate sensor system for driver health monitoring
    IZUMI Shintaro, MATSUNAGA Daichi, NAKAMURA Ryota, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Jul. 2017, The 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC’17), July. 2017, English
    International conference proceedings

  • UMEKI Yohei, IZUMI Shintaro, KITAHARA Hiroto, NAKAGAWA Tomoki, YANAGIDA Kouji, YOSHIMOTO Shusuke, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, KIMURA Hiromitsu, MARUMOTO Kyoji, FUCHIKAMI Takaaki, FUJIMORI Yoshikazu
    神戸大学大学院工学研究科, Feb. 2017, Memoirs of the Graduate Schools of Engineering and SystemInformatics Kobe University, no. 8, pp. 5-8, Feb. 2017., 8, English
    [Refereed]
    Research institution

  • Takashi Nakada, Shinobu Fujita, Masanori Hayashikoshi, Shintaro Izumi, Yoshikazu Fujimori, Hiroshi Nakamura
    Based on normally-off computing design methodology, we developed three practical systems that introduced normally-off computing. These systems are healthcare, mobile information device and sensor node for social infrastructure. These systems are selected from different types of application areas. Through implementing a variety of systems, universalness of normally-off computing is confirmed. Also we introduce our “Normally-Off Computing Project”, which supports these practical developments.
    Springer Japan, Jan. 2017, Normally-Off Computing, 103 - 127, English
    [Refereed]
    In book

  • Go Matsukawa, Taisuke Kodama, Yuri Nishizumi, Koichi Kajihara, Chikako Nakanishi, Shintaro Izumi, Hiroshi Kawaguchi, Toshio Goto, Takeo Kato, Masahiko Yoshimoto
    This paper describes a low-power object recognition processor VLSI for HDTV resolution video at 60 frames per second (fps) using an object recognition algorithm with Sparse FIND features. The VLSI processor features two-stage feature extraction processing by HOG and Sparse FIND, a highly parallel classification in the support vector machine (SVM), and a block-parallel processing for RAM access cycle reduction. Compared to the accuracy by the original Sparse FIND algorithm, the two-stage object detection demonstrates insignificant accuracy degradation. Using this architectural design, a 60 fps performance for object recognition of HDTV resolution video was attained at an operating frequency of 130 MHz. This 3.35 x 3.35 mm(2) chip, designed with 40 nm CMOS technology, contains 8.22 M gates and 5 Mb SRAM in the chip of 3.35 x 3.35 mm(2). The simulated power consumption at 133 MHz were 528 mW and 702 mW at the slow process condition (SS, 0.81 V, -40 degrees C) and typical process condition (TT, 0.9 V, 25 degrees C), respectively.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2017, IEICE Electronic Express, 14(15) (15), 20170668 - 20170668, English
    [Refereed]
    Scientific journal

  • Mio Tsukahara, Shintaro Izumi, Motofumi Nakanashi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Hiromitsu Kimura, Kyoji Maromoto, Takaaki Fuchikami, Yoshikazu Fujimori
    This paper presents a low-power metabolic equivalents (METs) estimation SoC for monitoring physical activity with wearable sensor. Long-term continuous METs monitoring can contribute to detection of non-communicable diseases. The proposed SoC consists of a non-volatile CPU and a dedicated hardware for heart rate extraction and METs estimation to reduce the power consumption. A test chip is fabricated in a 130-nm CMOS process. Evaluation results show that the proposed system, which consists of the test chip and an accelerometer, consumes about 19-mu A on average.
    IEEE, 2017, 2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 37 - 38, English
    [Refereed]
    International conference proceedings

  • A LAYER-BLOCK-WISE PIPELINE FOR MEMORY AND BANDWIDTH REDUCTION IN DISTRIBUTED DEEP LEARNING
    Mori, Haruki, Youkawa, Tetsuya, Izumi, Shintaro, Yoshimoto, Masahiko, Kawaguchi, Hiroshi, Inoue, Atsuki
    This paper describes a pipelined stochastic gradient descent (SGD) algorithm and its hardware architecture with a memory distributed structure. In the proposed architecture, a pipeline stage takes charge of multiple layers: a "layer block." The layer-block-wise pipeline has much less weight parameters for network training than conventional multithreading because weight memory is distributed to workers assigned to pipeline stages. The memory capacity of 2.25 GB for the four-stage proposed pipeline is about half of the 3.82 GB for multithreading when a batch size is 32 in VGG-F. Unlike multithreaded data parallelism, no parameter server for weight update or shared I/O data bus is necessary. Therefore, the memory bandwidth is drastically reduced. The proposed four-stage pipeline only needs memory bandwidths of 36.3 MB and 17.0 MB per batch, respectively, for forward propagation and backpropagation processes, whereas four-thread multithreading requires a bandwidth of 974 MB overall for send and receive processes to unify its weight parameters. At the parallelization degree of four, the proposed pipeline maintains training convergence by a factor of 1.12, compared with the conventional multithreaded architecture although the memory capacity and the memory bandwidth are decreased.
    IEEE, 2017, 2017 IEEE 27TH INTERNATIONAL WORKSHOP ON MACHINE LEARNING FOR SIGNAL PROCESSING, English
    [Refereed]
    International conference proceedings

  • Takumi Katsuura, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Shusuke Yoshimoto, Tsuyoshi Sekitani
    IEEE, 2017, Proc. of IEEE Biomedical Circuits and Systems Conference (BioCAS), pp. 721–724, Oct. 2017, 1 - 4, English
    [Refereed]
    International conference proceedings

  • FPGA Implementation of Object Recognition Processor for HDTV Resolution Video Using Sparse FIND Feature
    Nishizumi, Yuri, Matsukawa, Go, Kajihara, Koichi, Kodama, Taisuke, Izumi, Shintaro, Kawaguchi, Hiroshi, Nakanishi, Chikako, Goto, Toshio, Kato, Takeo, Yoshimoto, Masahiko
    This paper describes FPGA implementation of object recognition processor for HDTV resolution 30 fps video using the Sparse FIND feature. Two-stage feature extraction processing by HOG and Sparse FIND, a highly parallel classification in the support vector machine (SVM), and a block-parallel processing for RAM access cycle reduction are proposed to perform a real time object recognition with enormous computational complexity. From implementation of the proposed architecture in the FPGA, it was confirmed that detection using the Sparse FIND feature was performed for HDTV images at 47.63 fps, on average, at 90 MHz. The recognition accuracy degradation from the original Sparse FIND-base object detection algorithm implemented on software was 0.5%, which shows that the FPGA system provides sufficient accuracy for practical use.
    IEEE, 2017, 2017 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), English
    [Refereed]
    International conference proceedings

  • Yuki Nagasato, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    IEEE, 2017, The 13th IEEE BioMedical Circuits and Systems Conference(BioCAS), pp.400-403, Oct. 2017., 1 - 4, English
    [Refereed]
    International conference proceedings

  • A METABOLIC EQUIVALENTS ESTIMATION ALGORITHM USING TRIAXIAL ACCELEROMETER AND ADAPTIVE SAMPLING FOR WEARABLE DEVICES
    Nakanishi, Motofumi, Izumi, Shintaro, Tsukahara, Mio, Kawaguchi, Hiroshi, Yoshimoto, Masahiko
    This study describes a low-power metabolic equivalents estimation method. Low-power consumption is a key feature of wearable devices because it requires longer battery-life with small battery capacity. The proposed algorithm employs adaptive sampling for reducing the energy consumed by an accelerometer and by signal processing. The sampling frequency is adaptively changed according to an estimated physical activity group. Evaluation of the results shows that the sampling rate can be reduced by 86%, and there is 0.1 metabolic equivalents RMS error compared with a reference values. And it is seen that there is no significant error compared with other prediction methods in spite of very low average sampling frequency with proposed algorithm.
    IEEE, 2017, 2017 IEEE LIFE SCIENCES CONFERENCE (LSC), 107 - 110, English
    [Refereed]
    International conference proceedings

  • 産科を含む混合病棟における看護者の動線解析
    齋藤 いずみ, 和泉 慎太郎, 大滝 千文
    (公社)日本新生児成育医学会, Nov. 2016, 日本新生児成育医学会雑誌, 28(3) (3), 736 - 736, Japanese

  • 産科を含む混合病棟における情報通信技術を活用した看護可視化システムの検討
    和泉 慎太郎, 大滝 千文, 齋藤 いずみ
    (公社)日本新生児成育医学会, Nov. 2016, 日本新生児成育医学会雑誌, 28(3) (3), 737 - 737, Japanese

  • 消化管内へ留置する飲み込型センサの検討
    NAKAMURA Ryota, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, OHTA Hidetoshi
    Sep. 2016, 電気学会C部門大会, 2016年9月1日,神戸, 2016, Japanese

  • 加速度センサを用いた低消費電力運動強度推定アルゴリズム
    TSUKAHARA Mio, NAKANISHI Motofumi, IZUMI Shintaro, NAKAI Yozaburo, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Sep. 2016, 電気学会C部門大会, 2016年9月1日,神戸., 2016, Japanese

  • 加速度センサを用いた低消費電力運動強度推定アルゴリズム
    TSUKAHARA Mio, NAKANISHI Motofumi, IZUMI Shintaro, NAKAI Yozaburo, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Sep. 2016, IEICEソサイエティ大会, 2016年9月21日,札幌, 2016, Japanese
    Symposium

  • Ryota Nakamura, Shintaro Izumi, Hiroshi Kawaguchi, Hidetoshi Ohta, Masahiko Yoshimoto
    This paper presents a swallowable sensor device that can be ingested orally, later arriving to the stomach, where the device can indwell for a long term and can be egested at any time after it is triggered using wireless communication. This device can inflate a silicone balloon in the gastrointestinal tract using a chemical reaction. The balloon can be deflated later using electrolysis of water at the time of egestion. A motorless chemical-reaction-based egestion method is proposed to minimize the sensor device size. This device can achieve long-term monitoring in the gastrointestinal tract.
    IEEE, Aug. 2016, Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual International Conference, 2016, 3039 - 3042, English, International magazine
    [Refereed]
    Scientific journal

  • Haruki Mori, Yohei Umeki, Shusuke Yoshimoto, Shintaro Izumi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using 28-nm FD-SOI process technology. Our proposed SRAM accommodates eight-transistor bit cells comprising one-write/two-read ports and a majority logic circuit to save active energy. The test chip operates at a supply voltage of 0.46V and access time of 140 ns. The minimum energy point is a supply voltage of 0.54V and an access time of 55 ns (= 18.2 MHz), at which 484 fJ/cycle in a write operation and 650 fJ/cycle in a read operation are achieved assisted by majority logic. These factors are 69% and 47% smaller than those in a conventional 6T SRAM using the 28-nm FD-SOI process technology.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Aug. 2016, IEICE TRANSACTIONS ON ELECTRONICS, E99C(8) (8), 901 - 908, English
    [Refereed]
    Scientific journal

  • Go Matsukawa, Yuta Kimi, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    As technology nodes continue to shrink, the impact of radiation-induced soft error on processor reliability increases. Estimation of processor reliability and identification of vulnerable flip-flops requires accurate soft error rate (SER) analysis techniques. This paper presents a proposal for a soft error propagation analysis technique. We specifically examine single event upset (SEU) occurring at a flip-flop in sequential circuits. When SEUs propagate in sequential circuits, the faults can be masked temporally and logically. Conventional soft error propagation analysis techniques do not consider error convergent timing on re-convergent paths. The proposed technique can analyze soft error propagation while considering error-convergent timing on a re-convergent path by combinational analysis of temporal and logical effects. The proposed technique also considers the case in which the temporal masking is disabled with an enable signal of the erroneous flip-flop negated. Experimental results show that the proposed technique improves inaccuracy by 70.590, on average, compared with conventional techniques using ITC 99 and ISCAS 89 benchmark circuits when the enable probability is 1/3, while the runtime overhead is only 1.79( on average.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jun. 2016, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E99A(6) (6), 1198 - 1205, English
    [Refereed]
    Scientific journal

  • 298-fJ/writecycle 650-fJ/readcycle を実現する画像処理プロセッサ向け 28-nm FD-SOI 8T 3ポートSRAM
    MORI Haruki, NAKAGAWA Tomoki, KITAHARA Yuki, KAWAMOTO Yuta, TAKAGI Kenta, YOSHIMOTO Shusuke, IZUMI Shintaro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    電子情報通信学会, Apr. 2016, 信学技報, vol.116, no.3, pp.13-16, 2016年4月14日,東京., 116(3) (3), 13 - 16, Japanese

  • Process variation tolerant counter base read circuit for low-voltage operating STT-MRAM
    UMEKI Yohei, YANAGIDA Kouji, KUROTSU Hiroaki, KITAHARA Hiroto, MORI Haruki, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, YOSHIMOTO Shusuke, TSUNODA Koji, SUGII Toshihiro
    Mar. 2016, DATE EMS Workshop, Mar. 2016, English
    [Refereed]
    International conference proceedings

  • Capacitively Coupled ECG Sensor using a Single Electrode with Adaptive Power-Line Noise Cancellation
    Yuta Kawamoto, Shintaro Izumi, Yoshito Tanaka, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This report describes a small heartbeat monitoring system using capacitively coupled ECG sensors. Capacitively coupled sensors using an insulated electrode have been proposed to obtain ECG signals without pasting electrodes directly onto the skin. Although the sensors have better usability than conventional ECG sensors, it is difficult to remove noise contamination. Power-line noise can be a severe noise source that increases when only a single electrode is used. However, a multiple electrode system degrades usability. To address this problem, we propose a noise cancellation technique using an adaptive noise feedback approach, which can improve the availability of the capacitive ECG sensor using a single electrode. An instrumental amplifier is used in the proposed method for the first stage amplifier instead of voltage follower circuits. A microcontroller predicts the noise waveform from an ADC output. To avoid saturation caused by power-line noise, the predicted noise waveform is fed back to an amplifier input through a DAC. We implemented the prototype sensor system to evaluate the noise reduction performance. Measurement results using a prototype board show that the proposed method can suppress 28-dB power-line noise.
    IEEE, 2016, 2016 3RD IEEE EMBS INTERNATIONAL CONFERENCE ON BIOMEDICAL AND HEALTH INFORMATICS, 212 - 215, English
    [Refereed]
    International conference proceedings

  • An Soft Error Propagation Analysis Considering Logical Masking Effect on Re-convergent Path
    Shuhei Yoshida, Go Matsukawa, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents an accurate soft error propagation analysis technique. Especially, we focus on Single Event Upset (SEU) in flip-flop. The proposed technique can calculate the accurate error propagation probability considering logical masking on re-convergent paths with SAT solver efficiently. Experimental result shows that the proposed technique improves the computation time by 94.6% compared with the method with only SAT solver and the accuracy by 93.3% compared with the conventional method respectively.
    IEEE, 2016, 2016 IEEE 22ND INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS), 13 - 16, English
    [Refereed]
    International conference proceedings

  • Mio Tsukahara, Motofumi Nakanishi, Shintaro Izumi, Yozaburo Nakai, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a proposed low-power metabolic equivalent estimation algorithm that can calculate the value of metabolic equivalents (METs) from triaxial acceleration at an adaptively changeable sampling rate. This algorithm uses four rates of 32, 16, 8 and 4 Hz. The mode of switching them is decided from synthetic acceleration. Applying this proposed algorithm to acceleration measured for 1 day, we achieved the low root mean squared error (RMSE) of calculated METs, with current consumption that was 41.5 % of the value at 32 Hz, and 75.4 % of the value at 16 Hz.
    IEEE, 2016, 2016 38TH ANNUAL INTERNATIONAL CONFERENCE OF THE IEEE ENGINEERING IN MEDICINE AND BIOLOGY SOCIETY (EMBC), 2016, 1878 - 1881, English, International magazine
    [Refereed]
    International conference proceedings

  • Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii
    In this paper, in order to realize 0.4V operation of STT-MRAM, we propose the counter base read circuit. The proposed read circuit has tolerance for process variation and temperature fluctuation by changing dynamically the load curve in a time-axis at the read operation. We confirmed that the proposed read circuit can operate at the conditions of five process corners (TT, FF, FS, SF, and SS) and three temperatures (-20°C, 25°C, and 100°C) by HSPICE simulations. At the condition of TT corner and 25°C, read time of the proposed circuit is 271 ns, and energy consumption is 1.05 pJ at "1" read operation and 1.23 pJ at "0" read operation.
    Information Processing Society of Japan, 2016, IPSJ Transactions on System LSI Design Methodology, 9, 79 - 83, English
    [Refereed]
    Scientific journal

  • Adaptive Noise Cancellation Method for Capacitively Coupled ECG Sensor using Single Insulated Electrode
    Yoshito Tanaka, Shintaro Izumi, Yuta Kawamoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a noise reduction method for capacitively coupled ECG sensors. Capacitively coupled sensors using an insulated electrode have been proposed to obtain ECG signals without pasting electrodes directly onto the skin. It can achieve better usability than conventional ECG sensors. However, it is difficult to remove noise contamination, because the high input impedance and low input capacitance are required to realize the capacitively coupled ECG sensor. Especially, base-line drift and power-line noise are more serious problem when using a single electrode structure. To address this problem, we propose a noise cancellation technique using an adaptive noise feedback approach, which can improve the availability of the capacitive ECG sensor using a single electrode. An instrumental amplifier is used in the proposed method for the first stage amplifier instead of voltage follower circuits. A microcontroller predicts the noise waveform from an ADC output. To avoid saturation caused by base-line drift and power-line noise, the predicted noise waveform is fed back to an amplifier input through a DAC. We implemented the prototype sensor system to evaluate the noise reduction performance. Measurement results show that the proposed method can suppress both of base-line drift and power-line noise simultaneously.
    IEEE, 2016, PROCEEDINGS OF 2016 IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE (BIOCAS), 296 - 299, English
    [Refereed]
    International conference proceedings

  • Daichi Matsunaga, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a non-contact heart rate monitoring system using a microwave Doppler sensor. It can achieve better usability than conventional heart rate sensors, which require direct skin contact. The objective of this work is to detect an instantaneous heart rate using this non-contact system. The instantaneous heart rate can contribute to prevent heart disasters and to detect mental stress state. However, the Doppler sensor system is very sensitive and it can be easily contaminated by a body motion artifact including breathing. To address this problem, we introduce time frequency analysis with short window length. The heart rate extraction performance with various parameters is evaluated using a measured Doppler sensor output with 4 subjects. The proposed method achieves 4.5-ms RMS error with 50-cm distance for heart rate extraction from 60 s duration data.
    IEEE, 2016, 2016 IEEE 16TH INTERNATIONAL CONFERENCE ON BIOINFORMATICS AND BIOENGINEERING (BIBE), 172 - 175, English
    [Refereed]
    International conference proceedings

  • An Low-Energy 8T Dual-Port SRAM for Image Processor with Selective Sourceline Drive Scheme in 28-nm FD-SOI Process Technology
    Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents a low-energy and low-voltage 64-kb 8T dual-port image memory in a 28-nm FD-SOI process technology. Our proposed SRAM adopts the selective sourceline drive (SSD) scheme and the consecutive data write technique for improving active energy efficiency at the low voltage. We fabricated a 64-Kb 8T dual-port SRAM in the 28-nm FD-SOI process technology; the test chip exhibits 0.48 V operation and an access time of 135 ns. The energy minimum point is at a supply voltage of 0.56 V and an access time of 35 ns, where 265.0 fJ/cycle in write operation and 389.6 fJ/cycle in read operation are achieved; these factors are 30% and 26% smaller than those in the 8T dual-port SRAM with the conventional selective sourceline control (SSLC) scheme, respectively.
    IEEE, 2016, 23RD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS CIRCUITS AND SYSTEMS (ICECS 2016), 532 - 535, English
    [Refereed]
    International conference proceedings

  • A 15-mu A Metabolic Equivalents Monitoring System using Adaptive Acceleration Sampling and Normally Off Computing
    Mio Tsukahara, Shintaro Izumi, Motofumi Nakanishi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori
    This paper describes a low-power metabolic equivalents (METs) estimation method for monitoring physical activity. Long-term continuous METs monitoring can contribute to detection of non-communicable diseases. The proposed system consists of dedicated METs estimation hardware and a nonvolatile CPU. A test is fabricated in a 130-nm CMOS with a ferroelectric capacitor process. Evaluation results show that the proposed system, which consists of the test chip and an accelerometer, requires about 15-A on average.
    IEEE, 2016, 23RD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS CIRCUITS AND SYSTEMS (ICECS 2016), 61 - 64, English
    [Refereed]
    International conference proceedings

  • Keisuke Okuno, Shintaro Izumi, Kana Masaki, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This report describes an all-digital phase-locked loop (ADPLL) using a temperature compensated settling time reduction technique. The novelty of this work is autonomous oscillation control word estimation without a look-up table or memory circuits. The proposed ADPLL employs a multi-phase digitally controlled oscillator (DCO). In the proposed estimation method, the optimum oscillator tuning word (OTW) is estimated from the DCO frequency characteristic in the setup phase of ADPLL. The proposed ADPLL, which occupies 0.27 x 0.36mm(2), is fabricated by a 65 nm CMOS process. The temperature compensation PLL controller (TCPC) is implemented using an FPGA. Although the proposed method has 20% area overhead, measurement results show that the 47% settling time is reduced. The average settling time at 25 degrees C is 3 mu s. The average reduction energy is at least 42% from 0 degrees C to 100 degrees C.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Dec. 2015, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E98A(12) (12), 2592 - 2599, English
    [Refereed]
    Scientific journal

  • Shintaro Izumi, Ken Yamashita, Masanao Nakano, Shusuke Yoshimoto, Tomoki Nakagawa, Yozaburo Nakai, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto
    This paper describes an electrocardiograph (ECG) monitoring SoC using a non-volatile MCU (NVMCU) and a noise-tolerant instantaneous heartbeat detector. The novelty of this work is the combination of the non-volatile MCU for normally off computing and a noise-tolerant-QRS (heartbeat) detector to achieve both low-power and noise tolerance. To minimize the stand-by current of MCU, a non-volatile flip-flop and a 6T-4C NVRAM are used. Proposed plate-line charge-share and bit-line non-precharge techniques also contribute to mitigate the active power overhead of 6T-4C NVRAM. The proposed accurate heartbeat detector uses coarse-fine autocorrelation and a template matching technique. Accurate heartbeat detection also contributes system-level power reduction because the active ratio of ADC and digital block can be reduced using heartbeat prediction. Measurement results show that the fully integrated ECG-SoC consumes 6.14 μ A including 1.28- μA non-volatile MCU and 0.7- μA heartbeat detector.
    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, Oct. 2015, IEEE transactions on biomedical circuits and systems, 9(5) (5), 641 - 51, English, International magazine
    [Refereed]
    Scientific journal

  • Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto
    To prevent lifestyle diseases, wearable bio-signal monitoring systems for daily life monitoring have attracted attention. Wearable systems have strict size and weight constraints, which impose significant limitations of the battery capacity and the signal-to-noise ratio of bio-signals. This report describes an electrocardiograph (ECG) processor for use with a wearable healthcare system. It comprises an analog front end, a 12-bit ADC, a robust Instantaneous Heart Rate (IHR) monitor, a 32-bit Cortex-M0 core, and 64 Kbyte Ferroelectric Random Access Memory (FeRAM). The IHR monitor uses a short-term autocorrelation (STAC) algorithm to improve the heart-rate detection accuracy despite its use in noisy conditions. The ECG processor chip consumes 13.7 μA for heart rate logging application.
    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, Oct. 2015, IEEE transactions on biomedical circuits and systems, 9(5) (5), 733 - 42, English, International magazine
    [Refereed]
    Scientific journal

  • Motofumi Nakanishi, Shintaro Izumi, Sho Nagayoshi, Hironori Sato, Hiroshi Kawaguchi, Masahiko Yoshimoto, Takafumi Ando, Satoshi Nakae, Chiyoko Usui, Tomoko Aoyama, Shigeho Tanaka
    As described in this paper, a physical activity classification algorithm is proposed for energy expenditure estimation. The proposed algorithm can improve the classification accuracy using both the triaxial acceleration and heart rate. The optimal classification also contributes to improvement of the accuracy of the energy expenditures estimation. The proposed algorithm employs three indices: the heart rate reserve (%HRreserve), the filtered triaxial acceleration, and the ratio of filtered and unfiltered acceleration. The percentage HRreserve is calculated using the heart rate at rest condition and the maximum heart rate, which is calculated using Karvonen Formula. Using these three indices, a decision tree is constructed to classify physical activities into five classes: sedentary, household, moderate (excluding locomotive), locomotive, and vigorous. Evaluation results show that the average classification accuracy for 21 activities is 91%.
    IEEE, Aug. 2015, Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual International Conference, 2015, 510 - 3, English, International magazine
    [Refereed]
    Scientific journal

  • Taisuke Kodama, Shintaro Izumi, Kana Masaki, Hiroshi Kawaguchi, Kazusuke Maenaka, Masahiko Yoshimoto
    Recently, given Japan's aging society background, wearable healthcare devices have increasingly attracted attention. Many devices have been developed, but most devices have only a sensing function. To expand the application area of wearable healthcare devices, an interactive communication function with the human body is required using an actuator. For example, a device must be useful for medication assistance, predictive alerts of a disease such as arrhythmia, and exercise. In this work, a haptic stimulus actuator using a piezoelectric pump is proposed to realize a large displacement in wearable devices. The proposed actuator drives tactile sensation of the human body. The measurement results obtained using a sensory examination demonstrate that the proposed actuator can generate sufficient stimuli even if adhered to the chest, which has fewer tactile receptors than either the fingertip or wrist.
    IEEE, Aug. 2015, Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual International Conference, 2015, 1172 - 5, English, International magazine
    [Refereed]
    Scientific journal

  • Tomoki Nakagawa, Shintaro Izumi, Koji Yanagida, Yuki Kitahara, Shusuke Yoshimoto, Yohei Umeki, Haruki Mori, Hiroto Kitahara, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Masahiko Yoshimoto
    This report describes a low power 6T-4C nonvolatile memory design using a bit-line non-precharge and plate-line charge-share techniques. Two proposed techniques contribute to decrease energy consumption. The bit-line non-precharge technique can reduce 73% of write energy consumption and 76% of read energy consumption. The plate-line charge-share technique can reduce 22% of store energy consumption and 11% of recall energy consumption.
    Institute of Electrical and Electronics Engineers Inc., Jul. 2015, Proceedings - IEEE International Symposium on Circuits and Systems, 2015-, 2904 - 2907, English
    [Refereed]
    International conference proceedings

  • Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    We present a low-jitter design for a 10-bit second-order frequency shift oscillator time-to-digital converter (FSOTDC). As described herein, we analyze the relation between performance and FSOTDC parameters and provide insight to support the design of the FSOTDC. Results show that an oscillator jitter limits the FSOTDC resolution, particularly during the first stage. To estimate and design an FSOTDC, the frequency shift oscillator requires an inverter of a certain size. In a standard 65-nm CMOS process, an SNDR of 64 dB is achievable at an input signal frequency of 10 kHz and a sampling clock of 2MHz. Measurements of the test chip confirmed that the measurements match the analyses.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jul. 2015, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E98A(7) (7), 1475 - 1481, English
    [Refereed]
    Scientific journal

  • Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    We present an I/O-size second-order analog to digital converter (ADC) combined with a time-to-digital converter (TDC) and a voltage-to-time converter (VTC). Our proposed VTC is optimized for metal-oxide-metal (MOM) capacitances, and is charged to the MOM capacitances by an input voltage. In a standard 65-nm CMOS process, a signal to noise and distortion ratio (SNDR) of 50 dB (8 bits) is achievable at an input signal frequency of 78 kHz and a sampling rate of 20 MHz, where the respective area and power are 6468 mm(2) and 509 mu W. The measured maximum integral nonlinearity (INL) of the proposed ADC is 1.41 LSBs. The active area of the proposed ADC is smaller than an I/O buffer. The proposed ADC is useful as an ADC I/O.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jun. 2015, IEICE TRANSACTIONS ON ELECTRONICS, E98C(6) (6), 489 - 495, English
    [Refereed]
    Scientific journal

  • Shintaro Izumi, Masanao Nakano, Ken Yamashita, Yozaburo Nakai, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This report describes a robust method of instantaneous heart rate (IHR) extraction from noisy electrocardiogram (ECG) signals. Generally, R-waves are extracted from ECG using a threshold to calculate the IHR from the interval of R-waves. However, noise increases the incidence of misdetection and false detection in wearable healthcare systems because the power consumption and electrode distance are limited to reduce the size and weight. To prevent incorrect detection, we propose a short-time autocorrelation (STAC) technique. The proposed method extracts the IHR by determining the search window shift length which maximizes the correlation coefficient between the template window and the search window. It uses the similarity of the QRS complex waveform beat-by-beat. Therefore, it has no threshold calculation process. Furthermore, it is robust against noisy environments. The proposed method was evaluated using MIT-BIH arrhythmia and noise stress test databases. Simulation results show that the proposed method achieves a state-of-the-art success rate of IHR extraction in a noise stress test using a muscle artifact and a motion artifact.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, May 2015, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E98D(5) (5), 1095 - 1103, English
    [Refereed]
    Scientific journal

  • A 298-fJ/writecycle 650-fJ/readcycle 8T Three-Port SRAM in 28-nm FD-SOI Process Technology for Image Processor
    Haruki Mori, T. Nakagawa, Y. Kitahara, Y. Kawamoto, K. Takagi, S. Yoshimoto, S. Izumi, K. Nii, H. Kawaguchi, M. Yoshimoto
    This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using a 28-nm FD-SOI process technology. Our proposed SRAM accommodates eight-transistor bitcells comprising one-write/two-read ports and a majority logic circuit to save active energy. The test chip can operate at a supply voltage of 0.46 V and an access time of 140 ns. The energy minimum point is a supply voltage of 0.54 V and an access time of 55 ns (= 18.2 MHz), at which 298 fJ/cycle in a write operation and 650 fJ/cycle in a read operation are achieved with the help of the majority logic; these factor are 87% and 52% smaller than those in a 28-nm FD-SOI 6T SRAM.
    IEEE, 2015, 2015 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), English
    [Refereed]
    International conference proceedings

  • Yuta Kimi, Go Matsukawa, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    As technology nodes continue to shrink, the impact of radiation-induced soft error on processor reliability increases. Estimation of processor reliability and identification of vulnerable flip-flops requires accurate soft error rate (SER) analysis techniques. This paper presents a proposal for a soft error propagation analysis technique. We specifically examine single event upset (SEU) occurring at a flip-flop in sequential circuits. When SEUs propagate in sequential circuits, the faults can be masked temporally and logically. Conventional soft error propagation analysis techniques do not consider error convergent timing on re-convergent paths. The proposed technique can analyze soft error propagation while considering error-convergent timing on a re-convergent path by combinational analysis of temporal and logical effects. The proposed technique also considers the case in which the temporal masking is disabled with an enable signal of the erroneous flip-flop negated. Experimental results show that the proposed technique improves inaccuracy by 70.5%, on average, compared with conventional techniques using ITC 99 and ISCAS 89 benchmark circuits when the enable probability is 1/3, while the runtime overhead is only 1.7% on average.
    IEEE COMPUTER SOC, 2015, 2015 IEEE 24TH ASIAN TEST SYMPOSIUM (ATS), 139 - 144, English
    [Refereed]
    International conference proceedings

  • A Negative-Resistance Sense Amplifier for Low-Voltage Operating STT-MRAM
    Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, Koji Tsunoda, Toshihiro Sugii
    Jan. 2015, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) University LSI Design Contest, pp. 8 - 9, English
    [Refereed]
    International conference proceedings

  • A 14 mu A ECG Processor with Noise Tolerant Heart Rate Extractor and FeRAM for Wearable Healthcare Systems
    Yozaburo Nakai, Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This report describes an electrocardiograph (ECG) processor for use with a wearable healthcare system. It comprises an analog front end, a 12-bit ADC, a robust Instantaneous Heart Rate (IHR) monitor, a 32-bit Cortex-M0 core, and 64 Kbyte Ferroelectric Random Access Memory (FeRAM). The IHR monitor uses a short-term autocorrelation (STAC) algorithm to improve the heart-rate detection accuracy despite its use in noisy conditions. The ECG processor chip consumes 13.7 mu A for heart rate logging application.
    IEEE, 2015, 2015 20TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 16 - 17, English
    [Refereed]
    International conference proceedings

  • A Low Power 6T-4C Non-volatile Memory using Charge Sharing and Non-precharge Techniques
    Tomoki Nakagawa, Shintaro Izumi, Koji Yanagida, Yuki Kitahara, Shusuke Yoshimoto, Yohei Umeki, Haruki Mori, Hiroto Kitahara, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Masahiko Yoshimoto
    This report describes a low power 6T-4C nonvolatile memory design using a bit-line non-precharge and plate-line charge-share techniques. Two proposed techniques contribute to decrease energy consumption. The bit-line non-precharge technique can reduce 73% of write energy consumption and 76% of read energy consumption. The plate-line charge-share technique can reduce 22% of store energy consumption and 11% of recall energy consumption.
    IEEE, 2015, 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2904 - 2907, English
    [Refereed]
    International conference proceedings

  • An Accurate Soft Error Propagation Analysis Technique Considering Temporal Masking Disablement
    Yuta Kimi, Go Matsukawa, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents an accurate soft error propagation analysis technique for processor SER evaluation. Especially, we focus on Single Event Upset (SEU) in flip-flop which is a main contributor of processor SER. SEUs in flip-flops propagate combinational circuits with temporal masking and logical masking effects. The temporal masking is disabled when the erroneous flip-flop is disabled. The proposed technique is able to evaluate temporal masking disablement by combined analysis of temporal and logical effects. Experimental result shows that the proposed technique reduces 49.87% inaccuracy in average compared with the technique ignoring temporal masking disablement when the enabled probability of the erroneous flip-flop is 0.1.
    IEEE, 2015, 2015 IEEE 21ST INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), 23 - 25, English
    [Refereed]
    International conference proceedings

  • Daichi Matsunag, Shintaro Izumi, Keisuke Okuno, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a non-contact and noise-tolerant heart beat monitoring system. The proposed system comprises a microwave Doppler sensor and range imagery using Microsoft Kinect™. The possible application of the proposed system is a driver health monitoring. We introduce the sensor fusion approach to minimize the heart beat detection error. The proposed algorithm can subtract a body motion artifact from Doppler sensor output using time-frequency analysis. The body motion artifact is a crucially important problem for biosignal monitoring using microwave Doppler sensor. The body motion speed is obtainable from range imagery, which has 5-mm resolution at 30-cm distance. Measurement results show that the success rate of the heart beat detection is improved about 75% on average when the Doppler wave is degraded by the body motion artifact.
    IEEE, 2015, Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual International Conference, 2015, 6118 - 21, English, International magazine
    [Refereed]
    Scientific journal

  • Hidetoshi Ohta, Shintaro Izumi, Masahiko Yoshimoto
    Several types of implant devices have been proposed and introduced into healthcare and telemedicine systems for monitoring physiological parameters, sometimes for very long periods of time. To our disappointment, most of the devices are implanted invasively and by surgery. We often have to surgically remove such devices after they have finished their mission or before the battery becomes worn out. Wearable devices have the possibility to become new modalities for monitoring vital parameters less-invasively. However, for round-the-clock monitoring of data from sensors over long periods of time, it would be better to put them inside the body to avoid causing inconvenience to patients in their daily lives. This study tested a less invasive endoluminal approach and innovative tools (developed during our research into therapeutic capsule endoscopy) for remotely anchoring ingestible sensors to the stomach wall. Preliminary investigations are also described about wireless communication (NFC, ZigBee, and Bluetooth) for low power consumption and inductive extracorporeal power feeding wirelessly to the circuits in a phantom lined with swine gastric mucosa. Electrocardiogram and pH were monitored and those parameters were successfully transmitted by wireless communication ICs to the Internet via a portable device.
    IEEE, 2015, Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual International Conference, 2015, 4089 - 92, English, International magazine
    [Refereed]
    Scientific journal

  • A Ferroelectric-Based Non-Volatile Flip-Flop for Wearable Healthcare Systems
    Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Hiromitsu Kimura, Takaaki Fuchikami, Kyoji Marumoto, Yoshikazu Fujimori
    The low-power FE-based NVFF is developed by reduction of FE capacitor size. In the proposed NVFF, coupled FE capacitors with complementary data storage are introduced. The use of complementarily stored data in coupled FE capacitors achieves 88% FE capacitor size reduction while maintaining a wide read voltage margin of 240 mV (minimum) at 1.5 V, which results in 2.4 pJ low access energy with 10-year, 85 degrees C data retention capability. An access speed of FE capacitors can be adaptively changed according to required retention time, which becomes 1.6 mu s for 10-year data retention, and 170 ns for 10-hour data retention. Especially, short-term data retention is suitable for power gating implementation. As a design example, the proposed NVFF is applied to 32-bit CPU in a vital sensor LSI for wearable healthcare applications. The vital sensor LSI consists of an electrocardiogram (ECG) sensor, the 32-bit CPU core with NVFF, and a 16-Kbyte FE-based non-volatile memory (NVRAM) for data and instruction. Because the frequency range of vital signals is low, both the standby power reduction and sleep time maximization is important to system level power reduction. Its standby current can be cut when the state of CPU core transits to deep sleep. Then the data in the memory and register values of CPU core in the NVFF are stored sequentially to ferroelectric capacitors. The implementation result demonstrates that 87% of total power dissipation during measurement of the heart rate can be reduced with 64% area overhead using 130-nm CMOS with Pb(Zr,Ti)O-3(PZT) thin films.
    IEEE, 2015, 2015 15TH NON-VOLATILE MEMORY TECHNOLOGY SYMPOSIUM (NVMTS), pp.1 - 4, English
    [Refereed]
    International conference proceedings

  • 不揮発マイコンを用いたノーマリーオフ生体計測SoC
    松永 大地, 中井 陽三郎, 河本 優太, 中川 知己, 奥野 圭祐, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO
    Dec. 2014, 信学技報, vol. 114(no. 345) (no. 345), p. 49, Japanese
    Research society

  • ウェアラブル生体センサのための心電計測方法
    田中 義人, 河本 優太, 中井 陽三郎, 奥野 圭祐, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO
    Dec. 2014, 信学技報, vol. 114(no. 345) (no. 345), p. 47, Japanese
    Research society

  • Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii
    This paper reports a 65 nm 8 Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at a single supply voltage with a process-variation-tolerant sense amplifier. The proposed sense amplifier comprises a boosted-gate nMOS and negative-resistance pMOSs as loads, which maximizes the readout margin at any process corner. The STT-MRAM achieves a cycle time of 1.9 mu s (= 0.526 MHz) at 0.38 V. The operating power is 1.70 mu W at this voltage. The minimum energy per access is 1.12 pJ/bit when the supply voltage is 0.44 V. The proposed STT-MRAM operates at a lower energy than an SRAM when the utilization of the memory bandwidth is 14% or less.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Dec. 2014, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A(12) (12), 2411 - 2417, English
    [Refereed]
    Scientific journal

  • Kenta Takagi, Kotaro Tanaka, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    As described in this paper, a real-time object detection system using a Histogram of Oriented Gradients (HOG) feature extraction accelerator VLSI is presented. The VLSI [1, 2] enables the system to achieve real-time performance and scalability for multiple object detection under limited power condition. The VLSI employs three techniques: a VLSI-oriented HOG algorithm with early classification in Support Vector Machine (SVM) classification, a dual-core architecture for parallel feature extraction, and a detection-window-size scalable architecture with a reconfigurable MAC array for processing objects of different shapes. The test chip was fabricated using 65 nm CMOS technology. The measurement result shows that the VLSI consumes 43 mW at 42.9 MHz and 1.1 V to process HDTV (1920 x 1080 pixels) at 30 frames per second (fps). A multiple object detection system and a multiple scale object detection system are presented to demonstrate the system flexibility and scalability realized by VLSI and applicability for versatile application of object detection. On the multiple object detection system, a real-time object detection for HDTV resolution video is achieved with 84 mW of power consumption on a task to detect 2 types of targets while keeping comparable detection accuracy as software-based system. On the multiple scale object detection system, a task to detect 5 scales of a target is accomplished using a single VLSI. The power consumption of the VLSI is estimated to 102 mW on the task.
    SPRINGER, Sep. 2014, JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 76(3) (3), 261 - 274, English
    [Refereed]
    Scientific journal

  • Low-Power SRAM in 28-nm FD-SOI for Image Processor
    KAWAMOTO Yuta, YOSHIMOTO Shusuke, NAKAGAWA Tomomki, KITAHARA Yuki, MORI Haruki, TAKAGI Kenta, IZUMI Shintaro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    The Institute of Electronics, Information and Communication Engineers, Jan. 2014, Technical report of IEICE. ICD, 113(419) (419), 41 - 41, Japanese

  • Tomoki Nakagawa, Shintaro Izumi, Shusuke Yoshimoto, Koji Yanagida, Yuki Kitahara, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This report describes a high speed 6T-4C shadow memory design using a word line boosting and a plate line driver boosting. The proposed methods utilize a characteristic of ferroelectric capacitor. The word line and the plate line boosting method respectively reduce 21% write time and 33% plate line charging time. © 2014 IEEE.
    Institute of Electrical and Electronics Engineers Inc., 2014, Proceedings - IEEE International Symposium on Circuits and Systems, 2736 - 2739, English
    [Refereed]
    International conference proceedings

  • 磁性変化型メモリの書き込み速度を改善するメモリアーキテクチャ
    MORI Haruki, YANAGIDA Kouji, UMEKI Youhei, YOSHIMOTO Shusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, 角田 浩司, 杉井 寿博
    Jan. 2014, 信学技報, vol. 113(no. 419) (no. 419), p. 27, Japanese
    Research society

  • 強誘電体メモリの高速回路技術
    NAKAGAWA Tomoki, YOSHIMOTO Shusuke, KITAHARA Yuki, YANAGIDA Kouji, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Jan. 2014, 信学技報, vol. 113(no. 419) (no. 419), p. 39, Japanese
    Research society

  • Guangji He, Yuki Miyamoto, Kumpei Matsuda, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition. We implement parallel and pipelined architecture for GMM computation and Viterbi processing. It includes a 8-path Viterbi transition architecture to maximize the processing speed and adopts tri-gram language model to improve the recognition accuracy. A two-level cache architecture is implemented for the demo system. Measured results show that our implementation achieves 25% required frequency reduction (62.5 MHz) and 26% power consumption reduction (54.8mW) for 60 k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 3.02x and 2.25x times faster than real-time at 200MHz using the bigram and trigram language models, respectively.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2014, IEICE ELECTRONICS EXPRESS, 11(2) (2), pp. 1 - 9, English
    [Refereed]
    Scientific journal

  • Normally-Off Technologies for Healthcare Appliance
    Izumi, Shintaro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko, Fujimori, Yoshikazu
    Battery mass and power consumption of wearable system must be reduced because the key factors affecting wearable system usability are miniaturization and weight reduction. This report describes a wearable biosignal monitoring system using normally-off technologies to minimize the power consumption. Especially we focused on daily-life monitoring and electrocardiograph (ECG) processor. Our system employs Ferroelectric Random Access Memory (FeRAM) and Near Field Communication (NFC) for normally-off data logging and normally-off data communication. A robust heart rate monitor and Cortex M0 core are used to on-node processing for logging data reduction.
    IEEE, 2014, 2014 19TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 17 - 20, English
    [Refereed]
    International conference proceedings

  • A 6T-4C Shadow Memory using Plate Line and Word Line Boosting
    Nakagawa, Tomoki, Izumi, Shintaro, Yoshimoto, Shusuke, Yanagida, Koji, Kitahara, Yuki, Kawaguchi, Hiroshi, Yoshimoto, Masahiko
    This report describes a high speed 6T-4C shadow memory design using a word line boosting and a plate line driver boosting. The proposed methods utilize a characteristic of ferroelectric capacitor. The word line and the plate line boosting method respectively reduce 21% write time and 33% plate line charging time.
    IEEE, 2014, 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2736 - 2739, English
    [Refereed]
    International conference proceedings

  • Yozaburo Nakai, Shintaro Izumi, Masanao Nakano, Ken Yamashita, Takahide Fujii, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a robust method for heart beat detection from noisy electrocardiogram (ECG) signals. Generally, the QRS-complex of heart beat is extracted from the ECG using a threshold. However, in a noisy condition such a mobile and wearable bio-signal monitoring system, noise increases the incidence of misdetection and false detection of QRS-complex. To prevent incorrect detection, we introduce a novel template matching algorithm. The template waveform can be generated autonomously using a short-term autocorrelation method, which leverages the similarity of QRS-complex waveforms. Simulation results show the proposed method achieves state-of-the-art noise tolerance of heart beat detection.
    IEEE, 2014, Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual International Conference, 2014, 34 - 7, English, International magazine
    [Refereed]
    Scientific journal

  • A 6.14 mu A Normally-Off ECG-SoC with Noise Tolerant Heart Rate Extractor for Wearable Healthcare Systems
    Shintaro Izumi, Ken Yamashita, Masanao Nakano, Tomoki Nakagawa, Yuki Kitahara, Koji Yanagida, Shusuke Yoshimoto, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto
    This paper describes an electrocardiograph (ECG) monitoring SoC using a non-volatile MCU (NVMCU) and a noise tolerant instantaneous heart rate (IHR) monitor. The novelty of this work is the combination of the non-volatile MCU for normally-off computing and a noise-tolerant-QRS (heart beat) detection algorithm to achieve both low-power and noise tolerance. To minimize the stand-by current of MCU, a nonvolatile flip-flop and a 6T-4C NVRAM are employed. Proposed plate-line charge-share and bit-line non-precharge techniques also contribute to mitigate the active power overhead of 6T-4C NVRAM. The proposed accurate heart beat detector employs a coarse-fine autocorrelation and a template matching technique. Accurate heart beat detection also contributes system level power reduction because the active ratio of ADC and digital block can be reduced using a heart beat prediction. Then, at least 25% active time can be reduced. Measurement results show the fully integrated ECG-SoC consumes 6.14 mu A including 1.28-mu A nonvolatile MCU and 0.7-mu A heart rate extractor.
    IEEE, 2014, 2014 IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE (BIOCAS), 280 - 283, English
    [Refereed]
    International conference proceedings

  • A 2.4 pJ Ferroelectric-Based Non-Volatile Flip-Flop with 10-Year Data Retention Capability
    Kimura, Hiromitsu, Fuchikami, Takaaki, Marumoto, Kyoji, Fujimori, Yoshikazu, Izumi, Shintaro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko
    A ferroelectric-based (FE-based) non-volatile flip-flop (NVFF) is proposed for low-power LSI. Since leakage current in a logic circuit can be cut off by non-volatile storage capability of NVFFs, the standby power is reduced to zero. The use of complementarily stored data in coupled FE capacitors makes it possible to achieve 88% reduction of FE capacitor size while maintaining a wide read voltage margin of 240mV (minimum) at 1.5V, which results in 2.4pJ low access energy with 10-year, 85 degrees C data retention capability. An access speed of FE capacitors can be adaptively changed according to required retention time, which becomes 1.6 mu s for 10-year data retention, and 170ns for 10-hour data retention. Especially, short-term data retention is suitable for power gating implementation. Applying the proposed circuitry in 32bit CPU of a vital sensor LSI, its power consumption becomes 13% of that of conventional one with area overhead of 64% using 130nm CMOS with Pb(Zr,Ti)O-3(PZT) thin films.
    IEEE, 2014, 2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 21 - 24, English
    [Refereed]
    International conference proceedings

  • An 8-bit I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter
    Okuno, Keisuke, Konishi, Toshihiro, Izumi, Shintaro, Yoshimoto, Masahiko, Kawaguchi, Hiroshi
    We present an I/O-sized second-order analog to digital converter (ADC) combined with a time-to-digital converter (TDC) and a voltage-to-time converter (VTC). Our proposed VTC is optimized for metal-oxide-metal (MOM) capacitances, and is charged to the MOM capacitances by an input voltage. In a standard 65-nm CMOS process, an SNR of 50 dB (8 bits) is achievable at an input signal frequency of 78 kHz and a sampling rate of 20 MHz, where the respective area and power are 6468 mm(2) and 509 mu W. The active area of the proposed ADC is smaller than an I/O buffer. The proposed ADC is useful as an ADC I/O.
    IEEE, 2014, 2014 21ST IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 223 - 226, English
    [Refereed]
    International conference proceedings

  • A 2.23 ps RMS Jitter 3 mu s Fast Settling ADPLL using Temperature Compensation PLL Controller
    Okuno, Keisuke, Masaki, Kana, Izumi, Shintaro, Konishi, Toshihiro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko
    This report describes an all-digital phase-locked loop (ADPLL) with temperature-compensated settling time reduction. The novelty of this work is autonomous oscillation control word estimation without a look-up table or memory circuits. The proposed ADPLL includes a multi-phase oscillator as a digitally controlled oscillator (DCO). Digital timing error correction circuits are integrated to minimize the settling time that is degraded by phase conversion error. The ADPLL is fabricated using a 65 nm CMOS process. The test chip occupies 0.27 x 0.36 mm(2). It achieves 2.23 ps RMS jitter and -224 dB FoM at 2.4 GHz output frequency with 8.85 mW power dissipation. Measurement results show that the 47% settling time is reduced by the proposed estimation block. The average settling time at 25 degrees C is 3 mu s.
    IEEE, 2014, 2014 21ST IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 68 - 71, English
    [Refereed]
    International conference proceedings

  • A 2.4x-Real-Time VLSI Processor for 60-kWord Continuous Speech Recognition
    HE Guangji, MIYAMOTO Yuki, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). We implement parallel and pipelined architecture for GMM computation and Viterbi processing. It includes a 8-path Viterbi transition architecture to maximize the processing speed and adopts tri-gram language model to improve the recognition accuracy. A two-level cache architecture is implemented for the demo system. The test chip, fabricated in 40 nm CMOS technology, occupies 1.77 mm × 2.18 mm containing 2.98 M transistors for logic and 4.29 Mbit on-chip memory. The measured results show that our implementation achieves 25% required frequency reduction (62.5 MHz) and 26% power consumption reduction (54.8 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 3.02× and 2.25× times faster than real-time at 200 MHz using the bigram and trigram language models, respectively.
    The Institute of Electronics, Information and Communication Engineers, Sep. 2013, Technical report of IEICE. VLD, 113(235) (235), 29 - 34, Japanese

  • Soft-Error Tolerant N-P Reversed 6T SRAM Cell
    S. Yoshimoto, S. Izumi, H. Kawaguchi, YOSHIMOTO Masahiko
    Jul. 2013, IEEE Nuclear and Space Radiation Effects Conference (NSREC), PG - 3, English
    [Refereed]
    International conference proceedings

  • NMOS-Centered 6T SRAM Layout Reducing Neutron-Induced Multiple Cell Upsets
    YOSHIMOTO Shusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    This paper presents a proposed NMOS-centered 6T SRAM cell layout that reduces a neutron-induced multiple-cell-upset (MCU) SER on a same wordline. We implemented an 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67-98% compared with a general macro that has PMOS-centered 6T SRAM cells.
    The Institute of Electronics, Information and Communication Engineers, Apr. 2013, Technical report of IEICE. ICD, 113(1) (1), 121 - 126, Japanese

  • Kosuke Mizuno, Kenta Takagi, Yosuke Terachi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a Histogram of Oriented Gradients (HOG) feature extraction accelerator that features a VLSI-oriented HOG algorithm with early classification in Support Vector Machine (SVM) classification, dual core architecture for parallel feature extraction and multiple object detection, and detection-window-size scalable architecture with reconfigurable MAC array for processing objects of several shapes. To achieve low-power consumption for mobile applications, early classification reduces the amount of computations in SVM classification efficiently with no accuracy degradation. The dual core architecture enables parallel feature extraction in one frame for high-speed or low-power computing and detection of multiple objects simultaneously with low power consumption by HOG feature sharing. Objects of several shapes, a vertically long object, a horizontally long object, and a square object, can be detected because of cooperation between the two cores. The proposed methods provide processing capability for HDTV resolution video (1920 x 1080 pixels) at 30 frames per second (fps). The test chip, which has been fabricated using 65 nm CMOS technology, occupies 4.2 x 2.1 mm(2) containing 502 Kgates and 1.22 Mbit on-chip SRAMs. The simulated data show 99.5 mW power consumption at 42.9 MHz and 1.1 V.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2013, IEICE TRANSACTIONS ON ELECTRONICS, E96C(4) (4), 433 - 443, English
    [Refereed]
    Scientific journal

  • Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    We present a small-area second-order all-digital time-to-digital converter (TDC) with two frequency shift oscillators (FSOs) comprising inverter chains and dynamic flipflops featuring low jitter. The proposed FSOs can maintain their phase states through continuous oscillation, unlike conventional gated ring oscillators (GROs) that are affected by transistor leakage. Our proposed FSOTDC is more robust and is eligible for all-digital TDC architectures in recent leaky processes. Low-jitter dynamic flipflops are adopted as a quantization noise propagator (QNP). A frequency mismatch occurring between the two FSOs can be canceled out using a least mean squares (LMS) filter so that second-order noise shaping is possible. In a standard 65-nm CMOS process, an SNDR of 61 dB is achievable at an input bandwidth of 500 kHz and a sampling rate of 16 MHz, where the respective area and power are 700 mu m(2) and 281 mu W.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2013, IEICE TRANSACTIONS ON ELECTRONICS, E96C(4) (4), 546 - 552, English
    [Refereed]
    Scientific journal

  • Guangji He, Takanobu Sugahara, Yuki Miyamoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). It features a compression-decoding scheme to reduce the external memory bandwidth for Gaussian Mixture Model (GMM) computation and multi-path Viterbi transition units. We optimize the internal SRAM size using the max-approximation GMM calculation and adjusting the number of look-ahead frames. The test chip, fabricated in 40 nm CMOS technology, occupies 1.77 mm x 2.18 mm containing 2.52 M transistors for logic and 4.29 Mbit on-chip memory. The measured results show that our implementation achieves 34.2% required frequency reduction (83.3 MHz), 48.5% power consumption reduction (74.14 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work while 30% of the area is saved with recognition accuracy of 90.9%. This chip can maximally process 2.4x faster than real-time at 200 MHz and 1.1 V with power consumption of 168 mW. By increasing the beam width, better recognition accuracy (91.45%) can be achieved. In that case, the power consumption for real-time processing is increased to 97.4 mW and the max-performance is decreased to 2.08x because of the increased computation workload.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2013, IEICE TRANSACTIONS ON ELECTRONICS, E96C(4) (4), 444 - 453, English
    [Refereed]
    Scientific journal

  • Kosuke Mizuno, Yosuke Terachi, Kenta Takagi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a Histogram of Oriented Gradients (HOG)-based object detection processor. It features a simplified HOG algorithm with cell-based scanning and simultaneous Support Vector Machine (SVM) calculation, cell-based pipeline architecture, and parallelized modules. To evaluate the effectiveness of our approach, the proposed architecture is implemented onto a FPGA prototyping board. Results show that the proposed architecture can generate HOG features and detect objects with 40MHz for SVGA resolution video (800 × 600 pixels) at 72 frames per second (fps). © 2013 Information Processing Society of Japan.
    Feb. 2013, IPSJ Transactions on System LSI Design Methodology, 6, 42 - 51, English
    [Refereed]
    International conference proceedings

  • Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    This paper presents a second-order Delta Sigma analog-to-digital converter (ADC) operating in a time domain. In the proposed ADC architecture, a voltage-controlled delay unit (VCDU) converts an input analog voltage to a delay time. Then, the clocks outputs from a gated ring oscillator (GRO) are counted during the delay time. No switched capacitor or opamp is used. Therefore, the proposed ADC can be implemented in a small area and with low power. For that reason, it has process scalability: it can keep pace with Moore's law. A time error is propagated to the second GRO by a multi-stage noise-shaping (MASH) topology, which provides second-order noise-shaping. In a standard 40-nm CMOS process, a SNDR of 45 dB is achievable at input bandwidth of 16 kHz and a sampling rate of 8 MHz, where the power is 408.5 mu W. Its area is 608 mu m(2).
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Feb. 2013, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E96A(2) (2), 434 - 442, English
    [Refereed]
    Scientific journal

  • Guangji He, Yuki Miyamoto, Kumpei Matsuda, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a low-power VLSI chip for speakerindependent 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). We implement parallel and pipelined architecture for GMM computation and Viterbi processing. It includes a 8-path Viterbi transition architecture to maximize the processing speed and adopts tri-gram language model to improve the recognition accuracy. A two-level cache architecture is implemented for the demo system. The test chip, fabricated in 40 nm CMOS technology, occupies 1.77 mm × 2.18 mm containing 2.98 M transistors for logic and 4.29 Mbit on-chip memory. The measured results show that our implementation achieves 25% required frequency reduction (62.5 MHz) and 26% power consumption reduction (54.8 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 3.02× and 2.25× times faster than real-time at 200 MHz using the bigram and trigram language models, respectively. © 2013 IEEE.
    Institute of Electrical and Electronics Engineers Inc., 2013, IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, 147 - 152, English
    International conference proceedings

  • A 40-nm 144-mW VLSI Processor for Real-time 60-kWord Continuous Speech Recognition
    Guangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We have developed a low-power VLSI chip for 60- kWord real-time continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). Our implementation includes a cache architecture using locality of speech recognition, beam pruning using a dynamic threshold, two-stage language model searching, highly parallel Gaussian Mixture Model (GMM) computation based on the mixture level, a variable-frame look-ahead scheme, and elastic pipeline operation between the Viterbi transition and GMM processing. Results show that our implementation achieves 95% bandwidth reduction (70.86 MB/s) and 78% required frequency reduction (126.5 MHz). The test chip, fabricated using 40 nm CMOS technology, contains 1.9 M transistors for logic and 7.8 Mbit on-chip memory. It dissipates 144 mW at 126.5 MHz and 1.1 V for 60 kWord real-time continuous speech recognition.
    IEEE, 2013, 2013 18TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 71 - 72, English
    [Refereed]
    International conference proceedings

  • A SUB-100-MILLIWATT DUAL-CORE HOG ACCELERATOR VLSI FOR REAL-TIME MULTIPLE OBJECT DETECTION
    Kenta Takagi, Kosuke Mizuno, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    In this paper, a Histogram of Oriented Gradients (HOG) feature extraction accelerator for real-time multiple object detection is presented. The processor employs three techniques: a VLSI-oriented HOG algorithm with early classification in Support Vector Machine (SVM) classification, a dual core architecture for parallel feature extraction, and a detection-window-size scalable architecture with a reconfigurable MAC array for processing objects of different shapes. Early classification reduces the number of computations in SVM classification. The dual core architecture and the detection-window-size scalable architecture enable the processor to operate in several modes: highspeed mode, low-power mode, multiple object detection mode, and multiple shape object detection mode. These techniques expand the processor flexibility required for versatile application. The test chip was fabricated using 65 nm CMOS technology. The proposed architecture is designed to process HDTV resolution video (1920 x 1080 pixels) at 30 frames per second (fps). The performance of this accelerator is demonstrated on a pedestrian detection system.
    IEEE, 2013, 2013 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING (ICASSP), 2533 - 2537, English
    [Refereed]
    International conference proceedings

  • Temperature Compensation using Least Mean Squares for Fast Settling All-Digital Phase-Locked Loop
    Keisuke Okuno, Shintaro Izumi, Toshihiro Konishi, Song Dae-Woo, Masahiko Yoshimoto, Hiroshi Kawaguchi
    This paper presents a temperature compensation technique for a digitally controlled oscillator (DCO) using least means square (LMS) filtering. The proposed scheme contributes to reduction of the start-up settling time of all-digital phase-locked loop (ADPLL). The proposed method estimates the temperature using the output frequency of DCO because it is affected by temperature fluctuation. An optimal value of oscillation tuning word (OTW) for DCO can be estimated using the LMS algorithm because a linear relation exists between the output frequency of maximum OTW and the output frequency of other OTWs. These characteristics are confirmed using measurement results of the DCO, which is fabricated in 65-nm CMOS process. We modeled the ADPLL with the proposed temperature compensator in MATLAB using the measurement results of DCO. The simulation results show that the ADPLL with proposed temperature compensator achieves more than 53% settling time reduction and less than 10-MHz frequency error.
    IEEE, 2013, 2013 IEEE 11TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), pp.1 - 4, English
    [Refereed]
    International conference proceedings

  • A 38 mu A Wearable Biosignal Monitoring System with Near Field Communication
    Ken Yamashita, Shintaro Izumi, Masanao Nakano, Takahide Fujii, Toshihiro Konishi, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto
    This paper presents a low-power wearable biosignal monitoring system. The proposed system can communicate with smartphones using Near Field Communication (NFC) to check vital signs easily at any time. It comprises a battery, electrodes, a triaxial accelerometer IC, an NFC tag IC, and a biosignal processor LSI. The proposed biosignal processor LSI, fabricated using a 130-nm CMOS process, comprises heart rate monitoring circuits, a 32-kbyte ferroelectric random access memory (FeRAM), an accelerometer interface, and an NFC interface. The proposed system consumes 38.1 mu A for logging application at 32-kHz operating frequency, with 3.0-V supply voltage.
    IEEE, 2013, 2013 IEEE 11TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), pp.1 - 4, English
    [Refereed]
    International conference proceedings

  • Takahide Fujii, Masanao Nakano, Ken Yamashita, Toshihiro Konishi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a robust method of Instantaneous Heart Rate (IHR) and R-peak detection from noisy electrocardiogram (ECG) signals. Generally, the IHR is calculated from the R-wave interval. Then, the R-waves are extracted from the ECG using a threshold. However, in wearable bio-signal monitoring systems, noise increases the incidence of misdetection and false detection of R-peaks. To prevent incorrect detection, we introduce a short-term autocorrelation (STAC) technique and a small-window autocorrelation (SWAC) technique, which leverages the similarity of QRS complex waveforms. Simulation results show that the proposed method improves the noise tolerance of R-peak detection.
    IEEE, 2013, Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual International Conference, 2013, 7330 - 3, English, International magazine
    [Refereed]
    Scientific journal

  • Shintaro Izumi, Ken Yamashita, Masanao Nakano, Toshihiro Konishi, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto
    This report describes an electrocardiograph (ECG) processor for use with a wearable healthcare system. It comprises an analog front end, a 12-bit ADC, a robust Instantaneous Heart Rate (IHR) monitor, a 32-bit Cortex-M0 core, and 64 Kbyte Ferroelectric Random Access Memory (FeRAM). The IHR monitor uses a short-term autocorrelation (STAC) algorithm to improve the heart-rate detection accuracy despite its use in noisy conditions. The ECG processor chip consumes 13.7 μA for heart rate logging application. © 2013 IEEE.
    2013, European Solid-State Circuits Conference, 145 - 148, English
    [Refereed]
    International conference proceedings

  • A 40-NM 54-MW 3x-REAL-TIME VLSI PROCESSOR FOR 60-KWORD CONTINUOUS SPEECH RECOGNITION
    He, Guangji, Miyamoto, Yuki, Matsuda, Kumpei, Izumi, Shintaro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko
    This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). We implement parallel and pipelined architecture for GMM computation and Viterbi processing. It includes a 8-path Viterbi transition architecture to maximize the processing speed and adopts tri-gram language model to improve the recognition accuracy. A two-level cache architecture is implemented for the demo system. The test chip, fabricated in 40 nm CMOS technology, occupies 1.77 mm x 2.18 mm containing 2.98 M transistors for logic and 4.29 Mbit on-chip memory. The measured results show that our implementation achieves 25% required frequency reduction (62.5 MHz) and 26% power consumption reduction (54.8 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 3.02x and 2.25x times faster than real-time at 200 MHz using the bigram and trigram language models, respectively.
    IEEE, 2013, 2013 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), 147 - 152, English
    [Refereed]
    International conference proceedings

  • Low-power Hardware Implementation of Noise Tolerant Heart Rate Extractor for a Wearable Monitoring System
    Shintaro Izumi, Masanao Nakano, Ken Yamashita, Takahide Fujii, Hiroshi Kawaguchi, Masahiko Yoshimoto
    To prevent lifestyle diseases, wearable bio-signal monitoring systems for daily life monitoring have attracted attention. Wearable systems have strict size and weight constraints, which impose significant limitations of the battery capacity and the signal-to-noise ratio of bio-signals. The novelty of this work is the hardware implementation of a noise-tolerant heart rate extraction algorithm that can achieve low-power performance with high reliability. This report describes comparisons of the heart rate extraction algorithm performance and the dedicated hardware implementation of short-term autocorrelation ( STAC) method. The proposed heart rate extractor, implemented in 65-nm CMOS process using Verilog-HDL, consumes 1.65 mu A at 32.768-kHz operating frequency with 1.1 V supply voltage.
    IEEE, 2013, 2013 IEEE 13TH INTERNATIONAL CONFERENCE ON BIOINFORMATICS AND BIOENGINEERING (BIBE), pp.1 - 4, English
    [Refereed]
    International conference proceedings

  • A 0.38-V Operating STT-MRAM with Process Variation Tolerant Sense Amplifier
    Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii
    This paper exhibits a 65-nm 8-Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at a single supply voltage with a process-variation tolerant sense amplifier. The proposed sense amplifier comprises a boosted-gate nMOS and negative-resistance pMOSes as loads, which maximizes the readout margin in any process corner. The STT-MRAM achieves a cycle time of 1.9 mu s (=0.526 MHz) at 0.38 V. The operating power is 6.15 mu W at that voltage. The minimum energy per access is 3.89 pJ/bit when the supply voltage is 0.44 V. The proposed STT-MRAM operates at lower energy than SRAM when a utilization of a memory bandwidth is 14% or less.
    IEEE, 2013, PROCEEDINGS OF THE 2013 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 249 - 252, English
    [Refereed]
    International conference proceedings

  • A 2.4x-Real-Time VLSI Processor for 60-k Word Continuous Speech Recognition
    MIYAMOTO Yuuki, HE Guangji, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    This paper describes a low-power VLSI chip for 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). Our implementation includes a compression–decoding scheme to reduce the external memory bandwidth for Gaussian Mixture Model (GMM) computation and multi-path Viterbi transition units. We optimize the internal SRAM size using the max-approximation GMM calculation and adjusting the number of look-ahead frames. The measured results show that our implementation achieves 34.2% required frequency reduction (83.3 MHz) and reduces 48.5% power consumption (74.14 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 2.4× faster than real-time at 200 MHz and 1.1 V with power consumption of 168 mW.
    The Institute of Electronics, Information and Communication Engineers, Dec. 2012, Technical report of IEICE. ICD, 112(365) (365), 49 - 53, Japanese

  • Low-Power Ferroelectric 6T4C Shadow SRAM for Normally-Off Computing
    Nakagawa Tomoki, Yoshimoto Shusuke, Kitahara Yuki, Yanagida Koji, Umeki Yohei, Okumura Shunsuke, Izumi Shintaro, Kawaguchi Hiroshi, Yoshimoto Masahiko
    In recent years, sensor network has attracted much attention in agricultural, medical, and disaster-prevention area to collect on-field information. Each sensor node requires extremely low-power operation because its battery size is limited. In the sensor node chip, memory consumes large leakage power so a low-power memory technique is strongly required.

    This paper presents a novel low-power technique for a ferroelectric 6T4C shadow SRAM. The shadow SRAM works a high-speed SRAM in an active mode and a nonvolatile FeRAM in a sleep mode. The nonvolatility completely removes the leakage current from the memory. However, the ferroelectric capacitors increase the power consumption and decrease the cycle time of the SRAM. In this paper, the proposed technique is evaluated by SPICE simulation results.
    The Institute of Electronics, Information and Communication Engineers, Dec. 2012, Technical report of IEICE. ICD, 112(365) (365), 41 - 41, Japanese

  • FPGA Implementation of HOG-based Real-Time Object Detection Processor
    TAKAGI Kenta, MIZUNO Kosuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    Histogram of Oriented Gradients (HOG) is widely accepted feature descriptor for object detection. HOG is robust against changes in illumination and texture. Thus, HOG is highly effective for pedestrian detection and other object detection. In recent years, object detection techniques have been introduced to advanced automobile products and increasingly valuable. Additionally, recent progress of general-purpose processors enables to implement algorithms that require heavy computations such as HOG-based object detection. However, these processors suffer from high power consumption and are therefore unsuitable for mobile systems under limited battery conditions. Therefore, we propose a HOG-based object detection processor. It features a simplified HOG algorithm with cell-based scanning and simultaneous Support Vector Machine (SVM) calculation, cell-based pipeline architecture and parallelized modules. To evaluate the effectiveness of our approach, the proposed architecture is implemented onto a FPGA prototyping board. Results show that the proposed architecture can generate HOG features and detect objects with 40 MHz for SVGA resolution video (800 × 600 pixels) at 72 frames per second (fps).
    The Institute of Electronics, Information and Communication Engineers, Dec. 2012, Technical report of IEICE. ICD, 112(365) (365), 61 - 61, Japanese

  • Guangji He, Takanobu Sugahara, Yuki Miyamoto, Tsuyoshi Fujinaga, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We have developed a low-power VLSI chip for 60-kWord real-time continuous speech recognition based on a context-dependent hidden Markov model (HMM). Our implementation includes a cache architecture using locality of speech recognition, beam pruning using a dynamic threshold, two-stage language model searching, highly parallel Gaussian mixture model (GMM) computation based on the mixture level, a variable-frame look-ahead scheme, and elastic pipeline operation between the Viterbi transition and GMM processing. The accuracy degradation of the important parameters in Viterbi computation is strictly discussed. Results show that our implementation achieves 95% bandwidth reduction (70.86 MB/s) and 78% required frequency reduction (126.5 MHz) comparing to the referential Julius [1] system. The test chip, fabricated using 40 nm CMOS technology, contains 1.9 M transistors for logic and 7.8 Mbit on-chip memory. It dissipates 144 mW at 126.5 MHz and 1.1 V for 60-kWord real-time continuous speech recognition.
    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, Aug. 2012, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 59(8) (8), 1656 - 1666, English
    [Refereed]
    Scientific journal

  • Trading off ECU Footprint for Reliability in X-by-Wire Application with Hybrid TMR Architecture
    Y. Nakata, S. Izumi, H. Kawaguchi, YOSHIMOTO MASAHIKO
    Jun. 2012, DAC International Workshop on System Level-Design of Automotive Electronics/Software (SLDAES),, English
    [Refereed]
    International conference proceedings

  • Kosuke Mizuno, Yosuke Terachi, Kenta Takagi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a Histogram of Oriented Gradients (HOG) feature extraction processor for HDTV resolution video (1920 × 1080 pixels). It features a simplified HOG algorithm with cell-based scanning and simultaneous Support Vector Machine (SVM) calculation, cell-based pipeline architecture, and parallelized modules. To evaluate the effectiveness of our approach, the proposed architecture is implemented onto a FPGA prototyping board. Results show that the proposed architecture can generate HOG features and detect objects with 40 MHz for SVGA resolution video (800 × 600 pixels) at 72 frames per second (fps). The proposed schemes are easily expandable to HDTV resolution video at 30 fps with 76.2 MHz if a highresolution camera and higher operating frequency are available. © 2012 IEEE.
    2012, IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, 197 - 202, English
    [Refereed]
    International conference proceedings

  • Bit Error Rate Estimation in SRAM Considering Temperature Fluctuation
    Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, Shusuke Yoshimoto, Yohei Nakata, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    SRAM performance varies depending on the operating environment. This study specifically examines the bit error rate (BER) when considering temperature fluctuation. The SRAM performance is generally determined using a read margin because a half-select issue must be considered even in a write operation. As a metric of the SRAM's performance, we also adopt a static noise margin (SNM) with which we evaluate three methods to estimate the BER considering temperature fluctuation. Method 1 iterates calculations for the SNM many times with Monte Carlo simulation. BER is defined as the number of cells that have no margin. Method 2 includes the assumption that SNM forms a normal distribution. Its BER is defined as a probability distribution function. Method 3 includes the assumption that SNM is determined as either square but not the smaller one of the two squares. The BER estimations are compared with a test chip result implemented in a 65-nm CMOS technology: Method 2 has 11.10% and Method 3 has 4.09% difference (unfortunately, Method 1 has no data missing because of a lack of simulations). The shift of the minimum operating voltage between the low and high temperatures is 0.04 V at a 128-Kb capacity when the temperature fluctuates from 25 degrees C to 100 degrees C.
    IEEE, 2012, 2012 13TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), 516 - 519, English
    [Refereed]
    International conference proceedings

  • Takashi Matsuda, Shintaro Izumi, Yasuharu Sakai, Takashi Takeuchi, Hidehiro Fujiwara, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    One of the most challenging issues in wireless sensor networks is extension of the overall network lifetime. Data aggregation is one promising solution because it reduces the amount of network traffic by eliminating redundant data. In order to aggregate data, each sensor node must temporarily store received data, which requires a specific amount of memory. Most sensor nodes use static random access memory (SRAM) or flash memory for storage. SRAM can be implemented in a one-chip sensor node at low cost; however, SRAM requires standby energy, which consumes a lot of power, especially because the sensor node spends most of its time sleeping, i.e. its radio circuits are quiescent. This study proposes two types of divided SRAM: equal-size divided SRAM and equal-ratio divided SRAM. Simulations show that both proposed SRAM types offer reduced power consumption in various situations.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jan. 2012, IEICE TRANSACTIONS ON COMMUNICATIONS, E95B(1) (1), 178 - 188, English
    [Refereed]
    Scientific journal

  • Kosuke Mizuno, Yosuke Terachi, Kenta Takagi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a Histogram of Oriented Gradients (HOG) feature extraction processor for HDTV resolution video (1920 x 1080 pixels). It features a simplified HOG algorithm with cell-based scanning and simultaneous Support Vector Machine (SVM) calculation, cell-based pipeline architecture, and parallelized modules. To evaluate the effectiveness of our approach, the proposed architecture is implemented onto a FPGA prototyping board. Results show that the proposed architecture can generate HOG features and detect objects with 40 MHz for SVGA resolution video (800 x 600 pixels) at 72 frames per second (fps). The proposed schemes are easily expandable to HDTV resolution video at 30 fps with 76.2 MHz if a high-resolution camera and higher operating frequency are available.
    IEEE, 2012, 2012 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), 197 - 202, English
    [Refereed]
    International conference proceedings

  • A 62-dB SNDR Second-Order Gated Ring Oscillator TDC with Two-Stage Dynamic D-Type Flipflops as A Quantization Noise Propagator
    Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    This paper presents a second-order noise shaping time-to-digital converter (TDC) with two gated ring oscillators (GROs). The oscillating outputs from the GROs are counted and digitized. As a quantization noise propagator (QNP) between the two GROs, two-stage dynamic d-type flipflops (DDFFs) and a NOR gate are adopted. The proposed QNP does not propagate a time error caused by flipflop's metastability to the next GRO, and thus improves its linearity over the conventional masterslave d-type flipflop. In a standard 65-nm CMOS process, an SNDR of 62-dB is achievable at a sampling rate of 65MS/s.
    IEEE, 2012, 2012 IEEE 10TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 289 - 292, English
    [Refereed]
    International conference proceedings

  • Shimpei Soda, Masahide Nakamura, Shinsuke Matsumoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    The voice control is a promising user interface for the home network system (HNS). In our previous interface, a user had to be equipped with an actual microphone device, which imposed a burden on the user. This paper presents a hands-free voice interface using a microphone array network. The microphone array network enables voice quality enhancement, as well as sound source localization, by networking multiple microphone arrays. Attaching the arrays to the walls or ceiling, users can input voice operations to the HNS from anywhere in the room, without being aware of the microphone devices. We implement a prototype system with a 16ch microphone array, and evaluate the speech recognition rate and the accuracy of sound source localization in a real home network environment. A hands-free operation service and an automatic speech logging service are implemented.
    IEEE, 2012, 2012 THIRD INTERNATIONAL CONFERENCE ON NETWORKING AND COMPUTING (ICNC 2012), 195 - 200, English
    [Refereed]
    International conference proceedings

  • Shimpei Soda, Masahide Nakamura, Shinsuke Matsumoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We have been developing a hands-free voice controller for a home network system (HNS) by using microphone arrays. In our current implementation, however, all human-HNS interactions are performed by voice only. Hence, the interactions tend to be mechanical, dreary and uninformative. To achieve richer interactions, we try to introduce the virtual agent technology as a feedback interface of the HNS. In this paper, we implement the virtual agent as a Web service, by using MMDAgent Toolkit extensively. The agent is then integrated with the HNS and microphone arrays in a service-oriented fashion. Finally, we conduct a user experiment with three versions of virtual agents. In the experiment, we evaluate how the virtual agent can enrich the interactions.
    IEEE COMPUTER SOC, 2012, 2012 19TH ASIA-PACIFIC SOFTWARE ENGINEERING CONFERENCE (APSEC), VOL 1, 342 - 345, English
    [Refereed]
    International conference proceedings

  • A 51-dB SNDR DCO-Based TDC Using Two-Stage Second-Order Noise Shaping
    Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    This paper presents a two-stage second-order noise shaping time-to-digital converter (TDC) using a one-bit digitally-controlled oscillator (DCO). The clocks output from DCOs are counted and digitized as in a conventional gated ring oscillator (GRO) TDC. A time error is propagated to the second DCO, which provides second-order noise shaping. In the conventional GROTDC, internal oscillators must maintain their phase state. However, because of the leak current, the stored phase states are degraded or even lost. In our proposed architecture, the DCOs always oscillate and need not maintain their phase state. Therefore, our proposed TDC is more suitable in leaky recent process than a GROTDC is. Because no switched capacitor or opamp is used, the proposed TDC can be implemented in a small area and with low power. Mismatches in the oscillation frequency between the DCOs might occur. However, error detection and correction can be performed using a first-order least mean square (LMS) filter. In a standard 65-nm CMOS process, an SNDR of 51 dB is achievable at an input bandwidth of 3 MHz and a sampling rate of 65 MHz, where the power is 271 mu W.
    IEEE, 2012, 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), pp. 3170 - 3173, English
    [Refereed]
    International conference proceedings

  • Neutron-Induced Soft Error Rate Estimation for SRAM Using PHITS
    Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper presents a novel neutron-induced soft-error-rate (SER) estimation tool with a particle transport code: PHITS. The proposed tool can calculate the SER according to various data patterns and the layout of the memory cells in an SRAM. As layouts, two kinds of an NMOS-PMOS-NMOS 6T and an inside-out PMOS-NMOS-PMOS versions are considered. The proposed tool distinguishes a single-event-upset (SEU) SER, a horizontal multiple-cell-upset (MCU) SER, and a vertical MCU SER using an extracting function. The horizontal MCU SER in the inside-out version of the PMOS-NMOS-PMOS 6T SRAM cell layout was expected to be 26-41% less than that of the general NMOS-PMOS-NMOS 6T cell layout.
    IEEE, 2012, 2012 IEEE 18TH INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), 138 - 141, English
    [Refereed]
    International conference proceedings

  • Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    We present a small-area second-order all-digital time-to-digital converter (TDC) with two frequency shift oscillators (FSOs) comprising inverter chains and dynamic flipflops featuring low jitter. The proposed FSOs can maintain their phase states through continuous oscillation, unlike conventional gated ring oscillators (GROs) that are affected by transistor leakage. Our proposed FSOTDC is more robust and is eligible for all-digital TDC architectures in recent leaky processes. Low-jitter dynamic flipflops are adopted as a quantization noise propagator (QNP). A frequency mismatch occurring between the two FSOs can be canceled out using a least mean squares (LMS) filter so that second-order noise shaping is possible. In a standard 65-nm CMOS process, an SNDR of 61 dB is achievable at an input bandwidth of 500 kHz and a sampling rate of 16 MHz, where the respective area and power are 700 μm 2 and 281 μW. © 2012 IEEE.
    2012, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 190 - 191, English
    [Refereed]
    International conference proceedings

  • Masanao Nakano, Toshihiro Konishi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This report describes a robust method of Instantaneous Heart Rate (IHR) detection from noisy electrocardiogram (ECG) signals. Generally, the IHR is calculated from the interval of R-waves. Then, the R-waves are extracted from the ECG using a threshold. However, in wearable biosignal monitoring systems, various noises (e.g. muscle artifacts from myoelectric signals, electrode motion artifacts) increase incidences of misdetection and false detection because the power consumption and electrode distance of the wearable sensor are limited to reduce its size and weight. To prevent incorrect detection, we use a short-time autocorrelation technique. The proposed method uses similarity of the waveform of the QRS complex. Therefore, it has no threshold calculation Process and it is robust for noisy environment. Simulation results show that the proposed method improves the success rate of IHR detection by up to 37%.
    IEEE, 2012, Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual International Conference, 2012, 6703 - 6, English, International magazine
    [Refereed]
    Scientific journal

  • Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Takashi Takeuchi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    We propose a transfer gate phase coupler for a low-power multi-phase oscillator (MPOSC). The phase coupler is an nMOS transfer gate, which does not waste charge to the ground and thus achieves low power. The proposed MPOSC can set the number of outputs to an arbitrary number. The test circuit in a 180-nm process and a 65-nm process exhibits 20 phases, including 90 degrees different angles. The designs in a 180-nm CMOS process and a 65-nm CMOS process were fabricated to confirm its process scalability; in the respective designs, we observed 36.6% and 38.3% improvements in a power-delay products, compared with the conventional MPOSCs using inverters and nMOS latches. In a 65-nm process, the measured DNL and 3 sigma period jitter are, respectively, less than +/- 1.22 degrees and 5.82 ps. The power is 284 mu W at 1.85 GHz.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Dec. 2011, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E94A(12) (12), 2701 - 2708, English
    [Refereed]
    Scientific journal

  • SUGAHARA Takanobu, HE Guangji, FUJINAGA Tsuyoshi, MIYAMOTO Yuki, NOGUCHI Hiroki, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    We have developed a low-power VLSI chip for 60-kWord real-time continuous speech recognition based on a Hidden Markov Model (HMM). Our implementation includes a cache architecture using locality of speech recognition, beam pruning using a dynamic threshold, two-stage language model searching, highly parallel Gaussian Mixture Model (GMM) computation based on the mixture level, a variable 50-frame look-ahead scheme and elastic pipeline operation between the Viterbi transition and GMM processing. Results show that our implementation achieves 95% bandwidth reduction (70.86 MB/s) and 78% required frequency reduction (126.5 MHz) for 60-kWord real-time continuous speech recognition. The test chip, fabricated using 40 nm CMOS technology and containing 1.9 M transistors for logic and 7.8 Mbit on-chip memory, occupies 2.2 mm x 2.5 mm area. Measured data show 144 mW power consumption at 126.5 MHz and 1.1 V. © 2011 IEEE.
    Nov. 2011, Proceedings of the Custom Integrated Circuits Conference, 111(327) (327), 79 - 84, Japanese
    [Refereed]

  • A 40nm 144mW VLSI Processor for Realtime 60k Word Continuous Speech Recognition
    SUGAHARA Takanobu, HE Guangji, FUJINAGA Tsuyoshi, MIYAMOTO Yuki, NOGUCHI Hiroki, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    We have developed a low power VLSI chip for 60k-word real-time continuous speech recognition based on HMM(Hidden Markov Model). Our implementation includes a cache architecture using the locality of speech recognition, beam pruning using dynamic threshold, two-stage language model searching highly parallel Gaussian Mixture Model (GMM) computation based on mixture level, Variable 50 frames look-ahead scheme and elastic pipeline operation between Viterbi transition and GMM processing. Results show that our implementation achieves 97.94% bandwidth reduction (70.86MB/s) and 78% required frequency reduction (126.5MHz) for 60k-word real-time continuous speech recognition. The test chip has been fabricated in 40nm CMOS technology and occupies 2.2mm X 2.5mm containing 1.9M transistors for logic and 7.8 Mbit on-chip memory. Measured data show 144mW power consumption at 126.5MHz and 1.1V.
    The Institute of Electronics, Information and Communication Engineers, Nov. 2011, IEICE technical report. Component parts and materials, 111(326) (326), 79 - 84, Japanese

  • Toshihiro Konishi, Shintaro Izumi, Koh Tsuruda, Hyeokjong Lee, Takashi Takeuchi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    Concomitantly with the progress of wireless communications, cognitive radio has attracted attention as a solution for depleted frequency bands. Cognitive radio is suitable for wireless sensor networks because it reduces collisions and thereby achieves energy-efficient communication. To make cognitive radio practical, we propose a low-power multi-resolution spectrum sensing (MRSS) architecture that has flexibility in sensing frequency bands. The conventional MRSS scheme consumes much power and can be adapted only slightly to process scaling because it comprises analog circuits. In contrast, the proposed architecture carries out signal processing in a digital domain and can detect occupied frequency bands at multiple resolutions and with low power. Our digital MRSS module can be implemented in 180-nm and 65-nm CMOS processes using Verilog-HDL. We confirmed that the processes respectively dissipate 9.97 mW and 3.45 mW
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Nov. 2011, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E94A(11) (11), 2287 - 2294, English
    [Refereed]
    Scientific journal

  • Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Tsuyoshi Fujinaga, Shintaro Izumi, Yasuo Ariki, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a SIFT (Scale Invariant Feature Transform) descriptor generation engine which features a VLSI oriented SIFT algorithm, three-stage pipelined architecture and novel systolic array architectures for Gaussian filtering and key-point extraction. The ROI-based scheme has been employed for the VLSI oriented algorithm. The novel systolic array architecture drastically reduces the number of operation cycle and memory access. The cycle counts of Gaussian filtering module is reduced by 82%, compared with the SIMD architecture. The number of memory accesses of the Gaussian filtering module and the key-point extraction module are reduced by 99.8% and 66% respectively, compared with the results obtained assuming the SIMD architecture. The proposed schemes provide processing capability for HDTV resolution video (1920 x 1080 pixels) at 30 frames per second (fps). The test chip has been fabricated in 65 nm CMOS technology and occupies 4.2 x 4.2 mm(2) containing 1.1M gates and 1.38 Mbit on-chip memory. The measured data demonstrates 38.2 mW power consumption at 78 MHz and 1.2 V.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2011, IEICE TRANSACTIONS ON ELECTRONICS, E94C(4) (4), 448 - 457, English
    [Refereed]
    Scientific journal

  • Noguchi Hiroki, Takagi Tomoya, Kugata Koji, Izumi Shintaro, Yoshimoto Masahiko, Kawaguchi Hiroshi
    We propose a microphone array network that realizes ubiquitous sound acquisition. Several nodes with 16 microphones are connected to form a novel huge sound acquisition system, which carries out voice activity detection (VAD), sound source localization, and sound enhancement. The three operations are distributed among nodes. Using the distributed network, we produce a low-traffic data-intensive array network. To manage node power consumption, VAD is implemented. The system uses little power when speech is not active. For sound localization, a network-connected multiple signal classification (MUSIC) algorithm is used. The experimental result of the sound-source enhancement shows a signal-noise ratio (SNR) improvement of 7.75dB using 112 microphones. Network traffic is reduced by 99.11% when using 1,024 microphones.
    Information and Media Technologies Editorial Board, 2011, Information and Media Technologies, 6(2) (2), 307 - 318, English

  • Masanori Nishino, Hiroki Noguchi, Yusuke Shimai, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a low-power eight-core Mixed Integer Quadric Programming (MIQP) solver processor VLSI for real-time autonomous robot control. It features an eight-core architecture with operation-level and task-level parallel processing using speculative execution to solve a 75-variable MIQP problem within 100 ms. The VLSI, containing 12.2 M transistors and occupying 2.7 × 3.0 mm 2 area, was designed and fabricated using 40-nm CMOS technology. It consumes 568 mW with 135 MHz operation, allowing real-time, low-power capability for a 75-variable MIQP solver. © 2011 IEEE.
    2011, 2011 IEEE/SICE International Symposium on System Integration, SII 2011, 469 - 472, English
    [Refereed]
    International conference proceedings

  • Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    This paper presents a second-order ΔΣ analog to digital converter (ADC) operating in a time domain. In the proposed ADC architecture, a voltage-controlled delay unit (VCDU) converts an input analog voltage to a delay time. Then the number of clocks output from a gated ring oscillator (GRO) is counted up during the delay time. Because no switched capacitor or opamp is used, the proposed ADC can be implemented in a small area and at low power. For the same reason, it has process scalability: it can be in keeping with Moore's law. A time error is propagated to the second GRO by a multi-stage noise-shaping (MASH) topology, which provides second-order noise-shaping. In a standard 40-nm CMOS process, a SNDR of 45 dB is achievable at an input bandwidth of 3 MHz and a sampling rate of 100 MHz, where the power is 583.2 μW. Its area is 640 μm2. © 2011 IEEE.
    2011, Proceedings - IEEE International Symposium on Circuits and Systems, 518 - 521, English
    [Refereed]
    International conference proceedings

  • Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    We propose a microphone array network that realizes ubiquitous sound acquisition. Several nodes with 16 microphones are connected to form a novel huge sound acquisition system, which carries out voice activity detection (VAD), sound source localization, and sound enhancement. The three operations are distributed among nodes. Using the distributed network, we produce a low-traffic data-intensive array network. To manage node power consumption, VAD is implemented. The system uses little power when speech is not active. For sound localization, a network-connected multiple signal classification (MUSIC) algorithm is used. The experimental result of the sound-source enhancement shows a signal-noise ratio (SNR) improvement of 7.75dB using 112 microphones. Network traffic is reduced by 99.11% when using 1,024 microphones.
    Information Processing Society of Japan, 2011, Journal of Information Processing, 19, 129 - 140, English
    [Refereed]
    Scientific journal

  • Data Aggregation Protocol for Multiple Sound Sources Acquisition with Microphone Array Network
    Shintaro Izumi, Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shimpei Soda, Masahiko Yoshimoto, Hiroshi Kawaguchi
    In this paper, we propose a microphone array network that realizes ubiquitous sound acquisition for multiple sound sources. Several nodes with 16 microphones are connected to form a huge sound acquisition system, which carries out voice activity detection (VAD), sound source localization, and enhancement. The three operations are distributed among nodes with multi-hop data communication. Using the distributed network, we produce a low-traffic data-intensive array network. In the sound-source enhancement, we combine the delay-and-sum beam-forming algorithm with network data aggregation. The prototype of microphone array node is implemented in SUZAKU FPGA boards, which demonstrates a real-time multiple-sound-source enhancement operation.
    IEEE, 2011, 2011 20TH INTERNATIONAL CONFERENCE ON COMPUTER COMMUNICATIONS AND NETWORKS (ICCCN), English
    [Refereed]
    International conference proceedings

  • Shimpei Soda, Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    Physical positions are quite useful to realize an intuitive interface for communication among mobile terminals. We propose the placement of a microphone array on mobile terminals and the use of a network as an intuitive interface. The mobile terminals can obtain their relative positions by emitting a sound, which facilitates estimation of the directions of arrival (DOAs) among them. We produced a prototype using a tablet PC, 16 microphones, and an FPGA board. Then, we implemented two applications, exploiting the positioning system to elucidate its wider possibilities. © 2011 IEEE.
    2011, 2011 Joint Workshop on Hands-free Speech Communication and Microphone Arrays, HSCMA'11, 155 - 156, English
    [Refereed]
    International conference proceedings

  • A 40-nm 640-mu m(2) 45-dB Opampless All-Digital Second-Order MASH Delta Sigma ADC
    Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    This paper presents a second-order Delta Sigma analog to digital converter (ADC) operating in a time domain. In the proposed ADC architecture, a voltage-controlled delay unit (VCDU) converts an input analog voltage to a delay time. Then the number of clocks output from a gated ring oscillator (GRO) is counted up during the delay time. Because no switched capacitor or opamp is used, the proposed ADC can be implemented in a small area and at low power. For the same reason, it has process scalability: it can be in keeping with Moore's law. A time error is propagated to the second GRO by a multi-stage noise-shaping (MASH) topology, which provides second-order noise-shaping. In a standard 40-nm CMOS process, a SNDR of 45 dB is achievable at an input bandwidth of 3 MHz and a sampling rate of 100 MHz, where the power is 583.2 mu W. Its area is 640 mu m(2).
    IEEE, 2011, 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), pp. 518-521, 518 - 521, English
    [Refereed]
    International conference proceedings

  • Shintaro Izumi, Takashi Takeuchi, Takashi Matsuda, Hyeokjong Lee, Toshihiro Konishi, Koh Tsuruda, Yasuharu Sakai, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    This paper presents an ultra-low-power single-chip sensor-node VLSI for wireless-sensor-network applications A communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system. through a vertical cooperative design among circuits. architecture, and communication protocols The sensor-node LSI features a synchronous media access control (MAC) protocol and integrates a transceiver. 18051 microcontroller. and dedicated MAC processor The test chip occupies 3 x 3 mm(2) in a 180-nm CMOS process. including 1 38 M transistors It dissipates 58 0 mu W under a network environment
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Mar. 2010, IEICE TRANSACTIONS ON ELECTRONICS, E93C(3) (3), 261 - 269, English
    [Refereed]
    Scientific journal

  • A 34.7-mW Quad-Core MIQP Solver Processor for Robot Control
    Hiroki Noguchi, Junichi Tani, Yusuke Shimai, Masanori Nishino, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We propose a quad-core mixed integer quadric programming (MIQP) solver processor. The MIQP solver is applicable to hybrid control systems including real-time control robotics. Using multi-core architecture, fixed-point calculations, and branch-and-bound method with high-dispersion performance while processing a 50-variable problem, our design achieves 34.7-mW operation at a frequency of 52 MHz in measurement results, although a core 2 duo PC requires 3.16 GHz to solve it as rapidly.
    IEEE, 2010, IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010, English
    [Refereed]
    International conference proceedings

  • Toshihiro Konishi, Koh Tsuruda, Shintaro Izumi, Hyeokjong Lee, Hidehiro Fujiwara, Takashi Takeuchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We propose a novel image rejection scheme for a low-IF (low intermediate frequency,) receiver. A Delta-Sigma modulator converts I/Q signals to digital values, and then they are digitally processed. The Delta-Sigma modulator is a second-order complex band-pass type; the proposed architecture is suitable for various multi-channel communications and/or cognitive radio. As the first step in the digital signal processing, a spectrum is shifted so that the desired signal band is centered at 0 Hz. Next, by LPFs (low-pass filters), an image signal and the quantization noise of the Delta-Sigma modulator are removed. These LPFs also function as a decimation filter; thus a dedicated decimation filter is not needed, and an extra area and power for it are saved. The test chip occupies 0.75 mm2 in a 180-nm mixed-signal process. The power is 6.0 mW at 1.8 V. The IRR (image rejection ratio) achieves 60 dB.
    IEEE, 2009, 2009 IEEE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUTERS AND SIGNAL PROCESSING, VOLS 1 AND 2, 565 - 570, English
    [Refereed]
    International conference proceedings

  • A 58-mu W Single-Chip Sensor Node Processor Using Synchronous MAC Protocol
    Takashi Takeuchi, Shintaro Izumi, Takashi Matsuda, Hyeokjong Lee, Yu Otake, Toshihiro Konishi, Koh Tsuruda, Yasuharu Sakai, Hidehiro Fujiwara, Chikara Ohta, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We propose a single-chip ultralow-power sensor node processor with a synchronous media access control (MAC). It is comprised of a transceiver, i8051 micro processor, and dedicated MAC processor. The test chip occupies 3 x 3 mm(2) in a 180-nm CMOS process, including 1.38 M transistors. The power is 58.0 mu W under a network environment.
    JAPAN SOCIETY APPLIED PHYSICS, 2009, 2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 290 - 291, English
    [Refereed]
    International conference proceedings

  • Takashi Takeuchi, Shintaro Izumi, Takashi Matsuda, Hyeokjong Lee, Toshihiro Konishi, Koh Tsuruda, Yasuhiro Sakai, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    This paper presents an ultra-low-power single-chip sensor-node VLSI with a synchronous MAC protocol and divided data-buffer SRAM for wireless-sensor-network applications. One of the most challenging issues in wireless sensor networks is extension of the overall network lifetime. So a communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system, through a vertical cooperative design among circuits, architecture, and communication protocols. A transceiver, i8051 microcontroller, and dedicated MAC processor with divided SRAM are integrated in a single chip. The test chip occupies 3.0 x 1.7 mm(2) in a 180-nm CMOS process, including 0.63 M transistors. Divided data-buffer reduces 18.6% of average power and the LSI consumes 6.34 mu W under a network environment.
    IEEE, 2009, 2009 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2009), 202 - 207, English
    [Refereed]
    International conference proceedings

  • Shintaro Izumi, Takashi Takeuchi, Takashi Matsuda, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    Broadcasting is an elementary operation in wireless multihop networks. Flooding is a simple broadcast protocol but it frequently causes serious redundancy. contention and collisions. Probability based methods are promising because they can reduce broadcast messages without additional hardware and control packets. In this paper, the counter-based scheme which is one of the probability based methods is focused on as a broadcast protocol, and the RAD (Random Assessment Delay) Extension is proposed to improve the original counter-based scheme. The RAD Extension can be implemented without additional hardware, so that the strength of the counter-based scheme can be preserved. In addition, we propose the additional algorithm called Hop Count Aware RAD Extension to establish shorter path from the source node. Simulation results show that both of the RAD Extension and the Hop Count Aware RAD Extension reduce the number of retransmitting nodes by about 10% compared with the original scheme. Furthermore. the Hop Count Aware RAD Extension call establish almost the same path length as the counter-based scheme.
    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Nov. 2008, IEICE TRANSACTIONS ON COMMUNICATIONS, E91B(11) (11), 3489 - 3498, English
    [Refereed]
    Scientific journal

  • Takashi Matsuda, Shintaro Izumi, Takashi Takeuchi, Hidehiro Fujiwara, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    The most challenging issue of sensor networks is extension of overall network system lifetimes. It is important for the extension of system lifetime to determine the routing considering data aggregation. Data aggregation can reduce network traffic by the elimination of the redundant data. Though data aggregation is effective, sensor node needs a certain amount of RAM to aggregate data. RAM has standby energy, and its power consumption is one of the major factors in sensor node. In this work, we investigate the relationship among RAM capacity, data aggregation and power consumption. Then, we propose to use divided operating SRAM. Proposal method can reduce energy of sensor node even if RAM capacity is large. © 2008 IEICE.
    2008, 2008 7th Asia-Pacific Symposium on Information and Telecommunication Technologies, APSITT, pp. 130-134, 115 - 119, English
    [Refereed]
    International conference proceedings

  • Shintaro Izumi, Koh Tsuruda, Takashi Takeuchi, Hyeokjong Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto
    Concomitantly with the progress of wireless communications, cognitive radio has attracted attention as a solution for depleted frequency bands. Cognitive radio is suitable for wireless sensor networks because it reduces collisions and thereby achieves energy-efficient communication. To make cognitive radio practical, we propose a low-power multi-resolution spectrum sensing (MRSS) architecture that has flexibility in sensing frequency bands. The conventional MRSS scheme consumes much power and can be adapted only slightly to process scaling because it comprises analog circuits. In contrast, the proposed architecture carries out signal processing in a digital domain and can detect occupied frequency bands at multiple resolutions and with low power. Our digital MRSS module can be implemented in 180-nm and 65-nm CMOS processes using Verilog-HDL. We confirmed that the processes respectively dissipate 9.97 mW and 3.45 mW.
    IEEE, 2008, 2010 FOURTH INTERNATIONAL CONFERENCE ON SENSOR TECHNOLOGIES AND APPLICATIONS (SENSORCOMM), 39 - 44, English
    [Refereed]
    International conference proceedings

  • Hop Count Aware broadcast algorithm with Random Assessment Delay Extension for wireless sensor networks
    Shintaro Izumi, Takashi Matsuda, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    Broadcasting is an elementary operation in wireless multi-hop networks. Flooding is a simple broadcast protocol but it frequently causes serious redundancy, contention and collisions. Probability based methods are promising because they can reduce broadcast messages without additional hardwares and control packets. In this paper, the counter-based scheme which is one of the probability based methods is focused on as a broadcast protocol, and the RAD (Random Assessment Delay) Extension is proposed to improve the original counter-based scheme. The RAD Extension can be implemented without additional hardwares, so that the strength of the counter-based scheme can be preserved. In addition, we propose the additional algorithm called Hop Count Aware RAD Extension to establish shorter path from the source node. Simulation results show that both of the RAD Extension and the Hop Count Aware RAD Extension reduce the number of retransmitting nodes by about 10% compared with the original scheme. Furthermore, the Hop Count Aware RAD Extension can establish almost the same path length as the counter-based scheme.
    IEEE, 2008, 2008 7TH ASIA-PACIFIC SYMPOSIUM ON INFORMATION AND TELECOMMUNICATION TECHNOLOGIES, 207 - +, English
    [Refereed]
    International conference proceedings

  • Impact of divided static random access memory considering data aggregation for wireless sensor networks
    Takashi Matsuda, Shintaro Izumi, Takashi Takeuchi, Hidehiro Fujiwara, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    The most challenging issue of sensor networks is extension of overall network system lifetimes. It is important for the extension of system lifetime to determine the routing considering data aggregation. Data aggregation can reduce network traffic by the elimination of the redundant data. Though data aggregation is effective, sensor node needs a certain amount of RAM to aggregate data. RAM has standby energy, and its power consumption is one of the major factors in sensor node. In this work, we investigate the relationship among RAM capacity, data aggregation and power consumption. Then, we propose to use divided operating SRAM. Proposal method can reduce energy of sensor node even if RAM capacity is large.
    IEEE, 2008, 2008 7TH ASIA-PACIFIC SYMPOSIUM ON INFORMATION AND TELECOMMUNICATION TECHNOLOGIES, 115 - +, English
    [Refereed]
    International conference proceedings

  • A Flexible Baseband Processor with Multi-Resolution Spectrum-Sensing Functionality
    Koh Tsuruda, Shintaro Izumi, Hyeokjong Lee, Takashi Takeuchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    In this paper, we propose a reconfigurable baseband processor for a cognitive radio that has multi-resolution bandpass filters. By applying the distributed arithmetic algorithm to the reconfigurable baseband processor and rewriting SRAM data in it, a channel center frequency and bandwidth are reconfigurable. The filter bandwidth can be changed from 40 kHz to 240 kHz with a 10 kHz resolution on our prototype processor. The power is 13 mW at a supply voltage of 1.8 V in a 0.18-mu m CMOS process.
    IEEE, 2008, 2008 INTERNATIONAL SYMPOSIUM ON INFORMATION THEORY AND ITS APPLICATIONS, VOLS 1-3, 1422 - 1427, English
    [Refereed]
    International conference proceedings

  • Shintaro Izumi, Takashi Matsuda, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto
    Broadcasting is an elementary operation in wireless multi-hop networks. Flooding is a simple broadcast protocol but it causes serious redundancy, contention and collisions. Probability based methods are promising because they can reduce broadcast messages at the cost of slight additional hardware and without any control. In this paper, the counter-based scheme which is one of the probability based methods is focused on as a broadcast protocol, and the RAD (random assessment delay) extension is proposed to improve the original. The RAD extension can be realized by the almost same hardware as the original, so that the strength of the counter-based scheme is kept. Simulation results showed that the RAD extension can reduce the number of retransmitting nodes by about 10 % compared with the original scheme. © 2007 IEEE.
    2007, 2007 International Conference on Sensor Technologies and Applications, SENSORCOMM 2007, Proceedings, pp.76-81, 76 - 81, English
    [Refereed]
    International conference proceedings

MISC

  • Estimation of Heartbeat Intervals for Multiple Individuals using Non-contact Multimodal Sensors Utilizing Radio Waves and Acceleration
    和田紗希, 牧村英俊, 西本研悟, 稲沢良夫, 和泉慎太郎
    2024, 電子情報通信学会技術研究報告(Web), 123(446(MICT2023 77-82)) (446(MICT2023 77-82))

  • 電波と加速度を用いた非接触マルチモーダルセンサによる心拍間隔推定
    和田紗希, 牧村英俊, 西本研悟, 稲沢良夫, 和泉慎太郎
    2024, 日本生体医工学会大会プログラム・抄録集(Web), 63rd

  • Development of Flexible Thermoelectric Conversion Devices and Hot/Cold Display Technology Contributing to the Next Generation IoT Society
    菅原徹, 菅原徹, 和泉慎太郎, 和泉慎太郎, 佐藤克成, 佐藤克成, 吉國聖乃, 吉國聖乃, 伊藤雄一, 伊藤雄一, 伊庭野健造, 伊庭野健造
    2024, セラミックス, 59(6) (6)

  • Estimation of Heartbeat Intervals using Non-contact Multimodal Sensors Utilizing Radio Waves and Acceleration
    和田紗希, 牧村英俊, 西本研悟, 稲沢良夫, 和泉慎太郎
    2024, 日本生体医工学会大会プログラム・抄録集(Web), 63rd

  • Analysis of the waveform pattern classification of SpO2 in Sleep Apnea Syndrome patients
    高安みずき, 永野達也, 山本正嗣, 和泉慎太郎, 桂田直子, 吉崎飛鳥, 羽間大祐, 松村佳乃子, 立原素子, 小林和幸
    2024, 日本呼吸器学会誌(Web), 13

  • Comparison of two wearable respiratory monitors: a prospective observational study
    佐藤宏紀, 永野達也, 和泉慎太郎, 平位一廣, 吉村遼佑, 岩本夏彦, 藤本昌大, 福井崇文, 高田尚哉, 高安みずき, 山田潤, 矢谷敦彦, 三村千尋, 福田貴与子, 古川皓一, 羽間大祐, 桂田直子, 山本正嗣, 立原素子, 小林和幸
    2024, 日本呼吸器学会誌(Web), 13

  • Thin-film Organic Active Matrix for Ultraflexible Infrared Imagers
    川端玲, 川端玲, LI Kou, 荒木徹平, 荒木徹平, 秋山実邦子, 秋山実邦子, 杉町夏穂, 杉町夏穂, 松岡望, 松岡望, 高橋典華, 酒井大揮, 松崎勇斗, 越水瞭, 阿部岳晃, 和泉慎太郎, 和泉慎太郎, 栗平直子, 植村隆文, 河野行雄, 河野行雄, 関谷毅, 関谷毅, 関谷毅
    2024, Symposium on Microjoining and Assembly Technology in Electronics, 30th

  • Heartbeat-based Non-contact Biometric Authentication Using Microwave Doppler Sensor
    高橋宏太, 和泉慎太郎, 川口博
    [東京] : Institute of Electrical Engineers of Japan, Nov. 2023, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 40, 5p, Japanese

  • 和泉 慎太郎
    一般社団法人 電気学会, 01 Apr. 2023, 電気学会論文誌E(センサ・マイクロマシン部門誌), 143(4) (4), NL4_1 - NL4_1, Japanese

  • 利便性向上のためのメタプログラミング環境の検討
    吉川, 慎太郎, 和泉, 諭
    プログラミング言語C++では、メタプログラミングの1つであるテンプレートメタプログラミングという手法が広く使われている。この手法は最適化されたアセンブリの出力や擬似的な言語機能の拡張、コンパイル時に事前処理や計算ができる一方、プログラムの可読性の低下やエラーメッセージが煩雑になる問題がある。本研究では前述の問題を改善しC++開発の効率化を行うことを目的とし、拡張言語からC++のソースコードを生成するメタプログラミング環境を実装する。
    16 Feb. 2023, 第85回全国大会講演論文集, 2023(1) (1), 231 - 232, Japanese

  • Contactless respiration monitoring using spatial ultrasound Doppler sensor
    都甲尚志, 河合晃聖, 石井徹, 和泉慎太郎, 川口博
    2023, 電子情報通信学会大会講演論文集(CD-ROM), 2023

  • BIN KAMARULZAMAN M. Shahrul Amir, 濱邉理久, 安田祐人, 大原遼太郎, 佐藤駿, 和泉慎太郎, 川口博
    This paper presents a simulation method for bathroom surveillance using an ultrasonic raytracing technique. First, we explain the signal-capturing methods for the waves reflected by an object. Then, results obtained using this method are discussed. Object detection in an environment with significant interference is achieved through a signal-processing method, called beamforming. Evaluation results demonstrate that the proposed method achieved an average of 76.1% accuracy across seven different postures and positions, with an error range of 25 cm. Further evaluation shows that the results of our method were identical to the real measurements, which provides a foundation for future accuracy improvements through machine-learning techniques.
    2023, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 40th

  • 3D person location estimation using spatial ultrasound and VAE in the bathroom
    佐藤駿, 安田祐人, 大原遼太郎, 濱邉理玖, 玄田貴之, 今中翔哉, 和泉慎太郎, 川口博
    2023, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 40th

  • Bathroom acoustic event detection using machine learning
    森浩貴, 玄田貴之, 佐藤駿, 大原遼太郎, SHAHRUL Muhammad, 安田裕人, 河合晃聖, 濱邉理玖, 和泉慎太郎, 川口博
    2023, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 40th

  • 次世代IoT社会に資するフレキシブル熱電変換デバイスと温冷提示技術の開発
    菅原徹, 和泉慎太郎, 佐藤克成, 伊藤雄一, 伊庭野健造
    2023, クリーンテクノロジー, 33(3) (3)

  • Visualization of hand position of Leopold’s maneuvers using video image and the pose estimation and questionnaire survey of observation details -Comparison of beginners vs. experts-
    辻宅紀子, 齋藤いずみ, 和泉慎太郎
    2023, 看護理工学会誌(Web), 10

  • Road traffic monitoring by machine learning using ultrasonic and audible sound
    濱邉理玖, 大原遼太郎, 安田祐人, 佐藤駿, 川口博, 和泉慎太郎
    2023, 電子情報通信学会大会講演論文集(CD-ROM), 2023

  • Feature Extraction from Body Surface Potential using Variational Autoencoder
    吉野早耶, 和泉慎太郎, 川口博
    2023, 電子情報通信学会大会講演論文集(CD-ROM), 2023

  • 1W/8R20T SRAMコードブックメモリによる深層学習プロセッサの主記憶帯域削減
    大原遼太郎, 加太雅也, 大地正和, 大地正和, 安田祐人, 大地正和, 濱邉理玖, 和泉慎太郎, 川口博
    2023, 電子情報通信学会技術研究報告(Web), 123(143(SDM2023 35-53)) (143(SDM2023 35-53))

  • 頸髄不全損傷患者における下肢伸展挙上運動の体幹筋活動解析と歩行獲得の関連
    杉本達也, 杉本達也, 和泉慎太郎, 上田雄也, 目片幸二郎, 前沢寿亨, 瀧川朋亨, 伊藤康夫
    2023, 理学療法兵庫, (29) (29)

  • いびき音のディープラーニングによる睡眠時無呼吸症候群のスクリーニング
    永野達也, 関谷怜奈, 和泉慎太郎
    2023, 日本睡眠学会定期学術集会プログラム・抄録集, 45th

  • 体表面電位用シート型伸縮電極アレイと多チャネル小型無線計測システムの開発
    荒木徹平, 和泉慎太郎, 和泉慎太郎, 村瀬翔, 村瀬翔, 関谷毅
    2023, 臨床神経生理学(Web), 51(5) (5)

  • Masaki Ishibashi, Shintaro Izumi, Ryo Takamatsu, Shusuke Yoshimoto, Yuki Noda, Teppei Araki, Takafumi Uemura, Tsuyoshi Sekitani, Hiroshi Kawaguchi
    The use of piezoelectric film for pulse wave measurement is advantageous in terms of power consumption, but it has limitations in terms of sensitivity and noise resistance. This letter described a high-sensitivity pulse wave sensor that used a piezoelectric film. Furthermore, we proposed a 3-D gel structure to improve the sensor's skin contact condition and measurement sensitivity through structural innovations. Our approach was to increase the strain of the piezoelectric film by utilizing a structure with a tapered rate, which increased the sensitivity of the sensor structure. The subject was a healthy adult male (24 years old). We also fabricated a prototype pulse wave sensor with the proposed structure and continuously measured pulse waves at multiple locations on the radial artery of the wrist. Through signal processing, we were able to obtain measurement data that were effective for monitoring pulse wave propagation and showed that fluctuations in pulse wave velocity could be detected.
    2023, IEEE Sensors Letters, 7(9) (9)

  • Tsujitaku Noriko, Saito Izumi, Izumi Shintaro
    レオポルド触診法の習得は,経験則による部分が大きい.本研究は触診の実施状況を可視化し,段法ごとの差や初学者(看護学生)と熟練者(助産師)の相違点を調査することで効率的な手技習得に繋がる資料を得ることを目的とした.初学者と熟練者各5名が妊婦腹部触診モデルに対して触診法を実施する場面を動画像で記録し,骨格推定アルゴリズムで手指の位置を座標情報として検出した.動画像を目視で観察し,観察項目は質問紙にて調査した.目視の観察から,熟練者は定められた方法で触診を実施しない傾向を認めた.触診範囲については,第1・2段法で熟練者のほうが大きい傾向がみられ,触診部位については第3段法において熟練者がより胎児下降部に近い位置を触診する傾向を認めた.観察項目では,子宮収縮など熟練者のみが観察していた項目もあり熟練者・初学者間で差異がみられた.本研究のみでは教育への資料を得ることはむずかしく,さらなる研究が必要である.

    【キーメッセージ】
    1.今回の研究は看護・介護のどのような問題をテーマにしているのか?
    研究を行うきっかけとなったことはどのようなことか?
    → 看護技術を学ぶ際に感覚やイメージで補われている部分を量的に可視化できないかと考えたこと.

    2.この研究成果が看護・介護にどのように貢献できるのか?あるいは,将来的に貢献できることは何か?
    → 本研究の限界と課題をもとに研究を重ねることで,看護技術習得における資料を得られると考える.

    3.今後どのような技術が必要になるのか?
    → 本研究の課題を改善するためには手指の検出精度の向上や異常値の効率的な除外技術が必要である.
    The Society for Nursing Science and Engineering, 2023, Journal of Nursing Science and Engineering, 10, 135 - 145, Japanese

  • Non-contact vital monitoring using spatial ultrasound
    河合晃聖, 和泉慎太郎, 川口博, 近藤勲, 小椋朗広
    Institute of Electrical Engineers of Japan, Nov. 2022, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 39, 3p, Japanese

  • Analysis of SLR in spinal cord injury patients using multimodal sensing
    吉倉崚人, 和泉慎太郎, 杉本達也, 川口博, 杉本達也
    Institute of Electrical Engineers of Japan, Nov. 2022, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 39, 4p, Japanese

  • Ryo Takamatsu, Shogo Amano, Shintaro Izumi, Hiroshi Ohta, Toshikazu Nezu, Yuki Noda, Teppei Araki, Takafumi Uemura, Tsuyoshi Sekitani, Hiroshi Kawaguchi
    IEEE, 30 Oct. 2022, 2022 IEEE Sensors, 39, 1 - 4, Japanese

  • Wearable Perspiration Volume Sensor Using Dual-Frequency Impedance Measurement
    高松稜, 和泉慎太郎, 川口博
    2022, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 39th

  • Outdoor 3D object reconstruction method using spatial ultrasound and VAE
    佐藤駿, 安田祐人, 大原遼太郎, 濱邉理玖, 石井徹, 和泉慎太郎, 川口博
    2022, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 39th

  • Low Power Noise Reduction Technology for ECG Sensors Using Dry Electrodes
    元辻有貴, 和泉慎太郎, 川口博
    2022, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 39th

  • Changes in sock-wearing behavior and compensatory movements before and after wearing a materinty-simulation jacket -Study using video images and pose estimation algorithms-
    野田真優子, 齋藤いずみ, 和泉慎太郎
    2022, 看護理工学会誌(Web), 10

  • Thermal Stimulation Device Using Matrix Drive Circuitry
    江森俊哉, 和泉慎太郎, 和泉慎太郎, 伊庭野健造, 伊庭野健造, 伊藤雄一, 伊藤雄一, 佐藤克成, 佐藤克成, 菅原徹, 菅原徹, 川口博
    2022, 日本機械学会ロボティクス・メカトロニクス講演会講演論文集(CD-ROM), 2022

  • Development of flexible thermoelectric conversion device for Society of Internet of Things (IoT)
    菅原徹, 菅原徹, 菅原徹, 和泉慎太郎, 和泉慎太郎, 伊庭野健造, 伊庭野健造
    2022, 応用物理学会秋季学術講演会講演予稿集(CD-ROM), 83rd

  • Noda Mayuko, Saito Izumi, Izumi Shintaro
    As pregnancy progresses, the abdomen increases and pregnant womenss daily activities are expected to change. This study aimed to reproduce the changes in the body shape of pregnant females in third trimester using a maternity-simulation jacket, clarify the changes in movement patterns before and after wearing the jacket, and obtain useful suggestions for health guidance in pregnancy. Seventeen females were asked to put on socks in the sitting position before and after wearing the jacket; the characteristic changes in their movement were observed and evaluated from the recorded video images. Joint positions were estimated using a pose estimation algorithm, and three-dimensional coordinate information was extracted. Joint angles were calculated, and trends in movement patterns were analyzed using principal component analysis. In the end-occupant position, 8 (47.0%) wore socks with their thighs parallel to the mid-plane before wearing the device, and 9 (52.9%) wore socks with their hip joints in abduction and external rotation after wearing the device. The results suggest the necessity of using hip stretching and a sock-wearing self-help device.
    The Society for Nursing Science and Engineering, 2022, Journal of Nursing Science and Engineering, 10, 12 - 21, Japanese

  • Effects of the presence of parturient women on the length of time that nurses and midwives spend in the rooms of other patients during a night shift in a mixed obstetric ward
    寺岡歩, 齋藤いずみ, 和泉慎太郎, 大滝千文, 大滝千文, 西川美樹, 大澤佳代
    2022, 看護理工学会誌(Web), 9

  • Non-Contact Biometric Identification Using Microwave Doppler Sensor
    和泉慎太郎
    シーエムシー出版, 2021, 機能材料, 41(11) (11), 3 - 9, Japanese

  • An analysis of the locations visited by night shift midwives and the duration spent in each while providing round-the-clock critical care to high-risk mothers in a maternity ward
    西川美樹, 齋藤いずみ, 大滝千文, 大澤佳代, 和泉慎太郎
    2021, 看護理工学会誌(Web), 9

  • マイクロ波ドップラーセンサを用いた心拍計測における個人差の評価
    真鍋歩夢, 和泉慎太郎, 落合拓光, 川口博
    2021, 電子情報通信学会技術研究報告(Web), 121(24(WBS2021 1-21)) (24(WBS2021 1-21))

  • 大型船舶エンジンの燃料効率改善を目的とした回転体位相計測センサの開発
    小銭瞭介, 原田正康, 吉川裕木子, 石井徹, 和泉慎太郎, 川口博, 上村祥平, 荒木要, 松田真理子
    2021, マリンエンジニアリング学術講演会講演論文集, 91st

  • Analysis of night-shift nurses’ locations and durations using information communication equipment: A prospective observational study of a mixed obstetric ward with severe patients in Japan
    大滝千文, 齋藤いずみ, 和泉慎太郎, 大澤佳代, 大澤佳代
    2020, 看護理工学会誌(Web), 7

  • A Consideration of Heart Rate Measurement Technology with Doppler sensor
    落合拓光, 和泉慎太郎, 矢野裕二, 川口博, 吉本雅彦
    2020, 電子情報通信学会大会講演論文集(CD-ROM), 2020

  • A Study of Machine Learning Architecture for Wearable Bio-signal Sensor
    渡辺大輔, 矢野祐二, 和泉慎太郎, 川口博, 吉本雅彦
    2020, 電子情報通信学会大会講演論文集(CD-ROM), 2020

  • Low Power circuit for Electro-Cardiogram Measurement Using Body Temperature Power Generation
    藤井将裕, 和泉慎太郎, 矢野裕二, 川口博, 吉本雅彦
    2020, 電子情報通信学会大会講演論文集(CD-ROM), 2020

  • 加速度センサとひずみセンサを用いた咳嗽検出手法の検討
    渡辺大輔, 和泉慎太郎, 大歳丈博, 永野達也, 西村善博, 吉本雅彦, 川口博
    2020, 電子情報通信学会技術研究報告(Web), 120(219(MICT2020 7-20)) (219(MICT2020 7-20))

  • Analysis of day shift nurses’ and midwives’ locations and durations using information communication equipment: A prospective observational study of a mixed obstetric ward with critical patients in Japan
    大滝千文, 齋藤いずみ, 和泉慎太郎, 大澤佳代
    2020, 看護理工学会誌(Web), 7

  • Heart Rate Interval Error Compensation Method Using Multiple-Photoplethysmography
    親富彩花, 和泉慎太郎, 矢野裕二, 川口博, 吉本雅彦
    2020, 電子情報通信学会大会講演論文集(CD-ROM), 2020

  • Classification of nocturnal hypoxemia for the patients with idiopathic pulmonary fibrosis
    安田裕一郎, 永野達也, 安田美奈, 鶴野広介, 岡村佳代子, 船田泰弘, 高月清宣, 飛野和則, 西馬照明, 大西尚, 小林和幸, 和泉慎太郎, 西村善博
    2020, 日本呼吸器学会誌(Web), 9

  • 開発した新型パッチ式脳波計測シートの更年期診療への応用の可能性の検討
    志村宏太郎, 澤田健二郎, 香林正樹, 香林正樹, 山本実咲, 清水亜麻, 八木太郎, 和泉慎太郎, 倉智博久, 関谷毅, 木村正
    2020, 日本女性医学学会雑誌, 28(1) (1)

  • Otaki Chifumi, Saito Izumi, Izumi Shintaro, Osawa Kayo
    Approximately 80% of hospital-based childbirth in Japan takes place in mixed obstetric wards, which comprise a mix of the obstetrics department and other departments. Although mixed obstetric wards treat patients from multiple departments, previous studies have not clarified the procedures used by nursing staff in the ward, or nursing by night-time nurses. The purpose of this study was to reveal the actual status of night-shift nurses in a mixed obstetrics ward that treats severe patients. This time motion study used smartphones and beacons to measure the place and duration of stay for night-shift nurses working in a mixed obstetric ward. We found that nurses' mean bedside stay time per patient in a general patient room was 31.9 minutes on days when there were severe patients hospitalized in the severe patient room, and 33.6 minutes on days when there were no severe patients. Furthermore, the mean stay time in each place during a nurse's 13-hour shift was 39.2% in the nurse station, 34.4% in the general patient room, and 1.7% in the severe patient room. We believe that these results can be used as data for the placement of nursing staff involved in operating a safe mixed ward.
    The Society for Nursing Science and Engineering, 2020, Journal of Nursing Science and Engineering, 7(0) (0), 13 - 24, English

  • A Low-Power Photoplethysmography Sensor Using Current Integration Circuit
    笹井香菜, 和泉慎太郎, 渡辺健斗, 矢野祐二, 川口博, 吉本雅彦
    Institute of Electrical Engineers of Japan, 19 Nov. 2019, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 36, 4p, Japanese

  • 大面積シート型インフラモニタリングシステムの開発 (特集 3月研究会「IoT/AIに応える有機分子・バイオエレクトロニクスデバイス」)
    植村 隆文, 荒木 徹平, 吉本 秀輔, 野田 祐樹, 和泉 慎太郎, 関谷 毅, 森 時彦, 高宮 真, 桜井 貴康, 濱田 浩, 河村 直明, 塚田 智之, 小林 保之, 滝野 晶平, 井出 周治, 瀬下 雄一, 堤 知明, 桒原 惇, 大籏 英樹, 石井 伸晃, 尾藤 慎也, 金村 崇, 桑原 章史, 水野 晃太郎, 福原 克郎, 田中 稔彦, 高安 理寛, 山本 陽介
    応用物理学会有機分子・バイオエレクトロニクス分科会, Feb. 2019, Molecular electronics and bioelectronics = 応用物理学会,有機分子・バイオエレクトロニクス分科会会誌, 30(1) (1), 25 - 28, Japanese

  • 光電式容積脈波法を用いた脈拍測定の低消費電力化手法
    渡辺健斗, 和泉慎太郎, 矢野祐二, 川口博, 吉本雅彦
    2019, 電子情報通信学会技術研究報告, 118(383(MICT2018 59-67)(Web)) (383(MICT2018 59-67)(Web))

  • Noise Evaluation Method for EEG Measurement System
    稲岡美咲, 稲岡美咲, 和泉慎太郎, 吉本秀輔, 吉本秀輔, 根津俊一, 野田祐樹, 荒木徹平, 植村隆文, 植村隆文, 関谷毅, 関谷毅
    2019, 電子情報通信学会技術研究報告, 118(509(MICT2018 68-73)(Web)) (509(MICT2018 68-73)(Web))

  • 布電極を用いたマルチモーダル生体信号計測の検討
    天野将吾, 天野将吾, 天野将吾, 松場瑞生, 松場瑞生, 和泉慎太郎, 和泉慎太郎, 吉本秀輔, 野田祐樹, 荒木徹平, 荒木徹平, 荒木徹平, 植村隆文, 植村隆文, 伊藤晴彦, 関谷毅, 関谷毅, 関谷毅
    2019, 電子情報通信学会技術研究報告, 119(263(MICT2019 23-37)(Web)) (263(MICT2019 23-37)(Web))

  • ウェアラブル生体情報センサのための学習推論アルゴリズムの検討
    渡辺大輔, 矢野祐二, 和泉慎太郎, 川口博, 吉本雅彦
    2019, 電子情報通信学会技術研究報告, 119(263(MICT2019 23-37)(Web)) (263(MICT2019 23-37)(Web))

  • ARモデルを用いた心拍変動解析のための低消費電力アーキテクチャの検討
    吉田聖也, 和泉慎太郎, 矢野裕二, 川口博, 吉本雅彦
    2019, 電子情報通信学会大会講演論文集(CD-ROM), 2019

  • イリョウ キカン カラ ザイタク イリョウ ・ カンゴ ソウゴウ レンケイ ニ カンスル ケンキュウ 、 ザイタク イリョウ ・ カイゴ ニ カンスル ケンキュウ
    大滝 千文, 和泉 慎太郎, 岩佐 由美
    フランスベッド・メディカルホームケア研究・助成財団, 2019, 研究助成・事業助成ボランティア活動助成報告書, 30, 87 - 101, Japanese

  • 車載テクノロジー最前線 マイクロ波ドップラーセンサを用いた走行車両内での心拍計測
    和泉 慎太郎
    技術情報協会, Apr. 2018, 車載テクノロジー = Automotive technology, 5(4) (4), 44 - 47, Japanese

  • 産科混合病棟における情報通信機器を使った看護の可視化 産科と産科以外の科の患者のベッドサイド滞在時間の分析による考察
    齋藤いずみ, 寺岡歩, 中井かをり, 三井由紀子, 和泉慎太郎
    2018, 日本看護管理学会学術集会抄録集, 22nd

  • Wearable Monitoring Systems for Heart Rate Variability Analysis
    和泉慎太郎
    2018, 電子情報通信学会技術研究報告, 118(173(ICD2018 14-38)) (173(ICD2018 14-38))

  • メモリ容量と帯域幅削減のための分散深層学習ハードウェア
    川口博, 森陽紀, 陽川哲也, 和泉慎太郎, 井上淳樹
    2018, 電気関係学会関西連合大会講演論文集(CD-ROM), 2018

  • Field Intelligence搭載型大面積分散IoTプラットフォームの研究開発
    植村隆文, 荒木徹平, 吉本秀輔, 野田祐樹, 和泉慎太郎, 関谷毅, 加賀谷司, 森時彦, 高宮真, 桜井貴康, 濱田浩, 河村直明, 塚田智之, 井出周治, 瀬下雄一, 堤知明, 桑原惇, 大はた英樹, 石井伸晃, 尾藤慎也, 金村崇, 桑原章史, 水野晃太郎, 福原克郎, 田中稔彦, 片桐真吾, 高安理寛, 山本陽介
    2018, 電子情報通信学会大会講演論文集(CD-ROM), 2018

  • Chemical Reaction Actuator and Wireless Power Feeding for Swallowable Sensing Device
    中村 亮太, 和泉 慎太郎, 川口 博, 吉本 雅彦, 太田 英敏
    Institute of Electrical Engineers of Japan, 31 Oct. 2017, 「センサ・マイクロマシンと応用システム」シンポジウム論文集 電気学会センサ・マイクロマシン部門 [編], 34, 1 - 5, Japanese

  • Improvement of measurement accuracy and usability in wearable biosignal monitoring
    和泉慎太郎
    電子情報通信学会, 11 May 2017, 電子情報通信学会技術研究報告, 117(19) (19), 37 - 41, Japanese

  • 奨励講演 ウェアラブル生体情報計測における計測精度とユーザビリティの向上—Improvement of measurement accuracy and usability in wearable biosignal monitoring—ヘルスケア・医療情報通信技術
    和泉 慎太郎
    電子情報通信学会, May 2017, 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 117(20) (20), 37 - 41, Japanese

  • マイクロ波ドップラーセンサを用いた車両走行中の心拍計測手法
    松永大地, 和泉慎太郎, 川口博, 吉本雅彦
    2017, 電子情報通信学会大会講演論文集(CD-ROM), 2017

  • ヘルスケアIoTに向けた生体センシングの低消費電力化と非接触化
    和泉慎太郎
    2017, 電子情報通信学会大会講演論文集(CD-ROM), 2017

  • ノイズフィードバック技術を用いたウェアラブル向け容量結合型心電センサ
    永里佑樹, 和泉慎太郎, 川口博, 吉本雅彦
    2017, 電子情報通信学会大会講演論文集(CD-ROM), 2017

  • ウェアラブル生体センサの現状と小型軽量化・低消費電力化を実現する技術 (特集 ウェアラブルデバイスへ向けた薄くて曲がる電源,電池技術)
    和泉 慎太郎
    技術情報協会, Jun. 2016, エネルギーデバイス = Energy device, 3(5) (5), 50 - 53, Japanese

  • 前田 慎太郎, 濱田 和明, 和泉 昌宏, 橋本 和典
    【はじめに,目的】青少年期野球選手のみを対象として上腕骨小頭離断性骨軟骨炎(以下OCD)の病巣部位を調査した報告は非常に少ない。また,投球時痛を生じるタイミングとOCDの病巣部位の関連性を調査した報告は見当たらない。そこで,本研究ではOCDの病巣部位を調査し,さらに投球時痛を生じるphase(以下painful phase)による比較検討を行ったので報告する。【方法】対象は2010年1月から2015年9月に受診しOCDと診断された青少年期野球選手42名とした。年齢(平均±標準偏差)は発症時13.2±1.3歳,受診時13.7±1.4歳で,性別は全例男性であった。ポジションは投手20名,内野手16名,捕手3名,外野手3名であった。X線分類(岩堀2006)は中央型7名,広範囲型35名であった。病巣部位の検討は,MRIのT1強調矢状断像にて,上腕骨長軸線に対して病巣部後下縁と前上縁を結んだ線の垂線が成す角度(以下病巣角)を算出した。すなわち,病巣角が大きいほど病巣がより前方に位置することを意味する。次に,問診にて聴取可能であった34名をpainful phaseによって群分けし,各群間の病巣角を比較検討した。統計処理は一元配置分散分析を行い,多重比較検定はTukey-Kramer法を用いた。危険率5%未満を有意とした。【結果】全42名の病巣角の平均値は64.8±12.3°であった。次に,聴取可能であった34名のpainful phaseの内訳は,Late Cocking(LC)期が6名(18%),Acceleration(Acc)期が14名(41%),Deceleration(Dcl)期が8名(23%),投球中は痛くないが後で痛い(After pain)が3名(9%),痛みは全くない(No pain)が3名(9%)であった。各群の病巣角は,LC群77.6±12.0°,Acc群65.0±11.3°,Dcl群55.0±11.7°,After pain群66.9±4.2°,No pain群60.1±3.1°であった。LC群はDcl群よりも病巣角が有意に大きかった(p<0.01)。その他の各群間には有意な差を認めなかった。【結論】本研究の結果,病巣角は64.8±12.3°であった。これは,先行研究(室井ら2008)の報告における54.0±9.3°(n=16)と比較して約10°大きい値であり,OCDの病巣が小頭のより前方に位置することが示唆された。このことより,青少年期野球選手のOCD症例は,肘関節屈曲位を強めた投球動作を行うことで腕橈関節に特異的なストレスを生じている可能性が考えられる。また,painful phaseによる比較ではLC群がDcl群よりも有意に病巣角が大きく,LC群は小頭のより前方に,Dcl群はより後方に病巣が位置することが示唆された。これらより,投球動作時に痛みを生じる際の肘関節肢位とOCDの病巣部位に関連性がある可能性が考えられた。一方で,After pain群やNo pain群を約18%認めたことから,OCDは必ずしも投球時痛を伴うものではないという事実も考慮する必要があり,結果の解釈には注意を要する。本研究の結果はOCD発生要因検討の一助となると考える。今後は身体機能や投球フォームも含めた検討が必要である。
    公益社団法人 日本理学療法士協会, 2016, 理学療法学Supplement, 2015, 1260, Japanese

  • ヘルスケアデバイスと材料
    川口博, 和泉慎太郎, 吉本雅彦
    2016, 日本化学会春季年会講演予稿集(CD-ROM), 96th

  • 日常生活の常時モニタリングを実現する生体情報計測技術
    和泉慎太郎
    2016, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 33rd

  • 和泉 慎太郎, 川口 博, 吉本 雅彦
    一般社団法人 電気学会, 2016, 電気学会論文誌. E, センサ・マイクロマシン部門誌, 136(3) (3), NL3_2 - NL3_2, Japanese

  • マイクロ波ドップラーセンサーを用いた車載応用非接触心拍変動・呼吸モニタリング技術の開発
    和泉 慎太郎
    タカタ財団, 2016, タカタ財団助成研究論文集, 2016, 中扉1p,1 - 32, Japanese

  • IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

    Monitoring of daily life using a wearable sensor is useful to prevent lifestyle diseases. This paper presents an electrocardiograph (ECG) monitoring SoC using a non-volatile MCU and a noise-tolerant instantaneous heartbeat detector.

    The Japan Society of Applied Physics, 2016, Oyo Buturi, 85(4) (4), 301 - 305, Japanese
    Introduction scientific journal

  • Haptic Stimulus Actuator using Piezoelectric Pump for Wearable Devices
    児玉 泰佑, 和泉 慎太郎, 正木 何奈, 川口 博, 吉本 雅彦, 前中 一介
    Institute of Electrical Engineers of Japan, 28 Oct. 2015, 「センサ・マイクロマシンと応用システム」シンポジウム論文集 電気学会センサ・マイクロマシン部門 [編], 32, 1 - 5, Japanese

  • Daichi Matsunag, Shintaro Izumi, Keisuke Okuno, Hiroshi Kawaguchi, Masahiko Yoshimoto
    This paper describes a non-contact and noise-tolerant heart beat monitoring system. The proposed system comprises a microwave Doppler sensor and range imagery using Microsoft Kinect™. The possible application of the proposed system is a driver health monitoring. We introduce the sensor fusion approach to minimize the heart beat detection error. The proposed algorithm can subtract a body motion artifact from Doppler sensor output using time-frequency analysis. The body motion artifact is a crucially important problem for biosignal monitoring using microwave Doppler sensor. The body motion speed is obtainable from range imagery, which has 5-mm resolution at 30-cm distance. Measurement results show that the success rate of the heart beat detection is improved about 75% on average when the Doppler wave is degraded by the body motion artifact.
    Institute of Electrical Engineers of Japan, 28 Oct. 2015, Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual International Conference, 32, 1 - 5, Japanese, International magazine

  • A Noise-Tolerant ECG Sensing Method for Wearable Healthcare Systems
    TANAKA Yoshito, KAWAMOTO Yuta, NAKAI Youzaburo, OKUNO Keisuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    The Institute of Electronics, Information and Communication Engineers, 24 Nov. 2014, IEICE technical report. Computer systems, 114(346) (346), 47 - 47, Japanese

  • A Normally-off Wearable Monitoring SoC using Non-volatile MCU
    Matsunaga Daichi, NAKAI Yozaburo, KAWAMOTO Yuta, NAKAGAWA Tomoki, OKUNO Keisuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    The Institute of Electronics, Information and Communication Engineers, 24 Nov. 2014, Technical report of IEICE. ICD, 114(345) (345), 49 - 49, Japanese

  • 低消費電力貼り付け型センサのためのテンプレートマッチングを用いたロバスト心拍抽出手法の開発
    中井 陽三郎, 和泉 慎太郎, 中野 将尚
    Institute of Electrical Engineers of Japan, 20 Oct. 2014, 「センサ・マイクロマシンと応用システム」シンポジウム論文集 電気学会センサ・マイクロマシン部門 [編], 31, 1 - 4, Japanese

  • A 0.38-V Operating STT-MRAM with Process Variation Tolerant Sense Amplifier
    UMEKI Yohei, YANAGIDA Koji, YOSHIMOTO Shusuke, IZUMI Shintaro, YOSHIMOTO Masahiko, Kawaguchi Hiroshi, TSUNODA Koji, SUGII Toshihiro
    This paper exhibits a 65-nm 8-Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at a single supply voltage with a process-variation tolerant sense amplifier. The proposed sense amplifier comprises a boosted-gate nMOS and negative-resistance pMOSes as loads, which maximizes the readout margin in any process corner. The STT-MRAM achieves a cycle time of 1.9μs (=0.526MHz) at 0.38V. The operating power is 6.15μW at that voltage. The minimum energy per access is 3.89pJ/bit when the supply voltage is 0.44V. The proposed STT-MRAM operates at lower energy than SRAM when a utilization of a memory bandwidth is 14% or less.
    The Institute of Electronics, Information and Communication Engineers, 17 Apr. 2014, Technical report of IEICE. ICD, 114(13) (13), 47 - 51, Japanese

  • STT-MRAM Architecture for Improving Throughput
    Mori Haruki, Yanagida Koji, Umeki Yohei, Yoshimoto Shusuke, Izumi Shintaro, Yoshimoto Masahiko, Kawaguchi Hiroshi, Tsunoda Koji, Sugii Toshihiro
    The Institute of Electronics, Information and Communication Engineers, 21 Jan. 2014, Technical report of IEICE. ICD, 113(419) (419), 27 - 27, Japanese

  • High-Speed Ferroelectric 6T4C Shadow SRAM for Normally-Off Computing
    NAKAGAWA Tomoki, YOSHIMOTO Shusuke, KITAHARA Yuki, YANAGIDA Koji, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    The Institute of Electronics, Information and Communication Engineers, 21 Jan. 2014, Technical report of IEICE. ICD, 113(419) (419), 39 - 39, Japanese

  • Electrocardiogram analytical technique for wearable living body sensors wearable biomedical sensor
    NAKAI Yozaburo, IZUMI Shintaro, NAKANO Masanao, YAMASHITA Ken, FUJII Takahide, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    The Institute of Electronics, Information and Communication Engineers, 21 Jan. 2014, Technical report of IEICE. ICD, 113(419) (419), 61 - 61, Japanese

  • Cross-Layer Design for Ubiquitous Sensing Systems : From Circuit to Application
    IZUMI Shintaro
    The Institute of Electronics, Information and Communication Engineers, 21 Jan. 2014, Technical report of IEICE. ICD, 113(419) (419), 79 - 79, Japanese

  • ウェアラブルな生体情報常時計測システムのための心拍抽出手法の開発
    和泉慎太郎
    2014, 立石科学技術振興財団助成研究成果集, (23) (23)

  • A2.4x-Real-Time VLSI Processor for 60-k Word Continuous Speech Recognition
    何 光霽, 宮本 優貴, 松田 薫平, 和泉 慎太郎, 川口 博, 吉本 雅彦
    本稿では,6 万語彙の実時間連続音声認識のための低消費電力 VLSI チップについて説明する.高速,高精度,低消費電力で 6 万語彙連続音声認識を実現するために,以前試作した音声認識プロセッサの提案手法を用いた上で,高並列な 8-pass Viterbi 遷移アーキテクチャを実装することで,全体処理速度のネックとなっている Viterbi 部分をさらに高速化させた.また,探索処理において第 2 パスに tri-gram を用いることで,認識精度を bi-gram のみの場合より約 2% 向上できた.回路規模 2.98MTr,オンチップ SRAM 容量 4.29Mbits の 6 万語彙連続音声認識のための専用プロセッサを設計し,40nm プロセスで試作した.bi-gram のみを使う場合,実時間処理に必要な62.51MHz 動作時の消費電力は 54.8mW であった.標準電圧 (1.1V) で最大 200MHz (177.4mW) 動作が確認され,3 倍速動作を実現できた.また,tri-gram を使う場合,200MHz で最高処理速度は 2.25 倍速であり,消費電力は 174.56mW であった.This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). We implement parallel and pipelined architecture for GMM computation and Viterbi processing. It includes a 8-path Viterbi transition architecture to maximize the processing speed and adopts tri-gram language model to improve the recognition accuracy. A two-level cache architecture is implemented for the demo system. The test chip, fabricated in 40 nm CMOS technology, occupies 1.77 mm x 2.18 mm containing 2.98 M transistors for logic and 4.29 Mbit on-chip memory. The measured results show that our implementation achieves 25% required frequency reduction (62.5 MHz) and 26% power consumption reduction (54.8 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 3.02x and 2.25x times faster than real-time at 200 MHz using the bigram and trigram language models, respectively.
    30 Sep. 2013, 研究報告システムLSI設計技術(SLDM), 2013(7) (7), 1 - 6, Japanese

  • Normally-Off Computing: 4. Normally-off Computing Techniques for Wearable Healthcare Systems
    藤森 敬和, 和泉 慎太郎, 川口 博, 志賀 利一, 吉本 雅彦
    本稿ではウェアラブルな貼り付け型生体情報計測センサにおける課題と,生体信号計測のためのノーマリーオフコンピューティング手法について解説する.また,本研究で試作した貼り付け型生体情報計測センサLSIを紹介する.常時計測可能な貼り付け型生体情報計測センサノードを実現するためには,センサのサイズと重量を可能な限り削減する必要がある.貼り付け型センサノードを構成する要素の内,重量に対して最も支配的な要素はバッテリであり,ノーマリーオフコンピューティングによってセンサLSIの消費電力を極限まで削減することを目指している.
    情報処理学会 ; 1960-, 15 Jun. 2013, 情報処理, 54(7) (7), 677 - 682, Japanese

  • Introducing Multiple Microphone Arrays for Enhancing Smart Home Voice Control
    Shimpei Soda, Masahide Nakamura, Shinsuke Matsumoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
    We have previously developed a voice control system for a home network system (HNS), using a microphone array technology. Although the microphone array achieved a convenient hands-free controller, a single array had limitations on coverage of sound collection and speech recognition rate. In this paper, we try to overcome the limitations by increasing the number of the microphone arrays. Specifically, we construct a microphone array network using four separate arrays, and enhance algorithms of sound source localization (SSL) and sound source separation (SSS) on the network. We also conduct an experimental evaluation, where precision of SSL and speech recognition rate are evaluated in a real HNS test-bed. As a result, it is shown that the usage of multiple arrays significantly improves the coverage and speech recognition ratio, compared with the previous system.
    The Institute of Electronics, Information and Communication Engineers, Jan. 2013, 電子情報通信学会技術研究報告, 112(388) (388), 19 - 24, English

  • KAWAGUCHI Hiroshi, YOSHIMOTO Shusuke, OKUMURA Shunsuke, Amashita TAKURO, IZUMI Shintaro, YOSHIMOTO Masahiko
    Reliability Engineering Association of Japan, 2013, The Journal of Reliability Engineering Association of Japan, 35(8) (8), 432 - 432, Japanese

  • トクシュウ チイキハツ 、 モノ ズクリ サンギョウ ノ サイセイ
    和泉 慎太郎
    北海道東北地域経済総合研究所, 2013, NETT : North East Think Tank of Japan, (80) (80), 19 - 21, Japanese

  • Instantaneous Heart Rate Detection Using Short-Time Autocorrelation for Wearable Healthcare Systems
    YAMASHITA Ken, NAKANO Masanao, KONISHI Toshihiro, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    This report describes a robust method of Instantaneous Heart Rate (IHR) detection from noisy electrocardiogram (ECG) signals. Generally, the IHR is calculated from the interval of R-waves. Then, the R-waves are extracted from the ECG using a threshold. However, in wearable biosignal monitoring systems, various noises (e.g. muscle artifacts from myoelectric signals, electrode motion artifacts) increase incidences of misdetection and false detection because the power consumption and electrode distance of the wearable sensor are limited to reduce its size and weight. To prevent incorrect detection, we use a short-time autocorrelation technique. The proposed method uses similarity of the waveform of the QRS complex. Therefore, it has no threshold calculation Process and it is robust for noisy environment. By the proposed method, it is possible to reduce power consumption of Analog Front End and relax the performance requirements of the electrodes because IHR is calculated by digital signal processing.
    The Institute of Electronics, Information and Communication Engineers, 10 Dec. 2012, Technical report of IEICE. ICD, 112(365) (365), 27 - 27, Japanese

  • C-12-3 Bit Error Rate Estimation SRAM Considering Temperature Fluctuation
    Kitahara Yuki, Kagiyama Yuki, Okumura Shunsuke, Yanagida Koji, Yoshimoto Shusuke, Nakata Yohei, Izumi Shintaro, Kawaguchi Hiroshi, Yoshimoto Masahiko
    The Institute of Electronics, Information and Communication Engineers, 06 Mar. 2012, Proceedings of the IEICE General Conference, 2012(2) (2), 75 - 75, Japanese

  • Handsfree Voice Interface for Home Network Service Using a Microphone Array Network
    SODA Shimpei, NAKAMURA Masahide, MATSUMOTO Shinsuke, MATSUBARA Noriyuki, KUGATA Koji, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    The voice control is a promising user interface for the home network system (HNS). In our previous interface, a user had to be equipped with an actual microphone device, which imposed a burden on the user. This paper presents a hands-free voice interface using a microphone array network. The microphone array network enables voice quality enhancement, as well as sound source localization, by networking multiple microphone arrays. Attaching the arrays to the walls or ceiling, users can input voice operations to the HNS from anywhere in the room, without being aware of the microphone devices. We implement a prototype system with a 16ch microphone array, and evaluate the accuracy of speech recognition, sound source localization, and voice activity detection in a real home network environment. The hands-free operation service and automatic speech logging service are implemented as practical services.
    The Institute of Electronics, Information and Communication Engineers, 06 Mar. 2012, Technical report of IEICE. SS, 111(481) (481), 73 - 78, Japanese
    Report scientific journal

  • A 75-Variable MIQP Solver Processor for Real-Time Robot Control
    NISHINO Masanori, NOGUCHI Hiroki, SHIMAI Yusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    This paper describes a low-power eight-core Mixed Integer Quadric Programming (MIQP) solver processor VLSI for real-time autonomous robot control. It features an eight-core architecture with operation-level and task-level parallel processing using speculative execution to solve a 75-variable MIQP problem within 100 ms. The VLSI, containing 12.2 M transistors and occupying 2.7×3.0 mm2 area, was designed and fabricated using 40-nm CMOS technology. It consumes 568 mW with 135 MHz operation, allowing real-time, low-power capability for a 75-variable MIQP solver.
    The Institute of Electronics, Information and Communication Engineers, 19 Jan. 2012, Technical report of IEICE. ICD, 111(388) (388), 103 - 107, Japanese

  • A 75-Variable MIQP Solver Processor for Real-Time Robot Control
    西野 允雅, 野口 紘希, 嶋井 優介, 和泉 慎太郎, 川口 博, 吉本 雅彦
    本研究では,自律ロボット制御のための実時間混合整数2次計画(MIQP)問題ソルバープロセッサVLSIを提案する.実時間でのMIQP問題求解のために,演算レベルとタスクレベルにおける2つの並列化手法を提案し,8コアによる並列処理アーキテクチャを実現した.40nmCMOSプロセスを用いて提案プロセッサの試作を行い,動作周波数135MHz,消費電力568mWにおいて75変数MIQP問題を100ms以内に求解できることを確認した.This paper describes a low-power eight-core Mixed Integer Quadric Programming (MIQP) solver processor VLSI for real-time autonomous robot control. It features an eight-core architecture with operation-level and task-level parallel processing using speculative execution to solve a 75-variable MIQP problem within 100 ms. The VLSI, containing 12.2 M transistors and occupying 2.7 × 3.0 mm2 area, was designed and fabricated using 40-nm CMOS technology. It consumes 568 mW with 135 MHz operation, allowing real-time, low-power capability for a 75-variable MIQP solver.
    12 Jan. 2012, 研究報告計算機アーキテクチャ(ARC), 2012(19) (19), 1 - 5, Japanese

  • A 284-uW 1.85-GHz 20-Phase Oscillator Using Transfer Gate Phase Couplers
    OKUNO Keisuke, KONISHI Toshihiro, LEE Hyeokiong, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    We propose a transfer gate phase coupler for a low-power multi-phase oscillator (MPOSC). The phase coupler is an nMOS transfer gate, which does not waste charge to the ground and thus achieves low power. The proposed MPOSC can set the number of outputs to an arbitrary number. The test circuit in a 180-nm process and a 65-nm process exhibits 20 phases, including 90° different angles. The designs in a 180-nm CMOS process and a 65-nm CMOS process were fabricated to confirm its process scalability; in the respective designs, we observed 36.6% and 38.3% improvements in a power-delay products, compared with the conventional MPOSCs using inverters and nMOS latches. In a 65-nm process, the measured DNL and 3a periodjitter are, respectively, less than ±1.22° and 5.82 ps. The power is 284μW at 1.85 GHz.
    The Institute of Electronics, Information and Communication Engineers, 08 Dec. 2011, Technical report of IEICE. ICD, 111(352) (352), 149 - 154, Japanese

  • Data-Intensive Sound Acquisition System with Large-scale Microphone Array
    Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
    We propose a microphone array network that realizes ubiquitous sound acquisition. Several nodes with 16 microphones are connected to form a novel huge sound acquisition system, which carries out voice activity detection (VAD), sound source localization, and sound enhancement. The three operations are distributed among nodes. Using the distributed network, we produce a low-traffic data-intensive array network. To manage node power consumption, VAD is implemented. The system uses little power when speech is not active. For sound localization, a network-connected multiple signal classification (MUSIC) algorithm is used. The experimental result of the sound-source enhancement shows a signal-noise ratio (SNR) improvement of 7.75dB using 112 microphones. Network traffic is reduced by 99.11% when using 1,024 microphones.We propose a microphone array network that realizes ubiquitous sound acquisition. Several nodes with 16 microphones are connected to form a novel huge sound acquisition system, which carries out voice activity detection (VAD), sound source localization, and sound enhancement. The three operations are distributed among nodes. Using the distributed network, we produce a low-traffic data-intensive array network. To manage node power consumption, VAD is implemented. The system uses little power when speech is not active. For sound localization, a network-connected multiple signal classification (MUSIC) algorithm is used. The experimental result of the sound-source enhancement shows a signal-noise ratio (SNR) improvement of 7.75dB using 112 microphones. Network traffic is reduced by 99.11% when using 1,024 microphones.
    15 Mar. 2011, 情報処理学会論文誌, 52(3) (3), 1102 - 1113, English

  • A Feasibility Study of Home Services Using a Microphone Array Network
    祖田心平, 松本真佑, 中村匡秀, 和泉慎太郎, 川口博, 吉本雅彦
    The home network system (HNS), which provides value-added services by orchestrating networked home appliances, equipments and sensors, attracts great attention to realize the next-generation smart home. Implementing the location-aware services within the the HNS context is one of greatest challenges, where the appropriate services are performed based according to the location of the inhabitants. We have been studying the technologies of sound source localization and sound source separation using networked multiple microphone arrays. In this paper, we conduct a feasibility study of applying the microphone array network to the location-aware services within the HNS. Specifically, we first present three kinds of home services using illustrative examples. We then enumerate three kinds of requirements (accuracy requirement, installation requirement, user requirement), which are essential for implementing the location-aware home services using the microphone array network. In a preliminary experiment, we evaluate the accuracy requirement using an actual microphone array. Moreover, we conduct a directivity shape simulation assuming multiple arrays.
    The Institute of Electronics, Information and Communication Engineers, 2011, 電子情報通信学会技術研究報告, 111(255(CPSY2011 25-41)) (255(CPSY2011 25-41)), 61 - 66, Japanese
    Report scientific journal

  • Data-Intensive Sound Acquisition with Data Aggregation Protocol for Microphone Array Networks
    和泉 慎太郎, 野口 紘希, 高木 智也
    情報処理学会, Dec. 2010, 情報処理学会研究報告, 2010(4) (4), 6p, Japanese

  • Data-Intensive Sound Acquisition with Data Aggregation Protocol for Microphone Array Networks
    IZUMI Shintaro, NOGUCHI Hiroki, TAKAGI Tomoya, KUGATA Koji, SODA Shinpei, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi
    We propose a microphone array network that realizes ubiquitous sound acquisition. A number of nodes with sixteen microphones are connected to form a novel huge sound acquisition system, which carries out VAD (voice activity detection), sound source localization and separation. The three operations are distributed among nodes with multi-hop network. Using the distributed network, we achieve a low-traffic data-intensive array network.
    The Institute of Electronics, Information and Communication Engineers, 28 Sep. 2010, IEICE technical report, 110(217) (217), 95 - 100, Japanese

  • A 58-uW Sensor Node LSI with Synchronous MAC Protocol
    S. Izumi, T. Takeuchi, T. Matsuda, H. Lee, T. Konishi, K. Tsuruda, Y. Sakai, C. Ohta, H. Kawaguchi, M. Yoshimoto
    Sep. 2010, Proceedings of Asia-aPacific Radio Science Conference (AP-RASC), English
    [Refereed]
    Others

  • 分散処理を用いた超低消費電力ネットワーク型マイクロホンアレーの研究
    祖田心平, 久賀田耕史, 高木智也, 和泉慎太郎, 野口紘希, 吉本雅彦, 川口博
    2010, 日本音響学会研究発表会講演論文集(CD-ROM), 2010

  • A 58-μW Single-Chip Sensor Node Processor Using Synchronous MAC Protocol
    IZUMI Shintaro, TAKEUCHI Takashi, MATSUDA Takashi, LEE Hyeokjong, KONISHI Toshihiro, TSURUDA Koh, SAKAI Yasuharu, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko
    In this paper, we propose a single-chip ultra low-power sensor node processor with a synchronous media access control (MAC). It is comprised of a transceiver, i8051 micro processor, and dedicated MAC processor. The test chip occupies 3x3mm^2 in a 180-nm CMOS process, including 1.38M transistors. The power is 58.0μW under a network environment.
    The Institute of Electronics, Information and Communication Engineers, 24 Sep. 2009, IEICE technical report, 109(214) (214), 141 - 145, Japanese

  • Isochronous MAC Protocol for Low-Power Wireless Sensor Node VLSI
    IZUMI Shintaro, MATSUDA Takashi, TAKEUCHI Takashi, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko
    In this paper, we propose the isochronous media access control (I-MAC) processor by cross layer design. The I-MAC can be simplified because all nodes are synchronized and predict their operations. And then, the time synchronization system is implemented in physical layer. Hence, a simple processor for the I-MAC can be implemented as dedicated hardware. As well, the power management module (PMM) controls the power supplies of the components, based on the I-MAC state transition of I-MAC processor. The proposal processor achieves a power of 10.93uW. The chip area is 200x200um2 in a 180-nm CMOS process.
    The Institute of Electronics, Information and Communication Engineers, 24 Feb. 2009, IEICE technical report, 108(457) (457), 177 - 182, Japanese

  • Izumi Shintaro, Yoshimoto Masahiko, Takeuchi Takashi, Matsuda Takashi, Lee Hyeokjong, Konishi Toshihiro, Tsuruda Koh, Sakai Yasuharu, Kawaguchi Hiroshi, Ohta Chikara
    In this paper, we propose a single-chip ultra low-power sensor node processor with a synchronous media access control (MAC). It is comprised of a transceiver, i8051 micro processor, and dedicated MAC processor. The test chip occupies 3x3mm^2 in a 180-nm CMOS process, including 1.38M transistors. The power is 58.0μW under a network environment.
    The Institute of Image Information and Television Engineers, 2009, ITE Technical Report, 33(0) (0), 141 - 145, Japanese

  • Variable bandwidth digital bandpass filter for cognitive radio
    TSURUDA Koh, IZUMI Shintaro, LEE Hyeokjong, TAKEUCHI Takashi, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    本論文ではコグニティブ無線向け可変帯域ディジタルBPF(Band-Pass Filter)を用いたベースバンドプロセッサを提案する.BPFにDA(Distributed Arithmetic)アルゴリズムを適応することで,内蔵するSRAMのデータを書き換えるだけでBPFの特性(チャネル中心周波数とバンド幅)を変化させることが可能となる.試作したベースバンドプロセッサではバンド幅を40kHzから240kHzまで10kHz単位で変化させることが可能である.CMOS 180nmプロセスで設計し,電源電圧1.8Vで消費電力は13.5mWであった.
    The Institute of Electronics, Information and Communication Engineers, 15 Oct. 2008, IEICE technical report, 108(253) (253), 137 - 141, Japanese

  • B-20-10 Study on Divided Static Random Access Memory Considering Data Aggregation for Wireless Sensor Nodes
    Sakai Yasuharu, Matsuda Takashi, Izumi Shintaro, Takeuchi Takashi, Fujiwara Hidehiro, Kawaguchi Hiroshi, Ohta Chikara, Yoshimoto Masahiko
    The Institute of Electronics, Information and Communication Engineers, 02 Sep. 2008, Proceedings of the Society Conference of IEICE, 2008(2) (2), 346 - 346, Japanese

  • Tsuruda Koh, Izumi Shintaro, Lee Hyeokjong, Takeuchi Takashi, Kawaguchi Hiroshi, Yoshimoto Masahiko
    本論文ではコグニティブ無線向け可変帯域ディジタルBPF(Band-Pass Filter)を用いたベースバンドプロセッサを提案する.BPFにDA(Distributed Arithmetic)アルゴリズムを適応することで,内蔵するSRAMのデータを書き換えるだけでBPFの特性(チャネル中心周波数とバンド幅)を変化させることが可能となる.試作したベースバンドプロセッサではバンド幅を40kHzから240kHzまで10kHz単位で変化させることが可能である.CMOS 180nmプロセスで設計し,電源電圧1.8Vで消費電力は13.5mWであった.
    The Institute of Image Information and Television Engineers, 2008, ITE Technical Report, 32(0) (0), 137 - 141, Japanese

  • A-21-26 Improvement of Counter-based Broadcasting for Wireless Sensor Networks using Timer Control
    IZUMI S., MATSUDA T., MIKAMI S., KAWAGUCHI H., OHTA C., YOSHIMOTO M.
    The Institute of Electronics, Information and Communication Engineers, 07 Mar. 2007, Proceedings of the IEICE General Conference, 2007, 417 - 417, Japanese

Books And Other Publications

  • 第6章第1節 ウェアラブル生体センサ
    IZUMI Shintaro
    Others, シーエムシー出版, 2017, Japanese
    Scholarly book

  • Normally-Off Computing
    NAKADA Takashi, FUJITA Shinobu, HAYASHIKOSHI Masanori, IZUMI Shintaro, FUJIMORI Yoshikazu, NAKAMURA Hiroshi
    Joint work, Springer Japan, 2017, English
    Scholarly book

  • 第7章第3節 ウェアラブル生体センサの低消費電力化とノーマリーオフ技術," ウェアラブルデバイスの小型、薄型化と伸縮、柔軟性の向上技術 pp. 364-374
    IZUMI SHINTARO
    Others, 技術情報協会, Dec. 2015, Japanese
    General book

Lectures, oral presentations, etc.

  • 光電式容積脈波法による脈拍測定の低消費電力化手法
    WATANABE Kento, IZUMI Shintaro, YANO Yuji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    ヘルスケア・医療情報通信技術研究会(MICT), Jan. 2019, Japanese, 電子情報通信学会, 東京都千代田区明治大学駿河台キャンパス, Domestic conference
    Oral presentation

  • ウェアラブルデバイスのための心拍変動モニタリングにおけるサンプリングレート低減手法
    NISHIKAWA Yuki, IZUMI Shintaro, YANO Yuji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    第35回「センサ・マイクロマシンと応用システム」シンポジウム, Oct. 2018, Japanese, 電気学会 センサ・マイクロマシン部門, 北海道札幌市 札幌市民交流プラザ, Domestic conference
    Poster presentation

  • ウェアラブルデバイスのための圧電素子を用いたマルチモーダルな心血管情報の計測
    OKANO Takaaki, IZUMI Shintaro, KATSUURA Takumi, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    第34回「センサ・マイクロマシンと応用システム」シンポジウム,01am2-PS-135,広島,2017年11月1日, Nov. 2017, Japanese, Domestic conference
    Oral presentation

  • 消化管内への留置を目的とした飲み込み型デバイスの検討
    NAKAMURA Ryota, IZUMI Shintaro, KAWAGUCHI Hiroshi, OHTA Hidetoshi, YOSHIMOTO Masahiko
    第34回「センサ・マイクロマシンと応用システム」シンポジウム,31pm3-PS-46,広島,2017年10月31日, Oct. 2017, Japanese, Domestic conference
    Oral presentation

  • ノイズフィードバック技術を用いたウェアラブル向け容量結合型心電センサ
    NAGASATO Yuki, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    IEICEソサイエティ大会, 2017年9月12-15日,東京, Sep. 2017, Japanese, Domestic conference
    Oral presentation

  • 選択的ソース線駆動方式を用いた画像処理プロセッサ向け低消費電力28nm FD-SOI 8TデュアルポートSRAM
    MORI Haruki, NAKAGAWA Tomoki, KITAHARA Yuki, KAWAMOTO Yuta, TAKAGI Kenta, YOSHIMOTO Shusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    LSIとシステムのワークショップ2017 ポスターセッション, 東京, 2017年5月, May 2017, Japanese, Domestic conference
    Oral presentation

  • マイクロ波ドップラーセンサを用いた車両走行中の心拍計測手法
    MATSUNAGA DAICHI, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO
    電子情報通信学会総合大会,B-20-10, 名古屋, 2017年3月22日., Mar. 2017, Japanese, 名古屋, Domestic conference
    Oral presentation

  • 日常生活の常時モニタリングを実現する生体情報計測技術
    IZUMI SHINTARO
    第33回「センサ・マイクロマシンと応用システム」シンポジウム, Oct. 2016, Japanese, 平戸, Domestic conference
    [Invited]
    Invited oral presentation

  • プロセスばらつき耐性を有する低電圧動作STT-MRAM向けカウンターベース読出し回路
    UMEKI YOHEI, YANAGIDA KOUJI, YOSHIMOTO SHUSUKE, IZUMI SHINTARO, YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, TSUNODA KOJI, SUGII TOSHIHIRO
    LSIとシステムのワークショップ2016, May 2016, Japanese, Domestic conference
    Poster presentation

  • 消化管内に留置可能な飲み込み型生体センサー
    IZUMI Shintaro, NAKAMURA Ryota, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    電子情報通信学会総合大会, Mar. 2016, Japanese, 福岡, Domestic conference
    Oral presentation

  • Process variation tolerant counter base read circuit for low-voltage operating STT-MRAM
    UMEKI Yohei, YANAGIDA Koji, KUROTSU Hiroaki, KITAHARA Hiroto, MORI Haruki, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, YOSHIMOTO Shusuke, TSUNODA Koji, SUGII Toshihiro
    DATE EMS Workshop, Mar. 2016, English, Dresden,Germany, International conference
    Poster presentation

  • Design and testing of a low-power wearable sensor SoC
    IZUMI Shintaro
    29thIEEE International Conference on Microelectronic Test Structures(ICMTS), Mar. 2016, Japanese, 横浜, Domestic conference
    Public discourse

  • ウェアラブルヘルスケア応用超低消費電力SoCの開発
    IZUMI Shintaro
    応用物理学会東海支部50周年記念研究会「バイオメディカルエレクトロニクス」, Dec. 2015, Japanese, 名古屋, Domestic conference
    [Invited]
    Invited oral presentation

  • Analysis of Soft Error Propagation considering Masking Effects on Re-convergent Path
    KIMI Yuta, MATSUKAWA Go, YOSHIDA Shuhei, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    IEEE Asian Test Symposium (ATS), Nov. 2015, English, International conference
    Oral presentation

  • A 298-fJ/writecycle 650-fJ/readcycle 8T Three-Port SRAM in 28-nm FD-SOI Process Technology for Image Processor
    MORI Haruki, NAKAGAWA Tomoki, KITAHARA Yuki, KAWAMOTO Yuta, TAKAGI Kenta, YOSHIMOTO Shusuke, IZUMI Shintaro, Nii Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    IEEE Custom Integrated Circuits Conference (CICC), Sep. 2015, English, International conference
    Oral presentation

  • 低SNR環境向け心拍抽出アルゴリズム
    MATSUNAGA Daichi, KAWAMOTO Yuta, NAKAI Yozaburo, OKUNO Keisuke, IZUMI Shintaro, YOSHIMOTO Masahiko
    LSIとシステムのワークショップ2015, May 2015, Japanese, 小倉, Domestic conference
    Poster presentation

  • 時間デジタル変換器を用いたIOサイズ8bitAD変換器
    OKUNO Keisuke, 小西恵大, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi
    LSIとシステムのワークショップ2015 ポスターセッション, May 2015, Japanese, 小倉, Domestic conference
    Poster presentation

  • ウェアラブル心電図計測SoC
    TANAKA Yoshito, NAKAI Yozaburo, KAWAMOTO Yuta, OKUNO Keisuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, KIMURA Hiromitsu, MURAMOTO Kyoji, FUCHIKAMI Takaaki, FUJIMORI Yoshikazu, YOSHIMOTO Masahiko
    LSIとシステムのワークショップ2015, May 2015, Japanese, 小倉, Domestic conference
    Poster presentation

  • 6T4C型低消費電力不揮発メモリ
    KITAHARA Hiroto, NAKAGAWA Tomoki, IZUMI Shintaro, TANAGIDA Kouji, KITAHARA Yuki, YOSHIMOTO Shusuke, UMEKI Yohei, MORI Haruki, KAWAGUCHI Hiroshi, KIMURA Hiromitsu, MURAMOTO Kyoji, FUCHIKAMI Takaaki, FUJIMORI Yoshikazu, YOSHIMOTO Masahiko
    LSIとシステムのワークショップ2015, May 2015, Japanese, 小倉, Domestic conference
    Poster presentation

  • 温度補償回路を用いた高速セットリングADPLL
    奥野 圭祐, 正木 何奈, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO
    第37回アナログRF研究会, Dec. 2014, Japanese, Domestic conference
    Oral presentation

  • 低消費電力貼り付け型センサのためのテンプレートマッチングを用いたロバスト心拍抽出手法の開発
    中井 陽三郎, IZUMI SHINTARO, 中野 将尚, 山下 顕, 藤井 貴英, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO
    第31回「センサ・マイクロマシンと応用システム」シンポジウム, Oct. 2014, Japanese, Domestic conference
    Oral presentation

  • 磁性変化型メモリの書き込み高速化メモリアーキテクチャ
    森 陽紀, 柳田 晃司, 梅木 洋平, 吉本秀輔, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO, 角田 浩司, 杉井 寿博
    LSIとシステムのワークショップ2014 ポスターセッション, May 2014, Japanese, 電子情報通信学会集積回路研究専門委員会, 小倉, Domestic conference
    Poster presentation

  • 温度補償回路を用いた高速セットリングADPLL
    正木 何奈, 奥野 圭祐, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO
    LSIとシステムのワークショップ2014 ポスターセッション, May 2014, Japanese, 電子情報通信学会集積回路研究専門委員会, 小倉, Domestic conference
    Poster presentation

  • 38μAウェアラブル生体情報計測プロセッサ
    中井 陽三郎, IZUMI SHINTARO, 山下 顕, 中野 将尚, 藤井 貴英, 小西 恵大, KAWAGUCHI HIROSHI, 木村 啓明, 丸元 共治, 渕上 貴昭, 藤森 敬和, 中嶋 宏, 志賀 利一, YOSHIMOTO MASAHIKO
    LSIとシステムのワークショップ2014 ポスターセッション, May 2014, Japanese, Domestic conference
    Poster presentation

  • ロバストな瞬時心拍抽出機能を有する低消費電力ウェアラブルヘルスケアシステム
    IZUMI Shintaro, NAKANO Masanao, YAMASHITA Ken, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    第14回計測自動制御学会システムインテグレーション部門講演会SI2013, Dec. 2013, Japanese, 神戸市, Domestic conference
    [Invited]
    Invited oral presentation

  • 読出しビット線振幅制限機構及び読み出し加速回路を備えた8T SRAM
    UMEKI Yohei, YOSHIMOTO Shusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference
    Poster presentation

  • 核反応シミュレータを用いたソフトエラー率導出ツール及び耐マルチビットエラー6T SRAM
    YOSHIMOTO Shusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference
    Poster presentation

  • HDTV解像度対応 実時間HOG特徴量抽出と複数物体検出を実現する43mWデュアルコアプロセッサ
    TKAGI Kenta, MIZUNO Kosuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko
    LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference
    Poster presentation

  • 65nm 700-μm2 61-dB 低ジッター2次ΔΣT-D変換器
    OKUNO Keisuke, KONISHI Toshihiro, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi
    LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference
    Poster presentation

  • ウェアラブルヘルスケアシステムのための 短時間自己相関を用いた瞬時心拍検出手法
    中野将尚, 小西恵大, 和泉慎太郎, 川口博, YOSHIMOTO MASAHIKO
    電気学会センサ・マイクロマシン部門大会, Oct. 2012, Japanese, 北九州, Domestic conference
    Public symposium

  • 6万語彙実時間連続音声認識のための40nm, 144mW音声認識専用プロセッサの開発
    何光霽, 菅原隆伸, 藤永剛史, 宮本優貴, 野口紘希, 和泉慎太郎, 川口博, YOSHIMOTO MASAHIKO
    LSIとシステムのワークショップ 2012, May 2012, Japanese, 北九州, Domestic conference
    Poster presentation

  • 40nm 640μm2 7.2bit プロセススケーラブル・オペアンプレス時間演算型AD変換器
    小西恵大, 奥野圭祐, 和泉慎太郎, 吉本雅彦, KAWAGUCHI HIROSHI
    LSIとシステムのワークショップ 2012, May 2012, Japanese, 北九州, Domestic conference
    Poster presentation

Research Themes

  • Measurement and visualization of organ activity using a flexible multi-channel electrode sheet and a generative model
    和泉 慎太郎, 荒木 徹平, 村瀬 翔
    Japan Society for the Promotion of Science, Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Kobe University, 01 Apr. 2023 - 31 Mar. 2026

  • 空間超音波を用いた非接触バイタル計測技術
    和泉 慎太郎
    日本学術振興会, 科学研究費助成事業, 挑戦的研究(萌芽), 神戸大学, 30 Jun. 2023 - 31 Mar. 2025

  • Research on optical devices and integration technology to realize flexible sheet sensors enabling spectral analysis
    荒木 徹平, 和泉 慎太郎, 河野 行雄
    Japan Society for the Promotion of Science, Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (B), Osaka University, 01 Apr. 2022 - 31 Mar. 2025

  • Development of sheet-type pulse wave sensor system and visualization of blood flow networks
    Sekitani Tsuyoshi
    Japan Society for the Promotion of Science, Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (A), Grant-in-Aid for Scientific Research (A), Osaka University, 01 Apr. 2019 - 31 Mar. 2022
    In this research, we have developed a "patch-type blood flow sensor system" that enables quantitative wireless measurement of the human "blood flow network" using a flexible biometric signal measuring sheet. By simply affixing the patch to the body, we were able to realize a "flexible multi-point pulse wave sensor system" that can simultaneously measure pulse waves at multiple points and estimate "arterial stiffness" and "blood flow network" based on the pulse wave propagation velocity. The results were published in Nature Communicaitons, the world's most prestigious international academic journal, and attracted worldwide attention as a new sheet-type medical system.

  • Stretchable photodetector fabricated by wet-process and its application toward imaging system
    Araki Teppei
    Japan Society for the Promotion of Science, Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B), Grant-in-Aid for Scientific Research (B), Osaka University, 01 Apr. 2019 - 31 Mar. 2022
    Metallic nanomaterials and carbon nanotubes can realize functional devices that exhibit mechanical flexibility previously unattainable due to the specificity of nanomaterials while showing a high degree of compatibility with wet processes. With the goal of "wet process formation of stretchable light sensor elements using nanomaterials and applying them to imaging systems," this study attempted to create high-performance and highly functional light sensor elements by gaining a fundamental understanding of charge transport occurring between nanomaterials. As a result, we constructed a wet process-based sensor sheet with stretchable wiring and a multi-channel light sensor, and furthermore, established an imaging system and investigated its practical feasibility.

  • Izumi Shintaro
    Japan Society for the Promotion of Science, Grants-in-Aid for Scientific Research, Grant-in-Aid for Challenging Research (Exploratory), 大阪大学, 29 Jun. 2018 - 31 Mar. 2021, Principal investigator
    In this study, we proposed a method for biometric authentication using individual differences in heartbeats measured without contact. A microwave Doppler sensor was used to measure minute vibrations on the body surface to extract heartbeat. Because there are individual differences in the pattern of heartbeats, the proposed method can identify individuals using a machine learning approach. We also showed that the effect of noise can be reduced by using time-frequency analysis. The evaluation results show that 96.15% accuracy was achieved.
    Competitive research funding

  • Izumi Shintaro
    Japan Society for the Promotion of Science, Grants-in-Aid for Scientific Research Grant-in-Aid for Young Scientists (A), Grant-in-Aid for Young Scientists (A), 01 Apr. 2016 - 31 Mar. 2020, Principal investigator
    To realize a continuous biological signal monitoring, non-contact heart beat sensing systems have been developed. A appreciatively coupled Electrocardiograms sensor and a microwave Doppler sensor are studied, and they were evaluated both in the indoor and in a running vehicle environment. Furthermore, a sampling error compensation technique has been proposed to reduce these power consumption. These proposed methods are integrated to a prototype of human activity monitor system. The proposed system shows low-power consumption and high accuracy in the real environments.
    Competitive research funding

  • Sekitani Tsuyoshi, Uemura Takafumi, Izumi Shintaro, Araki Teppei, Noda Yuki, Yoshimoto Shusuke, Mochizuki Hideki, Murase Shou
    Japan Society for the Promotion of Science, Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (A), Grant-in-Aid for Scientific Research (A), Osaka University, 01 Apr. 2016 - 31 Mar. 2019
    We have successfully developed sheet-type sensor systems for monitoring functions of autonomic nervous system. This system consists of sheet-type electroencephalogram (EEG), electrocardiogram (ECG), electromyogram (EMG), and sweat sensors. For the realization of imperceptible electronic system, almost all the component has been manufactured on flexible and stretchable substrates, so that it can spread over arbitrary curved surfaces including human skins. With integrating the ultrafsoft gel electrodes, ultraflexible amplifier, Si-LSI platform consisting of wireless data-transmission module and analog-to-digital converter, Li-ion-based thin-film battery, and information engineering.The collaboration with medical doctors in Osaka University Medical Hospital, we have successful monitored the functions of autonomic nervous system using the developed systems, demonstrating the excellent feasibility of the newly-developed sheet-type system.

  • SAITO IZUMI, Izumi Shintaro, Nishi Motoi, Matsuo Takami, Yamada Hideto
    Japan Society for the Promotion of Science, Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B), Grant-in-Aid for Scientific Research (B), Kobe University, 01 Apr. 2015 - 31 Mar. 2018
    In the obstetrics mixed ward, it was investigated whether the nursing of non- obstetrics dead patients and the nursing of obstetrics deliveries overlap. In 14 of the 22 deaths, nursing at birth and delivery at delivery were overlapped. There were 4 out of 14 overlaps within 60 minutes. One of them was two minutes apart. From these results, it became clear that the measurement of the whole obstetrics mixed ward and the 24-hour nursing hours and the nursing practice using the information communication equipment is indispensable. The obstetrics one bedside average stay time 17.3 minutes, the non-obstetric one bedside average stay time 39 minutes, the one bedside average of all the patients was 21.6 minutes. Elucidation of the actual condition of nursing of obstetrics mixed ward is in the present condition that is hardly realized

  • Izumi Shintaro, Ohta Hidetoshi
    Japan Society for the Promotion of Science, Grants-in-Aid for Scientific Research Grant-in-Aid for Challenging Exploratory Research, Grant-in-Aid for Challenging Exploratory Research, Kobe University, 01 Apr. 2015 - 31 Mar. 2018, Principal investigator
    It is important to measure biological information related to a daily life to recognize and improve human lifestyles. We develop a biological tag that can be indwelled in the gastrointestinal tract and which can operate continuously for long durations by wireless power supply and communication. The conventional indwelling swallowable system uses a motor. It is not proposed as being of swallowable size. Therefore, we propose a mechanism using electrolysis, realizing a system without using a conventional actuator, but with a size that can be swallowed. A board of 7 mm × 20 mm was fabricated with a micro controller, an NFC-IC, an antenna connector, and a sensor. By printing on a flexible printed circuit board, the antenna can be folded and unfolded, which relaxes size restrictions. The communication distance was extended. Experiments using a human body model revealed that the device can be indwelled and egested in a swallowable size using the proposed method.
    Competitive research funding

  • IZUMI Shintaro
    Japan Society for the Promotion of Science, Grants-in-Aid for Scientific Research Grant-in-Aid for Young Scientists (B), Grant-in-Aid for Young Scientists (B), Kobe University, 01 Apr. 2012 - 31 Mar. 2014, Principal investigator
    In this research, a temperature compensation technique for a digitally controlled oscillator (DCO) using least means square (LMS) filtering was proposed. The proposed scheme contributes to reduction of the start-up settling time of all-digital phase-locked loop (ADPLL). The proposed method estimates the temperature using the output frequency of DCO because it is affected by temperature fluctuation. These characteristics are confirmed using measurement results of the test chip, which is fabricated in 65-nm CMOS process.
    Competitive research funding

  • 電力効率を3桁向上させるセンサネットワークのレイヤ間垂直統合研究
    和泉 慎太郎
    日本学術振興会, 科学研究費助成事業 特別研究員奨励費, 特別研究員奨励費, 神戸大学, 2009 - 2011
    平成23年度は、昨年度に引き続きアプリケーション層までを含んだセンサネットワークの垂直統合設計研究をおこなった。 本研究ではセンサネットワークの新たな応用分野としてマイクアレイを用いる音声インタフェースに着目し、センサネットワーク技術を用いたネットワーク型マイクアレイシステムを提案している。提案システムでは、小規模なマイクアレイ・センサノード(サブアレイ)を多数配置し、それらの間で有線ネットワークを構築して協調動作をおこなうことで、従来の大規模マイクアレイにおける演算量や消費電力の問題を解決する。小規模なマイクアレイ・センサノード(サブアレイ)を多数配置し、それらの間で有線ネットワークを構築して協調動作をおこなうことで、大規模なマイクアレイ音声処理システムを実現する。従来のデータ収集のみを目的としたアプリケーションとは異なり、ネットワーク型マイクアレイシステムには「リアルタイム処理」、「センサノード間の時刻同期」、「ネットワーク分散処理」という3つの機能が必要であった。 さらに本年度の研究成果として、複数音源に対応するマイクアレイネットワークシステムのためのクラスタベース経路構築手法を提案した。提案ルーティング手法をマイクアレイネットワークに適用することで、複数の音源位置に対して効率の良い経路を構築し、各音源からの音声を同時に収集することができる。これにより、例えば複数話者に対応した音声会議システムなどが実現できる。

Industrial Property Rights

  • 温冷触覚提示装置、ウェアラブル端末、かゆみ抑制装置、アイシング装置、マッサージ装置、口内保持具、及び食器
    伊庭野 健造, 菅原 徹, 伊藤 雄一, 佐藤 克成, 和泉 慎太郎
    特願2022-114631, 19 Jul. 2022, 大阪ヒートクール株式会社, 特開2022-159298, 17 Oct. 2022
    Patent right

  • 温冷触覚提示装置、ウェアラブル端末、かゆみ抑制装置、アイシング装置、マッサージ装置、口内保持具、及び食器
    伊庭野 健造, 菅原 徹, 伊藤 雄一, 佐藤 克成, 和泉 慎太郎
    特願2022-114631, 19 Jul. 2022, 大阪ヒートクール株式会社, 特開2022-159298, 17 Oct. 2022, 特許第7113586号, 28 Jul. 2022
    Patent right

  • 温冷触覚提示装置、ウェアラブル端末、かゆみ抑制装置、アイシング装置、マッサージ装置、口内保持具、及び食器
    伊庭野 健造, 菅原 徹, 伊藤 雄一, 佐藤 克成, 和泉 慎太郎
    JP2021046685, 17 Dec. 2021, 大阪ヒートクール株式会社, 特許第7113586号, 28 Jul. 2022
    Patent right

  • 咳嗽検出装置
    西村 善博, 永野 達也, 和泉 慎太郎
    特願2020-122053, 16 Jul. 2020, 国立大学法人神戸大学, 特開2022-018726, 27 Jan. 2022
    Patent right

  • 災害情報システム
    瀬下 雄一, 小島 浩, 栗田 哲史, 平岩 直哉, 土山 滋郎, 赤羽 省吾, 関谷 毅, 植村 隆文, 和泉 慎太郎, 荒木 徹平, 野田 祐樹, 吉本 秀輔
    特願2019-009541, 23 Jan. 2019, 東電設計株式会社, 東電タウンプランニング株式会社, 国立大学法人大阪大学, 特開2020-119231, 06 Aug. 2020
    Patent right

  • 災害情報システム
    瀬下 雄一, 小島 浩, 栗田 哲史, 平岩 直哉, 土山 滋郎, 赤羽 省吾, 関谷 毅, 植村 隆文, 和泉 慎太郎, 荒木 徹平, 野田 祐樹, 吉本 秀輔
    特願2019-009541, 23 Jan. 2019, 東電設計株式会社, 東電タウンプランニング株式会社, 国立大学法人大阪大学, 特開2020-119231, 06 Aug. 2020, 特許第7152718号, 04 Oct. 2022
    Patent right

  • 類型判別装置
    西村 善博, 永野 達也, 和泉 慎太郎
    特願2018-075034, 09 Apr. 2018, 国立大学法人神戸大学, 特開2019-180800, 24 Oct. 2019
    Patent right

  • 類型判別装置
    西村 善博, 永野 達也, 和泉 慎太郎
    特願2018-075034, 09 Apr. 2018, 国立大学法人神戸大学, 特開2019-180800, 24 Oct. 2019, 特許第7130228号, 26 Aug. 2022
    Patent right

  • 半導体記憶装置
    和泉 慎太郎, 中川 知己, 川口 博, 吉本 雅彦
    特願2019-013173, 29 Jan. 2019, ローム株式会社, 特開2019-079589, 23 May 2019
    Patent right

  • 半導体記憶装置
    和泉 慎太郎, 中川 知己, 川口 博, 吉本 雅彦
    特願2014-212787, 17 Oct. 2014, ローム株式会社, 特開2016-081549, 16 May 2016
    Patent right

  • TD変換器及びAD変換器
    川口 博, 吉本 雅彦, 小西 恵大, 和泉 慎太郎, 奥野 圭祐
    特願2012-203662, 14 Sep. 2012, 株式会社半導体理工学研究センター, 特開2014-003580, 09 Jan. 2014, 特許第5552514号, 30 May 2014
    Patent right

  • TD変換器及びAD変換器
    川口 博, 吉本 雅彦, 小西 恵大, 和泉 慎太郎, 奥野 圭祐
    特願2012-203662, 14 Sep. 2012, 株式会社半導体理工学研究センター, 特開2014-003580, 09 Jan. 2014
    Patent right

  • 位置測定システム
    川口 博, 吉本 雅彦, 祖田 心平, 高木 智也, 和泉 慎太郎
    特願2011-119072, 27 May 2011, 株式会社半導体理工学研究センター, 特開2012-247300, 13 Dec. 2012, 特許第5412470号, 15 Nov. 2013
    Patent right

  • センサネットワークシステムとその通信方法
    川口 博, 吉本 雅彦, 和泉 慎太郎
    特願2011-164986, 28 Jul. 2011, 株式会社半導体理工学研究センター, 特開2013-030946, 07 Feb. 2013, 特許第5289517号, 14 Jun. 2013
    Patent right

  • センサネットワークシステムとその通信方法
    川口 博, 吉本 雅彦, 和泉 慎太郎
    特願2011-164986, 28 Jul. 2011, 株式会社半導体理工学研究センター, 特開2013-030946, 07 Feb. 2013
    Patent right

  • 位置測定システム
    川口 博, 吉本 雅彦, 祖田 心平, 高木 智也, 和泉 慎太郎
    特願2011-119072, 27 May 2011, 株式会社半導体理工学研究センター, 特開2012-247300, 13 Dec. 2012
    Patent right

  • オペアンプレス・キャパシタレスAD変換器およびTD変換器
    川口 博, 吉本 雅彦, 小西 恵大, 和泉 慎太郎
    特願2011-108910, 14 May 2011, 株式会社半導体理工学研究センター, 特開2012-244199, 10 Dec. 2012
    Patent right