Research activity information

• 2018 電子情報通信学会, 電子情報通信学会ELEX Best Paper Award, A low power, VLSI object recognition processorusing Sparse FIND Feature for 60fps HDTV resolution video

  Matsukawa Go, Kodamda Taisuke, Nishizumi Yuri, Kajihara Koichi, Nakanishi Chikako, IZUMI Shintaro, KAWAGUCHI Hiroshi, Goto Toshio, Kato Takeo, YOSHIMOTO Masahiko

  Official journal


• Sep. 2017 IEEE International Workshop on Machine Learning for Signal Processing (MLSP), Sep. 2017., Best Student Paper Award, A Layer-Block-Wise Pipeline For Memory And Bandwidth Reduction In Distributed Deep Learning

  MORI Haruki, YOUKAWA Tetsuya, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, INOUE Atsuki

  International society


• May 2016 電子情報通信学会集積回路研究専門委員会, LSIとシステムのワークショップ2016 優秀ポスター賞（学生部門）, プロセスばらつき耐性を有する低電圧動作STT-MRAM向けカウンターベース読出し回路

  UMEKI Yohei, YANAGIDA Kouji, YOSHIMOTO Shusuke, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, TSUNODA Koji, SUGII Toshihiro

  Japan society


• May 2014 電子情報通信学会集積回路研究専門委員会, 優秀ポスター賞, 38μAウェアラブル生体情報計測プロセッサ

  中井 陽三郎, IZUMI SHINTARO, 山下 顕, 中野 将尚, 藤井 貴英, 小西 恵大, KAWAGUCHI HIROSHI, 木村 啓明, 丸元 共治, 渕上 貴昭, 藤森 敬和, 中嶋 宏, 志賀 利一, YOSHIMOTO MASAHIKO

  Japan society


• Jul. 2008 株式会社 半導体理工学研究センター, 優秀ポスター賞, 発話推定を用いたインテリジェント認識システムの低消費電力化技術

  NOGUCHI Hiroki, KAWAGUCHI Hiroshi


• Jul. 2008 STARC, STARCフォーラム/シンポジウム2008 学生ポスターセッション 優秀ポスター賞受賞, 発話推定を用いたインテリジェント認識システムの低消費電力化技術

  野口 紘希, 川口 博


• Apr. 2008 財団法人 電気・電子学術振興財団, 第10回LSI IPデザイン・アワード 研究助成賞, 長波帯標準電波を用いた低電力センサノードの垂直統合設計

  OTAKE Yu, ICHIEN Masumi, TAKEUCHI Takashi, GION Akihiro, MIKAMI Shinji, FUJIWARA Hidehiro, KAWAGUCHI Hirosi, OHTA Chikara, YOSHIMOTO Masahiko


• Apr. 2008 財団法人 電気・電子学術振興財団, 第10回LSI IPデザイン・アワード IP賞 2, サブ100mW H.264/AVC MP@L4.1 HDTV 解像度対応整数画素精度動き検出プロセッサコア

  MIZUNO Kosuke, MIYAKOSHI Junichi, MURACHI Yuichiro, HAMAMOTO Masaki, IINUMA Takahiro, ISHIHARA Tomokazu, 印 芳, KAMINO Tetsuya, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko


• Apr. 2008 財団法人 電気・電子学術振興財団, 第10回LSI IPデザイン・アワード IP賞 1, VGA 30fps 実時間動画像認識応用オプティカルフロープロセッサコア

  MURACHI Yuichiro, FUKUYAMA Yuki, YAMANOTO Ryo, MIYAKOSHI Junichi, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, ISHIHARA Hajime, MIYAMA Masahiko, MATSUDA Yoshio


• Dec. 2007 IEEE, SENSORCOMM 2007 ENOPT 2008 Workshop Best Paper Award, Cross-Layer Design for Low-Power Wireless Sensor Node Using Long-Wave Standard Time Code

  OTAKE Yu, ICHIEN Masumi, TAKEUCHI Takashi, GION Akihiro, MIKAMI Shinji, FUJIWARA Hidehiro, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko


• Nov. 2007 電子情報通信学会, 第11回システムLSIワークショップ IEEEシステムLSI技術賞, DVS環境下での小面積・低電圧動作8T SRAMの設計-32nm世代以降で8Tセルが小面積・低電圧動作を同時に実現

  MORITA Yasuhiro, FUJIWARA Hidehiro, NOGUCHI Hiroki, IGUCHI Yusuke, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko


• Sep. 2007 東京大学大規模集積システム設計教育研究センター, IEEE SSCS Japan Chapter Outstanding Design Award, ビット線電力を削減する，動画像処理応用 10T 非プリチャージ 2-port SRAM

  IGUCHI Yusuke, NOGUCHI Hiroki, OKUMURA Syunsuke, FUJIWARA Hidehiro, MORITA Yasuhiro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko


• Apr. 2007 財団法人 電気・電子学術振興財団, 第9回LSI IPデザイン・アワード 開発奨励賞, 消費電力を50%削減する動的電圧/周波数スケーリング型H.264 Main Profile@Level 4ビデオデコーダLSI

  KAWAKAMI Kentaro, TAKEMURA Jun, KURODA Mitsuhiko, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko


• Apr. 2007 財団法人 電気・電子学術振興財団, 第9回LSI IPデザイン・アワード IP賞 2, ット線電力を53%削減できる実時間動画像処理応用2ポートSRAM

  FUJIWARA Hidehiro, NII Koji, MIYAKOSHI Junichi, MURACHI Yuichiro, MORITA Yasuhiro, NOGUCHI Hiroki, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko


• Apr. 2007 財団法人 電気・電子学術振興財団, 第9回LSI IPデザイン・アワード IP賞 1, 超並列画像処理のための，任意位置・水平垂直連続複数画素を同時アクセスできるメモリアーキテクチャ

  ISHIHARA Tokokazu, MIYAKOSHI Junichi, MURACHI Yuichiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko


• Feb. 2007 IEEE, IEEE Kansai Section 2006 Gold Award, 低電力回路技術によるIEEEへの貢献

  KAWAGUCHI Hiroshi


• Feb. 2005 IEEE International Solid-State Circuits Conference, IEEE International Solid-State Circuits Conference Takuo Sugano Outstanding Paper Award, Cut-and-Paste Organic FET Customized ICs for Application to Artificial Skin

  SOMEYA Takao, KAWAGUCHI Hiroshi, SAKURAI Takayasu

• Evaluation of Patients' Levels of Walking Independence Using Inertial Sensors and Neural Networks in an Acute-Care Hospital.

  Tatsuya Sugimoto, Nobuhito Taniguchi, Ryoto Yoshikura, Hiroshi Kawaguchi, Shintaro Izumi

  This study aimed to evaluate walking independence in acute-care hospital patients using neural networks based on acceleration and angular velocity from two walking tests. Forty patients underwent the 10-m walk test and the Timed Up-and-Go test at normal speed, with or without a cane. Physiotherapists divided the patients into two groups: 24 patients who were monitored or independent while walking with a cane or without aids in the ward, and 16 patients who were not. To classify these groups, the Transformer model analyzes the left gait cycle data from eight inertial sensors. The accuracy using all the sensor data was 0.836. When sensor data from the right ankle, right wrist, and left wrist were excluded, the accuracy decreased the most. When analyzing the data from these three sensors alone, the accuracy was 0.795. Further reducing the number of sensors to only the right ankle and wrist resulted in an accuracy of 0.736. This study demonstrates the potential of a neural network-based analysis of inertial sensor data for clinically assessing a patient's level of walking independence.

  May 2024, Bioengineering (Basel, Switzerland), 11(6) (6), English, International magazine

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• Effects of the walking independence on lower extremity and trunk muscle activity during straight-leg raising following incomplete cervical cord injury.

  Tatsuya Sugimoto, Ryoto Yoshikura, Toshiyuki Maezawa, Kojiro Mekata, Yuya Ueda, Hiroshi Kawaguchi, Shintaro Izumi

  The purpose of this study was to compare the acceleration and surface electromyography (EMG) of the lower extremity and trunk muscles during straight-leg raising (SLR) in patients with incomplete cervical cord injury according to their levels of walking independence. Twenty-four patients were measured acceleration and EMG during SLR held for 10 s. Data were analyzed separately for the dominant and nondominant sides and compared between the nonindependent (NI) and independent (ID) groups based on their levels of walking independence. Frequency analysis of the EMG showed that the high-frequency (HF) band of the contralateral biceps femoris (BF) in the ID group and bands below the medium-frequency (MF) of the BF and the HF and MF bands of the rectus abdominis in the NI group were significantly higher during dominant and nondominant SLR. During the nondominant SLR, the low-frequency band of the internal oblique and the MF band of the external oblique were significantly higher in the NI group. The ID group mobilized muscle fiber type 2 of the BF, whereas the NI group mobilized type 1 of the BF and types 2 and 1 of the trunk muscles to stabilize the pelvis. This result was more pronounced during the nondominant SLR.

  Feb. 2024, Scientific reports, 14(1) (1), 4363 - 4363, English, International magazine

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A Case Study for Improving Performances of Deep-Learning Processor with MRAM

  Ryotaro Ohara, Atsushi Fukunaga, Masakazu Taichi, Masaya Kabuto, Riku Hamabe, Masato Ikegawa, Shintaro Izumi, Hiroshi Kawaguchi

  Feb. 2024, IPSJ Transactions on System LSI Design Methodology, 17, 7 - 15

  Scientific journal


• Ultrasonic raytracing Simulation Method for Data Augmentation to Surveil the Bathroom with Digital Twins

  Hiroshi Kawaguchi

  2024, Ieee Uffc Latin America Ultrasonics Symposium, Laus

  Scientific journal


• A Case Study for Improving Performances of Deep-Learning Processor with MRAM.

  Ryotaro Ohara, Atsushi Fukunaga, Masakazu Taichi, Masaya Kabuto, Riku Hamabe, Masato Ikegawa, Shintaro Izumi, Hiroshi Kawaguchi 0001

  2024, IPSJ Trans. Syst. LSI Des. Methodol., 17, 7 - 15

  Scientific journal


• Wearable Perspiration Characteristic Sensor Using Bi-Directional Driver Circuit.

  Ryo Takamatsu, Shintaro Izumi, Hiroshi Kawaguchi 0001

  2024, ICCE, 1 - 6

  International conference proceedings


• An Ultrasound-Based Surveillance System for Bathroom Posture and Location Estimation.

  Shun Sato, Ryotaro Ohara, M. Shahrul Amir Kamarulzaman, Yuto Yasuda, Shintaro Izumi, Hiroshi Kawaguchi 0001

  2024, ICCE, 1 - 5

  International conference proceedings


• 15-ch Wearable Body Surface Potential Sensor for Wireless Electrocardiogram Monitoring.

  Yusaku Goto, Shintaro Izumi, Ryotaro Ohara, Teppei Araki, Sho Murase, Hiroshi Kawaguchi 0001

  2024, ICCE, 1 - 5

  International conference proceedings


• A Mixed-Precision Quantization Method without Accuracy Degradation Using Semilayers

  Hiroshi Kawaguchi

  2023, Proceedings of Machine Learning Research

  Scientific journal


• Estimating Person Location in Bathroom with Spatial Ultrasound and Variational autoencoder

  Shun Sato, Yuto Yasuda, Ryotaro Ohara, Riku Hamabe, Takayuki Genda, Shoya Imanaka, Shintaro Izumi, Hiroshi Kawaguchi

  2023, IEEE International Ultrasonics Symposium, IUS

  International conference proceedings


• Contactless respiration measurement system using 25-kHz spatial ultrasound Doppler sensor

  Kousei Kawai, Ryotaro Ohara, Shun Sato, Toru Ishii, Shintaro Izumi, Hiroshi Kawaguchi

  2023, IEEE International Ultrasonics Symposium, IUS

  International conference proceedings


• An ultrasonic raytracing simulation method for bathroom surveillance

  M. Shahrul Amir Kamarulzaman, Riku Hamabe, Yuto Yasuda, Ryotaro Ohara, Shun Sato, Shintaro Izumi, Hiroshi Kawaguchi

  2023, IEEE International Ultrasonics Symposium, IUS

  International conference proceedings


• Quantitative Evaluation Method of Timed Up and Go Test for Hospitalized Patients Using Inertial Sensors.

  Tatsuya Sugimoto, Ryoto Yoshikura, Hiroshi Kawaguchi 0001, Shintaro Izumi

  2023, BSN, 1 - 4

  International conference proceedings

  Link to Kobe Univ. Repository (Kernel)


• Increasing the Sensitivity of Piezoelectric Pulse Wave Sensors for Pulse Wave Propagation Measurement

  Ishibashi, M., Izumi, S., Takamatsu, R., Yoshimoto, S., Noda, Y., Araki, T., Uemura, T., Sekitani, T., Kawaguchi, H.

  2023, IEEE Sensors Letters, 7(9) (9)

  Scientific journal


• Self-Supervised Learning with Atom Replacement for Catalyst Energy Prediction by Graph Neural Networks.

  Yasufumi Sakai, Thang Dang, Shigeki Fukuta, Koichi Shirahata, Atsushi Ishikawa, Atsuki Inoue, Hiroshi Kawaguchi, Árni Björn Höskuldsson, Egill Skúlason

  2023, INNS DLIA@IJCNN, 458 - 467

  International conference proceedings


• Semilayer-Wise Partial Quantization Without Accuracy Degradation or Back Propagation.

  Tomoya Matsuda, Kengo Matsumoto, Atsuki Inoue, Hiroshi Kawaguchi, Yasufumi Sakai

  Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2023, ICANN (9), 14262 LNCS, 283 - 295

  International conference proceedings

  Link to Kobe Univ. Repository (Kernel)


• A 1W8R 20T SRAM Codebook for 20% Energy Reduction in Mixed-Precision Deep-Learning Inference Processor System.

  Ryotaro Ohara, Masaya Kabuto, Masakazu Taichi, Atsushi Fukunaga, Yuto Yasuda, Riku Hamabe, Shintaro Izumi, Hiroshi Kawaguchi

  2023, AICAS, 1 - 5

  International conference proceedings


• 3D Reconstruction from Outdoor Ultrasonic Image Using Variation Autoencoder

  Ryotaro Ohara, Yuto Yasuda, Riku Hamabe, Ishii Toru, Shintaro Izumi, Hiroshi Kawaguchi

  IEEE, Oct. 2022, 2022 IEEE International Ultrasonics Symposium (IUS)


• Millimeter-Precision Ultrasonic DSSS Positioning Technique With Geometric Triangle Constraint

  Toru, I., Yasuda, Y., Sato, S., Izumi, S., Kawaguchi, H.

  Institute of Electrical and Electronics Engineers ({IEEE}), Aug. 2022, IEEE Sensors Journal, 22(16) (16), 16202 - 16211

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• Effectiveness of the heartbeat interval error and compensation method on heart rate variability analysis

  Ayaka Shintomi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi

  Institution of Engineering and Technology ({IET}), Feb. 2022, Healthcare Technology Letters, 9(1-2) (1-2), 9 - 15, English, International magazine

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• Greedy search algorithm for partial quantization of convolutional neural networks inspired by submodular optimization

  Tsuji, S., Yamada, F., Kawaguchi, H., Inoue, A., Sakai, Y.

  2022, Neural Computing and Applications

  Scientific journal


• Automatic Pruning Rate Derivation for Structured Pruning of Deep Neural Networks.

  Yasufumi Sakai, Akinori Iwakawa, Tsuguchika Tabaru, Atsuki Inoue, Hiroshi Kawaguchi

  IEEE, 2022, 26th International Conference on Pattern Recognition(ICPR), 2561 - 2567

  International conference proceedings


• Channel-wise quantization without accuracy degradation using Δloss analysis.

  Kazuki Okado, Kengo Matsumoto, Atsuki Inoue, Hiroshi Kawaguchi, Yasufumi Sakai

  ACM, 2022, ICMLT 2022: 7th International Conference on Machine Learning Technologies(ICMLT), 56 - 61

  International conference proceedings


• Machine Learning-Based Severity Classification of Spinal Cord Injury Patients Using Straight Leg Raising Test.

  Ryoto Yoshikura, Shintaro Izumi, Tatsuya Sugimoto, Hiroshi Kawaguchi

  IEEE, 2022, 2022 IEEE Sensors, 1 - 4

  International conference proceedings


• Non-contact Atrial Fibrillation Detection using a 24-GHz Microwave Doppler Radar.

  Shintaro Izumi, Sho Murase, Itsumi Fukuda, Kenta Taki, Kazunori Toyama, Tadashi Inuzuka, Hideki Mochizuki, Hiroshi Kawaguchi

  IEEE, 2022, 2022 IEEE Sensors, 1 - 4

  International conference proceedings


• 20-µs Accuracy Time-Synchronization Method using Bluetooth Low Energy for Internet-of-Things Sensors.

  Masayasu Harada, Shintaro Izumi, Ryosuke Kozeni, Yukiko Yoshikawa, Toru Ishii, Hiroshi Kawaguchi, Shohei Uemura, Kaname Araki

  IEEE, 2022, 19th IEEE Annual Consumer Communications & Networking Conference(CCNC), 181 - 186

  International conference proceedings

  Link to Kobe Univ. Repository (Kernel)


• Rapid Method Using Deep Learning With Multi-Focus Microphotographs To Measure Submicrometric Structures And Its Evaluation

  Narukage, R., Okada, G., Kawaguchi, H.

  2021, Journal of Laser Micro Nanoengineering, 16(2) (2)

  Scientific journal


• A High-Speed Neural Architecture Search Considering the Number of Weights.

  Fuyuka Yamada, Satoki Tsuji, Hiroshi Kawaguchi, Atsuki Inoue, Yasufumi Sakai

  Springer, 2021, KI 2021: Advances in Artificial Intelligence - 44th German Conference on AI(KI), 12873 LNAI, 109 - 115

  International conference proceedings


• Greedy Search Algorithm for Mixed Precision in Post-Training Quantization of Convolutional Neural Network Inspired by Submodular Optimization.

  Satoki Tsuji, Hiroshi Kawaguchi, Atsuki Inoue, Yasufumi Sakai, Fuyuka Yamada

  PMLR, 2021, Asian Conference on Machine Learning(ACML), 886 - 901

  International conference proceedings


• 12.5-m Distance Measurement in High-Interference Environment Using Ultrasonic Array Sensors.

  Yukiko Yoshikawa, Yuto Yasuda, Toru Ishii, Shintaro Izumi, Hiroshi Kawaguchi

  IEEE, 2021, IEEE International Instrumentation and Measurement Technology Conference(I2MTC), 1 - 6

  International conference proceedings


• Subcentimeter Precision Ranging System for Moving Targets With a Doppler-Effect- Compensated Ultrasonic Direct Sequence Spread Spectrum.

  Toru Ishii, Yukiko Yoshikawa, Shintaro Izumi, Hiroshi Kawaguchi

  2021, IEEE Trans. Instrum. Meas., 70, 1 - 8

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• Heartbeat Interval Error Compensation Method for Low Sampling Rates Photoplethysmography Sensors

  Kento Watanabe, Shintaro Izumi, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Jun. 2020, IEICE TRANSACTIONS ON COMMUNICATIONS, E103B(6) (6), 645 - 652, English

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• GPQ: Greedy Partial Quantization of Convolutional Neural Networks Inspired by Submodular Optimization

  Hiroshi Kawaguchi

  2020, 5TH INTERNATIONAL CONFERENCE ON SOFT COMPUTING & MACHINE INTELLIGENCE (ISCMI)

  Scientific journal


• Doppler shift compensation technique for ultrasonic DSSS ranging system.

  Toru Ishii, Yukiko Yoshikawa, Shintaro Izumi, Hiroshi Kawaguchi

  IEEE, 2020, 2020 IEEE International Instrumentation and Measurement Technology Conference(I2MTC), 1 - 6

  International conference proceedings


• A 1.15-TOPS 6.57-TOPS/W Neural Network Processor for Multi-Scale Object Detection With Reduced Convolutional Operations.

  Reiya Kawamoto, Masakazu Taichi, Masaya Kabuto, Daisuke Watanabe, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Go Matsukawa, Toshio Goto, Motoshi Kojima

  2020, IEEE J. Sel. Top. Signal Process., 14(4) (4), 634 - 645

  Scientific journal


• Heartbeat Interval Error Compensation Method for Low Sampling Rates Photoplethysmography Sensors.

  Kento Watanabe, Shintaro Izumi, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2020, IEICE Trans. Commun., 103-B(6) (6), 645 - 652

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• An Architectural Study for Inference Coprocessor Core at the Edge in IoT Sensing.

  Daisuke Watanabe, Yuji Yano, Shintaro Izumi, Hiroshi Kawaguchi, Kiyoshi Takeuchi, Toshiro Hiramoto, Shoichi Iwai, Masami Murakata, Masahiko Yoshimoto

  IEEE, 2020, 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems(AICAS), 305 - 309

  [Refereed]

  International conference proceedings


• A 1.15-TOPS 6.57-TOPS/W DNN Processor for Multi-Scale Object Detection.

  Reiya Kawamoto, Masakazu Taichi, Masaya Kabuto, Daisuke Watanabe, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi

  IEEE, 2020, 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems(AICAS), 203 - 207

  [Refereed]

  International conference proceedings


• A Low-Power Photoplethysmography Sensor using Correlated Double Sampling and Reference Readout Circuit

  Kana Sasai, Shintaro Izumi, Kento Watanabe, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Institute of Electrical and Electronics Engineers Inc., Oct. 2019, Proceedings of IEEE Sensors, 2019-, English

  International conference proceedings


• An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment.

  Yuji Yano, Seiya Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Tetsuya Hirose, Masaya Miyahara, Teruki Someya, Kenichi Okada, Ippei Akita, Yoshihiko Kurui, Hideyuki Tomizawa, Masahiko Yoshimoto

  IEEE, 2019, IEEE Asian Solid-State Circuits Conference(A-SSCC), 267 - 270

  [Refereed]

  International conference proceedings


• A Heartbeat Interval Error Compensation Method Using Multiple Linear Regression for Photoplethysmography Sensors.

  Seiya Yoshida, Shintaro Izumi, Yuki Nishikawa, Kento Watanabe, Kana Sasai, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto

  IEEE, 2019, 2019 IEEE Biomedical Circuits and Systems Conference(BioCAS), 1 - 4

  [Refereed]

  International conference proceedings


• Energy-Efficient Spectral Analysis Method Using Autoregressive Model-Based Approach for Internet of Things.

  Seiya Yoshida, Shintaro Izumi, Koichi Kajihara, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2019, IEEE Trans. Circuits Syst. I Regul. Pap., 66-I(10) (10), 3896 - 3905, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• Multimodal Cardiovascular Information Monitor Using Piezoelectric Transducers for Wearable Healthcare.

  Takaaki Okano, Shintaro Izumi, Takumi Katsuura, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2019, J. Signal Process. Syst., 91(9) (9), 1053 - 1062, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• Non-Contact Instantaneous Heart Rate Extraction System Using 24-GHz Microwave Doppler Sensor.

  Shintaro Izumi, Takaaki Okano, Daichi Matsunaga, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2019, IEICE Trans. Commun., 102-B(6) (6), 1088 - 1096, English

  [Refereed]

  Scientific journal


• Low-Noise Photoplethysmography Sensor Using Correlated Double Sampling for Heartbeat Interval Acquisition.

  Kento Watanabe, Shintaro Izumi, Kana Sasai, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2019, IEEE Trans. Biomed. Circuits and Systems, 13(6) (6), 1552 - 1562, English, International magazine

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme.

  Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2019, IEEE Trans. Circuits Syst. I Regul. Pap., 66-I(4) (4), 1442 - 1453, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• Estimating metabolic equivalents for activities in daily life using acceleration and heart rate in wearable devices.

  Motofumi Nakanishi, Shintaro Izumi, Sho Nagayoshi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Toshikazu Shiga, Takafumi Ando, Satoshi Nakae, Chiyoko Usui, Tomoko Aoyama, Shigeho Tanaka

  BACKGROUND: Herein, an algorithm that can be used in wearable health monitoring devices to estimate metabolic equivalents (METs) based on physical activity intensity data, particularly for certain activities in daily life that make MET estimation difficult. RESULTS: Energy expenditure data were obtained from 42 volunteers using indirect calorimetry, triaxial accelerations and heart rates. The proposed algorithm used the percentage of heart rate reserve (%HRR) and the acceleration signal from the wearable device to divide the data into a middle-intensity group and a high-intensity group (HIG). The two groups were defined in terms of estimated METs. Evaluation results revealed that the classification accuracy for both groups was higher than 91%. To further facilitate MET estimation, five multiple-regression models using different features were evaluated via leave-one-out cross-validation. Using this approach, all models showed significant improvements in mean absolute percentage error (MAPE) of METs in the HIG, which included stair ascent, and the maximum reduction in MAPE for HIG was 24% compared to the previous model (HJA-750), which demonstrated a 70.7% improvement ratio. The most suitable model for our purpose that utilized heart rate and filtered synthetic acceleration was selected and its estimation error trend was confirmed. CONCLUSION: For HIG, the MAPE recalculated by the most suitable model was 10.5%. The improvement ratio was 71.6% as compared to the previous model (HJA-750C). This result was almost identical to that obtained from leave-one-out cross-validation. This proposed algorithm revealed an improvement in estimation accuracy for activities in daily life; in particular, the results included estimated values associated with stair ascent, which has been a difficult activity to evaluate so far.

  Jul. 2018, Biomedical engineering online, 17(1) (1), 100 - 100, English, International magazine

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A 5-ms Error, 22-μA Photoplethysmography Sensor using Current Integration Circuit and Correlated Double Sampling.

  Kento Watanabe, Shintaro Izumi, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto

  This paper presents a low-power Photoplethysmography (PPG) sensing method. The PPG is commonly used in recent wearable devices to detect cardiovascular information including heartbeat. The heartbeat is useful for physical activity and stress monitoring. However, the PPG circuit consumes large power because it consists of LED and photodiode. To reduce its power consumption without accuracy degradation, a cooperative design of circuits and algorithms is proposed in this work. A straightforward way to reduce the power is intermittent driving of LED, but there is a disadvantage that the signal is contaminated by a noise while circuit switching. To overcome this problem, we introduce correlated double sampling (CDS) method, which samples an integration circuit output twice with short intervals after the LED turns on and uses the difference of these voltage. Furthermore, an up-conversion method using linear interpolation, and an error correction using autocorrelation are introduced. The proposed PPG sensor, which consists of the LED, the photodiode, the current integration circuit, a CMOS switch, an A/D converter, and an MCU, is prototyped. It is evaluated by actual measurement with 22-year-old subject. The measurement results show that 22-μA total current consumption is achieved with 5-ms mean absolute error.

  Jul. 2018, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2018, 5566 - 5569, English, International magazine

  [Refereed]

  Scientific journal


• Sampling Rate Reduction for Wearable Heart Rate Variability Monitoring

  Yuki Nishikawa, Shintaro Izumi, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Institute of Electrical and Electronics Engineers Inc., Apr. 2018, Proceedings - IEEE International Symposium on Circuits and Systems, 2018-, English

  International conference proceedings


• A 11.3-mu A Physical Activity Monitoring System Using Acceleration and Heart Rate

  Nakanishi, Motofumi, Izumi, Shintaro, Tsukahara, Mio, Kawaguchi, Hiroshi, Kimura, Hiromitsu, Marumoto, Kyoji, Fuchikami, Takaaki, Fujimori, Yoshikazu, Yoshimoto, Masahiko

  Apr. 2018, IEICE TRANSACTIONS ON ELECTRONICS, E101C(4) (4), 233 - 242, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• マイクロ波ドップラーセンサを用いた非接触生体認証

  OKANO Takaaki, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  電子情報通信学会, Mar. 2018, 信学技報, vol. 117, no. 511, MICT2017-54, pp. 17-20, 2018年3月, 117(511) (511), 17 - 20, Japanese

  Symposium


• Design of SRAM Resilient Against Dynamic Voltage Variations

  Hiroshi Kawaguchi

  2018, VLSI Design and Test for Systems Dependability

  Scientific journal


• A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme Using Simultaneously Copyable SRAM

  Hiroshi Kawaguchi

  2018, VLSI Design and Test for Systems Dependability

  Scientific journal


• Secondary bone/soft tissue sarcoma in childhood cancer survivors: a nationwide hospital-based case-series study in Japan

  Hiroshi Kawaguchi

  2018, Japanese Journal of Clinical Oncology

  Scientific journal


• Secondary cancer after a childhood cancer diagnosis: viewpoints considering primary cancer

  Hiroshi Kawaguchi

  2018, International Journal of Clinical Oncology

  Scientific journal


• Secondary Thyroid Cancer After the Diagnosis of Childhood Cancer: Hospital-Based Case Series

  Hiroshi Kawaguchi

  2018, Pediatric Blood and Cancer

  Scientific journal


• Delayed Weight Update for Faster Convergence in Data-Parallel Deep Learning.

  Tetsuya Youkawa, Haruki Mori, Yuki Miyauchi, Kazuki Yamada, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi

  2018, 2018 IEEE GLOBAL CONFERENCE ON SIGNAL AND INFORMATION PROCESSING (GLOBALSIP 2018), 663 - 667, English

  [Refereed]

  International conference proceedings


• A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video [IEICE Electronics Express Vol. 14(2017) No. 15 pp. 20170668].

  Go Matsukawa, Taisuke Kodama, Yuri Nishizumi, Koichi Kajihara, Chikako Nakanishi, Shintaro Izumi, Hiroshi Kawaguchi, Toshio Goto, Takeo Kato, Masahiko Yoshimoto

  2018, IEICE Electronic Express, 15(12) (12), 20188003 - 20188003, English

  [Refereed]

  Scientific journal


• Layer Skip Learning using LARS variables for 39% Faster Conversion Time and Lower Bandwidth

  Miyauchi, Yuki, Mori, Haruki, Youkawa, Tetsuya, Yamada, Kazuki, Izumi, Shintaro, Yoshimoto, Masahiko, Kawaguchi, Hiroshi, Inoue, Atsuki

  2018, 2018 25TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 673 - 676, English

  [Refereed]

  International conference proceedings


• Sampling Rate Reduction for Wearable Heart Rate Variability Monitoring

  Nishikawa, Yuki, Izumi, Shintaro, Yano, Yuji, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

  2018, 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), English

  [Refereed]

  International conference proceedings


• Hardware Implementation of Autoregressive Model Estimation Using Burg's Method for Low-Energy Spectral Analysis

  Kajihara, Koichi, Izumi, Shintaro, Yoshida, Seiya, Yano, Yuji, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

  2018, PROCEEDINGS OF THE 2018 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), 199 - 204, English

  [Refereed]

  International conference proceedings


• Adaptive Learning Rate Adjustment with Short-Term Pre-Training in Data-Parallel Deep Learning

  Yamada, Kazuki, Mori, Haruki, Youkawa, Tetsuya, Miyauchi, Yuki, Izumi, Shintaro, Yoshimoto, Masahiko, Kawaguchi, Hiroshi

  2018, PROCEEDINGS OF THE 2018 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), 100 - 105, English

  [Refereed]

  International conference proceedings


• 28-nm FD-SOI Dual-Port SRAM with MSB-Based Inversion Logic for Low-Power Deep Learning

  Mori, Haruki, Izumi, Shintaro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

  2018, 2018 25TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 161 - 164, English

  [Refereed]

  International conference proceedings


• Non-Contact Biometric Identification and Authentication Using Microwave Doppler Sensor

  OKANO Takaaki, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Oct. 2017, The 13th IEEE BioMedical Circuits and Systems Conference(BioCAS), pp.392-395, Oct. 2017., 392 - 395, English

  [Refereed]

  International conference proceedings


• A swallowable sensing device platform with wireless power feeding and chemical reaction actuator.

  Ryota Nakamura, Shintaro Izumi, Hiroshi Kawaguchi, Hidetoshi Ohta, Masahiko Yoshimoto

  This paper presents a swallowable sensor device that can be ingested orally, later passing to the stomach, where the device can indwell for long periods. Using wireless communication, it can be egested at any time after it is triggered. This device can indwell using a silicone balloon in the gastrointestinal tract. A chemical reaction inflates the balloon inside the stomach. Then it is deflated to egest the sensor device using an actuator with electrolysis of water. Energy for the actuator with electrolysis can be fed wirelessly. Near field communication and a flexible antenna are used for power feeding and wireless data communication. Because of the flexible balloon and the flexible antenna, the device size can be minimized without performance degradation.

  Jul. 2017, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2017, 3040 - 3043, English, International magazine

  [Refereed]

  Scientific journal


• A contact-less heart rate sensor system for driver health monitoring

  IZUMI Shintaro, MATSUNAGA Daichi, NAKAMURA Ryota, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jul. 2017, The 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC’17), July. 2017, English

  International conference proceedings


• A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video

  Matsukawa, Go, Kodama, Taisuke, Nishizumi, Yuri, Kajihara, Koichi, Nakanishi, Chikako, Izumi, Shintaro, Kawaguchi, Hiroshi, Goto, Toshio, Kato, Takeo, Yoshimoto, Masahiko

  Apr. 2017, IEICE ELECTRONICS EXPRESS, 14(15) (15), 1 - 12, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A Novel Test Scheme for Detecting Faulty Recall Margin Cells for6T-4C FeRAM,

  UMEKI Yohei, IZUMI Shintaro, KITAHARA Hiroto, NAKAGAWA Tomoki, YANAGIDA Kouji, YOSHIMOTO Shusuke, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, KIMURA Hiromitsu, MARUMOTO Kyoji, FUCHIKAMI Takaaki, FUJIMORI Yoshikazu

  神戸大学大学院工学研究科, Feb. 2017, Memoirs of the Graduate Schools of Engineering and SystemInformatics Kobe University, no. 8, pp. 5-8, Feb. 2017., 8, English

  [Refereed]

  Research institution

  Link to Kobe Univ. Repository (Kernel)


• A 19-mu A Metabolic Equivalents Monitoring SoC using Adaptive Sampling

  Tsukahara, Mio, Izumi, Shintaro, Nakanashi, Motofumi, Kawaguchi, Hiroshi, Yoshimoto, Masahiko, Kimura, Hiromitsu, Maromoto, Kyoji, Fuchikami, Takaaki, Fujimori, Yoshikazu

  2017, 2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 37 - 38, English

  [Refereed]

  International conference proceedings


• A LAYER-BLOCK-WISE PIPELINE FOR MEMORY AND BANDWIDTH REDUCTION IN DISTRIBUTED DEEP LEARNING

  Mori, Haruki, Youkawa, Tetsuya, Izumi, Shintaro, Yoshimoto, Masahiko, Kawaguchi, Hiroshi, Inoue, Atsuki

  2017, 2017 IEEE 27TH INTERNATIONAL WORKSHOP ON MACHINE LEARNING FOR SIGNAL PROCESSING, English

  [Refereed]

  International conference proceedings


• Wearable pulse wave velocity sensor using flexible piezoelectric film array.

  Takumi Katsuura, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Shusuke Yoshimoto, Tsuyoshi Sekitani

  IEEE, 2017, Proc. of IEEE Biomedical Circuits and Systems Conference (BioCAS), pp. 721–724, Oct. 2017, 1 - 4, English

  [Refereed]

  International conference proceedings


• Multimodal Cardiovascular Information Monitor using Piezoelectric Transducers for Wearable Healthcare

  Okano, Takaaki, Izumi, Shintaro, Katsuura, Takumi, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

  2017, 2017 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), English

  [Refereed]

  International conference proceedings


• FPGA Implementation of Object Recognition Processor for HDTV Resolution Video Using Sparse FIND Feature

  Nishizumi, Yuri, Matsukawa, Go, Kajihara, Koichi, Kodama, Taisuke, Izumi, Shintaro, Kawaguchi, Hiroshi, Nakanishi, Chikako, Goto, Toshio, Kato, Takeo, Yoshimoto, Masahiko

  2017, 2017 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), English

  [Refereed]

  International conference proceedings


• Capacitively coupled ECG sensor system with digitally assisted noise cancellation for wearable application.

  Yuki Nagasato, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  IEEE, 2017, The 13th IEEE BioMedical Circuits and Systems Conference(BioCAS), pp.400-403, Oct. 2017., 1 - 4, English

  [Refereed]

  International conference proceedings


• A METABOLIC EQUIVALENTS ESTIMATION ALGORITHM USING TRIAXIAL ACCELEROMETER AND ADAPTIVE SAMPLING FOR WEARABLE DEVICES

  Nakanishi, Motofumi, Izumi, Shintaro, Tsukahara, Mio, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

  2017, 2017 IEEE LIFE SCIENCES CONFERENCE (LSC), 107 - 110, English

  [Refereed]

  International conference proceedings


• Multimodal Cardiovascular Information Monitor using Piezoelectric Transducers for Wearable Healthcare

  Okano, Takaaki, Izumi, Shintaro, Katsuura, Takumi, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

  2017, 2017 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), 1 - 10, English

  [Refereed][Invited]

  International conference proceedings


• 消化管内へ留置する飲み込型センサの検討

  NAKAMURA Ryota, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, OHTA Hidetoshi

  Sep. 2016, 電気学会C部門大会, 2016年9月1日，神戸, 2016, Japanese

  Symposium


• 加速度センサを用いた低消費電力運動強度推定アルゴリズム

  TSUKAHARA Mio, NAKANISHI Motofumi, IZUMI Shintaro, NAKAI Yozaburo, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Sep. 2016, 電気学会C部門大会, 2016年9月1日，神戸., 2016, Japanese

  Symposium


• 加速度センサを用いた低消費電力運動強度推定アルゴリズム

  TSUKAHARA Mio, NAKANISHI Motofumi, IZUMI Shintaro, NAKAI Yozaburo, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Sep. 2016, IEICEソサイエティ大会, 2016年9月21日，札幌, 2016, Japanese

  Symposium


• Swallowable sensing device for long-term gastrointestinal tract monitoring.

  Ryota Nakamura, Shintaro Izumi, Hiroshi Kawaguchi, Hidetoshi Ohta, Masahiko Yoshimoto

  This paper presents a swallowable sensor device that can be ingested orally, later arriving to the stomach, where the device can indwell for a long term and can be egested at any time after it is triggered using wireless communication. This device can inflate a silicone balloon in the gastrointestinal tract using a chemical reaction. The balloon can be deflated later using electrolysis of water at the time of egestion. A motorless chemical-reaction-based egestion method is proposed to minimize the sensor device size. This device can achieve long-term monitoring in the gastrointestinal tract.

  Aug. 2016, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2016, 3039 - 3042, English, International magazine

  [Refereed]

  Scientific journal


• Low-power metabolic equivalents estimation algorithm using adaptive acceleration sampling.

  Mio Tsukahara, Motofumi Nakanishi, Shintaro Izumi, Yozaburo Nakai, Hiroshi Kawaguchi, Masahiko Yoshimoto

  This paper describes a proposed low-power metabolic equivalent estimation algorithm that can calculate the value of metabolic equivalents (METs) from triaxial acceleration at an adaptively changeable sampling rate. This algorithm uses four rates of 32, 16, 8 and 4 Hz. The mode of switching them is decided from synthetic acceleration. Applying this proposed algorithm to acceleration measured for 1 day, we achieved the low root mean squared error (RMSE) of calculated METs, with current consumption that was 41.5 % of the value at 32 Hz, and 75.4 % of the value at 16 Hz.

  Aug. 2016, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2016, 1878 - 1881, English, International magazine

  [Refereed]

  Scientific journal


• A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor

  Haruki Mori, Yohei Umeki, Shusuke Yoshimoto, Shintaro Izumi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Aug. 2016, IEICE TRANSACTIONS ON ELECTRONICS, E99C(8) (8), 901 - 908, English

  [Refereed]

  Scientific journal


• Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path

  Go Matsukawa, Yuta Kimi, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Jun. 2016, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E99A(6) (6), 1198 - 1205, English

  [Refereed]

  Scientific journal


• 298-fJ/writecycle 650-fJ/readcycle を実現する画像処理プロセッサ向け 28-nm FD-SOI 8T 3ポートSRAM

  MORI Haruki, NAKAGAWA Tomoki, KITAHARA Yuki, KAWAMOTO Yuta, TAKAGI Kenta, YOSHIMOTO Shusuke, IZUMI Shintaro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  電子情報通信学会, Apr. 2016, 信学技報, vol.116, no.3, pp.13-16, 2016年4月14日，東京., 116(3) (3), 13 - 16, Japanese

  Symposium


• Process variation tolerant counter base read circuit for low-voltage operating STT-MRAM

  UMEKI Yohei, YANAGIDA Kouji, KUROTSU Hiroaki, KITAHARA Hiroto, MORI Haruki, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, YOSHIMOTO Shusuke, TSUNODA Koji, SUGII Toshihiro

  Mar. 2016, DATE EMS Workshop, Mar. 2016, English

  [Refereed]

  International conference proceedings


• Capacitively Coupled ECG Sensor using a Single Electrode with Adaptive Power-Line Noise Cancellation

  Yuta Kawamoto, Shintaro Izumi, Yoshito Tanaka, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2016, 2016 3RD IEEE EMBS INTERNATIONAL CONFERENCE ON BIOMEDICAL AND HEALTH INFORMATICS, 212 - 215, English

  [Refereed][Invited]

  International conference proceedings


• An Soft Error Propagation Analysis Considering Logical Masking Effect on Re-convergent Path

  Shuhei Yoshida, Go Matsukawa, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2016, 2016 IEEE 22ND INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS), 13 - 16, English

  [Refereed]

  International conference proceedings


• A counter-based read circuit tolerant to process variation for 0.4-V operating STT-MRAM

  Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii

  Information Processing Society of Japan, 2016, IPSJ Transactions on System LSI Design Methodology, 9, 79 - 83, English

  [Refereed]

  Scientific journal


• Adaptive Noise Cancellation Method for Capacitively Coupled ECG Sensor using Single Insulated Electrode

  Yoshito Tanaka, Shintaro Izumi, Yuta Kawamoto, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2016, PROCEEDINGS OF 2016 IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE (BIOCAS), 296 - 299, English

  [Refereed]

  International conference proceedings


• Non-Contact Instantaneous Heart Rate Monitoring using Microwave Doppler Sensor and Time-Frequency Domain Analysis

  Daichi Matsunaga, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2016, 2016 IEEE 16TH INTERNATIONAL CONFERENCE ON BIOINFORMATICS AND BIOENGINEERING (BIBE), 172 - 175, English

  [Refereed]

  International conference proceedings


• An Low-Energy 8T Dual-Port SRAM for Image Processor with Selective Sourceline Drive Scheme in 28-nm FD-SOI Process Technology

  Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2016, 23RD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS CIRCUITS AND SYSTEMS (ICECS 2016), 532 - 535, English

  [Refereed]

  International conference proceedings


• A 15-mu A Metabolic Equivalents Monitoring System using Adaptive Acceleration Sampling and Normally Off Computing

  Mio Tsukahara, Shintaro Izumi, Motofumi Nakanishi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori

  2016, 23RD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS CIRCUITS AND SYSTEMS (ICECS 2016), 61 - 64, English

  [Refereed]

  International conference proceedings


• Batteryless sensorless bicycle speed recorder with hub dynamo and STT-MRAM

  A. Tanaka, T. Douseki, Y. Umeki, H. Kawaguchi, M. Yoshimoto, K. Tsunoda, T. Sugii

  Institute of Electrical and Electronics Engineers Inc., Dec. 2015, 2015 IEEE SENSORS - Proceedings, English

  [Refereed]

  International conference proceedings


• A Fast Settling All Digital PLL Using Temperature Compensated Oscillator Tuning Word Estimation Algorithm

  Keisuke Okuno, Shintaro Izumi, Kana Masaki, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Dec. 2015, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E98A(12) (12), 2592 - 2599, English

  [Refereed]

  Scientific journal


• Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector.

  Shintaro Izumi, Ken Yamashita, Masanao Nakano, Shusuke Yoshimoto, Tomoki Nakagawa, Yozaburo Nakai, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto

  This paper describes an electrocardiograph (ECG) monitoring SoC using a non-volatile MCU (NVMCU) and a noise-tolerant instantaneous heartbeat detector. The novelty of this work is the combination of the non-volatile MCU for normally off computing and a noise-tolerant-QRS (heartbeat) detector to achieve both low-power and noise tolerance. To minimize the stand-by current of MCU, a non-volatile flip-flop and a 6T-4C NVRAM are used. Proposed plate-line charge-share and bit-line non-precharge techniques also contribute to mitigate the active power overhead of 6T-4C NVRAM. The proposed accurate heartbeat detector uses coarse-fine autocorrelation and a template matching technique. Accurate heartbeat detection also contributes system-level power reduction because the active ratio of ADC and digital block can be reduced using heartbeat prediction. Measurement results show that the fully integrated ECG-SoC consumes 6.14 μ A including 1.28- μA non-volatile MCU and 0.7- μA heartbeat detector.

  IEEE, Oct. 2015, IEEE transactions on biomedical circuits and systems, 9(5) (5), 641 - 51, English, International magazine

  [Refereed]

  Scientific journal


• A Wearable Healthcare System With a 13.7 μA Noise Tolerant ECG Processor.

  Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto

  To prevent lifestyle diseases, wearable bio-signal monitoring systems for daily life monitoring have attracted attention. Wearable systems have strict size and weight constraints, which impose significant limitations of the battery capacity and the signal-to-noise ratio of bio-signals. This report describes an electrocardiograph (ECG) processor for use with a wearable healthcare system. It comprises an analog front end, a 12-bit ADC, a robust Instantaneous Heart Rate (IHR) monitor, a 32-bit Cortex-M0 core, and 64 Kbyte Ferroelectric Random Access Memory (FeRAM). The IHR monitor uses a short-term autocorrelation (STAC) algorithm to improve the heart-rate detection accuracy despite its use in noisy conditions. The ECG processor chip consumes 13.7 μA for heart rate logging application.

  IEEE, Oct. 2015, IEEE transactions on biomedical circuits and systems, 9(5) (5), 733 - 42, English, International magazine

  [Refereed]

  Scientific journal


• Physical activity group classification algorithm using triaxial acceleration and heart rate.

  Motofumi Nakanishi, Shintaro Izumi, Sho Nagayoshi, Hironori Sato, Hiroshi Kawaguchi, Masahiko Yoshimoto, Takafumi Ando, Satoshi Nakae, Chiyoko Usui, Tomoko Aoyama, Shigeho Tanaka

  As described in this paper, a physical activity classification algorithm is proposed for energy expenditure estimation. The proposed algorithm can improve the classification accuracy using both the triaxial acceleration and heart rate. The optimal classification also contributes to improvement of the accuracy of the energy expenditures estimation. The proposed algorithm employs three indices: the heart rate reserve (%HRreserve), the filtered triaxial acceleration, and the ratio of filtered and unfiltered acceleration. The percentage HRreserve is calculated using the heart rate at rest condition and the maximum heart rate, which is calculated using Karvonen Formula. Using these three indices, a decision tree is constructed to classify physical activities into five classes: sedentary, household, moderate (excluding locomotive), locomotive, and vigorous. Evaluation results show that the average classification accuracy for 21 activities is 91%.

  37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society(EMBC), Aug. 2015, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2015, 510 - 3, English, International magazine

  [Refereed][Invited]

  International conference proceedings


• Large displacement haptic stimulus actuator using piezoelectric pump for wearable devices.

  Taisuke Kodama, Shintaro Izumi, Kana Masaki, Hiroshi Kawaguchi, Kazusuke Maenaka, Masahiko Yoshimoto

  Recently, given Japan's aging society background, wearable healthcare devices have increasingly attracted attention. Many devices have been developed, but most devices have only a sensing function. To expand the application area of wearable healthcare devices, an interactive communication function with the human body is required using an actuator. For example, a device must be useful for medication assistance, predictive alerts of a disease such as arrhythmia, and exercise. In this work, a haptic stimulus actuator using a piezoelectric pump is proposed to realize a large displacement in wearable devices. The proposed actuator drives tactile sensation of the human body. The measurement results obtained using a sensory examination demonstrate that the proposed actuator can generate sufficient stimuli even if adhered to the chest, which has fewer tactile receptors than either the fingertip or wrist.

  37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society(EMBC), Aug. 2015, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2015, 1172 - 5, English, International magazine

  [Refereed][Invited]

  Scientific journal


• A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques

  Tomoki Nakagawa, Shintaro Izumi, Koji Yanagida, Yuki Kitahara, Shusuke Yoshimoto, Yohei Umeki, Haruki Mori, Hiroto Kitahara, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Masahiko Yoshimoto

  Institute of Electrical and Electronics Engineers Inc., Jul. 2015, Proceedings - IEEE International Symposium on Circuits and Systems, 2015-, 2904 - 2907, English

  [Refereed]

  International conference proceedings


• Low-Jitter Design for Second-Order Time-to-Digital Converter Using Frequency Shift Oscillators

  Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi

  Jul. 2015, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E98A(7) (7), 1475 - 1481, English

  [Refereed]

  Scientific journal


• An I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter

  Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi

  Jun. 2015, IEICE TRANSACTIONS ON ELECTRONICS, E98C(6) (6), 489 - 495, English

  [Refereed]

  Scientific journal


• Noise Tolerant Heart Rate Extraction Algorithm Using Short-Term Autocorrelation for Wearable Healthcare Systems

  Shintaro Izumi, Masanao Nakano, Ken Yamashita, Yozaburo Nakai, Hiroshi Kawaguchi, Masahiko Yoshimoto

  May 2015, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E98D(5) (5), 1095 - 1103, English

  [Refereed]

  Scientific journal


• A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme

  Go Matsukawa, Yohei Nakata, Yasuo Sugure, Shigeru Oho, Yuta Kimi, Masafumi Shimozawa, Shuhei Yoshida, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Apr. 2015, IEICE TRANSACTIONS ON ELECTRONICS, E98C(4) (4), 333 - 339, English

  [Refereed]

  Scientific journal


• A 298-fJ/writecycle 650-fJ/readcycle 8T Three-Port SRAM in 28-nm FD-SOI Process Technology for Image Processor

  Haruki Mori, T. Nakagawa, Y. Kitahara, Y. Kawamoto, K. Takagi, S. Yoshimoto, S. Izumi, K. Nii, H. Kawaguchi, M. Yoshimoto

  2015, 2015 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), English

  [Refereed]

  International conference proceedings


• Analysis of Soft Error Propagation considering Masking Effects on Re-convergent Path

  Kimi, Yuta, Matsukawa, Go, Yoshida, Shuhei, Izumi, Shintaro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

  2015, 2015 IEEE 24TH ASIAN TEST SYMPOSIUM (ATS), 139 - 144, English

  [Refereed]

  International conference proceedings


• A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance with Bit-Enhancing Memory and On-Chip Diagnosis Structures Delivering x91 Failure Rate Improvement

  Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2015, PROCEEDINGS OF THE FIFTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2014), 16 - +, English

  [Refereed]

  International conference proceedings


• A Negative-Resistance Sense Amplifier for Low-Voltage Operating STT-MRAM

  Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, Koji Tsunoda, Toshihiro Sugii

  Jan. 2015, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) University LSI Design Contest, pp. 8 - 9, English

  [Refereed]

  International conference proceedings


• A 14 mu A ECG Processor with Noise Tolerant Heart Rate Extractor and FeRAM for Wearable Healthcare Systems

  Yozaburo Nakai, Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2015, 2015 20TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 16 - 17, English

  [Refereed]

  International conference proceedings


• A Low Power 6T-4C Non-volatile Memory using Charge Sharing and Non-precharge Techniques

  Tomoki Nakagawa, Shintaro Izumi, Koji Yanagida, Yuki Kitahara, Shusuke Yoshimoto, Yohei Umeki, Haruki Mori, Hiroto Kitahara, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Masahiko Yoshimoto

  2015, 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2904 - 2907, English

  [Refereed][Invited]

  International conference proceedings


• An Accurate Soft Error Propagation Analysis Technique Considering Temporal Masking Disablement

  Yuta Kimi, Go Matsukawa, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2015, 2015 IEEE 21ST INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), 23 - 25, English

  [Refereed][Invited]

  International conference proceedings


• Non-contact and noise tolerant heart rate monitoring using microwave doppler sensor and range imagery.

  Daichi Matsunag, Shintaro Izumi, Keisuke Okuno, Hiroshi Kawaguchi, Masahiko Yoshimoto

  This paper describes a non-contact and noise-tolerant heart beat monitoring system. The proposed system comprises a microwave Doppler sensor and range imagery using Microsoft Kinect™. The possible application of the proposed system is a driver health monitoring. We introduce the sensor fusion approach to minimize the heart beat detection error. The proposed algorithm can subtract a body motion artifact from Doppler sensor output using time-frequency analysis. The body motion artifact is a crucially important problem for biosignal monitoring using microwave Doppler sensor. The body motion speed is obtainable from range imagery, which has 5-mm resolution at 30-cm distance. Measurement results show that the success rate of the heart beat detection is improved about 75% on average when the Doppler wave is degraded by the body motion artifact.

  37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society(EMBC), 2015, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2015, 6118 - 21, English, International magazine

  [Refereed][Invited]

  Scientific journal


• A Ferroelectric-Based Non-Volatile Flip-Flop for Wearable Healthcare Systems

  Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Hiromitsu Kimura, Takaaki Fuchikami, Kyoji Marumoto, Yoshikazu Fujimori

  2015, 2015 15TH NON-VOLATILE MEMORY TECHNOLOGY SYMPOSIUM (NVMTS), pp.1 - 4, English

  [Refereed][Invited]

  International conference proceedings


• 不揮発マイコンを用いたノーマリーオフ生体計測SoC

  松永 大地, 中井 陽三郎, 河本 優太, 中川 知己, 奥野 圭祐, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  Dec. 2014, 信学技報, vol. 114(no. 345) (no. 345), p. 49, Japanese

  Research society


• ウェアラブル生体センサのための心電計測方法

  田中 義人, 河本 優太, 中井 陽三郎, 奥野 圭祐, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  Dec. 2014, 信学技報, vol. 114(no. 345) (no. 345), p. 47, Japanese

  Research society


• STT-MRAM Operating at 0.38 V Using Negative-Resistance Sense Amplifier

  Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii

  Dec. 2014, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A(12) (12), 2411 - 2417, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• Soft-Error Resilient and Margin-Enhanced N-P Reversed 6T SRAM Bitcell

  Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Sep. 2014, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A(9) (9), 1945 - 1951, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A Real-time Scalable Object Detection System using Low-power HOG Accelerator VLSI

  Takagi, Kenta, Tanaka, Kotaro, Izumi, Shintaro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

  Sep. 2014, JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 76(3) (3), 261 - 274, English

  [Refereed]

  Scientific journal


• A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering x91 Failure Rate Improvement under 35% Supply Voltage Fluctuation

  Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Apr. 2014, IEICE TRANSACTIONS ON ELECTRONICS, E97C(4) (4), 332 - 341, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM

  G.Matsukawa, Y.Nakata, Y.Kimi, Y.Sugure, M.Shimozawa, S.Oho, H.Kawaguchi, M.Yoshimoto

  Feb. 2014, ARCS VERFE Workshop, pp.1 - 5, English

  [Refereed]

  Symposium


• Low-Power SRAM in 28-nm FD-SOI for Image Processor

  KAWAMOTO Yuta, YOSHIMOTO Shusuke, NAKAGAWA Tomomki, KITAHARA Yuki, MORI Haruki, TAKAGI Kenta, IZUMI Shintaro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  The Institute of Electronics, Information and Communication Engineers, Jan. 2014, Technical report of IEICE. ICD, 113(419) (419), 41 - 41, Japanese

  Research society


• Foreword: Special section on VLSI design and CAD algorithms

  Yamada, A., Higami, Y., Takagi, K., Amagasaki, M., Ikeda, M., Ishihara, T., Ito, K., Usami, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kurokawa, A., Shibata, Y., Seto, K., Song, T., Takashima, Y., Takahashi, A., Takenaka, T., Togawa, N., Tomiyama, H., Nakatake, S., Nakamura, Y., Hashimoto, M., Hamaguchi, K., Higuchi, H., Hirose, T., Fukuda, D., Matsumoto, T., Miura, Y., Minato, S.-I., Minami, F., Yamashita, S., Yuminaka, Y., Yoshikawa, M., Watanabe, T.

  2014, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E97A(12) (12), 2366 - 2366

  Scientific journal


• Foreword: Special section on VLSI design and CAD algorithms

  Yamada, A., Higami, Y., Takagi, K., Amagasaki, M., Ikeda, M., Ishihara, T., Ito, K., Usami, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kurokawa, A., Shibata, Y., Seto, K., Song, T., Takashima, Y., Takahashi, A., Takenaka, T., Togawa, N., Tomiyama, H., Nakatake, S., Nakamura, Y., Hashimoto, M., Hamaguchi, K., Higuchi, H., Hirose, T., Fukuda, D., Matsumoto, T., Miura, Y., Minato, S.-I., Minami, F., Yamashita, S., Yuminaka, Y., Yoshikawa, M., Watanabe, T.

  2014, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E97A(12) (12), 2366 - 2366

  Scientific journal


• Foreword: Special section on VLSI design and CAD algorithms

  Yamada, A., Higami, Y., Takagi, K., Amagasaki, M., Ikeda, M., Ishihara, T., Ito, K., Usami, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kurokawa, A., Shibata, Y., Seto, K., Song, T., Takashima, Y., Takahashi, A., Takenaka, T., Togawa, N., Tomiyama, H., Nakatake, S., Nakamura, Y., Hashimoto, M., Hamaguchi, K., Higuchi, H., Hirose, T., Fukuda, D., Matsumoto, T., Miura, Y., Minato, S.-I., Minami, F., Yamashita, S., Yuminaka, Y., Yoshikawa, M., Watanabe, T.

  2014, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E97A(12) (12), 2366 - 2366

  Scientific journal


• Foreword: Special section on VLSI design and CAD algorithms

  Yamada, A., Higami, Y., Takagi, K., Amagasaki, M., Ikeda, M., Ishihara, T., Ito, K., Usami, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kurokawa, A., Shibata, Y., Seto, K., Song, T., Takashima, Y., Takahashi, A., Takenaka, T., Togawa, N., Tomiyama, H., Nakatake, S., Nakamura, Y., Hashimoto, M., Hamaguchi, K., Higuchi, H., Hirose, T., Fukuda, D., Matsumoto, T., Miura, Y., Minato, S.-I., Minami, F., Yamashita, S., Yuminaka, Y., Yoshikawa, M., Watanabe, T.

  2014, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E97A(12) (12), 2366 - 2366

  Scientific journal


• A 6T-4C shadow memory using plate line and word line boosting

  Tomoki Nakagawa, Shintaro Izumi, Shusuke Yoshimoto, Koji Yanagida, Yuki Kitahara, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Institute of Electrical and Electronics Engineers Inc., 2014, Proceedings - IEEE International Symposium on Circuits and Systems, 2736 - 2739, English

  [Refereed]

  International conference proceedings


• 動作環境の動的変動を考慮した動作マージン拡大機能を有する自律制御キャッシュ

  KIMI Yuta, NAKATA Yohei, OKUMURA Syunsuke, JUNG Jinwook, 沢田 卓也, 利川 托, 永田 真, 中野 博文, 薮内 誠, 藤原 英弘, 新居 浩二, 河合 浩行, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jan. 2014, 信学技報, vol. 113(no. 419) (no. 419), p. 59, Japanese

  Research society


• 磁性変化型メモリの書き込み速度を改善するメモリアーキテクチャ

  MORI Haruki, YANAGIDA Kouji, UMEKI Youhei, YOSHIMOTO Shusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, 角田 浩司, 杉井 寿博

  Jan. 2014, 信学技報, vol. 113(no. 419) (no. 419), p. 27, Japanese

  Research society


• 強誘電体メモリの高速回路技術

  NAKAGAWA Tomoki, YOSHIMOTO Shusuke, KITAHARA Yuki, YANAGIDA Kouji, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jan. 2014, 信学技報, vol. 113(no. 419) (no. 419), p. 39, Japanese

  Research society


• ディペンダブルメモリを用いた低遅延デュアルコアロックステップアーキテクチャ

  MATSUKAWA Go, NAKATA Yohei, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jan. 2014, 信学技報, vol. 113(no. 419) (no. 419), p. 57, Japanese

  Research society


• ウェアラブル生体センサのための心電図解析方法

  NAKAI Yozaburo, IZUMI Shintaro, NAKANO Masanao, YAMASHITA Ken, FUJI Takahide, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jan. 2014, 信学技報, vol. 113(no. 419) (no. 419), p. 61, Japanese

  Research society


• A 54-mw 3x-real-time 60-kword continuous speech recognition processor VLSI

  Guangji He, Yuki Miyamoto, Kumpei Matsuda, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2014, IEICE ELECTRONICS EXPRESS, 11(2) (2), pp. 1 - 9, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• Normally-Off Technologies for Healthcare Appliance

  Izumi, Shintaro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko, Fujimori, Yoshikazu

  2014, 2014 19TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 17 - 20, English

  [Refereed]

  International conference proceedings


• A 6T-4C Shadow Memory using Plate Line and Word Line Boosting

  Nakagawa, Tomoki, Izumi, Shintaro, Yoshimoto, Shusuke, Yanagida, Koji, Kitahara, Yuki, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

  2014, 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2736 - 2739, English

  [Refereed]

  International conference proceedings


• Noise tolerant QRS detection using template matching with short-term autocorrelation.

  Yozaburo Nakai, Shintaro Izumi, Masanao Nakano, Ken Yamashita, Takahide Fujii, Hiroshi Kawaguchi, Masahiko Yoshimoto

  This paper describes a robust method for heart beat detection from noisy electrocardiogram (ECG) signals. Generally, the QRS-complex of heart beat is extracted from the ECG using a threshold. However, in a noisy condition such a mobile and wearable bio-signal monitoring system, noise increases the incidence of misdetection and false detection of QRS-complex. To prevent incorrect detection, we introduce a novel template matching algorithm. The template waveform can be generated autonomously using a short-term autocorrelation method, which leverages the similarity of QRS-complex waveforms. Simulation results show the proposed method achieves state-of-the-art noise tolerance of heart beat detection.

  2014, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2014, 34 - 7, English, International magazine

  [Refereed]

  Scientific journal


• A 6.14 mu A Normally-Off ECG-SoC with Noise Tolerant Heart Rate Extractor for Wearable Healthcare Systems

  Shintaro Izumi, Ken Yamashita, Masanao Nakano, Tomoki Nakagawa, Yuki Kitahara, Koji Yanagida, Shusuke Yoshimoto, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto

  2014, 2014 IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE (BIOCAS), 280 - 283, English

  [Refereed]

  International conference proceedings


• A 2.4 pJ Ferroelectric-Based Non-Volatile Flip-Flop with 10-Year Data Retention Capability

  Kimura, Hiromitsu, Fuchikami, Takaaki, Marumoto, Kyoji, Fujimori, Yoshikazu, Izumi, Shintaro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

  2014, 2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 21 - 24, English

  [Refereed]

  International conference proceedings


• An 8-bit I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter

  Okuno, Keisuke, Konishi, Toshihiro, Izumi, Shintaro, Yoshimoto, Masahiko, Kawaguchi, Hiroshi

  2014, 2014 21ST IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 223 - 226, English

  [Refereed]

  International conference proceedings


• A 2.23 ps RMS Jitter 3 mu s Fast Settling ADPLL using Temperature Compensation PLL Controller

  Okuno, Keisuke, Masaki, Kana, Izumi, Shintaro, Konishi, Toshihiro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

  2014, 2014 21ST IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 68 - 71, English

  [Refereed]

  International conference proceedings


• A 2.4x-Real-Time VLSI Processor for 60-kWord Continuous Speech Recognition

  HE Guangji, MIYAMOTO Yuki, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). We implement parallel and pipelined architecture for GMM computation and Viterbi processing. It includes a 8-path Viterbi transition architecture to maximize the processing speed and adopts tri-gram language model to improve the recognition accuracy. A two-level cache architecture is implemented for the demo system. The test chip, fabricated in 40 nm CMOS technology, occupies 1.77 mm × 2.18 mm containing 2.98 M transistors for logic and 4.29 Mbit on-chip memory. The measured results show that our implementation achieves 25% required frequency reduction (62.5 MHz) and 26% power consumption reduction (54.8 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 3.02× and 2.25× times faster than real-time at 200 MHz using the bigram and trigram language models, respectively.

  The Institute of Electronics, Information and Communication Engineers, Oct. 2013, Technical report of IEICE. ICD, 113(236) (236), 29 - 34, Japanese

  Research society


• Soft-Error Tolerant N-P Reversed 6T SRAM Cell

  S. Yoshimoto, S. Izumi, H. Kawaguchi, YOSHIMOTO Masahiko

  Jul. 2013, IEEE Nuclear and Space Radiation Effects Conference (NSREC), PG - 3, English

  [Refereed]

  International conference proceedings


• Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout

  Shusuke Yoshimoto, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Jul. 2013, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E96A(7) (7), 1579 - 1585, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• NMOS-Centered 6T SRAM Layout Reducing Neutron-Induced Multiple Cell Upsets

  YOSHIMOTO Shusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  This paper presents a proposed NMOS-centered 6T SRAM cell layout that reduces a neutron-induced multiple-cell-upset (MCU) SER on a same wordline. We implemented an 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67-98% compared with a general macro that has PMOS-centered 6T SRAM cells.

  The Institute of Electronics, Information and Communication Engineers, Apr. 2013, Technical report of IEICE. ICD, 113(1) (1), 121 - 126, Japanese

  Research society


• ゼロデータフラグを用いた低エネルギーSTT-RAMキャッシュ

  KIMI Yuta, JUNG Jinwook, NAKATA Yohei, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi

  Apr. 2013, 信学技報, vol. 113(no. 1) (no. 1), pp.47 - 52, Japanese

  Research society


• Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM

  Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Apr. 2013, IEICE TRANSACTIONS ON ELECTRONICS, E96C(4) (4), 528 - 537, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A Sub-100 mW Dual-Core HOG Accelerator VLSI for Parallel Feature Extraction Processing for HDTV Resolution Video

  Kosuke Mizuno, Kenta Takagi, Yosuke Terachi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Apr. 2013, IEICE TRANSACTIONS ON ELECTRONICS, E96C(4) (4), 433 - 443, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops

  Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi

  Apr. 2013, IEICE TRANSACTIONS ON ELECTRONICS, E96C(4) (4), 546 - 552, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A 168-mW 2.4x-Real-Time 60-kWord Continuous Speech Recognition Processor VLSI

  Guangji He, Takanobu Sugahara, Yuki Miyamoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Apr. 2013, IEICE TRANSACTIONS ON ELECTRONICS, E96C(4) (4), 444 - 453, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• SRAM Failure Injection to a Vehicle ECU and Its Behavior Evaluation

  Y. Takeuchi, Y. Nakata, Y. Ito, Y. Sugure, S. Oho, H. Kawaguchi, YOSHIMOTO MASAHIKO

  Mar. 2013, DATE RIIF Workshop, English

  [Refereed]

  International conference proceedings


• Model-Based Fault Injection for Large-Scale Failure Effect Analysis with 600-Node Cloud Computers

  Y. Nakata, Y. Ito, Y. Takeuchi, Y. Sugure, S. Oho, H. Kawaguchi, YOSHIMOTO MASAHIKO

  Mar. 2013, DATE RIIF Workshop, English

  [Refereed]

  International conference proceedings


• An FPGA implementation of a hog-based object detection processor

  Kosuke Mizuno, Yosuke Terachi, Kenta Takagi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Feb. 2013, IPSJ Transactions on System LSI Design Methodology, 6, 42 - 51, English

  [Refereed]

  International conference proceedings


• An Opampless Second-Order MASH Delta Sigma ADC with Using Gated Ring Oscillator Time-to-Digital Converter

  Konishi, Toshihiro, Okuno, Keisuke, Izumi, Shintaro, Yoshimoto, Masahiko, Kawaguchi, Hiroshi

  Feb. 2013, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E96A(2) (2), 434 - 442, English

  [Refereed]

  Scientific journal


• A 40-nm 54-mW 3×-real-time VLSI processor for 60-kWord continuous speech recognition

  Guangji He, Yuki Miyamoto, Kumpei Matsuda, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Institute of Electrical and Electronics Engineers Inc., 2013, IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, 147 - 152, English

  International conference proceedings


• Failure modes and effects analysis using virtual prototyping system with microcontroller model for automotive control system

  Yasuo Sugure, Yasuhiro Ito, Yohei Nakata, Yusuke Takeuchi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Shigeru Oho

  2013, IFAC Proceedings Volumes (IFAC-PapersOnline), 7(1) (1), 562 - 563, English

  [Refereed]

  International conference proceedings


• A Physical Unclonable Function Chip Exploiting Load Transistors' Variation in SRAM Bitcells

  S. Okumura, S. Yoshimoto, H. Kawaguchi, M. Yoshimoto

  2013, 2013 18TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 79 - 80, English

  [Refereed]

  International conference proceedings


• A 40-nm 144-mW VLSI Processor for Real-time 60-kWord Continuous Speech Recognition

  Guangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2013, 2013 18TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 71 - 72, English

  [Refereed]

  International conference proceedings


• A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique

  S. Yoshimoto, M. Terada, S. Okumura, T. Suzuki, S. Miyano, H. Kawaguchi, M. Yoshimoto

  2013, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 77 - 78, English

  [Refereed]

  International conference proceedings


• Energy-Efficient Spin-Transfer Torque RAM Cache Exploiting Additional All-Zero-Data Flags

  Jinwook Jung, Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi

  2013, PROCEEDINGS OF THE FOURTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2013), 216 - 222, English

  [Refereed]

  International conference proceedings


• A SUB-100-MILLIWATT DUAL-CORE HOG ACCELERATOR VLSI FOR REAL-TIME MULTIPLE OBJECT DETECTION

  Kenta Takagi, Kosuke Mizuno, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2013, 2013 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING (ICASSP), 2533 - 2537, English

  [Refereed]

  International conference proceedings


• Temperature Compensation using Least Mean Squares for Fast Settling All-Digital Phase-Locked Loop

  Keisuke Okuno, Shintaro Izumi, Toshihiro Konishi, Song Dae-Woo, Masahiko Yoshimoto, Hiroshi Kawaguchi

  2013, 2013 IEEE 11TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), pp.1 - 4, English

  [Refereed]

  International conference proceedings


• Multiple-Cell-Upset Hardened 6T SRAM Using NMOS-Centered Layout

  S. Yoshimoto, K. Nii, H. Kawaguchi, M. Yoshimoto

  2013, 2013 IEEE INTERNATIONAL MEETING FOR FUTURE OF ELECTRON DEVICES, KANSAI (IMFEDK2013), pp. 98 - 99, English

  [Refereed]

  International conference proceedings


• A 38 mu A Wearable Biosignal Monitoring System with Near Field Communication

  Yamashita, Ken, Izumi, Shintaro, Nakano, Masanao, Fujii, Takahide, Konishi, Toshihiro, Kawaguchi, Hiroshi, Kimura, Hiromitsu, Marumoto, Kyoji, Fuchikami, Takaaki, Fujimori, Yoshikazu, Nakajima, Hiroshi, Shiga, Toshikazu, Yoshimoto, Masahiko

  2013, 2013 IEEE 11TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), pp.1 - 4, English

  [Refereed]

  International conference proceedings


• Noise-tolerant instantaneous heart rate and R-peak detection using short-term autocorrelation for wearable healthcare systems.

  Takahide Fujii, Masanao Nakano, Ken Yamashita, Toshihiro Konishi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  This paper describes a robust method of Instantaneous Heart Rate (IHR) and R-peak detection from noisy electrocardiogram (ECG) signals. Generally, the IHR is calculated from the R-wave interval. Then, the R-waves are extracted from the ECG using a threshold. However, in wearable bio-signal monitoring systems, noise increases the incidence of misdetection and false detection of R-peaks. To prevent incorrect detection, we introduce a short-term autocorrelation (STAC) technique and a small-window autocorrelation (SWAC) technique, which leverages the similarity of QRS complex waveforms. Simulation results show that the proposed method improves the noise tolerance of R-peak detection.

  2013, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2013, 7330 - 3, English, International magazine

  [Refereed]

  Scientific journal


• A 40-nm 8T SRAM with Selective Source Line Control of Read Bitlines and Address Preset Structure

  S. Yoshimoto, S. Miyano, M. Takamiya, H. Shinohara, H. Kawaguchi, M. Yoshimoto

  2013, 2013 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), pp.1 - 4, English

  [Refereed]

  International conference proceedings


• A 14 μa ECG processor with robust heart rate monitor for a wearable healthcare system

  Shintaro Izumi, Ken Yamashita, Masanao Nakano, Toshihiro Konishi, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto

  2013, European Solid-State Circuits Conference, 145 - 148, English

  [Refereed]

  International conference proceedings


• A 40-NM 54-MW 3x-REAL-TIME VLSI PROCESSOR FOR 60-KWORD CONTINUOUS SPEECH RECOGNITION

  He, Guangji, Miyamoto, Yuki, Matsuda, Kumpei, Izumi, Shintaro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

  2013, 2013 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), 147 - 152, English

  [Refereed]

  International conference proceedings


• Low-power Hardware Implementation of Noise Tolerant Heart Rate Extractor for a Wearable Monitoring System

  Shintaro Izumi, Masanao Nakano, Ken Yamashita, Takahide Fujii, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2013, 2013 IEEE 13TH INTERNATIONAL CONFERENCE ON BIOINFORMATICS AND BIOENGINEERING (BIBE), pp.1 - 4, English

  [Refereed]

  International conference proceedings


• A 0.38-V Operating STT-MRAM with Process Variation Tolerant Sense Amplifier

  Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii

  2013, PROCEEDINGS OF THE 2013 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 249 - 252, English

  [Refereed]

  International conference proceedings


• A 2.4x-Real-Time VLSI Processor for 60-k Word Continuous Speech Recognition

  MIYAMOTO Yuuki, HE Guangji, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  This paper describes a low-power VLSI chip for 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). Our implementation includes a compression–decoding scheme to reduce the external memory bandwidth for Gaussian Mixture Model (GMM) computation and multi-path Viterbi transition units. We optimize the internal SRAM size using the max-approximation GMM calculation and adjusting the number of look-ahead frames. The measured results show that our implementation achieves 34.2% required frequency reduction (83.3 MHz) and reduces 48.5% power consumption (74.14 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 2.4× faster than real-time at 200 MHz and 1.1 V with power consumption of 168 mW.

  The Institute of Electronics, Information and Communication Engineers, Dec. 2012, Technical report of IEICE. ICD, 112(365) (365), 49 - 53, Japanese

  Scientific journal


• Low-Power Ferroelectric 6T4C Shadow SRAM for Normally-Off Computing

  Nakagawa Tomoki, Yoshimoto Shusuke, Kitahara Yuki, Yanagida Koji, Umeki Yohei, Okumura Shunsuke, Izumi Shintaro, Kawaguchi Hiroshi, Yoshimoto Masahiko

  In recent years, sensor network has attracted much attention in agricultural, medical, and disaster-prevention area to collect on-field information. Each sensor node requires extremely low-power operation because its battery size is limited. In the sensor node chip, memory consumes large leakage power so a low-power memory technique is strongly required.
  
  This paper presents a novel low-power technique for a ferroelectric 6T4C shadow SRAM. The shadow SRAM works a high-speed SRAM in an active mode and a nonvolatile FeRAM in a sleep mode. The nonvolatility completely removes the leakage current from the memory. However, the ferroelectric capacitors increase the power consumption and decrease the cycle time of the SRAM. In this paper, the proposed technique is evaluated by SPICE simulation results.

  The Institute of Electronics, Information and Communication Engineers, Dec. 2012, Technical report of IEICE. ICD, 112(365) (365), 41 - 41, Japanese

  Scientific journal


• Instantaneous Heart Rate Detection Using Short-Time Autocorrelation for Wearable Healthcare Systems

  YAMASHITA Ken, NAKANO Masanao, KONISHI Toshihiro, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  This report describes a robust method of Instantaneous Heart Rate (IHR) detection from noisy electrocardiogram (ECG) signals. Generally, the IHR is calculated from the interval of R-waves. Then, the R-waves are extracted from the ECG using a threshold. However, in wearable biosignal monitoring systems, various noises (e.g. muscle artifacts from myoelectric signals, electrode motion artifacts) increase incidences of misdetection and false detection because the power consumption and electrode distance of the wearable sensor are limited to reduce its size and weight. To prevent incorrect detection, we use a short-time autocorrelation technique. The proposed method uses similarity of the waveform of the QRS complex. Therefore, it has no threshold calculation Process and it is robust for noisy environment. By the proposed method, it is possible to reduce power consumption of Analog Front End and relax the performance requirements of the electrodes because IHR is calculated by digital signal processing.

  The Institute of Electronics, Information and Communication Engineers, Dec. 2012, Technical report of IEICE. ICD, 112(365) (365), 27 - 27, Japanese

  Scientific journal


• FPGA Implementation of HOG-based Real-Time Object Detection Processor

  TAKAGI Kenta, MIZUNO Kosuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Histogram of Oriented Gradients (HOG) is widely accepted feature descriptor for object detection. HOG is robust against changes in illumination and texture. Thus, HOG is highly effective for pedestrian detection and other object detection. In recent years, object detection techniques have been introduced to advanced automobile products and increasingly valuable. Additionally, recent progress of general-purpose processors enables to implement algorithms that require heavy computations such as HOG-based object detection. However, these processors suffer from high power consumption and are therefore unsuitable for mobile systems under limited battery conditions. Therefore, we propose a HOG-based object detection processor. It features a simplified HOG algorithm with cell-based scanning and simultaneous Support Vector Machine (SVM) calculation, cell-based pipeline architecture and parallelized modules. To evaluate the effectiveness of our approach, the proposed architecture is implemented onto a FPGA prototyping board. Results show that the proposed architecture can generate HOG features and detect objects with 40 MHz for SVGA resolution video (800 × 600 pixels) at 72 frames per second (fps).

  The Institute of Electronics, Information and Communication Engineers, Dec. 2012, Technical report of IEICE. ICD, 112(365) (365), 61 - 61, Japanese

  Scientific journal


• A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells

  Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Dec. 2012, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E95A(12) (12), 2226 - 2233, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure

  Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Oct. 2012, IEICE TRANSACTIONS ON ELECTRONICS, E95C(10) (10), 1675 - 1681, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A 40 nm 144 mW VLSI Processor for Real-Time 60-kWord Continuous Speech Recognition

  Guangji He, Takanobu Sugahara, Yuki Miyamoto, Tsuyoshi Fujinaga, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Aug. 2012, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 59(8) (8), 1656 - 1666, English

  [Refereed]

  Scientific journal


• Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process

  Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Koji Nii, Masahiko Yoshimoto, Hiroshi Kawaguchi

  Aug. 2012, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E95A(8) (8), 1359 - 1365, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• Trading off ECU Footprint for Reliability in X-by-Wire Application with Hybrid TMR Architecture

  Y. Nakata, S. Izumi, H. Kawaguchi, YOSHIMOTO MASAHIKO

  Jun. 2012, DAC International Workshop on System Level-Design of Automotive Electronics/Software (SLDAES),, English

  [Refereed]

  International conference proceedings


• SRAMセルを用いたLow書込みによるチップID生成手法

  奥村俊介, 吉本秀輔, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  Apr. 2012, 信学技報, vol. 112(no. 15) (no. 15), pp. 97 - 102, Japanese

  Scientific journal


• A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing

  Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Apr. 2012, IEICE TRANSACTIONS ON ELECTRONICS, E95C(4) (4), 523 - 533, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme

  Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Apr. 2012, IEICE TRANSACTIONS ON ELECTRONICS, E95C(4) (4), 572 - 578, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A 0.15-mu m FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme

  Shunsuke Okumura, Hidehiro Fujiwara, Kosuke Yamaguchi, Shusuke Yoshimoto, Masahiko Yoshimoto, Hiroshi Kawaguchi

  Apr. 2012, IEICE TRANSACTIONS ON ELECTRONICS, E95C(4) (4), 579 - 585, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy

  Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Mar. 2012, IEICE ELECTRONICS EXPRESS, 9(6) (6), 470 - 476, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• 0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme

  Nakata Yohei, Okumura Shunsuke, Kawaguchi Hiroshi, Yoshimoto Masahiko

  This paper presents a novel cache architecture using 7T/14T SRAM, which can improve its reliability with control lines dynamically. Our proposed 14T word-enhancing scheme can enhance its operating margin in word granularity by combining two words in a low-voltage mode. Furthermore, we propose a new testing method that maximizes the efficiency of the 14T word-enhancing scheme. In a 65-nm process, it can reduce the minimum operation voltage (V_min) to 0.5V to a level that is 42% and 21% lower, respectively, than those of a conventional 6T SRAM and a cache word-disable scheme. Measurement results show that the 14T word-enhancing scheme can reduce V_min of the 6T SRAM and 14T dependable modes by 25% and 19%, respectively. The respective dynamic power reductions are 89.2% and 73.9%. The respective total power reductions are 44.8% and 20.9%.

  Information and Media Technologies Editorial Board, 2012, IMT, 7(2) (2), 544 - 555, English


• Architectural study of HOG feature extraction processor for real-time object detection

  Kosuke Mizuno, Yosuke Terachi, Kenta Takagi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2012, IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, 197 - 202, English

  [Refereed]

  International conference proceedings


• Instantaneous Heart Rate Detection Using Short-Time Autocorrelation for Wearable Healthcare Systems

  Nakano, Masanao, Konishi, Toshihiro, Izumi, Shintaro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

  2012, 2012 ANNUAL INTERNATIONAL CONFERENCE OF THE IEEE ENGINEERING IN MEDICINE AND BIOLOGY SOCIETY (EMBC), 2012, 6703 - 6706, English, International magazine

  [Refereed]

  International conference proceedings


• Implementing virtual agent as an interface for smart home voice control

  Shimpei Soda, Masahide Nakamura, Shinsuke Matsumoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  IEEE Computer Society, 2012, Proceedings - Asia-Pacific Software Engineering Conference, APSEC, 1, 342 - 345, English

  [Refereed]

  International conference proceedings


• 読出しビット線リミット機構を備えた40-nm 256-Kb サブ10pJ/access動作8T SRAM

  吉本 秀輔, 寺田 正治, 梅木 洋平, 奥村 俊介, 川澄 篤, 鈴木 利一, 森脇 真一, 宮野 信治, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  This paper presents a novel read-bitline amplitude limiting (RBAL) scheme which suppresses dynamic energy dissipation caused by random variation. In addition, a discharge acceleration (DA) circuit is proposed to decrease delay overhead of RBAL. The proposed scheme improves the active energy dissipation in a read cycle by 22% at the center-center (CC) corner and 25℃. The maximum delay overhead is 32% at the fast-slow (FS) corner and -40℃. The circuits have been implemented using the 40-nm bulk CMOS process. The implemented 256-Kb 8T SRAM works fine with energy dissipation of sub-10 pJ / access from 0.5-0.7V.

  The Institute of Electronics, Information and Communication Engineers, 2012, 信学技報, vol. 112(no. 169) (no. 169), pp. 7 - 12, Japanese

  Scientific journal


• 低電力ディスターブ緩和技術を備えた40nm 12.9pJ/access 8T SRAM

  吉本 秀輔, 寺田 正治, 奥村 俊介, 鈴木 利一, 宮野 信治, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  2012, 信学技報, vol. 112(no. 15) (no. 15), pp. 67 - 72, Japanese

  Scientific journal


• 低エネルギ比較機能を有するDMR応用7T SRAM

  梅木 洋平, 奥村 俊介, 中田 洋平, 柳田 晃司, 鍵山 祐輝, 吉本 秀輔, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  This paper proposes a 7T SRAM that realizes a block-level instantaneous comparison feature. The proposed SRAM is useful for operation results comparison in dual modular redundancy (DMR). The data size that can be instantaneously compared is scalable using the proposed structure. The 1-Mb SRAM comprises 16-Kb blocks in which 8-Kb data can be compared in 130.0ns. The proposed scheme reduces energy consumption in data comparison to 1/418, compared to that of a parallel cyclic redundancy check (CRC) circuit.

  The Institute of Electronics, Information and Communication Engineers, 2012, 信学技報, vol. 112(no. 15) (no. 15), pp. 85 - 90, Japanese

  Scientific journal


• プロセスばらつきを考慮した低電圧動作混合連想度キャッシュ構造

  鄭 晋旭, 中田 洋平, 奥村 俊介, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  2012, 信学技報, vol. 112(no. 170) (no. 170), pp. 1 - 6, Japanese

  Scientific journal


• Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes

  Takashi Matsuda, Shintaro Izumi, Yasuharu Sakai, Takashi Takeuchi, Hidehiro Fujiwara, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

  Jan. 2012, IEICE TRANSACTIONS ON COMMUNICATIONS, E95B(1) (1), 178 - 188, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• 0.5-V 4-MB variation-aware cache architecture using 7T/14T SRAM and its testing scheme

  Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2012, IPSJ Transactions on System LSI Design Methodology, 5, 32 - 43, English

  [Refereed]

  Scientific journal


• Bit Error Rate Estimation in SRAM Considering Temperature Fluctuation

  Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, Shusuke Yoshimoto, Yohei Nakata, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2012, 2012 13TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), pp. 514-517, 516 - 519, English

  [Refereed]

  International conference proceedings


• A 40-nm 256-Kb 0.6-V Operation Half-Select Resilient 8T SRAM with Sequential Writing Technique Enabling 367-mV VDDmin Reduction

  M. Terada, S. Yoshimoto, S. Okumura, T. Suzuki, S. Miyano, H. Kawaguchi, M. Yoshimoto

  2012, 2012 13TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), pp. 487-490, 489 - 492, English

  [Refereed]

  International conference proceedings


• NMOS-Inside 6T SRAM Layout Reducing Neutron-Induced Multiple Cell Upsets

  Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2012, 2012 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), pp. 5B.5.1 - 5, English

  [Refereed]

  International conference proceedings


• A 51-dB SNDR DCO-Based TDC Using Two-Stage Second-Order Noise Shaping

  Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi

  2012, 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), pp. 3170 - 3173, English

  [Refereed]

  International conference proceedings


• Neutron-Induced Soft Error Rate Estimation for SRAM Using PHITS

  Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2012, 2012 IEEE 18TH INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), 138 - 141, English

  [Refereed]

  International conference proceedings


• A variation-aware 0.57-V set-associative cache with mixed associativity using 7T/14T SRAM

  Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2012, 2012 IEEE Faible Tension Faible Consommation, FTFC 2012, English

  [Refereed]

  International conference proceedings


• A 62-dB SNDR Second-Order Gated Ring Oscillator TDC with Two-Stage Dynamic D-Type Flipflops as A Quantization Noise Propagator

  Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi

  2012, 2012 IEEE 10TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), IEEE International New Circuit, 289 - 292, English

  [Refereed]

  International conference proceedings


• A 61-dB SNDR 700 μm 2 second-order all-digital TDC with low-jitter frequency shift oscillators and dynamic flipflops

  Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi

  2012, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 190 - 191, English

  [Refereed]

  International conference proceedings


• A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique

  S. Yoshimoto, M. Terada, S. Okumura, T. Suzuki, S. Miyano, H. Kawaguchi, M. Yoshimoto

  2012, IEICE ELECTRONICS EXPRESS, 9(12) (12), 1023 - 1029, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme

  Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2012, Proceedings of the International Symposium on Low Power Electronics and Design, 85 - 90, English

  [Refereed]

  International conference proceedings


• A 40-nm 168-mW 2.4x-Real-Time VLSI Processor for 60-kWord Continuous Speech Recognition

  Guangji He, Takanobu Sugahara, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2012, 2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), vol. 59(no. 8) (no. 8), pp.1656 - 1666, English

  [Refereed]

  International conference proceedings


• ARCHITECTURAL STUDY OF HOG FEATURE EXTRACTION PROCESSOR FOR REAL-TIME OBJECT DETECTION

  Kosuke Mizuno, Yosuke Terachi, Kenta Takagi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2012, 2012 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), 197 - 202, English

  [Refereed]

  International conference proceedings


• A 40-nm 168-mW 2.4x-Real-Time VLSI Processor for 60-kWord Continuous Speech Recognition

  Guangji He, Takanobu Sugahara, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2012, 2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), pp.1 - 4, English

  [Refereed]

  International conference proceedings


• HANDSFREE VOICE INTERFACE FOR HOME NETWORK SERVICE USING A MICROPHONE ARRAY NETWORK

  Shimpei Soda, Masahide Nakamura, Shinsuke Matsumoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2012, 2012 THIRD INTERNATIONAL CONFERENCE ON NETWORKING AND COMPUTING (ICNC 2012), 195 - 200, English

  [Refereed]

  International conference proceedings


• チップ間ばらつき及びチップ内ばらつきを抑制する基板バイアス制御回路を備えた0.42-V 576-Kb 0.15-um FD-SOI 7T/14T SRAM

  吉本 秀輔, 山口 幸介, 奥村 俊介, 吉本 雅彦, 川口 博

  We propose 7T/14T FD-SOI SRAM with a substrate bias control mechanism. The 14T configuration suppresses intra-die variation in a bit cell. The substrate bias control circuits detect a threshold voltage and automatically change it with the substrate bias. Thereby, the inter-die variation is suppressed. By combining these two schemes, we confirmed that a 576-kb SRAM test chip in a 0.15-μm FD-SOI works at 0.43 V.

  The Institute of Electronics, Information and Communication Engineers, Dec. 2011, 信学技報, vol. 111, no. 352, ICD2011-133(352) (352), 155 - 160, Japanese

  Scientific journal


• A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output

  Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Takashi Takeuchi, Masahiko Yoshimoto, Hiroshi Kawaguchi

  Dec. 2011, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E94A(12) (12), 2701 - 2708, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• 7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory

  Shunsuke Okumura, Yuki Kagiyama, Yohei Nakata, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Dec. 2011, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E94A(12) (12), 2693 - 2700, English

  [Refereed]

  Scientific journal


• A 40nm 144mW VLSI Processor for Realtime 60k Word Continuous Speech Recognition

  SUGAHARA Takanobu, HE Guangji, FUJINAGA Tsuyoshi, MIYAMOTO Yuki, NOGUCHI Hiroki, IZUMI Shintaro, KAWAGUCHi Hiroshi, YOSHIMOTO Masahiko

  We have developed a low power VLSI chip for 60k-word real-time continuous speech recognition based on HMM(Hidden Markov Model). Our implementation includes a cache architecture using the locality of speech recognition, beam pruning using dynamic threshold, two-stage language model searching highly parallel Gaussian Mixture Model (GMM) computation based on mixture level, Variable 50 frames look-ahead scheme and elastic pipeline operation between Viterbi transition and GMM processing. Results show that our implementation achieves 97.94% bandwidth reduction (70.86MB/s) and 78% required frequency reduction (126.5MHz) for 60k-word real-time continuous speech recognition. The test chip has been fabricated in 40nm CMOS technology and occupies 2.2mm X 2.5mm containing 1.9M transistors for logic and 7.8 Mbit on-chip memory. Measured data show 144mW power consumption at 126.5MHz and 1.1V.

  The Institute of Electronics, Information and Communication Engineers, Nov. 2011, Technical report of IEICE. ICD, 111(327) (327), 79 - 84, Japanese

  [Refereed]

  Scientific journal


• A Low-Power Multi Resolution Spectrum Sensing Architecture for a Wireless Sensor Network with Cognitive Radio

  Toshihiro Konishi, Shintaro Izumi, Koh Tsuruda, Hyeokjong Lee, Takashi Takeuchi, Masahiko Yoshimoto, Hiroshi Kawaguchi

  Nov. 2011, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E94A(11) (11), 2287 - 2294, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A 40-nm 0.5-V 20.1-uW/MHz 8T SRAM with Low-Energy Disturb Mitigation Scheme,

  Syusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Jun. 2011, Digest of Technical Papers 2011 Symposium on VLSI Circuits, pp. 72-73, 72 - 73, English

  [Refereed]

  Scientific journal


• VLSI Architecture of GMM Processing and Viterbi Decoder for 60,000-Word Real-Time Continuous Speech Recognition

  Hiroki Noguchi, Kazuo Miura, Tsuyoshi Fujinaga, Takanobu Sugahara, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Apr. 2011, IEICE TRANSACTIONS ON ELECTRONICS, E94C(4) (4), 458 - 467, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition

  Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Tsuyoshi Fujinaga, Shintaro Izumi, Yasuo Ariki, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Apr. 2011, IEICE TRANSACTIONS ON ELECTRONICS, E94C(4) (4), 448 - 457, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• Data-Intensive Sound Acquisition System with Large-scale Microphone Array

  Noguchi Hiroki, Takagi Tomoya, Kugata Koji, Izumi Shintaro, Yoshimoto Masahiko, Kawaguchi Hiroshi

  We propose a microphone array network that realizes ubiquitous sound acquisition. Several nodes with 16 microphones are connected to form a novel huge sound acquisition system, which carries out voice activity detection (VAD), sound source localization, and sound enhancement. The three operations are distributed among nodes. Using the distributed network, we produce a low-traffic data-intensive array network. To manage node power consumption, VAD is implemented. The system uses little power when speech is not active. For sound localization, a network-connected multiple signal classification (MUSIC) algorithm is used. The experimental result of the sound-source enhancement shows a signal-noise ratio (SNR) improvement of 7.75dB using 112 microphones. Network traffic is reduced by 99.11% when using 1,024 microphones.

  Information and Media Technologies Editorial Board, 2011, Information and Media Technologies, 6(2) (2), 307 - 318, English


• Design Choice in 45-nm Dual-Port SRAM — 8T, 10T Single End, and 10T Differential

  Noguchi Hiroki, Iguchi Yusuke, Fujiwara Hidehiro, Okumura Shunsuke, Nii Koji, Kawaguchi Hiroshi, Yoshimoto Masahiko

  As process technology is scaled down, a large-capacity SRAM will be used. Its power must be lowered. The Vth variation of the deep-submicron process affects the SRAM operation and its power. This paper compares the macro area, readout power, and operating frequency among dual-port SRAMs: an 8T SRAM, 10T single-end SRAM, and 10T differential SRAM considering the multi-media applications. The 8T SRAM has the lowest transistor count, and is the most area efficient. However, the readout power becomes large and the access time increases because of peripheral circuits. The 10T single-end SRAM, in which a dedicated inverter and transmission gate are appended as a single-end read port, can reduce the readout power by 74%. The operating frequency is improved by 195%, over the 8T SRAM. However, the 10T differential SRAM can operate fastest (256% faster than the 8T SRAM) because its small differential voltage of 50mV achieves high-speed operation. In terms of the power efficiency, however, the readout current is affected by the Vth variation and the timing of sense cannot be optimized singularly among all memory cells in a 45-nm technology. The readout power remains 34% lower than that of the 8T SRAM (33% higher than the 10T single-end SRAM); even its operating voltage is the lowest of the three. The 10T single-end SRAM always consumes less readout power than the 8T or 10T differential SRAM.

  Information and Media Technologies Editorial Board, 2011, Information and Media Technologies, 6(2) (2), 296 - 306, English


• A 40-nm 640-μm2 45-dB opampless all-digital second-order MASH ΔΣ ADC

  Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi

  2011, Proceedings - IEEE International Symposium on Circuits and Systems, 518 - 521, English

  [Refereed]

  International conference proceedings


• Design choice in 45-nm dual-port SRAM - 8T, 10T single end, and 10T differential

  Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2011, IPSJ Transactions on System LSI Design Methodology, 4, 80 - 90, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• 0.42-V 576-kb 0.15-um FD-SOI SRAM with 7T/14T Bit Cells and Substrate Bias Control Circuits for Intra-Die and Inter-Die Variability Compensation

  K. Yamaguchi, S. Okumura, M. Yoshimoto, H. Kawaguchi

  We propose 7T/14T FD-SOI SRAM with a substrate bias control mechanism. The 14T configuration suppresses intra-die variation in a bit cell. The substrate bias control circuits detect a threshold voltage and automatically change it with the substrate bias. Thereby, the inter-die variation is suppressed. By combining these two schemes, we confirmed that a 576-kb SRAM test chip in a 0.15-μm FD-SOI works at 0.43 V.

  The Institute of Electronics, Information and Communication Engineers, Jan. 2011, Proceedings of 7th Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EUROSOI), pp. 37-38(352) (352), 155 - 160, English

  [Refereed]

  Scientific journal


• Data-intensive sound acquisition system with large-scale microphone array

  Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi

  Information Processing Society of Japan, 2011, Journal of Information Processing, 19, 129 - 140, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• 0.45-V Operating V-t-Variation Tolerant 9T/18T Dual-Port SRAM

  Hiroki Noguchi, Shunsuke Okumura, Tomoya Takagi, Koji Kugata, Masahiko Yoshimoto, Hiroshi Kawaguchi

  2011, 2011 12TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), pp. 219-222, 225 - 228, English

  [Refereed]

  International conference proceedings


• Bit Error and Soft Error Hardenable 7T/14T SRAM with 150-nm FD-SOI Process

  Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Kosuke Yamaguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi

  2011, 2011 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), pp. 876-881, English

  [Refereed]

  International conference proceedings


• Positioning system for mobile terminals using a microphone array network as an intuitive interface

  Shimpei Soda, Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi

  2011, 2011 Joint Workshop on Hands-free Speech Communication and Microphone Arrays, HSCMA'11, 155 - 156, English

  [Refereed]

  International conference proceedings


• A 40-nm 640-mu m(2) 45-dB Opampless All-Digital Second-Order MASH Delta Sigma ADC

  Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi

  2011, 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), pp. 518-521, 518 - 521, English

  [Refereed]

  International conference proceedings


• Model-based fault injection for failure effect analysis evaluation of dependable SRAM for vehicle control units

  Yohei Nakata, Yasuhiro Ito, Yasuo Sugure, Shigeru Oho, Yusuke Takeuchi, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2011, Proceedings of the International Conference on Dependable Systems and Networks, pp. 91-96, 91 - 96, English

  [Refereed]

  International conference proceedings


• Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure

  S. Yoshimoto, T. Amashita, D. Kozuwa, T. Takata, M. Yoshimura, Y. Matsunaga, H. Yasuura, H. Kawaguchi, M. Yoshimoto

  2011, 2011 IEEE 17TH INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), pp.151-156, English

  [Refereed]

  International conference proceedings


• Data Aggregation Protocol for Multiple Sound Sources Acquisition with Microphone Array Network

  Shintaro Izumi, Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shimpei Soda, Masahiko Yoshimoto, Hiroshi Kawaguchi

  2011, 2011 20TH INTERNATIONAL CONFERENCE ON COMPUTER COMMUNICATIONS AND NETWORKS (ICCCN), English

  [Refereed]

  International conference proceedings


• A process-variation-adaptive network-on-chip with variable-cycle routers

  Yohei Nakata, Yukihiro Takeuchi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2011, Proceedings - 2011 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011, pp. 801-804, 801 - 804, English

  [Refereed]

  International conference proceedings


• Low-Power Block-Level Instantaneous Comparison 7T SRAM for Dual Modular Redundancy

  Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2011, 2011 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), pp. 1-4, English

  [Refereed]

  International conference proceedings


• A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10-19

  Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2011, European Solid-State Circuits Conference, pp. 527-530, 527 - 530, English

  [Refereed]

  International conference proceedings


• A 75-variable MIQP solver processor for real-time autonomous robot control

  Masanori Nishino, Hiroki Noguchi, Yusuke Shimai, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2011, 2011 IEEE/SICE International Symposium on System Integration, SII 2011, pp. 469-472, 469 - 472, English

  [Refereed]

  International conference proceedings


• 256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V

  Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2011, 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011, pp. 524-527, 524 - 527, English

  [Refereed]

  International conference proceedings


• Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure

  S. Yoshimoto, T. Amashita, D. Kozuwa, T. Takata, M. Yoshimura, Y. Matsunaga, H. Yasuura, H. Kawaguchi, M. Yoshimoto

  2011, 2011 IEEE 17TH INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), Vol. E95-C(No. 10,) (No. 10,), pp. 1675 - 1681, English

  [Refereed]

  International conference proceedings

  Link to Kobe Univ. Repository (Kernel)


• システムレベル故障注入技術を用いたディペ ンダブルプロセッサアーキテクチャの評価・ 検証

  Y. Nakata, ITO Hiroaki, SUGURE Yasuo, OHO Shigeru, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Nov. 2010, 電子情報通信学会技術研究報告, vol. 110, no. 317, VLD2010-74,, Japanese

  Scientific journal


• The Area Criteria of 6T and 8T SRAM Cells,

  S. Yoshimoto, S. Okumura, H. Kawaguchi, M. Yoshimoto

  Nov. 2010, EEE/ACM Workshop on Variability Modeling and Characterization (VMC), p.4, English

  Scientific journal


• ブロック一括コピー機能を有する7T SRAM

  S. Okumura, Y. Kagiyama, S. Yoshimoto, K. Yamaguchi, Y. Nakata, H. Kawaguchi, M. Yoshimoto

  Oct. 2010, 電子情報通信学会CEATEC JAPAN 2010 連携企画研究報告 （Digital Harmony を支えるプロ セッサとDSP，画像処理の最先 端）, pp.49-54 (2010), Japanese

  Scientific journal


• ネットワーク型マイクロホンアレイ間のデー タ集約による音声信号ビームフォーミング

  IZUMI Shintaro, NOGUCHI Hiroki, TAKAGI Tomoya, KUGATA Koji, SODA Shinpei, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi

  Oct. 2010, 電子情報通信学会CEATEC JAPAN 2010 連携企画研究報告 （Digital Harmony を支えるプロ セッサとDSP、画像処理の最先 端）, pp.95-100 (2010)(217(IE2010 71-86)) (217(IE2010 71-86)), Japanese

  Scientific journal


• A power-variation model fo r sensor node and the impact against life time of wireless sensor networks

  Takashi Matsuda, Takashi Takeuchi, Takefumi Aonishi, Masumi Ichien, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

  Network protocols for wireless sensor networks should be evaluated in terms of life time in a whole system. There exists power variation node due to the manufacturing variation. In this paper, we develop a power model, in which we consider threshold-voltage variation. We implement it to QualNet in order to evaluate the impact against a life time. The simulation results show that the conventional model has overestimated the life time longer than our model when nodes are randomly deployed. In addition, the network life time is extended by 19.3% compared with the conventional model by an optimum deployment.

  The Institute of Electronics, Information and Communication Engineers(IEICE), Mar. 2010, IEICE Electron. Express, Vol. 7, No. 3, pp.197-202(3) (3), 197 - 202, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A 58-mu W Single-Chip Sensor Node Processor with Communication Centric Design

  Shintaro Izumi, Takashi Takeuchi, Takashi Matsuda, Hyeokjong Lee, Toshihiro Konishi, Koh Tsuruda, Yasuharu Sakai, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

  Mar. 2010, IEICE TRANSACTIONS ON ELECTRONICS, E93C(3) (3), 261 - 269, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A 284-mu W 1.85-GHz 20-Phase Oscillator Using Transfer Gate Phase Couplers

  Hyeokjong Lee, Takashi Takeuchi, Masahiko Yoshimoto, Hiroshi Kawaguchi

  2010, 2010 ASIA-PACIFIC MICROWAVE CONFERENCE, 594 - 597, English

  [Refereed]

  International conference proceedings


• Intelligent Ubiquitous Sensor Network for Sound Acquisition

  Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi

  2010, 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 1414 - 1417, English

  [Refereed]

  International conference proceedings


• MICROPHONE ARRAY NETWORK FOR UBIQUITOUS SOUND ACQUISITION

  Tomoya Takagi, Hiroki Noguchi, Koji Kugata, Masahiko Yoshimoto, Hiroshi Kawaguchi

  2010, 2010 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, pp. 1474-1477, 1474 - 1477, English

  [Refereed]

  International conference proceedings


• Live Demonstration: Intelligent Ubiquitous Sensor Network for Sound Acquisition

  Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi

  2010, 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, p. 1413, 1413 - 1413, English

  [Refereed]

  International conference proceedings


• Live Demonstration: Intelligent Ubiquitous Sensor Network for Sound Acquisition

  Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi

  2010, 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, pp. 1414-1417, 1413 - 1413, English

  [Refereed]

  International conference proceedings


• A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks

  Takashi Takeuchi, Shinji Mikami, Hyeokjong Lee, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

  Jun. 2009, IEICE TRANSACTIONS ON ELECTRONICS, E92C(6) (6), 815 - 821, English

  [Refereed]

  Scientific journal


• A Dependable SRAM with 7T/14T Memory Cells

  Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Apr. 2009, IEICE TRANSACTIONS ON ELECTRONICS, E92C(4) (4), 423 - 432, English

  [Refereed]

  Scientific journal


• 低消費電力センサノードVLSIのための時刻同期型MACプロトコルの研究

  IZUMI Shintaro, MATSUDA Takashi, TAKEUCHI Takashi, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  Mar. 2009, 電子情報通信学会技術研究報告(信学技報), vol. 108, no. 457, NS2008-174,(457(NS2008 143-233)) (457(NS2008 143-233)), Japanese

  International conference proceedings


• 7T/14TディペンダブルSRAMおよびそのセル配置構造

  FUJIWARA Hidehiro, OKUMURA Syunsuke, IGUCHI Yusuke, NOGUCHI Hiroki, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Mar. 2009, 電子情報通信学会総合大会, 0, Japanese

  International conference proceedings


• A low-power portable H.264/AVC decoder using elastic pipeline

  Yoshinori Sakata, Kentaro Kawakami, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2009, Lecture Notes in Electrical Engineering, 28(2) (2), 25 - 32, English

  [Refereed]

  International conference proceedings


• Low-power control techniques for silicon and organic circuits with array structures

  Hiroshi Kawaguchi

  2009, Proceedings of the IEEE International Conference on Control Applications, 326 - 333, English

  [Refereed]

  International conference proceedings


• A 58-mu W Single-Chip Sensor Node Processor Using Synchronous MAC Protocol

  Takeuchi, Takashi, Izumi, Shintaro, Matsuda, Takashi, Lee, Hyeokjong, Otake, Yu, Konishi, Toshihiro, Tsuruda, Koh, Sakai, Yasuharu, Fujiwara, Hidehiro, Ohta, Chikara, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

  2009, 2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 290 - 291, English

  [Refereed]

  International conference proceedings


• A 7T/14T Dependable SRAM and Its Array Structure to Avoid Half Selection

  Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2009, 22ND INTERNATIONAL CONFERENCE ON VLSI DESIGN HELD JOINTLY WITH 8TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS, pp. 295-300, 295 - 300, English

  [Refereed]

  International conference proceedings


• A 0.56-V 128kb 10T SRAM Using Column Line Assist (CLA) Scheme

  Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2009, ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2, 0, 659 - +, English

  [Refereed]

  International conference proceedings


• A 58-μW Single-Chip Sensor Node Processor Using Synchronous MAC Protocol

  Izumi Shintaro, Yoshimoto Masahiko, Takeuchi Takashi, Matsuda Takashi, Lee Hyeokjong, Konishi Toshihiro, Tsuruda Koh, Sakai Yasuharu, Kawaguchi Hiroshi, Ohta Chikara

  In this paper, we propose a single-chip ultra low-power sensor node processor with a synchronous media access control (MAC). It is comprised of a transceiver, i8051 micro processor, and dedicated MAC processor. The test chip occupies 3x3mm^2 in a 180-nm CMOS process, including 1.38M transistors. The power is 58.0μW under a network environment.

  The Institute of Image Information and Television Engineers, 2009, ITE Technical Report, 33(0) (0), 141 - 145, Japanese

  [Refereed]

  Scientific journal


• A 60-dB Image Rejection Filter Using Delta-Sigma Modulation and Frequency Shifting

  Toshihiro Konishi, Koh Tsuruda, Shintaro Izumi, Hyeokjong Lee, Hidehiro Fujiwara, Takashi Takeuchi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2009, 2009 IEEE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUTERS AND SIGNAL PROCESSING, VOLS 1 AND 2, pp. 565-570, 565 - 570, English

  [Refereed]

  International conference proceedings


• Parallelized Viterbi Processor for 5,000-Word Large-Vocabulary Real-Time Continuous Speech Recognition FPGA System

  Tsuyoshi Fujinaga, Kazuo Miura, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2009, INTERSPEECH 2009: 10TH ANNUAL CONFERENCE OF THE INTERNATIONAL SPEECH COMMUNICATION ASSOCIATION 2009, VOLS 1-5, pp.1483-1486, 1495 - 1498, English

  [Refereed]

  International conference proceedings


• AN ULTRA-LOW-POWER VAD HARDWARE IMPLEMENTATION FOR INTELLIGENT UBIQUITOUS SENSOR NETWORKS

  Hiroki Noguchi, Tomoya Takagi, Masahiko Yoshimoto, Hiroshi Kawaguchi

  2009, SIPS: 2009 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS, pp. 214-219, 214 - 219, English

  [Refereed]

  International conference proceedings


• A Single-Chip Sensor Node LSI with Synchronous MAC Protocol and Divided Data-Buffer SRAM

  Takashi Takeuchi, Shintaro Izumi, Takashi Matsuda, Hyeokjong Lee, Toshihiro Konishi, Koh Tsuruda, Yasuhiro Sakai, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

  2009, 2009 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2009), 202 - 207, English

  [Refereed]

  International conference proceedings


• チップ間ばらつき 補正機能を有する基板バイアス制御を用いた0.42V動作486kb FD-SOI SRAM

  山口 幸介, 藤原 英弘, 竹内 隆, 大竹 優, 吉本 雅彦, 川口 博

  We propose a novel substrate-bias control scheme for FD-SOI SRAM that suppresses inter-die variability and achieves low-voltage operation. Substrate-bias control circuits automatically detect an inter-die threshold-voltage variation, and then maximize read/write margins of memory cells. We confirmed that a 486-kb SRAM operates at 0.42V, in which an FS/SF corners can be compensated as much as 0.14V or more.

  The Institute of Electronics, Information and Communication Engineers, Dec. 2008, 電子情 報通信学会技術研究報告(信学技報), vol. 108, no. 347, ICD2008-127(347) (347), 131 - 136, Japanese

  Scientific journal


• Cross-Layer Design for Low-Power Wireless Sensor Node Using Wave Clock

  Takashi Takeuchi, Yu Otake, Masumi Ichien, Akihiro Gion, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

  Nov. 2008, IEICE TRANSACTIONS ON COMMUNICATIONS, E91B(11) (11), 3480 - 3488, English

  [Refereed]

  Scientific journal


• Counter-Based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks

  Shintaro Izumi, Takashi Takeuchi, Takashi Matsuda, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

  Nov. 2008, IEICE TRANSACTIONS ON COMMUNICATIONS, E91B(11) (11), 3489 - 3498, English

  [Refereed]

  Scientific journal


• 全整数計画問題ソルバーのFPGA実装,

  TANI Junichi, NOGUCHI Hiroki, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Oct. 2008, 情報処理学会関西支部大会,, D-05, Japanese

  International conference proceedings


• ワイヤレスセンサネットワークのためのデータ集約を考慮した部分起動メモリの電力削減効果に関する研究

  SAKAI Yasuharu, MATSUDA Takashi, IZUMI Shintaro, TAKEUCHI Takashi, FUJIWARA Hidehiro, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  Sep. 2008, 電子情報通信学会ソサイエティ大会, B-20-10, pp. 346, Japanese

  International conference proceedings


• Novel video memory reduces 45% of bitline power using majority logic and data-bit reordering

  Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Jun. 2008, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 16(6) (6), 620 - 627, English

  [Refereed]

  Scientific journal


• 高信頼性モードと高速アクセスモードを有するディペンダブルSRAM

  OKUMURA Syunsuke, FUJIWARA Hidehiro, IGUCHI Yusuke, NOGUCHI Hiroki, MORITA Yasuhiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  We propose a novel dependable SRAM with 7T memory cell pair, and introduce a new concept, "quality of a bit (QoB)" for it. The proposed SRAM has three modes: a typical mode, high-speed mode, and dependable mode, in which the QoB is scalable. That is, the area, speed, reliability, and/or power of one-bit information can be controlled. In the typical mode, assignment of information is as usual as one memory cell has one bit. On the other hand, in the high-speed or dependable mode, one-bit information is stored in two memory cells, which boosts the speed or increases the reliability. In the high speed mode, the cell current is increased by 142%, and bitline discharge time is reduced by 66.3%. Furthermore, in dependable mode, Bit error rate (BER) in proposed SRAM is improved by 2.5×10^<-2>. Compared with the conventional 6T memory cell, the respective area overheads are 30% and 12%, in the nMOS and pMOS additional cases.

  The Institute of Electronics, Information and Communication Engineers, May 2008, 電子情報通信学会技術研究報告,, VLD2008-12, pp.31-36(23) (23), 31 - 36, Japanese

  International conference proceedings


• サブ 100mW H.264 AVC MP@L4.1 HDTV 解像度対応整数画素精度動き検出プロセッサコア

  MIZUNO Kosuke, MIYAKOSHI Junichi, MURACHI Yuichiro, HAMAMOTO Masaki, IINUMA Takahiro, ISHIHARA Tomokazu, YIN Fang, LEE Jangchung, KAMINO Tetsuya, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  As digital terrestrial broadcasting prevails more, it is more important to develop techniques for compressing images of high resolution. This work focused on integer-pel motion estimation (IME) occupying more 90% workload in H.264/AVC encoder for HDTV resolution and aimed to realize a low power and high picture-quality IME processor.

  The Institute of Electronics, Information and Communication Engineers, May 2008, 電子情報通信学会技術研究報告, VLD2008-12, pp.25-30(23) (23), 25 - 30, Japanese

  International conference proceedings


• A sub 100 mW H.264 MP@L4.1 integer-pel motion estimation processor core for MBAFF encoding with reconfigurable ring-connected systolic array and segmentation-free, rectangle-access search-window buffer

  Yuichiro Murachi, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Apr. 2008, IEICE TRANSACTIONS ON ELECTRONICS, E91C(4) (4), 465 - 478, English

  [Refereed]

  Scientific journal


• A 10T non-precharge two-port SRAM reducing readout power for video processing

  Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Apr. 2008, IEICE TRANSACTIONS ON ELECTRONICS, E91C(4) (4), 543 - 552, English

  [Refereed]

  Scientific journal


• An H.264/AVC MP@L4.1 quarter-pel motion estimation processor VLSI for real-time MBAFF encoding

  Kosuke Mizuno, Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2008, Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, 1179 - 1182, English

  [Refereed]

  International conference proceedings


• A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding

  Yuichiro Murachi, Kosuke Mizuno, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2008, Proceedings - IEEE International Symposium on Circuits and Systems, 848 - 851, English

  [Refereed]

  International conference proceedings


• A VGA 30-fps realtime optical-flow processor core for moving picture recognition

  Yuichiro Murachi, Yuki Fukuyama, Ryo Yamamoto, Junichi Miyakoshi, Hiroshi Kawaguchi, Hajime Ishihara, Masayuki Miyama, Yoshio Matsuda, Masahiko Yoshimoto

  Institute of Electronics, Information and Communication, Engineers, IEICE, 2008, IEICE Transactions on Electronics, E91-C(4) (4), 457 - 464, English

  [Refereed]

  Scientific journal


• Quality of a bit (QoB): A new concept in dependable SRAM

  Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2008, ISQED 2008: PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, pp. 98-102, 98 - 102, English

  [Refereed]

  International conference proceedings


• Impact of divided static random access memory considering data aggregation for wireless sensor networks

  Takashi Matsuda, Shintaro Izumi, Takashi Takeuchi, Hidehiro Fujiwara, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

  2008, 2008 7TH ASIA-PACIFIC SYMPOSIUM ON INFORMATION AND TELECOMMUNICATION TECHNOLOGIES, pp. 130-134, 115 - +, English

  [Refereed]

  International conference proceedings


• Hop Count Aware broadcast algorithm with Random Assessment Delay Extension for wireless sensor networks

  Shintaro Izumi, Takashi Matsuda, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

  2008, 2008 7TH ASIA-PACIFIC SYMPOSIUM ON INFORMATION AND TELECOMMUNICATION TECHNOLOGIES, pp. 30-35, 207 - +, English

  [Refereed]

  International conference proceedings


• A power-efficient SRAM core architecture with segmentation-free and rectangular accessibility for super-parallel video processing

  Yuichiro Murachi, Tetsuya Kamino, Junichi Miyakoshi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2008, 2008 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM, pp. 63-66, 63 - +, English

  [Refereed]

  International conference proceedings


• Which is the best dual-port SRAM in 45-nm process technology? 8T, 10T single end, and 10T differential

  Hiroki Noguchi, Shunsuke Okumura, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2008, 2008 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS, pp.55-58,, 55 - 58, English

  [Refereed]

  International conference proceedings


• A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding

  Yuichiro Murachi, Kosuke Mizuno, Junichi Miyakoshi, Masaki Harnarnoto, Takahiro Linurna, Tornokazu Ishibara, Fang Yin, Jangchung Lee, Tetsuya Karnino, Hiroshi Kawaguchi, Masahiko Yoshirnoto

  2008, PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 0, 848 - 851, English

  [Refereed]

  International conference proceedings


• Variable bandwidth digital bandpass filter for cognitive radio

  Tsuruda Koh, Izumi Shintaro, Lee Hyeokjong, Takeuchi Takashi, Kawaguchi Hiroshi, Yoshimoto Masahiko

  本論文ではコグニティブ無線向け可変帯域ディジタルBPF(Band-Pass Filter)を用いたベースバンドプロセッサを提案する.BPFにDA(Distributed Arithmetic)アルゴリズムを適応することで,内蔵するSRAMのデータを書き換えるだけでBPFの特性(チャネル中心周波数とバンド幅)を変化させることが可能となる.試作したベースバンドプロセッサではバンド幅を40kHzから240kHzまで10kHz単位で変化させることが可能である.CMOS 180nmプロセスで設計し,電源電圧1.8Vで消費電力は13.5mWであった.

  The Institute of Image Information and Television Engineers, 2008, ITE Technical Report, 32(0) (0), 137 - 141, Japanese

  International conference proceedings


• An Inter-Die Variability Compensation Scheme for 0.42-V 486-kb FD-SOI SRAM using Substrate Control

  Hidehiro Fujiwara, Takashi Takeuchi, Yu Otake, Masahiko Yoshimoto, Hiroshi Kawaguchi

  2008, 2008 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, pp. 93-94, 93 - 94, English

  [Refereed]

  International conference proceedings


• Memory Bandwidth Gaussian Mixture Model (GMM) Processor for 20,000-Word Real-Time Speech Recognition FPGA System

  Kazuo Miura, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2008, PROCEEDINGS OF THE 2008 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY, 0, 341 - 344, English

  [Refereed]

  International conference proceedings


• A Flexible Baseband Processor with Multi-Resolution Spectrum-Sensing Functionality

  Koh Tsuruda, Shintaro Izumi, Hyeokjong Lee, Takashi Takeuchi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2008, 2008 INTERNATIONAL SYMPOSIUM ON INFORMATION THEORY AND ITS APPLICATIONS, VOLS 1-3, pp. 1423-1428, 1422 - 1427, English

  [Refereed]

  International conference proceedings


• Low-Traffic and Low-Power Data-Intensive Sound Acquisition with Perfect Aggregation Specialized for Microphone Array Networks

  Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Masahiko Yoshimoto, Hiroshi Kawaguchi

  2008, 2010 FOURTH INTERNATIONAL CONFERENCE ON SENSOR TECHNOLOGIES AND APPLICATIONS (SENSORCOMM), pp. 157-162, 157 - 162, English

  [Refereed]

  International conference proceedings


• 超並列画像処理応用 任意位置任意サイズ矩形画素の1サイクルアクセスが可能なブロックアクセスメモリアーキテクチャ

  MURACHI Yuichiro, MIYAKOSHI Junichi, KAMINO Tetsuya, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  映像情報メディア学会, Dec. 2007, 電子情報通信学会技術研究報告,ICD2007-128, Vol.107,No.382,pp.47-52(63) (63), 47 - 52, Japanese

  International conference proceedings


• Data transmission scheduling based on RTS/CTS exchange for periodic data gathering sensor networks

  Takashi Matsuda, Masumi Ichien, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

  Dec. 2007, IEICE TRANSACTIONS ON COMMUNICATIONS, E90B(12) (12), 3410 - 3418, English

  [Refereed]

  Scientific journal


• Area comparison between 6T and 8T SRAM cells in dual-V-dd scheme and DVS scheme

  Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Dec. 2007, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E90A(12) (12), 2695 - 2702, English

  [Refereed]

  Scientific journal


• Stacked-chip implementation of on-chip buck converter for distributed power supply system in sips

  Kohei Onizuka, Kenichi Inagaki, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai

  Nov. 2007, IEEE Journal of Solid-State Circuits, 42(11) (11), 2404 - 2410, English

  [Refereed]

  International conference proceedings


• Area optimization in 6T and 8T SRAM cells considering V-th variation in future processes

  Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Oct. 2007, IEICE TRANSACTIONS ON ELECTRONICS, E90C(10) (10), 1949 - 1956, English

  [Refereed]

  Scientific journal


• An elastic pipeline architecture for dynamic voltage scaling and its application to low-power portable H.264/AVC decoder with embedded frame buffer SRAM

  SAKATA Yoshinori, KAWAKAMI Kentaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Sep. 2007, EUROPEAN COMPUTING CONFERENCE, pp.00-00, English

  [Refereed]

  International conference proceedings


• DVS環境下での小面積・低電圧動作8T SRAMの設計

  MORITA Yasuhiro, FUJIWARA Hidehiro, NOGUCHI Hiroki, IGUCHI Yusuke, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Aug. 2007, 電子情報通信学会技術研究報告,ICD2007-95, Vol.107,No.195,pp.139-144, Japanese

  International conference proceedings


• 電源電圧と周波数の動的制御によるH.264/AVC デコーダの低消費電力化

  SAKATA Yoshinori, 川上 健太郎, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  映像情報メディア学会, Jul. 2007, 電子情報通信学会技術研究報告,ICD2007-52, Vol.107,No.163,pp.89-94(34) (34), 89 - 94, Japanese

  International conference proceedings


• 長波帯標準電波を用いた低電力センサーノードのための垂直統合設計

  OTAKE Yu, ICHIEN Masumi, TAKEUCHI Takashi, GION Akihiro, MIKAMI Shinji, FUJIWARA Hidehiro, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  Jul. 2007, 電子情報通信学会技術研究報告,ICD2007-49, Vol.107,No.163,pp.71-76, Japanese

  International conference proceedings


• ワイヤレスセンサーネットワーク応用キャリアセンス機能を持つ433MHz帯、356-uW電圧増幅器

  LEE Hyeokjong, MIKAMI Shinji, TAKEUCHI Takashi, ICHIEN Masumi, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  Jul. 2007, 電子情報通信学会技術研究報告,ICD2007-50, Vol.107,No.163,pp.77-82, Japanese

  International conference proceedings


• ビット線電力を74%削減する動画像処理応用 10T 非プリチャージ 2-port SRAMの設計

  OKUMURA Syunsuke, NOGUCHI Hiroki, IGUCHI Yusuke, FUJIWARA Hidehiro, MORITA Yasuhiro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jul. 2007, 電子情報通信学会技術研究報告,ICD2007-53, Vol.107,No.163,pp.95-100, Japanese

  International conference proceedings


• ビット線の電力を削減する実時間動画像処理応用2-port SRAM

  FUJIWARA Hidehiro, NII Koji, NOGUCHI Hiroki, MIYAKOSHI Junichi, MURACHI Yuichiro, MORITA Yasuhiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  We propose a low-power two-port SRAM for real-time video processing that exploits statistical similarity in images. To minimize discharge power on a read bitline in the precharge scheme, a majority-logic circuit decides if input data should be inverted in a write cycle, so that "1"s are in the majority. Write-in data are reordered into digit groups from the most significant bit group to the least significant bit group, and then a flag bit is appended to each group. If the number of "0"s in a group is more than that of "1"s, the input data are inverted by the majority logic. The majority-logic circuit reduces needless discharges on the read bitlines, and thus saves power in a read operation. The measurement result in a 68-kb SRAM fabricated in a 90-nm process demonstrates that thte 45% power saving on the read bitline is achieved as an H.264 reconstructed-image memory. The speed and area overhead are 4% and 7%, respectively.

  The Institute of Electronics, Information and Communication Engineers, Apr. 2007, 電子情報通信学会技術研究報告,ICD2007-7, Vol.107,No.1,pp.35-40(1) (1), 35 - 40, Japanese

  International conference proceedings


• Wireless power transmission sheet with organic FETs and plastic MEMS switches

  M. Takamiya, T. Sekitani, Y. Miyamoto, Y. Noguchi, H. Kawaguchi, T. Someya, T. Sakurai

  2007, IDW '07 - Proceedings of the 14th International Display Workshops, 1, 95 - 98, English

  International conference proceedings


• Sheet-type Braille displays by integrating organic field-effect transistors and polymeric actuators

  Hiroshi Kawaguchi

  2007, IEEE Transactions on Electron Devices

  Scientific journal


• A VGA 30-fps optical-flow processor core based on Pyramidal Lucas and Kanade algorithm

  Hajime Ishihara, Masayuki Miyama, Yoshio Matsuda, Yuichiro Murachi, Yuki Fukuyama, Ryo Yamamoto, Junichi Miyakoshi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  IEEE Computer Society, 2007, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, 188 - 191, English

  [Refereed]

  International conference proceedings


• Closed-form expressions for crosstalk noise and worst-case delay on capacitively coupled distributed RC lines

  Hiroshi Kawaguchi, Danardono Dwi Antono, Takayasu Sakurai

  Institute of Electronics, Information and Communication, Engineers, IEICE, 2007, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E90-A(12) (12), 2669 - 2681, English

  [Refereed]

  Scientific journal


• A design methodology of chip-to-chip wireless power transmission system

  Kohei Onizuka, Makoto Takamiya, Hiroshi Kawaguchi, Takayasu Sakurai

  2007, Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT, 143 - 146, English

  [Refereed]

  International conference proceedings


• Design for mixed circuits of organic FETs and plastic MEMS switches for wireless power transmission sheet

  Makoto Takamiya, Tsuyoshi Sekitani, Yoshio Miyamoto, Yoshiaki Noguchi, Hiroshi Kawaguchi, Takao Someya, Takayasu Sakurai

  2007, Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT, 168 - 171, English

  [Refereed]

  International conference proceedings


• Half VDD clock-swing flip-flop with reduced contention for up to 60% power saving in clock distribution

  David Levacq, Muhammad Yazid, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai

  2007, ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference, 190 - 193, English

  [Refereed]

  International conference proceedings


• Design solutions for a multi-object wireless power transmission sheet based on plastic switches

  Makoto Takamiya, Tsuyoshi Sekitani, Yoshio Miyamoto, Yoshiaki Noguchi, Hiroshi Kawaguchi, Takao Someya, Takayasu Sakurai

  2007, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 355 - 609, English

  [Refereed]

  International conference proceedings


• A self-alignment row-by-row variable-VDD scheme reducing 90 of active-leakage power in SRAM's

  Fayez Robert Saliba, Hiroshi Kawaguchi, Takayasu Sakurai

  Institute of Electronics, Information and Communication, Engineers, IEICE, 2007, IEICE Transactions on Electronics, E90-C(4) (4), 743 - 748, English

  [Refereed]

  Scientific journal


• Data transmission scheduling based on RTS/CTS exchange for periodic data gathering sensor networks

  Takashi Matsuda, Masumi Ichien, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

  Institute of Electronics, Information and Communication, Engineers, IEICE, 2007, IEICE Transactions on Communications, E90-B(12) (12), 3410 - 3418, English

  [Refereed]

  Scientific journal


• Power and memory bandwidth reduction of an H.264/AVC HDTV decoder LSI with elastic pipeline architecture

  Kentaro Kawakami, Mitsuhiko Kuroda, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2007, PROCEEDINGS OF THE ASP-DAC 2007, pp.292-297, 292 - +, English

  [Refereed]

  International conference proceedings


• An organic FET SRAM with back gate to increase static noise margin and its application to Braille sheet display

  Makoto Takamiya, Tsuyoshi Sekitani, Yusaku Kato, Hiroshi Kawaguchi, Takao Someya, Takayasu Sakurai

  Jan. 2007, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 42(1) (1), 93 - 100, English

  [Refereed]

  Scientific journal


• An efficiency degradation model of power amplifier and the impact against transmission power control for wireless sensor networks

  Shinji Mikami, Takashi Takeuchi, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

  2007, Proceedings - 2007 IEEE Radio and Wireless Symposium, RWS, pp.447-450, 447 - 450, English

  [Refereed]

  International conference proceedings


• A 356-μW, 433-MHz, rail-to-rail voltage amplifier with carrier sensing function for wireless sensor networks

  Shinji Mikami, Masumi Ichien, Takashi Takeuchi, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

  2007, Proceedings - 2007 IEEE Radio and Wireless Symposium, RWS, pp.451-454, 451 - 454, English

  [Refereed]

  International conference proceedings


• A 10T non-precharge two-port SRAM for 74% power reduction in video processing

  Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2007, IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS, pp.107-112, 107 - +, English

  [Refereed]

  International conference proceedings


• An area-conscious low-voltage-oriented 8T-SRAM design under DVS environment

  Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2007, 2007 Symposium on VLSI Circuits, Digest of Technical Papers, pp.256-257, 256 - 257, English

  [Refereed]

  International conference proceedings


• Multipath routing using Isochronous medium access control with multi wakeup period for wireless sensor networks

  Takashi Matsuda, Takafumi Aonishi, Takashi Takeuchi, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

  2007, 2007 FOURTH INTERNATIONAL SYMPOSIUM ON WIRELESS COMMUNICATION SYSTEMS, VOLS 1 AND 2, pp.718-721, 796 - 799, English

  [Refereed]

  International conference proceedings


• Improvement of counter-based broadcasting by random assessment delay extension for wireless sensor networks

  Shintaro Izumi, Takashi Matsuda, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

  2007, 2007 International Conference on Sensor Technologies and Applications, SENSORCOMM 2007, Proceedings, pp.76-81, 76 - 81, English

  [Refereed]

  International conference proceedings


• Cross-layer design for low-power wireless sensor node using long-wave standard time code

  Yu Otake, Masumi Ichien, Takashi Takeuchi, Akihiro Gion, Shinji Mikami, Hidehiro Fujiwara, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

  2007, 2007 International Conference on Sensor Technologies and Applications, SENSORCOMM 2007, Proceedings, pp.341-346, 341 - 346, English

  [Refereed]

  International conference proceedings


• Simple waveform model of inductive interconnects by Delayed Quadratic Transfer Function with application to scaling trend of inductive effects in VLSI's

  Danardono Dwi Antono, Kenichi Inagaki, Hiroshi Kawaguchi, Takayasu Sakurai

  Dec. 2006, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E89A(12) (12), 3569 - 3578, English

  [Refereed]

  Scientific journal


• A sub-mW H.264 baseline-profile motion estimation processor core with a VLSI-oriented block partitioning strategy and SIMD/systolic-array architecture

  Junichi Miyakoshi, Yuichiro Murachi, Tetsuro Matsuno, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masayuki Miyama, Masahiko Yoshimoto

  Dec. 2006, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E89A(12) (12), 3623 - 3633, English

  [Refereed]

  Scientific journal


• A 50 % power reduction in H.264/AVC HDTV video decoder LSI by dynamic voltage scaling in elastic pipeline

  Kentaro Kawakami, Jun Takemura, Mitsuhiko Kuroda, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Dec. 2006, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E89A(12) (12), 3642 - 3651, English

  [Refereed]

  Scientific journal


• A 0.3-V operating,V-th-variation-tolerant SRAM under DVS environment for memory-rich SoC in 90-nm technology era and beyond

  Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Kentaro Kawakami, Junichi Miyakoshi, Shinji Mikami, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Dec. 2006, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E89A(12) (12), 3634 - 3641, English

  [Refereed]

  Scientific journal


• V-DD-hopping accelerators for on-chip power supply circuit to achieve nano second-order transient time

  Kohei Onizuka, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai

  Nov. 2006, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 41(11) (11), 2382 - 2389, English

  [Refereed]

  Scientific journal


• A power- and area-efficient SRAM core architecture with segmentation-free and horizontal/vertical accessibility for super-parallel video processing

  Junichi Miyakoshi, Yuichiro Murachi, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Nov. 2006, IEICE TRANSACTIONS ON ELECTRONICS, E89C(11) (11), 1629 - 1636, English

  [Refereed]

  Scientific journal


• Isochronous MAC using Low Frequency Radio Wave Time Synchronization for Wireless Sensor Networks

  ICHIEN Mashumi, TAKEUCHI Takashi, MIKAMI Shinji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  This paper proposes Isochronous-MAC (I-MAC), which utilizes low-frequency radio waves time synchronization for radio controlled clocks, for sensor networks. Using I-MAC, based on the Low Power Listening (LPL), all sensor nodes wake and listen channel periodically and synchronously. Since a sender can easily predict wakeup time of an intended receiver, it can shorten the length of preamble to make the receiver prepare for reception of the following data packet. In the paper, we use an analytical model to investigate the impact of the data transmission frequency, the number of neighboring nodes, the wakeup period, the clock drift, and the time-synchronization frequency on the power consumption for consideration of the power overhead to perform the time synchronization. Those results demonstrate that I-MAC allows determination of any arbitrary wakeup period without much difficulty, whereas LPL requires a much more careful setting of the wakeup period because its optimum wakeup period is sensitive to the frequency of data transmission as well as to the number of neighboring nodes. Therefore, I-MAC has a great potential to reduce the power consumption in most situations compared with LPL, in spite of the overhead to perform time synchronization.

  The Institute of Electronics, Information and Communication Engineers, Oct. 2006, Proc. First International Conference on Communications Electronics (ICCE 2006), p.172-177(310) (310), 73 - 76, English

  [Refereed]

  International conference proceedings


• Aggregation efficiency-aware greedy incremental tree routing for wireless sensor networks

  Shinji Mikami, Takafumi Aonishi, Hironori Yoshino, Chikara Ohta, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Oct. 2006, IEICE TRANSACTIONS ON COMMUNICATIONS, E89B(10) (10), 2741 - 2751, English

  [Refereed]

  Scientific journal


• A 3-D-stack organic sheet-type scanner with double-wordline and double-bitline structure

  Hiroshi Kawaguchi, Shingo Iba, Yusaku Kato, Tsuyoshi Sekitani, Takao Someya, Takayasu Sakurai

  Oct. 2006, IEEE SENSORS JOURNAL, 6(5) (5), 1209 - 1217, English

  [Refereed]

  Scientific journal


• しきい値電圧ばらつきを克服したDVS環境下における0.3V動作SRAMの開発

  NOGUCHI Hiroki, MORITA Yasuhiro, FUJIWARA Hidehiro, KAWAKAMI Kentaro, MIYAKOSHI Junichi, MIKAMI Shinji, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Aug. 2006, 電子情報通信学会技術研究報告, ICD2006-106Vol.106No.206pp.155, 155 - 160, Japanese

  International conference proceedings


• AVC HDTVデコーダアーキテクチャ

  KAWAKAMI Kentaro, TAKEMURA Jun, KURODA Mitsuhiko, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  We propose an elastic pipeline that can apply dynamic voltage scaling (DVS) to hardwired logic circuits. In order to demonstrate its feasibility, a hardwired H.264/AVC HDTV decoder is designed as a real-time application. The designed decoder reduces 48% of execution cycles for H.264 HDTV decoding. In case of DVS is applied with this reduced cycles, the proposed decoder achieves a power reduction of 50% in a 90-nm process technology, compared to the conventional clock-gating scheme.

  The Institute of Electronics, Information and Communication Engineers, Jun. 2006, 電子情報通信学会技術研究報告, ICD-2006-45 Vol.106 No.92 pp.3(92) (92), 31 - 36, Japanese

  International conference proceedings


• A Vth-Variation-Tolerant SRAM with 0.3-V Minimum Operation Voltage for Memory-Rich SoC under DVS Environment

  MORITA Yasuhiro, FUJIWARA Hidehiro, NOGUCHI Hiroki, KAWAKAMI Kentaro, MIYAKOSHI Junichi, MIKAMI Shinji, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jun. 2006, 2006 Symposium on VLSI Circuits Digest of Technical Papers, pp.16-17, 13 - 14, English

  [Refereed]

  International conference proceedings


• Managing subthreshold leakage in charge-based analog circuits with low-VTH transistors by analog T- Switch (AT-Switch) and super cut-off CMOS (SCCMOS)

  Koichi Ishida, Kouichi Kanda, Atit Tamtrakarn, Hiroshi Kawaguchi, Takayasu Sakurai

  Apr. 2006, IEEE Journal of Solid-State Circuits, 41(4) (4), 859 - 866, English

  [Refereed]

  International conference proceedings


• 定期情報収集型センサネットワークのためのRTS/CTS交換に基づくデータ送信スケジューリング

  MATSUDA Takashi, ICHIEN Masumi, MIKAMI Shinji, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  One of challenging issues on the sensor networks is to extend lifetime of network system as a whole. In periodic data gathering applications, idle time occupies longer than transmission time in the state of a sensor node. Consequently, it is important to decrease wasteful power consumption during idle time. In this study, we propose a scheduling algorithm based on history of RTS/CTS exchange during setup phase. Scheduling the transmission during transfer phase enables each node to turn off its RF circuit during idle time. By tracing ongoing RTS/CTS exchange during data transfer phase, each node knows progress of data transfer process so that it can wait to receive packets for data aggregation. Simulation results show that system lifetime of our scheduling extends 220% longer than that of existing "power scheduling."

  The Institute of Electronics, Information and Communication Engineers, Apr. 2006, 電子情報通信学会技術研究報告, NS2006-7Vol.106No.14pp.25-28(14) (14), 25 - 28, Japanese

  International conference proceedings


• 送信電力制御による効率劣化の影響

  MIKAMI Shinji, TAKEUCHI Takashi, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  ワイヤレスセンターネットワークの長寿命化において送信電力はその重要な1つの方法として考えられる。従来研究においては、消費電力はO(d^n)(ここでdは最大通信距離、nはパス損失係数)で変化すると仮定されてきた。しかし、この仮定は送信効率が常に一定の場合において成り立つものであり、実際には送信効率は変動すると考えられる。そこで本稿では、送信器の最終段であるパワーアンプ、インピーダンス整合回路、アンテナをモデル化し,インピーダンス整合理論ならびに,典型的なA、C級パワーアンの実回路シミュレーションにより、送信効率の劣化が及ぼす影響を検討した。その結果、送信効率が劣化する場合、送信器の消費電力がO(d^r)([numerilal formulu])により変化することを明らかにした。 In order to extend available period of wireless sensor networks, transmission power control is regarded as one of the promising schemes. In most of previous research about transmission power control, it is assumed that a transmitter has power consumption of O(d^n), where d and n denote maximum communication distance and pass loss factor. This assumption substantially holds under the condition that the transmitter efficiency is always constant (efficiency-fixed model). In practice, however, the transmitter efficiency can vary with antenna-output power. In this paper, we show a transmitter with its efficiency degradation has power consumption of O(d^r), where [numerilal formulu] (efficiency degradation model). To do so, we model the final stage of transmitter including antenna as an integrated circuit of PA (power amplifier), impedance matching circuit and antenna impedance, and then analyze the model in two ways. The first analysis is based on matching theorem. The second analysis treats of a typical and realistic circuit for class-A and C power amplifiers, and also verify the analytical results by circuit simulations.

  一般社団法人電子情報通信学会, Apr. 2006, 電子情報通信学会技術研究報告, NS2006-4Vol.106No.14pp.13-16(14) (14), 13 - 16, Japanese

  International conference proceedings


• 製造ばらつきを考慮したセンサネットワークノード消費電力モデルの提案と評価

  TAKEUCHI Takashi, YOSHINO Hironori, ICHIEN Masumi, MATSUDA Takashi, MIKAMI Shinji, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  We introduced manufacturing variation into a power model for a wireless sensor network node. Network protocols for wireless sensor networks such as media access control and routing should be evaluated in terms of life time as a whole system. In fact, there exists variation in power node-by-node due to the manufacturing variation. In the previous research, however, this effect has not been investigated at all since it has been supposed that all nodes have the same power. In this paper, we develop a more exact power model for sensor nodes, which we name the threshold-voltage variation model, considering threshold-voltage variation in a manufacturing process. A microprocessor and RF part are considered as hardware blocks in the model, which is then implemented to QualNet in order to evaluate the impact on the life time. The simulation results show that the conventional model overestimates the life time longer than our model.

  The Institute of Electronics, Information and Communication Engineers, Apr. 2006, 電子情報通信学会技術研究報告, NS2006-6Vol.106No.14pp.21-24(14) (14), 21 - 24, Japanese

  International conference proceedings


• センサネットワークのための長波帯標準電波時刻同期を用いた周期起動型MACの提案

  ICHIEN Masumi, TAKEUCHI Takashi, MIKAMI Shinji, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  This paper proposes Isochronous-MAC (I-MAC), which utilizes low-frequency radio waves time synchronization for radio controlled clocks, for sensor networks. Using I-MAC, based on the Low Power Listening (LPL), all sensor nodes wake and listen channel periodically and synchronously. Since a sender can easily predict wakeup time of an intended receiver, it can shorten the length of preamble to make the receiver prepare for reception of the following data packet. In the paper, we use an analytical model to investigate the impact of the data transmission frequency, the number of neighboring nodes, the wakeup period, the clock drift, and the time-synchronization frequency on the power consumption for consideration of the power overhead to perform the time synchronization. Those results demonstrate that I-MAC allows determination of any arbitrary wakeup period without much difficulty, whereas LPL requires a much more careful setting of the wakeup period because its optimum wakeup period is sensitive to the frequency of data transmission as well as to the number of neighboring nodes. Therefore, I-MAC has a great potential to reduce the power consumption in most situations compared with LPL, in spite of the overhead to perform time synchronization.

  The Institute of Electronics, Information and Communication Engineers, Apr. 2006, 電子情報通信学会技術研究報告, NS2006-8Vol.106No.14pp.29-32(14) (14), 29 - 32, Japanese

  International conference proceedings


• センサネットワークのための集約率を考慮したGIT経路制御の評価

  AONISHI Takafumi, YOSHINO Hironori, MIKAMI Shinji, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  In most research work for sensor network routings, perfect aggregation has been assumed. Such an assumption might limit the application of the wireless sensor networks. We address the impact of aggregation efficiency on energy consumption in the context of GIT routing. Our question is the extent to which energy consumption can decrease compared to the original GIT. In this paper, we propose an improved GIT: "aggregation efficiency-aware routing", or AGIT. We also consider a suppression scheme for exploratory messages: "hop exploratory." Our simulation results show that the AGIT saves the energy consumption of the data transmission compared to the original GIT.

  The Institute of Electronics, Information and Communication Engineers, Apr. 2006, 電子情報通信学会技術研究報告, NS2006-9Vol.106No.14pp.33-36(14) (14), 33 - 36, Japanese

  International conference proceedings


• Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-mn and sub-l-V-V-DD LSIs

  KS Min, HD Choi, HY Choi, H Kawaguchi, T Sakurai

  Apr. 2006, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 14(4) (4), 430 - 435, English

  [Refereed]

  Scientific journal


• An Architecture Study of Scalable Optical-Flow Processor for Real-Time Video Segmentation

  YAMAMOTO Ryo, FUKAYAMA Yuuki, KATAGIRI Tadayoshi, MIYAKOSHI Junichi, KURODA Yuki, MINEGISHI Noriyuki, MIYAMA Masayuki, KAWAGUCHI Hiroshi, IMAMURA Kosuke, HASHIMOTO Hideo, YOSHIMOTO Masahiko

  Apr. 2006, Proc. IEEE Symposium on Low-Power High-Speed Chips (COOL Chips IX), pp. 225-240, English

  [Refereed]

  International conference proceedings


• Trends of on-chip interconnects in deep sub-micron VLSI

  DD Antono, K Inagaki, H Kawaguchi, T Sakurai

  Mar. 2006, IEICE TRANSACTIONS ON ELECTRONICS, E89C(3) (3), 392 - 394, English

  [Refereed]

  Scientific journal


• An Organic FET SRAM for Braille Sheet Display with Back Gate to Increase Static Noise Margin

  TAKAMIYA Makoto, SEKITANI Tsuyoshi, KATO Yusaku, KAWAGUCHI Hiroshi, SOMEYA Takao, SAKURAI Takayasu

  Feb. 2006, IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 276-277, 276 - 278

  [Refereed]

  International conference proceedings


• Fully-Depleted SOI CMOS circuits and technology: For ultralow-power applications

  Sakurai, T., Matsuzawa, A., Douseki, T., Matsuhashi, H., Tsuchiya, T., Omura, Y., Shimomura, H., Yonemaru, M., Fujii, K., Kameyama, A., Kawaguchi, H., Tsukahara, T., Kozaki, M., Kinoshita, M., Sawada, A., Matsuya, Y., Terada, J., Inagaki, Y., Fuse, T., Ohtomo, Y., Koizumi, H., Baba, S., Nishimura, K., Yoshida, Y., Hama, N., Mogami, T., Hiramoto, T., Uchida, K., Takagi, S.-I., Numata, T.

  Fully-Depleted SOI CMOS Circuits and Technology: For Ultralow-Power Applications, 2006, Fully-Depleted SOI CMOS Circuits and Technology: For Ultralow-Power Applications

  Scientific journal


• Low power and flexible braille sheet display with organic FET's and plastic actuators

  Makoto Takamiya, Tsuyoshi Sekitani, Yusaku Kato, Hiroshi Kawaguchi, Takao Someya, Takayasu Sakurai

  2006, 2006 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS, 219 - +, English

  International conference proceedings


• A large-area flexible wireless power transmission sheet using printed plastic MEMS switches and organic field-effect transistors

  Tsuyoshi Sekitani, Makoto Takamiya, Yoshiaki Noguchi, Shintaro Nakano, Yusaku Kato, Kazuki Hizu, Hiroshi Kawaguchi, Takayasu Sakurai, Takao Someya

  2006, Technical Digest - International Electron Devices Meeting, IEDM, English

  [Refereed]

  International conference proceedings


• Chip-to-chip inductive wireless power transmission system for SiP applications

  Kohei Onizuka, Hiroshi Kawaguchi, Makoto Takamiya, Tadahiro Kuroda, Takayasu Sakurai

  2006, Proceedings of the Custom Integrated Circuits Conference, 575 - 578, English

  [Refereed]

  International conference proceedings


• Stacked-chip implementation of on-chip buck converter for power-aware distributed power supply systems

  Kohei Onizuka, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai

  2006, 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006, 127 - 130, English

  [Refereed]

  International conference proceedings


• Special section on VLSI Design and CAD Algorithms

  Hidetoshi Onodera, Makoto Ikeda, Tohru Ishihara, Tsuyoshi Isshiki, Koji Inoue, Kenichi Okada, Seiji Kajihara, Mineo Kaneko, Hiroshi Kawaguchi, Shinji Kimura, Morihiro Kuga, Atsushi Kurokawa, Takashi Sato, Toshiyuki Shibuya, Yoichi Shiraishi, Kazuyoshi Takagi, Atsushi Takahashi, Yoshinori Takeuchi, Nozomu Togawa, Hiroyuki Tomiyama, Yuichi Nakamura, Kiyoharu Hamaguchi, Yukiya Miura, Shin-Ichi Minato, Ryuichi Yamaguchi, Masaaki Yamada, Yasushi Yuminaka, Takayuki Watanabe, Masanori Hashimoto, Masayuki Miyazaki

  Institute of Electronics, Information and Communication, Engineers, IEICE, 2006, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E89-A(12) (12), 3377, English

  [Refereed]

  Scientific journal


• Organic transistor integerated circuits for large-area sensors

  T. Someya, T. Sekitani, S. Iba, Y. Kato, T. Sakurai, H. Kawaguchi

  2006, Molecular Crystals and Liquid Crystals, 444, 13 - 22, English

  [Refereed]

  International conference proceedings


• Low-power low-leakage FPGA design using zigzag power gating, dual-V(TH)/V(DD) and micro-V(DD)-hopping

  Canh Quang Tran, Hiroshi Kawaguchi, Takayasu Sakurai

  Institute of Electronics, Information and Communication, Engineers, IEICE, 2006, IEICE Transactions on Electronics, E89-C(3) (3), 280 - 286, English

  [Refereed]

  Scientific journal


• Isochronous MAC using long-wave standard time code for wireless sensor networks

  Masumi Ichien, Takashi Takeuchi, Shinji Mikami, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

  2006, 2006 FIRST INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND ELECTRONICS, 172 - +, English

  [Refereed]

  International conference proceedings


• Use of laser drilling in the manufacture of organic inverter circuits

  S Iba, Y Kato, T Sekitani, H Kawaguchi, T Sakurai, T Someya

  Jan. 2006, ANALYTICAL AND BIOANALYTICAL CHEMISTRY, 384(2) (2), 374 - 377, English

  [Refereed]

  Scientific journal


• An energy-harvesting wireless-interface SoC for short-range data communication

  Shinji Mikami, Tetsuro Matsuno, Masayuki Miyama, Hiroshi Kawaguchi, Masahiko Yoshimoto, Hiroaki Ono

  Institute of Electrical Engineers of Japan, 2006, IEEJ Transactions on Electronics, Information and Systems, 126(5) (5), 565 - 570, English

  [Refereed]

  Scientific journal


• Impact of aggregation efficiency on GIT routing for wireless sensor networks

  Takafumi Aonishi, Takashi Matsuda, Shinji Mikami, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

  2006, 2006 INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING WORKSHOPS, PROCEEDINGS, pp.00-00, 151 - +, English

  [Refereed]

  International conference proceedings


• A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering

  Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2006, ISLPED '06: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, pp.61-66, 61 - 66, English

  [Refereed]

  International conference proceedings


• A power-variation model for sensor node and the impact against life time of wireless sensor networks

  Takashi Matsuda, Takashi Takeuchi, Hironori Yoshino, Masumi Ichien, Shinji Mikami, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

  2006, 2006 FIRST INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND ELECTRONICS, pp.106-111, 106 - +, English

  [Refereed]

  International conference proceedings


• A power- and area-efficient SRAM core architecturt for super-parallel video processing

  Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto, Tetsuro Matsuno

  2006, IFIP VLSI-SOC 2006: IFIP WG 10.5 INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION & SYSTEM-ON-CHIP, pp.192-197, 192 - +, English

  [Refereed]

  International conference proceedings


• An 800-μW H.264 baseline-profile motion estimation processor core

  Takahiro Iinuma, Junichi Miyakoshi, Yuichiro Murachi, Tetsuro Matsuno, Masaki Hamamoto, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto, Masayuki Miyama

  2006, 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006, pp.99-102, 99 - 102, English

  [Refereed]

  International conference proceedings


• Integration of organic FETs with organic photodiodes for a large area, flexible, and lightweight sheet image scanners

  T Someya, Y Kato, S Iba, Y Noguchi, T Sekitani, H Kawaguchi, T Sakurai

  Nov. 2005, IEEE TRANSACTIONS ON ELECTRON DEVICES, 52(11) (11), 2502 - 2511, English

  [Refereed]

  Scientific journal


• センサネットワークのための集約率を考慮したGIT経路制御の評価

  AONISHI Takafumi, YOSHINO Hironori, MIKAMI Shinji, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  In most research work for sensor network routings, perfect aggregation has been assumed. Such an assumption might limit the application of the wireless sensor networks. We address the impact of aggregation efficiency on energy consumption in the context of GIT routing. Our question is the extent to which energy consumption can decrease compared to the original GIT. In this paper, we propose an improved GIT : "aggregation efficiency-aware routing", or AGIT. We also consider two suppression schemes for exploratory messages : "minimum exploratory" and "hop exploratory." Our simulation results show that the AGIT saves the energy consumption of the data transmission compared to the original GIT.

  The Institute of Electronics, Information and Communication Engineers, Oct. 2005, 電子情報通信学会技術研究報告;NS2005-108, Vol.105; No.357; pp.37-40(357) (357), 37 - 40, Japanese

  International conference proceedings


• ワイヤレスセンサノードのための送信電力制御におけるインピーダンス不整合の影響

  MIKAMI Shinji, TAKEUCHI Takashi, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Sep. 2005, 2005年電子情報通信学会ソサイエティ大会;B-5-148, p.148, Japanese

  International conference proceedings


• (Invited) Recent Progress of Organic Transistor Integrated Circuits for Large-Area Sensor Applications

  SOMEYA Takao, SAKURAI Takayasu, SEKITANI Tsuyoshi, KAWAGUCHI Hiroshi, IBA Shingo, KATO Yusaku, NOGUCHI Yoshiaki

  Sep. 2005, Proceedings of International Conference on Solid State Devices and Materials (SSDM), pp. 380-381

  [Refereed]

  International conference proceedings


• Conformable, flexible, large-area networks of pressure and thermal sensors with organic transistor active matrixes

  T Someya, Y Kato, T Sekitani, S Iba, Y Noguchi, Y Murase, H Kawaguchi, T Sakurai

  Aug. 2005, PROCEEDINGS OF THE NATIONAL ACADEMY OF SCIENCES OF THE UNITED STATES OF AMERICA, 102(35) (35), 12321 - 12325, English

  [Refereed]

  Scientific journal


• Control of threshold voltage of organic field-effect transistors with double-gate structures

  S Iba, T Sekitani, Y Kato, T Someya, H Kawaguchi, M Takamiya, T Sakurai, S Takagi

  Jul. 2005, APPLIED PHYSICS LETTERS, 87(2) (2), English

  [Refereed]

  Scientific journal


• Frequency-voltage cooperative CPU power control: A design rule and its application by feedback prediction

  Keisuke Toyama, Satoshi Misaka, Kazuo Aisaka, Toshiyuki Aritsuka, Kunio Uchiyama, Koichiro Ishibashi, Hiroshi Kawaguchi, Takayasu Sakurai

  Jun. 2005, Systems and Computers in Japan, 36(6) (6), 39 - 48, English

  [Refereed]

  Scientific journal


• Time Revising Robust Frequency-Voltage Cooperative Power Reduction for Multi-tasking Multimedia Applications

  MISAKA Satoshi, KAWAGUCHI Hiroshi, SAKURAI Takayasu

  Apr. 2005, IEEE International Symposium on Low-Power and High-Speed Chips (COOL Chips), pp. 165-180

  [Refereed]

  International conference proceedings


• μITRON-LP: Power-conscious real-time OS based on cooperative voltage scaling for multimedia applications

  Hiroshi Kawaguchi, Youngsoo Shin, Takayasu Sakurai

  Feb. 2005, IEEE Transactions on Multimedia, 7(1) (1), 67 - 74, English

  [Refereed]

  Scientific journal


• Sheet image scanner with organic transistor integrated circuits

  T. Someya, T. Sakurai, T. Sekitani, H. Kawaguchi, Y. Kato, S. Iba

  2005, IDW/AD'05 - Proceedings of the 12th International Display Workshops in Conjunction with Asia Display 2005, (2) (2), 1037 - 1040, English

  International conference proceedings


• More than two orders of magnitude leakage current reduction in look-up table for FPGA's

  Canh Q. Tran, Hiroshi Kawaguchi, Takayasu Sakurai

  2005, Proceedings - IEEE International Symposium on Circuits and Systems, 4701 - 4704, English

  [Refereed]

  International conference proceedings


• Subthreshold-leakage suppressed switched capacitor circuit based on super cut-off CMOS (SCCMOS)

  K. Ishida, K. Kanda, A. Tamtrakarn, H. Kawaguchi, T. Sakurai

  2005, Proceedings - IEEE International Symposium on Circuits and Systems, 3119 - 3122, English

  [Refereed]

  International conference proceedings


• Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) scheme for two orders of magnitude leakage current reduction of sub-1-V-VDD SRAM's

  Kyeong-Sik Min, Kouichi Kanda, Hiroshi Kawaguchi, Kenichi Inagaki, Fayez Robert Saliba, Hoon-Dae Choi, Hyun-Young Choi, Daejeong Kim, Dong Myong Kim, Takayasu Sakurai

  Institute of Electronics, Information and Communication, Engineers, IEICE, 2005, IEICE Transactions on Electronics, E88-C(4) (4), 760 - 767, English

  [Refereed]

  Scientific journal


• Cut-and-paste customization of organic FET integrated circuit and its application to electronic artificial skin

  Hiroshi Kawaguchi, Takao Someya, Tsuyoshi Sekitani, Takayasu Sakurai

  Jan. 2005, IEEE Journal of Solid-State Circuits, 40(1) (1), 177 - 185, English

  [Refereed]

  International conference proceedings


• Subthreshold-leakage suppressed switched capacitor circuit based on super cut-off CMOS (SCCMOS)

  K Ishida, K Kanda, A Tamtrakarn, H Kawaguchi, T Sakurai

  2005, 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, pp. 3119-3122, 3119 - 3122, English

  [Refereed]

  International conference proceedings


• More than two orders of magnitude leakage current reduction in look-up table for FPGA's

  CQ Tran, H Kawaguchi, T Sakurai

  2005, 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, pp. 4701-4704, 4701 - 4704, English

  [Refereed]

  International conference proceedings


• Low-power high-speed level shifter design for block-level dynamic voltage scaling environment

  CQ Tran, H Kawaguchi, T Sakurai

  2005, 2005 International Conference on Integrated Circuit Design and Technology, pp. 229-232, 229 - 232, English

  [Refereed]

  International conference proceedings


• Recent advances in applications of organic integrated circuits for large-area electronics

  T Someya, T Sakurai, T Sekitani, H Kawaguchi, S Iba, Y Kato

  2005, 2005 International Conference on Integrated Circuit Design and Technology, pp. 57-58, 57 - 58, English

  [Refereed]

  International conference proceedings


• Managing leakage in charge-based analog circuits with low-V-TH transistors by analog T-switch (AT-switch) and super cut-off CMOS

  K Ishida, K Kanda, A Tamtrakarn, H Kawaguchi, T Sakurai

  2005, 2005 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 122-125, 122 - 125, English

  [Refereed]

  International conference proceedings


• Experimental verification of row-by-row variable V-DD scheme reducing 95% active leakage power of SRAM's

  FR Saliba, H Kawaguchi, T Sakurai

  2005, 2005 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 162-165, 162 - 165, English

  [Refereed]

  International conference proceedings


• Pocket scanner using organic transistors and detectors

  T Someya, T Sakurai, T Sekitani, H Kawaguchi, Y Kato, S Iba

  2005, 2005 IEEE LEOS Annual Meeting Conference Proceedings (LEOS), pp. 59-60, 59 - 60, English

  [Refereed]

  International conference proceedings


• 95% Leakage-reduced FPGA using zigzag power-gating, dual-V(TH)/V(DD) and micro-VDD-hopping

  Canh Q. Tran, Hiroshi Kawaguchi, Takayasu Sakurai

  2005, 2005 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS, pp. 149-152, 149 - 152, English

  [Refereed]

  International conference proceedings


• A flexible, lightweight Braille sheet display with plastic actuators driven by an organic field-effect transistor active matrix

  Y Kato, S Iba, T Sekitani, Y Noguchi, K Hizu, XZ Wang, K Takenoshita, Y Takamatsu, S Nakano, K Fukuda, K Nakamura, T Yamaue, M Doi, K Asaka, H Kawaguchi, M Takamiya, T Sakurai, T Someya

  2005, IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST, pp. 105-108, 105 - 108, English

  [Refereed]

  International conference proceedings


• 95% Leakage-reduced FPGA using zigzag power-gating, dual-V(TH)/V(DD) and micro-VDD-hopping

  Canh Q. Tran, Hiroshi Kawaguchi, Takayasu Sakurai

  2005, 2005 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS, vol. E89-C, no. 3, pp. 280-286, 149 - 152, English

  [Refereed]

  International conference proceedings


• Managing leakage in charge-based analog circuits with low-V-TH transistors by analog T-switch (AT-switch) and super cut-off CMOS

  K Ishida, K Kanda, A Tamtrakarn, H Kawaguchi, T Sakurai

  2005, 2005 Symposium on VLSI Circuits, Digest of Technical Papers, vol.41:no. 4:pp. 859-867, 122 - 125, English

  [Refereed]

  International conference proceedings


• A large-area, flexible pressure sensor matrix with organic field-effect transistors for artificial skin applications

  Takao Someya, Tsuyoshi Sekitani, Shingo Iba, Yusaku Kato, Hiroshi Kawaguchi, Takayasu Sakurai

  Jul. 2004, Proceedings of the National Academy of Sciences of the United States of America, 101(27) (27), 9966 - 9970, English

  [Refereed]

  Scientific journal


• High mobility of pentacene field-effect transistors with polyimide gate dielectric layers

  Yusaku Kato, Shingo Iba, Ryohei Teramoto, Tsuyoshi Sekitani, Takao Someya, Hiroshi Kawaguchi, Takayasu Sakurai

  May 2004, Applied Physics Letters, 84(19) (19), 3789 - 3791, English

  [Refereed]

  Scientific journal


• A large-area, flexible, and lightweight sheet image scanner integrated with organic field-effect transistors and organic photodiodes

  Takao Someya, Shingo Iba, Yusaku Kato, Tsuyoshi Sekitani, Yoshiaki Noguchi, Yousuke Murase, Hiroshi Kawaguchi, Takayasu Sakurai

  2004, Technical Digest - International Electron Devices Meeting, IEDM, 365 - 368, English

  International conference proceedings


• Organic field-effect transistors with bending radius down to 1 mm

  Hiroshi Kawaguchi

  2004, Materials Research Society Symposium - Proceedings

  Scientific journal


• 0.5V, 400MHz, VDD-hopping processor with zero VTH FD-SOI technology

  Hiroshi Kawaguchi, Kouichi Kanda, Koichi Nose, Sadaaki Hattori, Danardono Dwi Antono, Daisuke Yamada, Takayuki Miyazaki, Kenichi Inagaki, Toshiro Hiramoto, Takayasu Sakurai

  2003, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 101 - 481, English

  International conference proceedings


• Row-by-row dynamic source-line voltage control (RRDSV) scheme for two orders of magnitude leakage current reduction of sub-1-V-V-DD SRAM's

  KS Min, K Kanda, T Sakurai

  2003, ISLPED'03: PROCEEDINGS OF THE 2003 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, vol. E88-C, no. 4, pp. 760-767, 66 - 71, English

  [Refereed]

  International conference proceedings


• V TH-hopping scheme to reduce subthreshold leakage for low-power processors

  Koichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi, Seongsoo Lee, Takayasu Sakurai

  Mar. 2002, IEEE Journal of Solid-State Circuits, 37(3) (3), 413 - 419, English

  [Refereed]

  Scientific journal


• A controller LSI for realizing V-DD-hopping scheme with off-the-shelf processors and its application to MPEG4 system

  Hiroshi Kawaguchi

  2002, IEICE Transactions on Electronics

  Scientific journal


• A controller LSI for realizing V_DD-hopping scheme with off-the-shelf processors and its application to MPEG4 system

  Kawaguchi, H., Zhang, G., Lee, S., Shin, Y., Sakurai, T.

  2002, IEICE Transactions on Electronics, E85-C(2) (2)

  Scientific journal


• Two orders of magnitude leakage power reduction of low voltage SRAM's by row-by-row dynamic VDD control (RRDV) scheme

  Kouichi Kanda, Takayuki Miyazaki, Mitt Kyeong Sik, Hiroshi Kawaguchi, Takayasu Sakurai

  Institute of Electrical and Electronics Engineers Inc., 2002, Proceedings of the Annual IEEE International ASIC Conference and Exhibit, 2002-, 381 - 385, English

  [Refereed]

  International conference proceedings


• Design impact of positive temperature dependence on drain current in sub-1-V CMOS VLSIs

  Kouichi Kanda, Kouichi Nose, Hiroshi Kawaguchi, Takayasu Sakurai

  Oct. 2001, IEEE Journal of Solid-State Circuits, 36(10) (10), 1559 - 1564, English

  [Refereed]

  Scientific journal


• Optimum device parameters and scalability of variable threshold voltage complementary MOS (VTCMOS)

  T Hiramoto, M Takamiya, H Koura, T Inukai, H Gomyo, H Kawaguchi, T Sakurai

  Apr. 2001, JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 40(4B) (4B), 2854 - 2858, English

  [Refereed]

  Scientific journal


• Author and Subject Index Vol. 125, Suppl. 1, 2001

  Hiroshi Kawaguchi

  2001, International Archives of Allergy and Immunology

  Scientific journal


• An LSI for VDD-hopping and MPEG4 system based on the chip

  Hiroshi Kawaguchi, Gang Zhang, Seongsoo Lee, Takayasu Sakurai

  2001, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings, 4, 918 - 921, English

  [Refereed]

  International conference proceedings


• Super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current

  Hiroshi Kawaguchi, Koichi Nose, Takayasu Sakurai

  IEEE, Oct. 2000, IEEE Journal of Solid-State Circuits, 35(10) (10), 1498 - 1501, English

  [Refereed]

  Scientific journal


• Lack of association with interleukin 1 receptor antagonist and interleukin-1 beta gene polymorphisms in sarcoidosis patients

  Hiroshi Kawaguchi

  2000, Respiratory Medicine

  Scientific journal


• Boosted gate MOS (BGMOS): Device/circuit cooperation scheme to achieve leakage-free giga-scale integration

  T Inukai, M Takamiya, K Nose, H Kawaguchi, T Hiramoto, T Sakurai

  2000, PROCEEDINGS OF THE IEEE 2000 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 409 - 412, English

  [Refereed]

  International conference proceedings


• Vitamin D receptor gene polymorphism in sarcoidosis

  Hiroshi Kawaguchi

  1999, American Journal of Respiratory and Critical Care Medicine

  Scientific journal


• A reduced clock-swing flip-flop (RCSFF) for 63% power reduction

  Hiroshi Kawaguchi, Takayasu Sakurai

  John Wiley and Sons Inc., Jan. 1999, High-Performance System Design: Circuits and Logic, 349 - 353, English

  [Refereed]

  In book


• A Reduced Clock-Swing Flip-Flop (RCSFF) for 63% power reduction

  Hiroshi Kawaguchi, Takayasu Sakurai

  May 1998, IEEE Journal of Solid-State Circuits, 33(5) (5), 807 - 811, English

  [Refereed]

  Scientific journal


• Delay and noise formulas for capacitively coupled distributed RC lines

  Hiroshi Kawaguchi

  1998, PROCEEDINGS OF THE ASP-DAC - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE WITH EDA TECHNO FAIR

  Scientific journal

• マイクロ波ドップラーセンサを用いた非接触生体認証—Heartbeat-based Non-contact Biometric Authentication Using Microwave Doppler Sensor

  高橋 宏太, 和泉 慎太郎, 川口 博

  [東京] : Institute of Electrical Engineers of Japan, Nov. 2023, 「センサ・マイクロマシンと応用システム」シンポジウム論文集 電気学会センサ・マイクロマシン部門 [編], 40, 5p, Japanese


• Contactless respiration monitoring using spatial ultrasound Doppler sensor

  都甲尚志, 河合晃聖, 石井徹, 和泉慎太郎, 川口博

  2023, 電子情報通信学会大会講演論文集(CD-ROM), 2023


• Ray-tracing ultrasonic simulation method for bathroom surveillance

  BIN KAMARULZAMAN M. Shahrul Amir, 濱邉理久, 安田祐人, 大原遼太郎, 佐藤駿, 和泉慎太郎, 川口博

  2023, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 40th


• 3D person location estimation using spatial ultrasound and VAE in the bathroom

  佐藤駿, 安田祐人, 大原遼太郎, 濱邉理玖, 玄田貴之, 今中翔哉, 和泉慎太郎, 川口博

  2023, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 40th


• Bathroom acoustic event detection using machine learning

  森浩貴, 玄田貴之, 佐藤駿, 大原遼太郎, SHAHRUL Muhammad, 安田裕人, 河合晃聖, 濱邉理玖, 和泉慎太郎, 川口博

  2023, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 40th


• Road traffic monitoring by machine learning using ultrasonic and audible sound

  濱邉理玖, 大原遼太郎, 安田祐人, 佐藤駿, 川口博, 和泉慎太郎

  2023, 電子情報通信学会大会講演論文集(CD-ROM), 2023


• Feature Extraction from Body Surface Potential using Variational Autoencoder

  吉野早耶, 和泉慎太郎, 川口博

  2023, 電子情報通信学会大会講演論文集(CD-ROM), 2023


• 1W/8R20T SRAMコードブックメモリによる深層学習プロセッサの主記憶帯域削減

  大原遼太郎, 加太雅也, 大地正和, 大地正和, 安田祐人, 大地正和, 濱邉理玖, 和泉慎太郎, 川口博

  2023, 電子情報通信学会技術研究報告(Web), 123(143(SDM2023 35-53)) (143(SDM2023 35-53))


• 空間超音波を用いた非接触バイタルモニタリング—Non-contact vital monitoring using spatial ultrasound

  河合 晃聖, 和泉 慎太郎, 川口 博, 近藤 勲, 小椋 朗広

  Institute of Electrical Engineers of Japan, Nov. 2022, 「センサ・マイクロマシンと応用システム」シンポジウム論文集 電気学会センサ・マイクロマシン部門 [編], 39, 3p, Japanese


• マルチモーダルセンシングによる脊髄損傷患者の下肢伸展挙上の解析—Analysis of SLR in spinal cord injury patients using multimodal sensing

  吉倉 崚人, 和泉 慎太郎, 杉本 達也, 川口 博

  Institute of Electrical Engineers of Japan, Nov. 2022, 「センサ・マイクロマシンと応用システム」シンポジウム論文集 電気学会センサ・マイクロマシン部門 [編], 39, 4p, Japanese


• Wearable Perspiration Volume Sensor Using Dual-Frequency Impedance Measurement.

  Ryo Takamatsu, Shogo Amano, Shintaro Izumi, Hiroshi Ohta, Toshikazu Nezu, Yuki Noda, Teppei Araki, Takafumi Uemura, Tsuyoshi Sekitani, Hiroshi Kawaguchi

  IEEE, Nov. 2022, 2022 IEEE Sensors, 39, 3p - 4, Japanese


• Outdoor 3D object reconstruction method using spatial ultrasound and VAE

  佐藤駿, 安田祐人, 大原遼太郎, 濱邉理玖, 石井徹, 和泉慎太郎, 川口博

  2022, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 39th


• Low Power Noise Reduction Technology for ECG Sensors Using Dry Electrodes

  元辻有貴, 和泉慎太郎, 川口博

  2022, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 39th


• Thermal Stimulation Device Using Matrix Drive Circuitry

  江森俊哉, 和泉慎太郎, 和泉慎太郎, 伊庭野健造, 伊庭野健造, 伊藤雄一, 伊藤雄一, 佐藤克成, 佐藤克成, 菅原徹, 菅原徹, 川口博

  2022, 日本機械学会ロボティクス・メカトロニクス講演会講演論文集(CD-ROM), 2022


• マイクロ波ドップラーセンサを用いた心拍計測における個人差の評価

  真鍋歩夢, 和泉慎太郎, 落合拓光, 川口博

  2021, 電子情報通信学会技術研究報告(Web), 121(24(WBS2021 1-21)) (24(WBS2021 1-21))


• 大型船舶エンジンの燃料効率改善を目的とした回転体位相計測センサの開発

  小銭瞭介, 原田正康, 吉川裕木子, 石井徹, 和泉慎太郎, 川口博, 上村祥平, 荒木要, 松田真理子

  2021, マリンエンジニアリング学術講演会講演論文集, 91st


• A Consideration of Heart Rate Measurement Technology with Doppler sensor

  落合拓光, 和泉慎太郎, 矢野裕二, 川口博, 吉本雅彦

  2020, 電子情報通信学会大会講演論文集(CD-ROM), 2020


• A Study of Machine Learning Architecture for Wearable Bio-signal Sensor

  渡辺大輔, 矢野祐二, 和泉慎太郎, 川口博, 吉本雅彦

  2020, 電子情報通信学会大会講演論文集(CD-ROM), 2020


• Low Power circuit for Electro-Cardiogram Measurement Using Body Temperature Power Generation

  藤井将裕, 和泉慎太郎, 矢野裕二, 川口博, 吉本雅彦

  2020, 電子情報通信学会大会講演論文集(CD-ROM), 2020


• 加速度センサとひずみセンサを用いた咳嗽検出手法の検討

  渡辺大輔, 和泉慎太郎, 大歳丈博, 永野達也, 西村善博, 吉本雅彦, 川口博

  2020, 電子情報通信学会技術研究報告(Web), 120(219(MICT2020 7-20)) (219(MICT2020 7-20))


• Heart Rate Interval Error Compensation Method Using Multiple-Photoplethysmography

  親富彩花, 和泉慎太郎, 矢野裕二, 川口博, 吉本雅彦

  2020, 電子情報通信学会大会講演論文集(CD-ROM), 2020


• A Low-Power Photoplethysmography Sensor Using Current Integration Circuit

  笹井 香菜, 和泉 慎太郎, 渡辺 健斗, 矢野 祐二, 川口 博, 吉本 雅彦

  Institute of Electrical Engineers of Japan, 19 Nov. 2019, 「センサ・マイクロマシンと応用システム」シンポジウム論文集 電気学会センサ・マイクロマシン部門 [編], 36, 4p, Japanese


• 光電式容積脈波法を用いた脈拍測定の低消費電力化手法

  渡辺健斗, 和泉慎太郎, 矢野祐二, 川口博, 吉本雅彦

  2019, 電子情報通信学会技術研究報告, 118(383(MICT2018 59-67)(Web)) (383(MICT2018 59-67)(Web))


• ウェアラブル生体情報センサのための学習推論アルゴリズムの検討

  渡辺大輔, 矢野祐二, 和泉慎太郎, 川口博, 吉本雅彦

  2019, 電子情報通信学会技術研究報告, 119(263(MICT2019 23-37)(Web)) (263(MICT2019 23-37)(Web))


• ARモデルを用いた心拍変動解析のための低消費電力アーキテクチャの検討

  吉田聖也, 和泉慎太郎, 矢野裕二, 川口博, 吉本雅彦

  2019, 電子情報通信学会大会講演論文集(CD-ROM), 2019


• メモリ容量と帯域幅削減のための分散深層学習ハードウェア

  川口博, 森陽紀, 陽川哲也, 和泉慎太郎, 井上淳樹

  2018, 電気関係学会関西連合大会講演論文集(CD-ROM), 2018


• Chemical Reaction Actuator and Wireless Power Feeding for Swallowable Sensing Device

  中村 亮太, 和泉 慎太郎, 川口 博, 吉本 雅彦, 太田 英敏

  Institute of Electrical Engineers of Japan, 31 Oct. 2017, 「センサ・マイクロマシンと応用システム」シンポジウム論文集 電気学会センサ・マイクロマシン部門 [編], 34, 1 - 5, Japanese


• マイクロ波ドップラーセンサを用いた車両走行中の心拍計測手法

  松永大地, 和泉慎太郎, 川口博, 吉本雅彦

  2017, 電子情報通信学会大会講演論文集(CD-ROM), 2017


• ノイズフィードバック技術を用いたウェアラブル向け容量結合型心電センサ

  永里佑樹, 和泉慎太郎, 川口博, 吉本雅彦

  2017, 電子情報通信学会大会講演論文集(CD-ROM), 2017


• ウェアラブルデバイスのための圧電素子を用いたマルチモーダルな心血管情報の計測

  岡野孝昭, 和泉慎太郎, 勝浦巧, 川口博, 吉本雅彦

  2017, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 34th


• ヘルスケアデバイスと材料

  川口博, 和泉慎太郎, 吉本雅彦

  2016, 日本化学会春季年会講演予稿集(CD-ROM), 96th


• 加速度センサを用いた低消費電力運動強度推定アルゴリズム

  塚原美緒, 中西基文, 和泉慎太郎, 中井陽三郎, 川口博, 吉本雅彦

  2016, 電気学会電子・情報・システム部門大会講演論文集(CD-ROM), 2016


• 研究室だより：神戸大学大学院システム情報学研究科情報科学専攻 吉本・川口研究室

  和泉 慎太郎, 川口 博, 吉本 雅彦

  一般社団法人 電気学会, 2016, 電気学会論文誌. E, センサ・マイクロマシン部門誌, 136(3) (3), NL3_2 - NL3_2, Japanese


• A low-power wearable electrocardiogram sensor SoC

  IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Monitoring of daily life using a wearable sensor is useful to prevent lifestyle diseases. This paper presents an electrocardiograph (ECG) monitoring SoC using a non-volatile MCU and a noise-tolerant instantaneous heartbeat detector.

  The Japan Society of Applied Physics, 2016, Oyo Buturi, 85(4) (4), 301 - 305, Japanese

  [Refereed][Invited]

  Introduction scientific journal


• Haptic Stimulus Actuator using Piezoelectric Pump for Wearable Devices

  児玉 泰佑, 和泉 慎太郎, 正木 何奈, 川口 博, 吉本 雅彦, 前中 一介

  Institute of Electrical Engineers of Japan, 28 Oct. 2015, 「センサ・マイクロマシンと応用システム」シンポジウム論文集 電気学会センサ・マイクロマシン部門 [編], 32, 1 - 5, Japanese


• Non-contact and Noise Tolerant Heart Rate Monitoring using Microwave Doppler Sensor and Range Imagery

  松永 大地, 和泉 慎太郎, 奥野 圭祐, 川口 博, 吉本 雅彦

  Institute of Electrical Engineers of Japan, 28 Oct. 2015, 「センサ・マイクロマシンと応用システム」シンポジウム論文集 電気学会センサ・マイクロマシン部門 [編], 32, 1 - 5, Japanese


• Dependable Memory Design for Robust VLSI System

  吉本 秀輔, 川口 博, 吉本 雅彦

  [電子情報通信学会], 03 Aug. 2015, 回路とシステムワークショップ論文集 Workshop on Circuits and Systems, 28, 276 - 281, Japanese


• A Noise-Tolerant ECG Sensing Method for Wearable Healthcare Systems

  TANAKA Yoshito, KAWAMOTO Yuta, NAKAI Youzaburo, OKUNO Keisuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  The Institute of Electronics, Information and Communication Engineers, 24 Nov. 2014, IEICE technical report. Computer systems, 114(346) (346), 47 - 47, Japanese


• A Normally-off Wearable Monitoring SoC using Non-volatile MCU

  Matsunaga Daichi, NAKAI Yozaburo, KAWAMOTO Yuta, NAKAGAWA Tomoki, OKUNO Keisuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  The Institute of Electronics, Information and Communication Engineers, 24 Nov. 2014, IEICE technical report. Computer systems, 114(346) (346), 49 - 49, Japanese


• A 0.38-V Operating STT-MRAM with Process Variation Tolerant Sense Amplifier

  UMEKI Yohei, YANAGIDA Koji, YOSHIMOTO Shusuke, IZUMI Shintaro, YOSHIMOTO Masahiko, Kawaguchi Hiroshi, TSUNODA Koji, SUGII Toshihiro

  This paper exhibits a 65-nm 8-Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at a single supply voltage with a process-variation tolerant sense amplifier. The proposed sense amplifier comprises a boosted-gate nMOS and negative-resistance pMOSes as loads, which maximizes the readout margin in any process corner. The STT-MRAM achieves a cycle time of 1.9μs (=0.526MHz) at 0.38V. The operating power is 6.15μW at that voltage. The minimum energy per access is 3.89pJ/bit when the supply voltage is 0.44V. The proposed STT-MRAM operates at lower energy than SRAM when a utilization of a memory bandwidth is 14% or less.

  The Institute of Electronics, Information and Communication Engineers, 17 Apr. 2014, Technical report of IEICE. ICD, 114(13) (13), 47 - 51, Japanese


• STT-MRAM Architecture for Improving Throughput

  Mori Haruki, Yanagida Koji, Umeki Yohei, Yoshimoto Shusuke, Izumi Shintaro, Yoshimoto Masahiko, Kawaguchi Hiroshi, Tsunoda Koji, Sugii Toshihiro

  The Institute of Electronics, Information and Communication Engineers, 21 Jan. 2014, Technical report of IEICE. ICD, 113(419) (419), 27 - 27, Japanese


• High-Speed Ferroelectric 6T4C Shadow SRAM for Normally-Off Computing

  NAKAGAWA Tomoki, YOSHIMOTO Shusuke, KITAHARA Yuki, YANAGIDA Koji, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  The Institute of Electronics, Information and Communication Engineers, 21 Jan. 2014, Technical report of IEICE. ICD, 113(419) (419), 39 - 39, Japanese


• Electrocardiogram analytical technique for wearable living body sensors wearable biomedical sensor

  NAKAI Yozaburo, IZUMI Shintaro, NAKANO Masanao, YAMASHITA Ken, FUJII Takahide, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  The Institute of Electronics, Information and Communication Engineers, 21 Jan. 2014, Technical report of IEICE. ICD, 113(419) (419), 61 - 61, Japanese


• 低消費電力貼り付け型センサのためのテンプレートマッチングを用いたロバスト心拍抽出手法の開発

  中井陽三郎, 和泉慎太郎, 中野将尚, 山下顕, 藤井貴英, 川口博, 吉本雅彦

  2014, センサ・マイクロマシンと応用システムシンポジウム(CD-ROM), 31st


• 5.5 A Reconfigurable Architecture for Dependable Cache(5. Time-Dependent Degradation in Device Characteristics,Dependable VLSI System)

  YOSHIMOTO Masahiko, NAKATA Yohei, KIMI Yuta, Jung Jinwook, KAWAGUCHI Hiroshi

  Reliability Engineering Association of Japan (REAJ), 01 Dec. 2013, The journal of Reliability Engineering Association of Japan, 35(8) (8), 462 - 462, Japanese


• Normally-Off Computing: 4. Normally-off Computing Techniques for Wearable Healthcare Systems

  藤森 敬和, 和泉 慎太郎, 川口 博, 志賀 利一, 吉本 雅彦

  本稿ではウェアラブルな貼り付け型生体情報計測センサにおける課題と，生体信号計測のためのノーマリーオフコンピューティング手法について解説する．また，本研究で試作した貼り付け型生体情報計測センサLSIを紹介する．常時計測可能な貼り付け型生体情報計測センサノードを実現するためには，センサのサイズと重量を可能な限り削減する必要がある．貼り付け型センサノードを構成する要素の内，重量に対して最も支配的な要素はバッテリであり，ノーマリーオフコンピューティングによってセンサLSIの消費電力を極限まで削減することを目指している．

  情報処理学会 ; 1960-, 15 Jun. 2013, 情報処理, 54(7) (7), 677 - 682, Japanese


• 2.5 Soft-Error Tolerant SRAM Cell Layout(2. Radiation-Induced Soft Errors,Dependable VLSI System)

  KAWAGUCHI Hiroshi, YOSHIMOTO Shusuke, OKUMURA Shunsuke, Amashita TAKURO, IZUMI Shintaro, YOSHIMOTO Masahiko

  Reliability Engineering Association of Japan, 2013, The Journal of Reliability Engineering Association of Japan, 35(8) (8), 432 - 432, Japanese


• Introducing Multiple Microphone Arrays for Enhancing Smart Home Voice Control

  Shimpei Soda, Masahide Nakamura, Shinsuke Matsumoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  We have previously developed a voice control system for a home network system (HNS), using a microphone array technology. Although the microphone array achieved a convenient hands-free controller, a single array had limitations on coverage of sound collection and speech recognition rate. In this paper, we try to overcome the limitations by increasing the number of the microphone arrays. Specifically, we construct a microphone array network using four separate arrays, and enhance algorithms of sound source localization (SSL) and sound source separation (SSS) on the network. We also conduct an experimental evaluation, where precision of SSL and speech recognition rate are evaluated in a real HNS test-bed. As a result, it is shown that the usage of multiple arrays significantly improves the coverage and speech recognition ratio, compared with the previous system.

  The Institute of Electronics, Information and Communication Engineers, Jan. 2013, 電子情報通信学会技術研究報告, 112(388) (388), 19 - 24, English


• A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme

  YOSHIMOTO Shusuke, TERADA Masaharu, OKUMURA Shunsuke, SUZUKI Toshikazu, MIYANO Shinji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  This paper presents a novel disturb mitigation scheme which achieves low-power and low-voltage operation for a deep sub-micron SRAM macro. The classic write-back scheme overcame a half-select problem and improved a yield; however, the conventional scheme consumed more power due to charging and discharging all write bitlines (WBLs) in a sub block. Our proposed scheme consists of a floating bitline technique and a low-swing bitline driver (LSBD). This scheme decreases active leakage and active power by 33% and 37% at the FF corner, respectively. In other process corners, more active power reduction can be expected. We fabricated a 512-Kb 8T SRAM test chip that operates at a single 0.5-V supply voltage. The proposed scheme achieves 1.52-μW/MHz active energy in a write cycle and 72.8-MW leakage power, which are 59.4% and 26.0% better than the conventional write-back scheme. The total energy is 12.9 μW/MHz at 0.5 V in a 50%-read / 50%-write operation.

  The Institute of Electronics, Information and Communication Engineers, 16 Apr. 2012, Technical report of IEICE. ICD, 112(15) (15), 73 - 78, Japanese


• C-12-4 A Block-Basis On-Line Built-In Self-Test Architecture for Dependable SRAM

  Fujikawa Asuka, Yoshikawa Masahiro, Okumura Shunsuke, Nakata Yohei, Kagiyama Yuki, Kawaguchi Hiroshi, Yoshimoto Masahiko

  The Institute of Electronics, Information and Communication Engineers, 06 Mar. 2012, Proceedings of the IEICE General Conference, 2012(2) (2), 76 - 76, Japanese


• C-12-1 A 40-nm 0.6-V Operation Half-Select Resilient 8T SRAM with Sequential Writing Technique

  Umeki Youhei, Terada Masaharu, Yoshimoto Shusuke, Kawaguchi Hiroshi, Yoshimoto Masahiko

  The Institute of Electronics, Information and Communication Engineers, 06 Mar. 2012, Proceedings of the IEICE General Conference, 2012(2) (2), 73 - 73, Japanese


• C-12-3 Bit Error Rate Estimation SRAM Considering Temperature Fluctuation

  Kitahara Yuki, Kagiyama Yuki, Okumura Shunsuke, Yanagida Koji, Yoshimoto Shusuke, Nakata Yohei, Izumi Shintaro, Kawaguchi Hiroshi, Yoshimoto Masahiko

  The Institute of Electronics, Information and Communication Engineers, 06 Mar. 2012, Proceedings of the IEICE General Conference, 2012(2) (2), 75 - 75, Japanese


• マイクアレイネットワークを用いたホームネットワークサービス向けハンズフリー音声インタフェース

  SODA Shimpei, NAKAMURA Masahide, MATSUMOTO Shinsuke, MATSUBARA Noriyuki, KUGATA Kouji, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Mar. 2012, 電子情報通信学会技術研究報告, Vol. 111, No. 481, pp.73-78(481(SS2011 57-82)) (481(SS2011 57-82)), Japanese

  Report scientific journal


• Associativity-Variable Cache to Adaptively Expand Operating Voltage Margin

  JUNG Jinwook, NAKATA Yohei, OKUMURA Shunsuke, KAWAGUCHI Hiroshi, Yoshimoto Masahiko

  This paper presents a dependable cache memory for which associativity can be reconfigured dynamically. The proposed associativity-reconfigurable cache consists of pairs of cache ways. The proposed cache can dynamically enhance its reliability in the dependable mode, thereby trading off its performance. The reliability of the proposed cache can be scaled by reconfiguring its associativity. Moreover, the configuration can be chosen based upon current operating conditions. Our chip measurement results show that the proposed dependable cache possesses the scalable characteristic of reliability. Moreover, it can decrease the minimum operating voltage by 115 mV. The cycle accurate simulation shows that designing the L1, L2 caches using the proposed scheme results in 4.93% IPC loss on average. Area estimation results show that the proposed cache adds area overhead of 1.91% and 5.57% in 32-KB and 256-KB caches, respectively.

  The Institute of Electronics, Information and Communication Engineers, 19 Jan. 2012, Technical report of IEICE. ICD, 111(388) (388), 55 - 60, Japanese


• A 75-Variable MIQP Solver Processor for Real-Time Robot Control

  NISHINO Masanori, NOGUCHI Hiroki, SHIMAI Yusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  This paper describes a low-power eight-core Mixed Integer Quadric Programming (MIQP) solver processor VLSI for real-time autonomous robot control. It features an eight-core architecture with operation-level and task-level parallel processing using speculative execution to solve a 75-variable MIQP problem within 100 ms. The VLSI, containing 12.2 M transistors and occupying 2.7×3.0 mm2 area, was designed and fabricated using 40-nm CMOS technology. It consumes 568 mW with 135 MHz operation, allowing real-time, low-power capability for a 75-variable MIQP solver.

  The Institute of Electronics, Information and Communication Engineers, 19 Jan. 2012, Technical report of IEICE. ICD, 111(388) (388), 103 - 107, Japanese


• A 75-Variable MIQP Solver Processor for Real-Time Robot Control

  西野 允雅, 野口 紘希, 嶋井 優介, 和泉 慎太郎, 川口 博, 吉本 雅彦

  本研究では，自律ロボット制御のための実時間混合整数2次計画（MIQP）問題ソルバープロセッサVLSIを提案する．実時間でのMIQP問題求解のために，演算レベルとタスクレベルにおける2つの並列化手法を提案し，8コアによる並列処理アーキテクチャを実現した．40nmCMOSプロセスを用いて提案プロセッサの試作を行い，動作周波数135MHｚ，消費電力568mWにおいて75変数MIQP問題を100ms以内に求解できることを確認した．This paper describes a low-power eight-core Mixed Integer Quadric Programming (MIQP) solver processor VLSI for real-time autonomous robot control. It features an eight-core architecture with operation-level and task-level parallel processing using speculative execution to solve a 75-variable MIQP problem within 100 ms. The VLSI, containing 12.2 M transistors and occupying 2.7 × 3.0 mm2 area, was designed and fabricated using 40-nm CMOS technology. It consumes 568 mW with 135 MHz operation, allowing real-time, low-power capability for a 75-variable MIQP solver.

  12 Jan. 2012, 研究報告計算機アーキテクチャ（ARC）, 2012(19) (19), 1 - 5, Japanese


• Associativity-Variable Cache to Adaptively Expand Operating Voltage Margin

  鄭 晋旭, 中田 洋平, 奥村 俊介, 川口 博, 吉本 雅彦

  本論文では、低電圧動作時における最適なキャッシュの構成が得られる連想度可変キャッシュを提案する。連想度可変キャッシュは 2 つのキャッシュウェイをペアで構成した構造を持ち、メモリセルとして ７T/14T SRAM を使用する。それにより、連想度を可変にすることが可能となり、動作環境に応じて連想度を適切に選ぶことでキャッシュの動作マージンを拡大する。すなわち、動作環境に適したキャッシュの構成を取ることで低電圧動作時の信頼性改善が可能である。実チップの測定に基づく評価の結果、4.93％ の IPC 劣化で最低動作電圧が 115mV 改善できることを確認した｡また､面積評価の結果､32KB キャッシュの場合 1.91％､256KB キャッシュの場合 5.57％ の面積オーバヘッドがあることを確認した。This paper presents a dependable cache memory for which associativity can be reconfigured dynamically. The proposed associativity-reconfigurable cache consists of pairs of cache ways. The proposed cache can dynamically enhance its reliability in the dependable mode, thereby trading off its performance. The reliability of the proposed cache can be scaled by reconfiguring its associativity. Moreover, the configuration can be chosen based upon current operating conditions. Our chip measurement results show that the proposed dependable cache possesses the scalable characteristic of reliability. Moreover, it can decrease the minimum operating voltage by 115 mV. The cycle accurate simulation shows that designing the L1, L2 caches using the proposed scheme results in 4.93% IPC loss on average. Area estimation results show that the proposed cache adds area overhead of 1.91% and 5.57% in 32-KB and 256-KB caches, respectively.

  12 Jan. 2012, 研究報告計算機アーキテクチャ（ARC）, 2012(11) (11), 1 - 6, Japanese


• Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure

  UMEKI Youhei, YOSHIMOTO Shusuke, AMASHITA Takurou, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  This paper presents a new 8T (8-transistor) SRAM cell layout mitigating multiple-bit upset (MBU) in a divided wordline structure. Because bitlines along unselected columns are not activated, the divided wordline structure eliminates a half-select problem and achieves low-power operation, which is often preferred for low-power / low-voltage applications. However, the conventional 8T SRAM with the divided wordline structure engenders MBUs because all bits in the same word are physically adjoining. Consequently, error correction coding (ECC) techniques are difficult to apply. This paper presents a new 8T cell layout pattern that separates internal latches in SRAM cells using both an n-well and a p-substrate. We investigated an SEU cross section of nMOS that is 3.5-4.5 times higher than that of pMOS. Using an iRoC TFIT simulator, we confirmed that the proposed 8T cell has better neutron-induced MBU tolerance. The MBU in the proposed 8T SRAM is improved by 90.70% and the MBU soft error rate (SER) is decreased to 3.46 FIT at 0.9 V when ECC is implemented. Additionally, we conducted Synopsys 3-D TCAD simulation, which indicates that the LET threshold (LETth) in single-event upset (SEU) is also improved by 66.47% in the proposed 8T SRAM by a common-mode effect.

  The Institute of Electronics, Information and Communication Engineers, 15 Dec. 2011, Technical report of IEICE. ICD, 111(352) (352), 161 - 166, Japanese


• A 284-uW 1.85-GHz 20-Phase Oscillator Using Transfer Gate Phase Couplers

  OKUNO Keisuke, KONISHI Toshihiro, LEE Hyeokiong, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  We propose a transfer gate phase coupler for a low-power multi-phase oscillator (MPOSC). The phase coupler is an nMOS transfer gate, which does not waste charge to the ground and thus achieves low power. The proposed MPOSC can set the number of outputs to an arbitrary number. The test circuit in a 180-nm process and a 65-nm process exhibits 20 phases, including 90° different angles. The designs in a 180-nm CMOS process and a 65-nm CMOS process were fabricated to confirm its process scalability; in the respective designs, we observed 36.6% and 38.3% improvements in a power-delay products, compared with the conventional MPOSCs using inverters and nMOS latches. In a 65-nm process, the measured DNL and 3a periodjitter are, respectively, less than ±1.22° and 5.82 ps. The power is 284μW at 1.85 GHz.

  The Institute of Electronics, Information and Communication Engineers, 08 Dec. 2011, Technical report of IEICE. ICD, 111(352) (352), 149 - 154, Japanese


• Dependability evaluation of processor using the dependable SRAM by system-level fault injection

  TAKEUCHI Yusuke, NAKATA Yohei, ITO Yasuhiro, SUGURE Yasuo, OHO Shigeru, OKUMURA Shunsuke, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  We propose a fault-injection system (FIS) that can inject faults such as read/write margin failures and soft errors into a SRAM environment. The fault case generator (FCG) generates time-series SRAM failures in 7T/14T or 6T SRAM, and the proposed device model and fault injection flow are applicable for system-level verification. For evaluation, an abnormal termination rate in vehicle engine control was adopted. We confirmed that the vehicle engine control system with the 7T/14T SRAM improves system-level dependability compared with the conventional 6T SRAM.

  The Institute of Electronics, Information and Communication Engineers, 14 Oct. 2011, IEICE technical report. Computer systems, 111(255) (255), 1 - 6, Japanese


• A Feasibility Study of Home Services Using a Microphone Array Network

  SODA Shimpei, MATSUMOTO Shinsuke, NAKAMURA Masahide, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  The home network system (HNS), which provides value-added services by orchestrating networked home appliances, equipments and sensors, attracts great attention to realize the next-generation smart home. Implementing the location-aware services within the the HNS context is one of greatest challenges, where the appropriate services are performed based according to the location of the inhabitants. We have been studying the technologies of sound source localization and sound source separation using networked multiple microphone arrays. In this paper, we conduct a feasibility study of applying the microphone array network to the location-aware services within the HNS. Specifically, we first present three kinds of home services using illustrative examples. We then enumerate three kinds of requirements (accuracy requirement, installation requirement, user requirement), which are essential for implementing the location-aware home services using the microphone array network. In a preliminary experiment, we evaluate the accuracy requirement using an actual microphone array. Moreover, we conduct a directivity shape simulation assuming multiple arrays.

  The Institute of Electronics, Information and Communication Engineers, 14 Oct. 2011, IEICE technical report. Computer systems, 111(255) (255), 61 - 66, Japanese

  Report scientific journal


• 局所特徴量抽出アルゴリズムのハードウェアコストと精度のトレードオフ解析

  水野孝祐, 寺地陽祐, 黒田光彦, 川口博, 吉本雅彦

  20 Jul. 2011, 画像の認識・理解シンポジウム(MIRU2011)論文集, 2011, 117 - 124, Japanese


• Data-Intensive Sound Acquisition System with Large-scale Microphone Array

  Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi

  We propose a microphone array network that realizes ubiquitous sound acquisition. Several nodes with 16 microphones are connected to form a novel huge sound acquisition system, which carries out voice activity detection (VAD), sound source localization, and sound enhancement. The three operations are distributed among nodes. Using the distributed network, we produce a low-traffic data-intensive array network. To manage node power consumption, VAD is implemented. The system uses little power when speech is not active. For sound localization, a network-connected multiple signal classification (MUSIC) algorithm is used. The experimental result of the sound-source enhancement shows a signal-noise ratio (SNR) improvement of 7.75dB using 112 microphones. Network traffic is reduced by 99.11% when using 1,024 microphones.We propose a microphone array network that realizes ubiquitous sound acquisition. Several nodes with 16 microphones are connected to form a novel huge sound acquisition system, which carries out voice activity detection (VAD), sound source localization, and sound enhancement. The three operations are distributed among nodes. Using the distributed network, we produce a low-traffic data-intensive array network. To manage node power consumption, VAD is implemented. The system uses little power when speech is not active. For sound localization, a network-connected multiple signal classification (MUSIC) algorithm is used. The experimental result of the sound-source enhancement shows a signal-noise ratio (SNR) improvement of 7.75dB using 112 microphones. Network traffic is reduced by 99.11% when using 1,024 microphones.

  15 Mar. 2011, 情報処理学会論文誌, 52(3) (3), 1102 - 1113, English


• Multiple-Bit- Upset Tolerant 8T SRAM Cell Layout with Divided Wordline Structure

  S. Yoshimoto, T. Amashita, D. Kozuwa, T. Takata, M. Yoshimura, Y. Matsunaga, H. Yasuura, H. Kawaguchi, M. Yoshimoto

  Mar. 2011, Proceedings of Silicon Errors in Logic - System Effects (SELSE), pp. 106 -111, English

  [Refereed]

  Others


• Block-Basis On-Line BIST Architecture for Embedded SRAM Using Wordline and Bitcell Voltage Optimal Control

  Masahiro Yoshikawa, Shunsuke Okumura, Yohei Nakata, Yuki Kagiyama, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2011, 2011 12TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), pp. 322- 325, 322 - 325, English

  [Refereed]

  Others


• Fault-Inject ion using Virtualized Environment for Validating Automotive Systems

  伊藤 康宏, 中田 洋平, 川口 博

  情報処理学会, Dec. 2010, 情報処理学会研究報告, 2010(4) (4), 5p, Japanese


• Fault-Injection using Virtualized Environment for Validating Automotive Systems

  ITO Yasuhiro, NAKATA Yohei, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, SUGURE Yasuo, OHO Shigeru

  Fault Injection System: a system level co-simulation environment with fault-injection in memory access was developed. It accepted a fault scenario that includes when and where memory failures occur, and imposed SRAM access failure. A virtual bus-bridge model added in a memory bus of target system disguised SRAM access failure by intervening memory transactions Consequently, it was possible to maintain the tartget system noninvasive from modification. This approach was adopted to a validation of vehicle engine control, as a result a ignition failure occured by SRAM fault was observed

  The Institute of Electronics, Information and Communication Engineers, 22 Nov. 2010, IEICE technical report, 110(316) (316), 119 - 123, Japanese


• An Investigation of Variation-Aware NoC Architecture

  NAKATA Yohei, TAKEUCHI Yukihiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  プロセステクノロジの微細化に伴い，LSI 設計におけるプロセスばらつきによる閾値電圧ばらつきの影響が増加している． 微細プロセスにおける NoC (Network-on-Chip) プロセッサは多くのプロセッサコアによって構成され，プロセスばらつきの影響によって個々のコアの特性が異なるという特徴を持つ．本項では NoC プロセッサにおけるプロセスばらつきの影響を考慮し，影響を抑制可能であるアーキテクチャについて検討を行う．As process technology advances, its minimum feature size decreases, which enables manufacturing with higher density and lower costs. However, technology scaling increases the threshold-voltage (Vth) variation of MOS transistors. NoC processor in an advanced process technology has many cores which have different characteristics individually. This paper shows an investigation of Variation-Aware NoC (Network-on-Chip) Architecture which enables to suppress the effect of process variation.

  情報処理学会, 11 Oct. 2010, 研究報告計算機アーキテクチャ（ARC）, 2010(5) (5), 1 - 5, Japanese


• A 58-uW Sensor Node LSI with Synchronous MAC Protocol

  S. Izumi, T. Takeuchi, T. Matsuda, H. Lee, T. Konishi, K. Tsuruda, Y. Sakai, C. Ohta, H. Kawaguchi, M. Yoshimoto

  Sep. 2010, Proceedings of Asia-aPacific Radio Science Conference (AP-RASC), English

  [Refereed]

  Others


• 分散処理を用いた超低消費電力ネットワーク型マイクロホンアレーの研究

  祖田心平, 久賀田耕史, 高木智也, 和泉慎太郎, 野口紘希, 吉本雅彦, 川口博

  2010, 日本音響学会研究発表会講演論文集(CD-ROM), 2010


• Parallel-Processing VLSI Architecture for Mixed Integer Linear Programming

  Hiroki Noguchi, Junichi Tani, Yusuke Shimai, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2010, 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, pp. 2362-2365, 2362 - 2365, English

  [Refereed]

  Others


• Scalable parallel processing for H.264 encoding application to multi/many-core processor

  Yukihiro Takeuchi, Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2010, Proceedings of 2010 International Conference on Intelligent Control and Information Processing, ICICIP 2010, pp. 163-170(2) (2), 163 - 170, English

  [Refereed]

  Others


• Fast and low-memory-bandwidth architecture of SIFT descriptor generation with scalability on speed and accuracy for VGA video

  Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2010, Proceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010, pp608-611, 608 - 611, English

  [Refereed]

  Others


• 0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM

  Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2010, Proceedings of the International Symposium on Low Power Electronics and Design, pp. 219-224, 219 - 224, English

  [Refereed]

  Others


• A 34.7-mW Quad-Core MIQP Solver Processor for Robot Control

  Hiroki Noguchi, Junichi Tani, Yusuke Shimai, Masanori Nishino, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2010, IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010, English

  [Refereed]

  Others


• 7T SRAM Enabling Low-Energy Simultaneous Block Copy

  Shunsuke Okumura, Shusuke Yoshimoto, Kosuke Yamaguchi, Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2010, IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010, Dig. Tech. Papers, English

  [Refereed]

  Others


• A 58-μW Single-Chip Sensor Node Processor Using Synchronous MAC Protocol

  IZUMI Shintaro, TAKEUCHI Takashi, MATSUDA Takashi, LEE Hyeokjong, KONISHI Toshihiro, TSURUDA Koh, SAKAI Yasuharu, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  In this paper, we propose a single-chip ultra low-power sensor node processor with a synchronous media access control (MAC). It is comprised of a transceiver, i8051 micro processor, and dedicated MAC processor. The test chip occupies 3x3mm^2 in a 180-nm CMOS process, including 1.38M transistors. The power is 58.0μW under a network environment.

  The Institute of Electronics, Information and Communication Engineers, 24 Sep. 2009, IEICE technical report, 109(214) (214), 141 - 145, Japanese


• FPGA implementation of mixed integer quadratic programming solver for mobile robot control

  Yusuke Shimai, Junichi Tani, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2009, Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09, pp. 447-450, 447 - 450, English

  Others


• Variable bandwidth digital bandpass filter for cognitive radio

  TSURUDA Koh, IZUMI Shintaro, LEE Hyeokjong, TAKEUCHI Takashi, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  本論文ではコグニティブ無線向け可変帯域ディジタルBPF(Band-Pass Filter)を用いたベースバンドプロセッサを提案する.BPFにDA(Distributed Arithmetic)アルゴリズムを適応することで,内蔵するSRAMのデータを書き換えるだけでBPFの特性(チャネル中心周波数とバンド幅)を変化させることが可能となる.試作したベースバンドプロセッサではバンド幅を40kHzから240kHzまで10kHz単位で変化させることが可能である.CMOS 180nmプロセスで設計し,電源電圧1.8Vで消費電力は13.5mWであった.

  The Institute of Electronics, Information and Communication Engineers, 15 Oct. 2008, IEICE technical report, 108(253) (253), 137 - 141, Japanese


• A Low-Power Multi Resolution Spectrum Sensing (MRSS) Architecture for a Wireless Sensor Network with Cognitive Radio

  Shintaro Izumi, Koh Tsuruda, Takashi Takeuchi, Hyeokjong Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2008, 2010 FOURTH INTERNATIONAL CONFERENCE ON SENSOR TECHNOLOGIES AND APPLICATIONS (SENSORCOMM), pp. 39-44, 39 - 44, English

  [Refereed]

  Others


• A VGA 30-fps Real-Time Optical-Flow Processor Core for Video Recognition

  ISHIHARA Hajime, MIYAMA Masayuki, MURACHI Yuichiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, MATSUDA Yoshio

  This paper proposes an optical-flow processor for real-time video recognition. This processor is based on the Pyramidal Lucas and Kanade (PLK) algorithm and has smaller chip size, higher resolution and higher accuracy than conventional ones. Introduction of search range limitation and Carman filter to the original algorithm improves accuracy by 0.59°and reduces the processor hardware cost by 96%. Furthermore, the window interleaving and window overlap methods can reduce the necessary clock frequency of the processor by 70%. The proposed processor can handle a VGA 30-fps image sequence with 332MHz clock frequency. The core size and power consumption in 90-nm process technology are estimated as 3.5×3.0mm^2 and 600mW, respectively.

  The Institute of Electronics, Information and Communication Engineers, 06 Dec. 2007, IEICE technical report, 107(382) (382), 65 - 70, Japanese


• Circuits Technologies for Wireless Power Transmission Sheet with Organic FETs and Plastic MEMS Switches

  KAWAGUCHI Hiroshi, TAKAMIYA Makoto, SEKITANI Tsuyoshi, MIYAMOTO Yoshio, NOGUCHI Yoshiaki, SOMEYA Takao, SAKURAI Takayasu

  Design innovations to overcome the shortcomings of a wireless power transmission sheet made with plastic MEMS switches and OFET for printable low-cost electronics are shown. The mixed circuits of MEMS switches and OFETs with two different frequencies reduce the number of coil sheets form 2 to 1. OFET level-shifters, with the current-source loads with enhancement/depletion mixed threshold voltages realized by controlling the back-gate voltage, bridge the operation voltage gap between silicon VLSIs(below 5V) and OFETs/MEMS(above 40V).

  The Institute of Electronics, Information and Communication Engineers, 19 Jul. 2007, IEICE technical report, 107(163) (163), 153 - 158, Japanese


• Circuits technologies for wireless power transmission sheet with organic FETs and plastic MEMS switches

  川口 博, 高宮 真, 関谷 毅

  映像情報メディア学会, Jul. 2007, ITE technical report, 31(34) (34), 153 - 158, Japanese


• A Real-Time Optical-Flow Processor and its Evaluation System Using an FPGA Board

  ISHIHARA Hajime, MIYAMA Masayuki, YAMAMOTO Ryo, FUKUYAMA Yuki, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, MATSUDA Yoshio

  This paper proposes an optical-flow processor architecture for real-time video recognition based on the Pyramidal Lucas & Kanade (PLK) algorithm. This processor is implemented on an FPGA to verify function and performance of the processor. The FPGA processor is able to handle a QCIF-30 image sequence. A real-time evaluation system including the FPGA processor is also constructed. The evaluation system can capture image, calculate its optical flow, and display the optical flow on the image in real-time.

  The Institute of Electronics, Information and Communication Engineers, 08 Jun. 2007, IEICE technical report, 107(94) (94), 1 - 6, Japanese


• A-3-11 A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing

  Iguchi Yusuke, Noguchi H., Fujiwara H., Morita Y., Nii K., Kawaguchi H., Yoshimoto M.

  The Institute of Electronics, Information and Communication Engineers, 07 Mar. 2007, Proceedings of the IEICE General Conference, 2007, 101 - 101, Japanese


• A-21-26 Improvement of Counter-based Broadcasting for Wireless Sensor Networks using Timer Control

  IZUMI S., MATSUDA T., MIKAMI S., KAWAGUCHI H., OHTA C., YOSHIMOTO M.

  The Institute of Electronics, Information and Communication Engineers, 07 Mar. 2007, Proceedings of the IEICE General Conference, 2007, 417 - 417, Japanese


• C-12-42 A Two-port SRAM for Real-Time Video Processor Saving 53% of Bitline Power with Majority Logic and Data-Bit Reordering

  Fujiwara Hidehiro, Nii K., Miyakoshi J., Murachi Y., Noguchi H., Morita Y., Kawaguchi H., Yoshimoto M.

  The Institute of Electronics, Information and Communication Engineers, 07 Sep. 2006, Proceedings of the Society Conference of IEICE, 2006(2) (2), 103 - 103, Japanese


• Dynamic Voltage Scaling in an Elastic Pipeline and Its Application to an H.264/AVC HDTV Video Decoder LSI

  KAWAKAMI Kentaro, TAKEMURA Jun, KURODA Mitsuhiko, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  We propose an elastic pipeline that can apply dynamic voltage scaling (DVS) to hardwired logic circuits. In order to demonstrate its feasibility, a hardwired H.264/AVC HDTV decoder is designed as a real-time application. The designed decoder reduces 48% of execution cycles for H.264 HDTV decoding. In case of DVS is applied with this reduced cycles, the proposed decoder achieves a power reduction of 50% in a 90-nm process technology, compared to the conventional clock-gating scheme.

  Information Processing Society of Japan (IPSJ), 08 Jun. 2006, IPSJ SIG Notes, 2006(62) (62), 31 - 36, Japanese


• 有機トランジスタとプラスチックアクチュエータを集積化したフレキシブルな点字ディスプレイ向けの回路技術

  KAWAGUCHI Hiroshi, TAKAMIYA Makoto, SEKITANI Takeshi, KATO Yusaku, SOMEYA Takao, SAKURAI Takayasu

  Organic FETs (OFETs) are integrated with actuators, and a Braille sheet display is demonstrated. A newly developed back-gated OFETs SRAM and the circuits technology for the Braille sheet display to enhance speed, yield and lifetime are presented, which will be essential for future large-area electronics made with OFETs.

  The Institute of Electronics, Information and Communication Engineers, May 2006, 電子情報通信学会技術研究報告, ICD2006-22、1-6ページ(71) (71), 1 - 6, Japanese

  [Refereed]

  Others


• BS-10-5 Long-lived network by considering production tolerance or sensor node

  Yoshino Hironori, Aonishi Takafumi, Ichien Masumi, Matsuda Takashi, Ohta Chikara, Kawaguchi Hiroshi, Yoshimoto Masahiko

  The Institute of Electronics, Information and Communication Engineers, 08 Mar. 2006, Proceedings of the IEICE General Conference, 2006(2) (2), "S - 72"-"S-73", Japanese


• Low Leakage-power FPGA Design using Zigzag Power-gating, Dual V_/V_

  and Micro-V_

  -Hopping

  TRAN Canh Quang, KAWAGUCHI Hiroshi, SAKURAI Takayasu

  映像情報メディア学会, 26 Jan. 2006, ITE technical report, 30(8) (8), 19 - 24, Japanese


• Low Leakage-power FPGA Design using Zigzag Power-gating, Dual V_/V_

  and Micro-V_

  -Hopping

  TRAN Canh Quang, KAWAGUCHI Hiroshi, SAKURAI Takayasu

  Low-power FPGA architecture is proposed based on fine-grained V_

  control scheme called micro-V_

  -hopping. Four Configurable Logic Blocks (CLB) are grouped into one block where V_

  is shared. In the micro-V_

  -hopping scheme, V_

  of each block is varied between the higher V_

  (V_) and the lower V_

  (V_) spatially and temporally to achieve lower power without performance degraded. A level shifter that has less contention is proposed. The FPGA also incorporates Zigzag power-gating scheme, special care has been taken to cope with sneak leakage path problem. To reduce power dissipated by interconnect, low swing interconnect is adopted. The proposed FPGA is fabricated using 0.35μm CMOS technology together with the conventional fixed-V_

  FPGA. Measurement shows that the dynamic power can be reduced by 86% when the required speed is half of the maximum achievable speed. Simulation using 90nm CMOS technology shows that a leakage power reduction of 95% can be achieved, when the proposed method is used. Area overhead of the proposed FPGA is 2%.

  The Institute of Electronics, Information and Communication Engineers, 19 Jan. 2006, Technical report of IEICE. ICD, 105(569) (569), 19 - 24, Japanese


• Low-Power High-Speed Reduced-Clock-Swing Flip-Flops Based on Contention Reduction Techniques

  YAZID Muhammad, KAWAGUCHI Hiroshi, SAKURAI Takayasu

  VLSIの消費電力の多くの部分を消費しているクロックシステムの低消費電力化は重要な課題である。本論文では、低クロック電圧振幅を用いて低電力化するために必須である、低クロック振幅対応のフリップフロップ回路を提案する。従来と違い、基板バイアスに頼らず、contentionを減少させるメカニズムを導入することにより、低クロック振幅での遅延と消費電力が、それぞれ、従来比30%、20%小さいことがシミュレーションにより示された。

  The Institute of Electronics, Information and Communication Engineers, 16 Dec. 2005, IEICE technical report, 105(476) (476), 19 - 24, English


• A Sheet-Type Scanner Based on a 3D Stacked Organic-Transistor Circuit with Double Word-line and Double Bit-line Structure

  KAWAGUCHI Hiroshi, IBA Shingo, KATO Yusaku, SEKITANI Tsuyoshi, SOMEYA Takao, SAKURAI Takayasu

  Double word-line and bit-line structure in an organic FET-based sheet-type scanner is described. This structure reduces the line delay by a fact or of 5, and the power by a factor of 7. To realize the structure in a pixel array, 3D stacked organic FETs are manufactured. The active leakage is reduced by a dynamic serially connected decoder.

  The Institute of Electronics, Information and Communication Engineers, 19 May 2005, Technical report of IEICE. ICD, 105(95) (95), 19 - 21, Japanese


• Integration of organic transistors and organic photodiodes : Applications to sheet image scanners

  IBA Shingo, KATO Yusaku, SEKITANI Tsuyoshi, KAWAGUCHI Hiroshi, SAKURAI Takayasu, SOMEYA Takao

  映像情報メディア学会, 03 Mar. 2005, ITE technical report, 29(18) (18), 19 - 22, Japanese


• 有機エレクトロニクス 有機材料採用の曲げられるスキャナ回路技術で市販品並みの高速動作

  染谷 隆夫, 桜井 貴康, 川口 博

  電子ペーパーや有機ELパネル，太陽電池，人工皮膚など，有機半導体を利用した曲げられるエレクトロニクス素子の研究開発が活発だ。この分野に新たなデバイスが加わった。東京大学が開発したシート型スキャナである。

  日経BP社, 28 Feb. 2005, 日経エレクトロニクス, (894) (894), 123 - 132, Japanese


• Integration of organic transistors and organic photodiodes : Applications to sheet image scanners

  IBA Shingo, KATO Yusaku, SEKITANI Tsuyoshi, KAWAGUCHI Hiroshi, SAKURAI Takayasu, SOMEYA Takao

  We have manufactured a large-area, flexible, and lightweight sheet image scanner on plastic films, for the first time, integrating high-quality organic transistors and organic photodetectors. The present image-capturing device with organic transistors are shock-resistant and potentially very inexpensive since they requires no optics or moving parts, and therefore suitable for mobile electronics.

  The Institute of Electronics, Information and Communication Engineers, 24 Feb. 2005, Technical report of IEICE. OME, 104(688) (688), 19 - 22, Japanese


• Cut-and-Paste Organic FET Customized ICs for Application to Artificial Skin

  SOMEYA Takao, KAWAGUCHI Hiroshi, SAKURAI Takayasu

  The Concept of cut-and-paste customization is introduced for the first time in designing integrated circuits based on organic field effect transistors. The customized integrated circuits are manufactured by comprising a pressure-sensor array, row decoders, and column selectors to read out pressure information over large area. The pressure-sensor array formed on a plastic film and pressure-sensitive conductive rubber are mechanically flexible, and therefore suitable for electronic artificial skin application. The physical cut-and-paste procedure is employed to make scalable circuits, which are manufactured by cutting a part of the circuits and pasting it to another circuit with a connecting plastic tape. The integrated circuits are designed with a standard SPICE simulator and layout design tool, and the operation is confirmed by measurement.

  The Institute of Electronics, Information and Communication Engineers, 14 May 2004, ISSCC Dig. of Tech. Papers, Feb. 2004, 104(67) (67), 37 - 40, Japanese


• Large-area, flexible sensors for electronic artificial skins : A new class of applications of organic transistors

  SOMEYA Takao, SAKURAI Takayasu, KAWAGUCHI Hiroshi, SEKITANI Tsuyoshi

  応用物理学会, 10 May 2004, 應用物理, 73(5) (5), 610 - 614, Japanese


• Frequency-Voltage Cooperative CPU Poser Control : A Design Rule and Its Application by Feedback Prediction

  TOYAMA Keisuke, MISAKA Satoshi, AISAKA Kazuo, ARITSUKA Toshiyuki, UCHIYAMA Kunio, ISHIBASHI Koichiro, KAWAGUCHI Hiroshi, SAKURAI Takayasu

  周波数-電圧協調型電力制御(FV制御)は,ソフトウェアの負荷情報を利用してハードウェアの動作条件を動的に制御するため,プログラム動作時のCPUの消費電力を低減する効果が大きい.本論文では,このFV制御の方式と効果を解析的に導いて,必要となる周波数決定のルールを得,フィードバック型のアルゴリズムを提案してそれによるFV制御の実装について示した.2種の周波数と電圧によってMPEG-4及びMP3デコーダに適用し,動作時のCPU消費電力の72%を削減している.更に,FV制御の開始時を低周波数とするCool-Start方式で電力削減効果が向上することを示した.

  The Institute of Electronics, Information and Communication Engineers, 01 Apr. 2004, The Transactions of the Institute of Electronics,Information and Communication Engineers., 87(4) (4), 452 - 461, Japanese


• Statistical Leakage Current Reduction by Self - Timed Cut - Off Scheme for High Leakage Environments

  XU Yingxue, CHOI Jin-Hyeok, MIYAZAKI Takayuki, KAWAGUCHI Hiroshi, SAKURAI Takayasu

  This paper describes a statistical leakage current reduction scheme that can reduce leakage current even if the chip is in an active mode. The scheme utilizes a self-timed cut-off switch that puts a given block into a sleep mode if the block is not used for a certain number of cycles. The effectiveness of the proposed scheme is verified by an 8-bit RISC microprocessor using Verilog HDL, and demonstrated by a 64bit carry look-ahead adder fabricated with dual-V SOI technology.

  Information Processing Society of Japan (IPSJ), 23 Oct. 2003, 情報処理学会研究報告システムLSI設計技術（SLDM）, 2003(105) (105), 157 - 162, Japanese


• Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's

  ROBERT SALIBA Fayez, MIN Kyeong-Sik, KAWAGUCHI Hiroshi, KANDA Kouichi, SAKURAI Takayasu

  A new Row-by-Row Dynamic Source-line Voltage control (RRDSV) scheme is proposed to reduce the active leakage as well as the stand-by leakage in SRAM. By dynamically controlling the source-line voltage of cells row by row, the cell leakage through inactive cells can be reduced by two orders of magnitude. Moreover, the bit-line leakage through pass transistors can be completely cut off. This leakage reduction is caused from the cooperation of reverse body-to-source biasing and Drain Induced Barrier Lowering (DIBL) effects. A test chip has been fabricated using 0.18-um triple-well CMOS technology to verify the data retention capability of this RRDSV scheme. The minimum retention voltage in the RRDSV is measured to be reduced by more than 60mV, when shielding metal is inserted to protect the memory cell nodes from bit-line coupling noise. It can reduce the leakage by another 50% in addition to the reduction by two orders of magnitude.

  The Institute of Electronics, Information and Communication Engineers, 17 Oct. 2003, Technical report of IEICE. DSP, 103(380) (380), 71 - 76, English


• Statistical Leakage Current Reduction by Self-Timed Cut-Off Scheme for High Leakage Environments

  XU Yingxue, CHOI Jin-Hyeok, MIYAZAKI Takayuki, KAWAGUCHI Hiroshi, SAKURAI Takayasu

  This paper describes a statistical leakage current reduction scheme that can reduce leakage current even if the chip is in an active mode. The scheme utilizes a self-timed cut-off switch that puts a given block into a sleep mode if the block is not used for a certain number of cycles. The effectiveness of the proposed scheme is verified by an 8-bit RISC microprocessor using Verilog HDL, and demonstrated by a 64bit carry look-ahead adder fabricated with dual-V_ SOI technology.

  The Institute of Electronics, Information and Communication Engineers, 17 Oct. 2003, Technical report of IEICE. DSP, 103(380) (380), 65 - 70, English


• A-3-11 Fast Block-Wise V_

  -Hopping Scheme

  Xu Ying xue, Miyazaki Takayuki, Kawaguchi Hiroshi, Sakurai Takayasu

  The Institute of Electronics, Information and Communication Engineers, 10 Sep. 2003, Proceedings of the Society Conference of IEICE, 2003, 61 - 61, English


• A Low Leakage Power Digital Circuit Scheme for Digital Appliance : Zigzag SCCMOS Scheme

  MIYAZAKI Takayuki, MIN Kyeong-Sik, KAWAGUCHI Hiroshi, SAKURAI Takayasu

  Zigzag Super Cut-off CMOS is proposed as clock-gating replacement in deep sub-micron era. The proposed scheme is applicable in V_

  less than 1-V, since it uses only low threshold voltage transistor in power switches. By inserting the power switches in zigzag, the serially connected transistors in power switch of Super Cut-off CMOS is avoided without any overstresses. Wake-up time of less than 1/3 the clock cycle and three-orders-of-magnitude leakage current reduction are confirmed. A method for switching the higher-man-V_

  and lower-than-VSs voltage is proposed. Furthermore, it is shown that the proposed scheme is applicable to a selector circuit.

  The Institute of Electronics, Information and Communication Engineers, 17 Jul. 2003, Technical report of IEICE. ICD, 103(216) (216), 1 - 6, Japanese


• A O.5V, 400MHz, V_

  -Hopping Processor with Zero-V_ FD-SOI Technology

  KAWAGUCHI Hiroshi, KANDA Kouichi, NOSE Koichi, HATTORI Sadaaki, ANTONO Danardono Dwi, YAMADA Daisuke, MIYAZAKI Takayuki, INAGAKI Kenichi, HIRAMOTO Toshiro, SAKURAI Takayasu

  A 0.5V, 400MHz, V_

  -Hopping processor with zero-V_ FD-SOI was designed and evaluated. The logic blocks use zero-V_ cells for high speed and the memory and register file use high V_

  , high V_ cells to suppress leakage current. The test chip consumes 3.5mW at 0.5V V_

  . Software cooperation scheme namely V_

  -Hopping was shown to be effective in reducing power in leakage dominant era.

  The Institute of Electronics, Information and Communication Engineers, 22 May 2003, Technical report of IEICE. ICD, 103(89) (89), 55 - 58, Japanese


• 1.27Gb/s/pin, 3mW/pin Wireless Superconnect (WSC) Interface Scheme

  KANDA Kouichi, ANTONO Danardono Dwi, ISHIDA Koichi, KAWAGUCHI Hiroshi, KURODA Tadahiro, SAKURAI Takayasu

  A low-power high-speed chip-to-chip interface scheme is described having a density of 625pins/mm^2. The interface utilizes capacitively coupled contactless minipads, return-to-V_

  /2 signaling and sense amplifying flip-flops. The measured test chip fabricated in 0.35μm CMOS delivers up to 1.27Gb/s/pin at 3mW/pin.

  The Institute of Electronics, Information and Communication Engineers, 21 May 2003, Technical report of IEICE. ICD, 103(88) (88), 19 - 22, Japanese


• Design Rule and its Algorithm for Frequency-Voltage Cooperative Power Control

  AISAKA Kazuo, ARITSUKA Toshiyuki, MISAKA Satoshi, TOYAMA Keisuke, UCHIYAMA Kunio, ISHIBASHI Koichiro, KAWAGUCHI Hiroshi, SAKURAI Takayasu

  Frequency-voltage cooperative power control (FVC) is considered a powerful method to reduce the power consumption because of its dynamic feature. The authors first give a minute evaluation with the two-to-one frequency rule already proposed, under the restriction of operation voltage limit. Then we give an design algorithm for an FVC system which includes the decision criteria for the number of(F, V) sets to be prepared in the FVC system.

  The Institute of Electronics, Information and Communication Engineers, 16 Aug. 2002, Technical report of IEICE. ICD, 102(274) (274), 49 - 52, Japanese


• Design Rule and its Algorithm for Frequency-Voltage Cooperative Power Control

  AISAKA Kazuo, ARITSUKA Toshiyuki, MISAKA Satoshi, TOYAMA Keisuke, UCHIYAMA Kunio, ISHIBASHI Koichiro, KAWAGUCHI Hiroshi, SAKURAI Takayasu

  Frequency-voltage cooperative power control (FVC) is considered a powerful method to reduce the power consumption because of its dynamic feature. The authors first give a minute evaluation with the two-to-one frequency rule already proposed, under the restriction of operation voltage limit. Then we give an design algorithm for an FVC system which includes the decision criteria for the number of (F, V) sets to be prepared in the FVC system.

  The Institute of Electronics, Information and Communication Engineers, 16 Aug. 2002, Technical report of IEICE. SDM, 102(272) (272), 49 - 52, Japanese


• Design Rule for Frequency-Voltage Cooperative Power Control and Its Application to an MPEG-4 Decoder

  AISAKA Kazuo, ARITSUKA Toshiyuki, MISAKA Satoshi, TOYAMA Keisuke, UCHIYAMA Kunio, ISHIBASHI Koichiro, KAWAGUCHI Hiroshi, SAKURAI Takayasu

  Frequency-voltage cooperative power control (FVC) is considered a powerful method to reduce the power consumption of a program, because it utilizes the information of software loads dynamically. The authors first show through a mathematical analysis that a two-to-one rule is sufficient to prepare the frequency sets with a FVC system. Then we show an experimental result that FVC feedback control on an MPEG-4 video decoder can reduce the power to one-fourth.

  The Institute of Electronics, Information and Communication Engineers, 18 Jul. 2002, Technical report of IEICE. ICD, 102(234) (234), 13 - 16, Japanese


• Coupling-driven bus design for low-power application-specific systems

  YAMADA Daisuke, SHIN Youngsoo, KAWAGUCHI Hiroshi, SAKURAI Takayasu

  In modern embedded systems including communication and multimedia applications, large fraction of power is consumed during memory access. Thus, buses should be designed and optimized to consume reasonable power while delivering sufficient performance. In this paper, we address a bus ordering problem for low-power application-specific systems. A heuristic algorithm is proposed to determine the order in a way that effective lateral component of capacitance is reduced, thereby reducing the power consumed by buses. Experimental results for various examples indicate that the average power saving from 30% to 46.7% depending on capacitance components can be obtained without any circuit overhead.

  The Institute of Electronics, Information and Communication Engineers, 17 Aug. 2001, Technical report of IEICE. ICD, 101(266) (266), 1 - 8, Japanese


• Cooperative Voltage Scaling (CVS) and V_

  -Hopping among OS, Applications and Hardware for Low-Power Real-Time Embedded Systems

  KAWAGUCHI Hiroshi, ZHANG Gang, LEE Seongsoo, SHIN Youngsoo, SAKURAI Takayasu

  Power-efficient design of real-time embedded systems becomes more important as system functionality is increasingly realized by software. This paper presents a cooperative power-optimization scheme among an operation system, application programs and hardware. This scheme is shown to reduce the power to less than 1/4 compared to the conventional rate-monotonic scheduling with fixed supply voltage. The power saving is achieved without degrading the real-time features.

  The Institute of Electronics, Information and Communication Engineers, 18 May 2001, Technical report of IEICE. ICD, 101(85) (85), 59 - 65, Japanese


• V_-hopping Scheme in Low-Voltage and Low-Power Processors

  NOSE Koichi, HIRABAYASHI Masayuki, KAWAGUCHI Hiroshi, LEE Seongsoo, SAKURAI Takayasu

  A threshold voltage hopping (V_-hopping) scheme is proposed where V_ is dynamically controlled through software depending on a workload. V_-hopping is shown to reduce the power to 18% of the fixed low-V_ circuits in 0.5V supply voltage regime for multimedia applications. A positive back-gate bias scheme within V_-hopping is presented for the high-performance and low-voltage processors. The measurement result shows about 90% power reduction is possible by using V_-hopping.

  The Institute of Electronics, Information and Communication Engineers, 18 May 2001, Technical report of IEICE. ICD, 101(85) (85), 67 - 73, Japanese


• Abnormal Leakage Suppression (ALS) scheme for low standby current SRAMs

  KANDA Kouichi, MINH Nguyen Duc, KAWAGUCHI Hiroshi, SAKURAI Takayasu

  Abnormal Leakage Suppression (ALS) scheme is proposed to repair standby current errors in SRAMs. By introducing Leakage sensors, shift registers and fuses, the ALS senses 1μA of abnormal leakage, isolates the memory cell from V_

  lines and thus suppresses abnoamal leakage current. A 64Kbit test SRAM is fabricated and the effectiveness is demonstrated. The area overhead is 7%.

  The Institute of Electronics, Information and Communication Engineers, 05 Apr. 2001, Technical report of IEICE. ICD, 101(1) (1), 21 - 25, Japanese


• Boosted Gate MOS (BGMOS) : Leakage-Free Circuits by Device/Circuit Cooperation Scheme

  INUKAI T., TAKAMIYA M., NOSE K., KAWAGUCHI H., SAKURAI T., HIRAMOTO T.

  An increase of stand-by power is one of the most important issues in future LSI devices. In this paper, a new device/circuit cooperation scheme, Boosted Gate MOS(BGMOS), is proposed to achieve leakage free circuits. In the proposed scheme, CMOS circuits consist of MOSFETs with low V_ and ultra-thin oxide to obtain hign speed and low voltage operation. On the other hand, low leakage devices with hign V_ and thick oxide are inserted in series with CMOS circuits and driven by higher gate voltage to achieve extremely low stand-by power while maintaining small area penalty. The application of the proposed scheme to other components such as SRAMs is also discussed.

  The Institute of Electronics, Information and Communication Engineers, 18 Aug. 2000, IEICE technical report. Electron devices, 100(266) (266), 1 - 8, Japanese


• A CMOS Scheme for 0.5V Supply Voltage with Pico-Ampere Standby Current

  KAWAGUCHI Hiroshi, NOSE Kouichi, SAKURAI Takayasu

  If a VLSI should be operated in 0.5V〜0.8V VDD range for low-power consumption, the threshold voltage of MOSFET's VTH, should be well below 0.5V to turn the MOSFET's on.The low VTH like 0.1V〜0.2V, however, causes 10nA order subthreshold leakage current per logic gate in a standby mode, which leads to 10mA order standby current for one million gate VLSI's.In this paper, super cut-off CMOS(SCCMOS) circuit is proposed to overcome this situation.With the SCCMOS, an operation is possible under 0.5V〜0.8V VDD with 0.1V〜0.2V VTH and at the same time pA order standby current per logic gate can be achieved.

  The Institute of Electronics, Information and Communication Engineers, 23 Jul. 1998, Technical report of IEICE. ICD, 98(195) (195), 45 - 49, English


• A CMOS Scheme for 0.5V Supply Voltage with Pico-Ampere Standby Current

  KAWAGUCHI Hiroshi, NOSE Kouichi, SAKURAI Takayasu

  If a VLSI should be operated in 0.5V-0.8V VDD range for low-power consumption, the threshold voltage of MOSFET's, VTH, should be well below 0.5V to turn the MOSFET's on. The low VTH like 0.1V-0.2V, however, causes 10nA order subthreshold leakage current perlogic gate in a standby mode, which leads to 10mA order standby current for one million gate VLSI's. In this paper, super cut-off CMOS(SCCMOS)circuit is proposed to overcome this situation. With the SCCMOS, an operation is possible under 0.5V-0.8V VDD with 0.1V-0.2V VTH and at the same time pA order standby current per logic gate can be achieved.

  The Institute of Electronics, Information and Communication Engineers, 23 Jul. 1998, Technical report of IEICE. SDM, 98(193) (193), 45 - 49, English


• Dynamic Leakage Cut-off Scheme for Low-Voltage SRAM's

  KAWAGUCHI Hiroshi, ITAKA Yasuhito, SAKURAI Takayasu

  A 0.5V SRAM circuit scheme is proposed and fabricated which speeds up the conventional low-voltage SRAM by a factor of 2.5 without applying excessive voltage to gate oxide and with maintaining the subthreshold leakage current in a tolerable level. N-and P-well bias voltage are dynamically changed to V_

  and V_ respectively for selected memory cells, while the well bias of the dormant memory cells are kept 2V_

  and -V_

  .

  The Institute of Electronics, Information and Communication Engineers, 19 Jun. 1998, IEICE technical report. Electron devices, 98(117) (117), 1 - 4, Japanese

• 光電式容積脈波法による脈拍測定の低消費電力化手法

  WATANABE Kento, IZUMI Shintaro, YANO Yuji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  ヘルスケア・医療情報通信技術研究会（MICT）, Jan. 2019, Japanese, 電子情報通信学会, 東京都千代田区明治大学駿河台キャンパス, Domestic conference

  Oral presentation


• ウェアラブルデバイスのための心拍変動モニタリングにおけるサンプリングレート低減手法

  NISHIKAWA Yuki, IZUMI Shintaro, YANO Yuji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  第35回「センサ・マイクロマシンと応用システム」シンポジウム, Oct. 2018, Japanese, 電気学会 センサ・マイクロマシン部門, 北海道札幌市 札幌市民交流プラザ, Domestic conference

  Poster presentation


• ウェアラブルデバイスのための圧電素子を用いたマルチモーダルな心血管情報の計測

  OKANO Takaaki, IZUMI Shintaro, KATSUURA Takumi, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  第34回「センサ・マイクロマシンと応用システム」シンポジウム，01am2-PS-135，広島，2017年11月1日, Nov. 2017, Japanese, Domestic conference

  Oral presentation


• 消化管内への留置を目的とした飲み込み型デバイスの検討

  NAKAMURA Ryota, IZUMI Shintaro, KAWAGUCHI Hiroshi, OHTA Hidetoshi, YOSHIMOTO Masahiko

  第34回「センサ・マイクロマシンと応用システム」シンポジウム，31pm3-PS-46，広島，2017年10月31日, Oct. 2017, Japanese, Domestic conference

  Oral presentation


• ノイズフィードバック技術を用いたウェアラブル向け容量結合型心電センサ

  NAGASATO Yuki, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  IEICEソサイエティ大会, 2017年9月12-15日，東京, Sep. 2017, Japanese, Domestic conference

  Oral presentation


• 選択的ソース線駆動方式を用いた画像処理プロセッサ向け低消費電力28nm FD-SOI 8TデュアルポートSRAM

  MORI Haruki, NAKAGAWA Tomoki, KITAHARA Yuki, KAWAMOTO Yuta, TAKAGI Kenta, YOSHIMOTO Shusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  LSIとシステムのワークショップ2017 ポスターセッション, 東京, 2017年5月, May 2017, Japanese, Domestic conference

  Oral presentation


• マイクロ波ドップラーセンサを用いた車両走行中の心拍計測手法

  MATSUNAGA DAICHI, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  電子情報通信学会総合大会，B-20-10, 名古屋, 2017年3月22日., Mar. 2017, Japanese, 名古屋, Domestic conference

  Oral presentation


• プロセスばらつき耐性を有する低電圧動作STT-MRAM向けカウンターベース読出し回路

  UMEKI YOHEI, YANAGIDA KOUJI, YOSHIMOTO SHUSUKE, IZUMI SHINTARO, YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, TSUNODA KOJI, SUGII TOSHIHIRO

  LSIとシステムのワークショップ2016, May 2016, Japanese, Domestic conference

  Poster presentation


• 消化管内に留置可能な飲み込み型生体センサー

  IZUMI Shintaro, NAKAMURA Ryota, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  電子情報通信学会総合大会, Mar. 2016, Japanese, 福岡, Domestic conference

  Oral presentation


• ヘルスケアデバイスから見た材料科学への期待

  KAWAGUCHI Hiroshi

  日本化学会第96春季年会, Mar. 2016, Japanese, 京都, Domestic conference

  [Invited]

  Invited oral presentation


• Process variation tolerant counter base read circuit for low-voltage operating STT-MRAM

  UMEKI Yohei, YANAGIDA Koji, KUROTSU Hiroaki, KITAHARA Hiroto, MORI Haruki, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, YOSHIMOTO Shusuke, TSUNODA Koji, SUGII Toshihiro

  DATE EMS Workshop, Mar. 2016, English, Dresden,Germany, International conference

  Poster presentation


• Analysis of Soft Error Propagation considering Masking Effects on Re-convergent Path

  KIMI Yuta, MATSUKAWA Go, YOSHIDA Shuhei, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  IEEE Asian Test Symposium (ATS), Nov. 2015, English, International conference

  Oral presentation


• A 298-fJ/writecycle 650-fJ/readcycle 8T Three-Port SRAM in 28-nm FD-SOI Process Technology for Image Processor

  MORI Haruki, NAKAGAWA Tomoki, KITAHARA Yuki, KAWAMOTO Yuta, TAKAGI Kenta, YOSHIMOTO Shusuke, IZUMI Shintaro, Nii Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  IEEE Custom Integrated Circuits Conference (CICC), Sep. 2015, English, International conference

  Oral presentation


• 時間デジタル変換器を用いたIOサイズ8bitAD変換器

  OKUNO Keisuke, 小西恵大, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi

  LSIとシステムのワークショップ2015 ポスターセッション, May 2015, Japanese, 小倉, Domestic conference

  Poster presentation


• ウェアラブル心電図計測SoC

  TANAKA Yoshito, NAKAI Yozaburo, KAWAMOTO Yuta, OKUNO Keisuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, KIMURA Hiromitsu, MURAMOTO Kyoji, FUCHIKAMI Takaaki, FUJIMORI Yoshikazu, YOSHIMOTO Masahiko

  LSIとシステムのワークショップ2015, May 2015, Japanese, 小倉, Domestic conference

  Poster presentation


• 6T4C型低消費電力不揮発メモリ

  KITAHARA Hiroto, NAKAGAWA Tomoki, IZUMI Shintaro, TANAGIDA Kouji, KITAHARA Yuki, YOSHIMOTO Shusuke, UMEKI Yohei, MORI Haruki, KAWAGUCHI Hiroshi, KIMURA Hiromitsu, MURAMOTO Kyoji, FUCHIKAMI Takaaki, FUJIMORI Yoshikazu, YOSHIMOTO Masahiko

  LSIとシステムのワークショップ2015, May 2015, Japanese, 小倉, Domestic conference

  Poster presentation


• 温度補償回路を用いた高速セットリングADPLL

  奥野 圭祐, 正木 何奈, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  第37回アナログRF研究会, Dec. 2014, Japanese, Domestic conference

  Oral presentation


• 低消費電力貼り付け型センサのためのテンプレートマッチングを用いたロバスト心拍抽出手法の開発

  中井 陽三郎, IZUMI SHINTARO, 中野 将尚, 山下 顕, 藤井 貴英, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  第31回「センサ・マイクロマシンと応用システム」シンポジウム, Oct. 2014, Japanese, Domestic conference

  Oral presentation


• 動作環境変動に応じて動的に動作マージンを拡大する自律制御キャッシュ

  KIMI YUTA, NAKATA YOHEI, OKUMURA SYUNSUKE, JUNG Jinwook, 澤田 卓也, 利川 托, NAGATA MAKOTO, 中野 博文, 藪内 誠, 藤原 英弘, 新居 浩二, 河合 浩行, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  LSIとシステムのワークショップ2014 ポスターセッション, May 2014, Japanese, 小倉, Domestic conference

  Poster presentation


• 磁性変化型メモリの書き込み高速化メモリアーキテクチャ

  森 陽紀, 柳田 晃司, 梅木 洋平, 吉本秀輔, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO, 角田 浩司, 杉井 寿博

  LSIとシステムのワークショップ2014 ポスターセッション, May 2014, Japanese, 電子情報通信学会集積回路研究専門委員会, 小倉, Domestic conference

  Poster presentation


• 温度補償回路を用いた高速セットリングADPLL

  正木 何奈, 奥野 圭祐, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  LSIとシステムのワークショップ2014 ポスターセッション, May 2014, Japanese, 電子情報通信学会集積回路研究専門委員会, 小倉, Domestic conference

  Poster presentation


• 一括コピー・比較が可能なSRAMを用いた低遅延デュアルコアロックステップアーキテクチャ

  吉田 周平, 松川 豪, 中田 洋平, 木美 雄太, 勝 康夫, 下澤 晶史, 於保 茂, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  LSIとシステムのワークショップ2014 ポスターセッション, May 2014, Japanese, 電子情報通信学会集積回路研究専門委員会, 小倉, Domestic conference

  Poster presentation


• 38μAウェアラブル生体情報計測プロセッサ

  中井 陽三郎, IZUMI SHINTARO, 山下 顕, 中野 将尚, 藤井 貴英, 小西 恵大, KAWAGUCHI HIROSHI, 木村 啓明, 丸元 共治, 渕上 貴昭, 藤森 敬和, 中嶋 宏, 志賀 利一, YOSHIMOTO MASAHIKO

  LSIとシステムのワークショップ2014 ポスターセッション, May 2014, Japanese, Domestic conference

  Poster presentation


• ロバストな瞬時心拍抽出機能を有する低消費電力ウェアラブルヘルスケアシステム

  IZUMI Shintaro, NAKANO Masanao, YAMASHITA Ken, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  第14回計測自動制御学会システムインテグレーション部門講演会SI2013, Dec. 2013, Japanese, 神戸市, Domestic conference

  [Invited]

  Invited oral presentation


• 読出しビット線振幅制限機構及び読み出し加速回路を備えた8T SRAM

  UMEKI Yohei, YOSHIMOTO Shusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference

  Poster presentation


• 車載ECUのSRAMへの故障注入による自動車制御システムの挙動評価

  FUJIKAWA Asuka, TAKEUCHI Yusuke, NAKATA Yohei, 伊藤 康宏, 勝 康夫, 於保 茂, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference

  Poster presentation


• 核反応シミュレータを用いたソフトエラー率導出ツール及び耐マルチビットエラー6T SRAM

  YOSHIMOTO Shusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference

  Poster presentation


• ラウドコンピュータを用いたディペンダブルプロセッサの大規模故障注入評価

  MATSUKAWA Go, NAKATA Yohei, 伊藤 康宏, TAKEUTCI Yusuke, 勝 康夫, 於保 茂, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference

  Poster presentation


• ゼロデータを利用したSTT-RAMキャッシュの低エネルギー化設計

  KIMI Yuta, JUNG Jinwook, NAKATA Yohei, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi

  LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference

  Poster presentation


• HDTV解像度対応 実時間HOG特徴量抽出と複数物体検出を実現する43mWデュアルコアプロセッサ

  TKAGI Kenta, MIZUNO Kosuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference

  Poster presentation


• 65nm 700-μm2 61-dB 低ジッター2次ΔΣT-D変換器

  OKUNO Keisuke, KONISHI Toshihiro, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi

  LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference

  Poster presentation


• ウェアラブルヘルスケアシステムのための 短時間自己相関を用いた瞬時心拍検出手法

  中野将尚, 小西恵大, 和泉慎太郎, 川口博, YOSHIMOTO MASAHIKO

  電気学会センサ・マイクロマシン部門大会, Oct. 2012, Japanese, 北九州, Domestic conference

  Public symposium


• 低電圧動作マージン拡大機能を有する連想度可変キャッシュ

  鄭晋旭, 中田洋平, 奥村俊介, 川口博, YOSHIMOTO MASAHIKO

  LSIとシステムのワークショップ 2012, May 2012, Japanese, 北九州, Domestic conference

  Poster presentation


• プロセスばらつきを考慮したNoCアーキテクチャ

  中田洋平, 川口博, YOSHIMOTO MASAHIKO

  LSIとシステムのワークショップ 2012, May 2012, Japanese, 北九州, Domestic conference

  Poster presentation


• 6万語彙実時間連続音声認識のための40nm, 144mW音声認識専用プロセッサの開発

  何光霽, 菅原隆伸, 藤永剛史, 宮本優貴, 野口紘希, 和泉慎太郎, 川口博, YOSHIMOTO MASAHIKO

  LSIとシステムのワークショップ 2012, May 2012, Japanese, 北九州, Domestic conference

  Poster presentation


• 40nm 640μm2 7.2bit プロセススケーラブル・オペアンプレス時間演算型AD変換器

  小西恵大, 奥野圭祐, 和泉慎太郎, 吉本雅彦, KAWAGUCHI HIROSHI

  LSIとシステムのワークショップ 2012, May 2012, Japanese, 北九州, Domestic conference

  Poster presentation


• 0.5V 12.9pJ/accessを実現する低電力ライトバック技術を備えた40nm 8T SRAM

  吉本秀輔, 寺田正治, 奥村俊介, 鈴木利一, 宮野信治, 川口博, YOSHIMOTO MASAHIKO

  LSIとシステムのワークショップ 2012, May 2012, Chinese, 北九州, Domestic conference

  Poster presentation


• 温度変化を考慮したSRAMのBER導出手法の検討

  KITAHARA Yuki, KAGIYAMA Yuki, OKUMURA Shunsuke, YANAGIDA Koji, YOSHIMOTO Syusuke, NAKATA Yohei, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  電子情報通信学会総合大会, Mar. 2012, Japanese, 電子情報通信学会, 岡山市, Domestic conference

  Oral presentation


• マイクアレイネットワークを用いたホームネットワークサービス向けハンズフリー音声インタフェース

  SODA_Shinpei, NAKAMURA_Masahide, MAtSUMOTO_Shinsuke, MATSUBARA_Noriyuki, KUGATA_Koji, 和泉 慎太郎_IZUMI_Shintaro, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  電子情報通信学会研究会, Mar. 2012, Japanese, 電子情報通信学会集積回路研究専門委員会, 那覇市, Domestic conference

  Oral presentation


• ディペンダブルSRAMのためのオンライン故障診断技術の開発

  FUJIKAWA Asuka, YOSHIKAWA Masahiro, OKUMURA Shunsuke, NAKATA Yohei, KAGIYAMA Yuki, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  電子情報通信学会総合大会, Mar. 2012, Japanese, 電子情報通信学会, 岡山市, Domestic conference

  Oral presentation


• 0.6V動作可能なハーフセレクト耐性を向上させる差動書込み技術を用いた40-nm 8T SRAM

  UMEKI_Yohei, TERADA_Masaharu, YOSHIMOTO_Syusuke, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  電子情報通信学会総合大会, Mar. 2012, Japanese, 電子情報通信学会, 岡山市, Domestic conference

  Oral presentation


• 低電圧動作におけるマージン拡大機能を有する連想度可変キャッシュ

  JUNG_JinWook, NAKATA_Yohei, OKUMURA_Shunsuke, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  電子情報通信学会研究会, Jan. 2012, Japanese, 電子情報通信学会集積回路研究専門委員会, 東京, Domestic conference

  Oral presentation


• 実時間ロボット制御のための75変数MIQP問題ソルバープロセッサ

  NISHINO Masanori, NOGUCHI Hiroki, SHIMAI Yusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  電子情報通信学会研究会, Jan. 2012, Japanese, 電子情報通信学会集積回路研究専門委員会, 東京, Domestic conference

  Oral presentation


• 低電力20相出力発振回路

  OKUNO_Keisuke, KONISHI_Toshihiro, LEE_Hyeokjong, 和泉 慎太郎_IZUMI_Shintaro, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  電子情報通信学会研究会, Dec. 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 大阪, Domestic conference

  Oral presentation


• マルチビットアップセット耐性及びシングルビットアップセット耐性を備えた8T SRAM セルレイアウト

  UMEKI_Yohei, YOSHIMOTO_Syusuke, AMASHITA_Takro, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  電子情報通信学会研究会, Dec. 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 大阪, Domestic conference

  Oral presentation


• チップ間ばらつき及びチップ内ばらつきを抑制する基板バイアス制御回路を備えた0.42-V 576-Kb 0.15-um FD-SOI 7T/14T SRAM

  YOSHIMOTO Syusuke, YAMAGUCHI Kosuke, OKUMURA Shunsuke, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi

  電子情報通信学会研究会 (2011), Dec. 2011, Japanese, Domestic conference

  Poster presentation


• 6万語彙実時間連続音声認識のための40nm,144mW音声認識専用プロセッサの開発

  SUGAHARA_Takanobu, HE_Guangji, FUJINAGA_Tsuyoshi, MIYAMOTO_Yuki, NOGUCHI_Hiroki, 和泉 慎太郎_IZUMI_Shintaro, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  デザインガイア2011, Nov. 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 宮崎市, Domestic conference

  Oral presentation


• 故障注入技術を用いたディペンダブルSRAMを搭載するプロセッサの信頼性評価・検証

  TAKEUCHI_Yusuke, NAKATA_Yohei, ITO_Yasuhiro, SUGURE_Yasuo, OHO_Shigeru, OKUMURA_Shunsuke, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  コンピュータシステム研究会, Oct. 2011, Japanese, 電子情報通信学会, 神戸市, Domestic conference

  Oral presentation


• マイクアレイネットワークを用いた宅内サービス実現可能性の検討

  SODA_Shinpei, NAKAMURA_Masahide, MAtSUMOTO_Shinsuke, MATSUBARA_Noriyuki, KUGATA_Koji, 和泉 慎太郎_IZUMI_Shintaro, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  コンピュータシステム研究会, Oct. 2011, Japanese, 電子情報通信学会, 神戸市, Domestic conference

  Oral presentation


• 低電力20相出力発振回路

  OKUNO_Keisuke, KONISHI_Toshihiro, 和泉 慎太郎_IZUMI_Shintaro, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  LSIとシステムのワークショップ 2011, May 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference

  Poster presentation


• 次世代知能ロボット制御のための混合整数2次計画問題(MIQP)ソルバーコアプロセッサ

  NISHINO Masanori, NOGUCHI Hiroki, TANI Junichi, SHIMAI Yusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  LSIとシステムのワークショップ 2011, May 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference

  Poster presentation


• マルチビットアップセット耐性を備えた8T SRAMセルレイアウト

  AMASHITA_Takro, YOSHIMOTO_Syusuke, KOZUWA_Daisuke, TAKATA_Taiga, YOSHIMURA_Masayoshi, MATSUNAGA_Yusuke, YASUURA_Hiroto, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  LSIとシステムのワークショップ 2011, May 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference

  Poster presentation


• ブロックデータ一括コピー機能を有する7T SRAM

  KAGIYAMA_Yuki, OKUMURA_Shunsuke, YOSHIMOTO_Syusuke, NAKATA_Yohei, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  LSIとシステムのワークショップ 2011, May 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference

  Poster presentation


• フルHDTV実時間動画像認識のための低消費電力SIFT特徴量抽出プロセッサ

  TERACHI_Yosuke, MIZUNO_Kosuke, HE_Guangji, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  LSIとシステムのワークショップ 2011, May 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference

  Poster presentation


• ビットエラー耐性及びソフトエラー耐性を備えたFD-SOI 7T/14T SRAM

  吉本 秀輔, 天下 卓郎, 奥村 俊介, 山口 幸介, 吉本 雅彦, 川口 博

  LSIとシステムのワークショップ 2011, May 2011, Japanese, 北九州市, Domestic conference

  Poster presentation


• システムレベル故障注入技術によるディペンダブルメモリを搭載したプロセッサの評価・検証

  TAKEUCHI_Yusuke, NAKATA_Yohei, ITO_Yasuhiro, SUGURE_Yasuo, OHO_Shigeru, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  LSIとシステムのワークショップ 2011, May 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference

  Poster presentation


• 18TデュアルポートSRAM

  YANAGIDA Koji, NOGUCHI Hiroki, OKUMURA Shunsuke, TAKAGI Tomoya, KUGATA Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  LSIとシステムのワークショップ 2011, May 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference

  Poster presentation


• 7T/14T SRAMの細粒度制御による低電圧動作キャッシュアーキテクチャ

  JUNG JinWook, NAKATA Yohei, OKUMURA Shunsuke, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  LSIとシステムのワークショップ 2011, May 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference

  Poster presentation


• 18TデュアルポートSRAM

  YANAGIDA Koji, NOGUCHI Hiroki, OKUMURA Shunsuke, TAKAGI Tomoya, KUGATA Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  電子情報通信学会研究会, Apr. 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 神戸市, Domestic conference

  Poster presentation


• プロセスばらつきを考慮したNoCアーキテクチャの検討

  中田 洋平, 竹内 幸大, 川口 博, 吉本 雅彦

  情報処理学会研究報告 計算機アーキテクチャ(ARC), Oct. 2010, Japanese, Domestic conference

  Others


• 分散処理を用いた超低消費電力 ネットワーク型マイクロホンアレーの研究

  祖田 心平, 久賀田 耕史, 高木 智也, 和泉 慎太郎, 野口 紘希, 吉本 雅彦, 川口 博

  日本音響学会2010年秋季研究発表会, Sep. 2010, Japanese, 関西大学, Domestic conference

  Poster presentation


• マルチコアプロセッサにおけるH.264/AVC符号化処理の並列度とメモリアクセスに関する高効率実装

  中田 洋平, 竹内 幸大, 川口 博, 吉本 雅彦

  DAシンポジウム2010, Sep. 2010, Japanese, 豊橋市, Domestic conference

  Poster presentation


• 高精度音源定位および音源分離機能を有する低消費電力ユビキタス・センサネットの開発

  TAKAGI Tomoya, 川口 博, 吉本 雅彦

  STARCフォーラム/シンポジウム2009, Aug. 2010, Japanese, Domestic conference

  Poster presentation


• ネットワーク分散処理を用いた超低消費電力音声信号処理プロセッサ

  久賀田 耕史, 野口 紘希, 高木 智也, 祖田 心平, 吉本 雅彦, 川口 博

  STARC フォーラム/シンポジウム２０１０, Aug. 2010, Japanese, 横浜市, Domestic conference

  Poster presentation


• 分散処理型ユビキ タスセンサネットワークのための超低消費電力音声処理プロセッサ

  高木 智也, 野口 紘希, 久賀田 耕史, 吉本 雅彦, 川口 博

  LSIとシステムのワークショップ 2010, May 2010, Japanese, 北九州市, Domestic conference

  Poster presentation


• 知能ロボットのためのマルチコアMIQPソルバープロセッサのFPGA実装

  嶋井 優介, 谷 純一, 野口 紘輝, H. Kawaguchi, M. Yoshimoto

  LSIとシステムのワークショップ 2010, May 2010, Japanese, 北九州, Domestic conference

  Poster presentation


• 大語彙連続音声認識のための並列Viterbiプロセッサアーキテクチャ

  藤永 剛史, 三浦 和夫, 野口 紘輝, 川口 博, M. Yoshimoto

  LSIとシステムのワークショップ 2010, May 2010, Japanese, 北九州, Domestic conference

  Poster presentation


• ワイヤレスセンサネットワークのためのΔ-Σ変調とデジタルアシストを用いたイメージ信号除去に関する研究

  小西 恵大, 李 赫鍾, 和泉 慎太郎, 竹内 隆, H. Kawaguchi, 吉本 雅彦

  LSIとシステムのワークショップ 2010, May 2010, Japanese, 北九州市, Domestic conference

  Poster presentation


• 7T/14T SRAMを内部メモリに用いたマルチコアプロセッサアーキテクチャ

  中田 洋平, 川口 博, 吉本 雅彦

  LSIとシステムのワークショップ 2010, May 2010, Japanese, 北九州市, Domestic conference

  Poster presentation


• "時刻同期型MACプロトコルを用いる6.4μWシングルチップセンサーノードLSI,

  和泉 慎太郎, 李 赫鍾, 小西 恵大, 岡 顕久, 松田 隆志, 竹内 隆, 太田 能, 川口 博, 吉本 雅彦

  LSIとシステムのワークショップ 2010, May 2010, Japanese, 北九州市, Domestic conference

  Poster presentation


• 時刻同期型MACプロトコルを用いる58-uWワンチップセンサノードプロセッサ

  和泉 慎太郎, 竹内 隆, 松田 隆志, 李 赫鍾, 小西 恵大, 鶴田 嵩, 酒井 康晴, 川口 博, 太田 能, 吉本 雅彦

  電子情報通信学会技術研究報告, Oct. 2009, Japanese, 電子情報通信学会, Domestic conference

  Poster presentation


• 高精度音源定位および音源分離機能を有する低消費電力ユビキタス・センサネットの開発

  高木 智也, 川口 博

  STARCフォーラム/シンポジウム2009 学生ポスターセッション, Aug. 2009, Japanese, 株式会社 半導体理工学研究センター（STARC）, 新横浜国際ホテル, Domestic conference

  Poster presentation


• 7T/14T SRAMを内部メモリに用いたマルチコアプロセッサアーキテクチャの検討

  中田 洋平, 川口 博, 吉本 雅彦

  DAシンポジウム2009, Aug. 2009, Japanese, 情報処理学会 システムLSI設計技術研究会, 石川, Domestic conference

  Poster presentation


• 全整数計画問題のソルバーのFPGA実装

  谷 純一, 野口 紘希, 嶋井 優介, 川口 博, 吉本 雅彦

  LSIとシステムのワークショップ2009 ポスターセッション, May 2009, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, Domestic conference

  Poster presentation


• 時間同期型MACプロトコルの垂直統合設計によるセンサノードVLSIの低消費電力化

  和泉 慎太郎, 松田 隆志, 竹内 隆, 川口 博, 太田 能, 吉本 雅彦

  LSIとシステムのワークショップ2009 ポスターセッション, May 2009, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, Domestic conference

  Poster presentation


• 高信頼性モードを有する7T/14TディペンダブルSRAM,

  奥村 俊介, 藤原 英弘, 井口 友輔, 野口 紘希, 川口 博, 吉本 雅彦

  LSIとシステムのワークショップ2009 ポスターセッション, May 2009, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, Domestic conference

  Poster presentation


• リアルタイム20,000語彙連続音声認識のためのGMMプロセッサのFPGA実装

  三浦 和夫, 野口 紘希, 藤永 剛史, 川口 博, 吉本 雅彦

  LSIとシステムのワークショップ2009 ポスターセッション, May 2009, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, Domestic conference

  Poster presentation


• マイクロホンアレイ・センサネットワークによるインテリジェント・ユビキタス音声処理システムと，その低消費電力LSIの提案,

  高木 智也, 野口 紘希, 吉本 雅彦, 川口 博

  LSIとシステムのワークショップ2009 ポスターセッション, May 2009, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, Domestic conference

  Poster presentation


• チップ間ばらつき補正機能を有する基板バイアス制御を用いた0.42V動作486-kb FD-SOI SRAM,

  山口 幸介, 藤原 英弘, 竹内 隆, 大竹 優, 吉本 雅彦, 川口 博

  LSIとシステムのワークショップ2009 ポスターセッション, May 2009, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, Domestic conference

  Poster presentation


• カラム線制御回路を用いた0.56V動作128-kb10T小面積SRAM,

  吉本 秀輔, 井口 友輔, 奥村 俊介, 藤原 英弘, 野口 紘希, 新居 浩二, 川口 博, 吉本 雅彦

  LSIとシステムのワークショップ2009 ポスターセッション, May 2009, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, Domestic conference

  Poster presentation


• 低電圧・低消費電力SRAM

  川口 博

  IEEE Solid-State Circuits Society Kansai Chapter Technical Seminar, Dec. 2008, Japanese, Domestic conference

  Invited oral presentation


• 発話推定を用いたインテリジェント認識システムの低消費 電力化技術

  野口 紘希, 川口 博

  半導体理工学研究センター(STARC)フォーラム／シンポジウム学生ポ スターセッション, Jul. 2008, Japanese, パシフィコ横浜, Domestic conference

  Poster presentation


• 発話推定を用いたインテリジェント認識システムの低消費電力化技術

  NOGUCHI Hiroki, KAWAGUCHI Hiroshi

  STARCフォーラム/シンポジウム2008 学生ポスターセッション, Jul. 2008, Japanese, 半導体理工学研究センター, 横浜, Domestic conference

  Poster presentation


• 動的電源電圧/周波数制御によるフレームバッファSRAM内蔵型H.264 AVCデコーダの低消費電力化

  SAKATA Yoshinori, NAKATA Youhei, KAWAKAMI Kentaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  第11回システムLSIワークショップ ポスタセッション, Nov. 2007, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, Domestic conference

  Poster presentation


• 長波帯標準電波を用いた低電力センサノードのための垂直統合設計

  OTAKE Yu, ICHIEN Masumi, TAKEUCHI Takashi, GION Akihiro, MIKAMI Shinji, FUJIWARA Hidehiro, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  第11回システムLSIワークショップ ポスタセッション, Nov. 2007, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, Domestic conference

  Poster presentation


• 超並列画像処理プロセッサ応用任意位置任意サイズ矩形データの1サイクルアクセスが可能なメモリアーキテクチャ

  KAMINO Tetsuya, MIYAKOSHI Junichi, MURACHI Yuichiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  第11回システムLSIワークショップ ポスタセッション, Nov. 2007, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, Domestic conference

  Poster presentation


• サブ100mW H.264 MP@L4.1 HDTV解像度対応 整数画素精度動き検出プロセッサコア

  MIZUNO Kosuke, MIYAKOSHI Junichi, MURACHI Yuichiro, HAMAMOTO Masaki, IINUMA Takahiro, ISHIHARA Tomokazu, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  第11回システムLSIワークショップ ポスタセッション, Nov. 2007, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, Domestic conference

  Poster presentation


• VGA 30fps実時間動画像認識応用オプティカルフロープロセッサコア

  MURACHI Yuichiro, FUKUYAMA Yuki, YAMAMOTO Ryo, MIYAKOSHI Junichi, KAWAGUCHI Hiroshi, ISHIHARA Hajime, MIYAMA Masayuki, MATSUDA Yoshio, 吉本 雅彦

  第11回システムLSIワークショップ ポスタセッション, Nov. 2007, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, Domestic conference

  Poster presentation


• H.264 MP@L4.1エンコーダLSIのためのHDTV解像度対応適応的階層探索動き検出アルゴリズム

  印 芳, MURACHI Yuichiro, HAMAMOTO Masaki, IINUMA Takahiro, ISHIHARA Tomokazu, 李 将充, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  第11回システムLSIワークショップ ポスタセッション, Nov. 2007, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, Domestic conference

  Poster presentation


• DVS環境下での小面積・低電圧動作8T SRAMの設計-32nm世代以降で8Tセルが小面積・低電圧動作を同時に実現

  MORITA Yasuhiro, FUJIWARA Hidehiro, NOGUCHI Hiroki, IGUCHI Yusuke, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  第11回システムLSIワークショップ ポスタセッション, Nov. 2007, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, Domestic conference

  Poster presentation


• ビット線電力を削減する;動画像処理応用 10T 非プリチャージ 2-port SRAM

  IGUCHI Yusuke, NOGUCHI Hiroki, OKUMURA Syunsuke, FUJIWARA Hidehiro, MORITA Yasuhiro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  VDEC LSIデザイナーフォーラム2007(若手の会)ポスターセッション, Sep. 2007, Japanese, 東京大学大規模集積システム設計教育研究センター, 北海道, Domestic conference

  Poster presentation


• ワイヤレスセンサネットワークのためのタイマ制御によるカウンターベースブロードキャスティング方式の改良

  IZUMI Shintaro, MATSUDA Takashi, MIKAMI Shinji, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  2007年電子情報通信学会総合大会, Mar. 2007, Japanese, 電子情報通信学会, 名古屋, Domestic conference

  Oral presentation


• ビット線電力を8割削減する動画像処理応用 10T非プリチャージ2-port SRAM

  IGUCHI Yusuke, NOGUCHI Hiroki, FUJIWARA Hidehiro, MORITA Yasuhiro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  2007年電子情報通信学会総合大会, Mar. 2007, Japanese, 電子情報通信学会, 名古屋, Domestic conference

  Oral presentation


• Design Solutions for a Multi-Object Wireless Power Transmission Sheet Based on Plastic Switches

  TAKAMIYA Makoto, SEKITANI Takeshi, MIYAMOTO Yoshio, NOGUCHI Yoshiaki, KAWAGUCHI Hiroshi, SAKURAI Takayasu, SOMEYA Takao

  IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), Feb. 2007, English, IEEE, San Francisco, USA, International conference

  Oral presentation


• A Large-area Flexible Wireless Power Transmission Sheet Using Printed Plastic MEMS Switches and Organic Field-effect Transistors

  SEKITANI Takeshi, TAKAMIYA Makoto, NOGUCHI Yoshiaki, S. NAKANO, KATO Yusaku, K. HIZU, KAWAGUCHI Hiroshi, SAKURAI Takayasu, SOMEYA Takao

  IEEE International Electron Devices Meeting Digest of Technical Papers (IEDM), Dec. 2006, English, IEEE, San Francisco, USA, International conference

  Oral presentation


• (Invited) Flexible Braille Sheet Display with Organic FETs and Plastic Actuators

  TAKAMIYA Makoto, SEKITANI Takeshi, KATO Yusaku, KAWAGUCHI Hiroshi, SOMEYA Takao, SAKURAI Takayasu

  International Display Workshops (IDW), Dec. 2006, English, Ootsu city JAPAN, International conference

  [Invited]

  Invited oral presentation


• 超並列画像処理のための、任意位置・水平垂直連続複数画素を同時アクセスできるメモリアーキテクチャ

  ISHIHARA Tomokazu, MIYAKOSHI Junichi, MURACHI Yuichiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  第10回システムLSIワークショップ ポスタセッション, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference

  Poster presentation


• 消費電力を50%削減する動的電圧/周波数スケーリング型H.264 Main Profile@Level 4ビデオデコーダLSI

  KAWAKAMI Kentaro, KURODA Mitsuhiko, SAKATA Yoshinori, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  第10回システムLSIワークショップ ポスタセッション, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference

  Poster presentation


• 実時間動画像認識応用スケーラブルオプティカルフロープロセッサ

  FUKUYAMA Yuuki, YAMAMOTO Ryo, MIYAKOSHI Junichi, KATAGIRI Tadayoshi, MINEGISHI Noriyuki, KAWAGUCHI Hiroshi, MIYAMA Masayuki, IMAMURA Kosuke, HASHIMOTO Hideo, YOSHIMOTO Masahiko

  第10回システムLSIワークショップ ポスタセッション, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference

  Poster presentation


• ワイヤレスセンサーネットワーク応用キャリアセンス機能を持つ433MHz帯、356-uW電圧増幅器

  OTAKE Yu, MIKAMI Shinji, TAKEUCHI Takashi, ICHIEN Masumi, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  第10回システムLSIワークショップ ポスタセッション, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference

  Poster presentation


• ワイヤレスセンサーネットワークにおける送信電力制御による送信効率劣化が消費電力モデルに与えるネガティブインパクト

  MIKAMI Shinji, TAKEUCHI Takashi, OTAKE Yu, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  第10回システムLSIワークショップ ポスタセッション, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference

  Poster presentation


• ビット線電力を53%削減できる実時間動画像処理応用2ポートSRAM

  FUJIWARA Hidehiro, NII Koji, MIYAKOSHI Junichi, MURACHI Yuichiro, MORITA Yasuhiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  第10回システムLSIワークショップ ポスタセッション, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference

  Poster presentation


• しきい値電圧ばらつきを克服したDVS環境下における0.3V動作SRAMの開発

  NOGUCHI Hiroki, MORITA Yasuhiro, FUJIWARA Hidehiro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  第10回システムLSIワークショップ ポスタセッション, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference

  Poster presentation


• Stacked-Chip Implementation of On-Chip Buck Converter for Power-Aware Distributed Power Supply Systems

  ONIZUKA Kohei, KAWAGUCHI Hiroshi, TAKAMIYA Makoto, SAKURAI Takayasu

  IEEE Asian Solid-State Circuits Conference Proceedings of Technical Papers (A-SSCC), Nov. 2006, English, IEEE, Hangzhou, China, International conference

  Oral presentation


• 800-μW H.264 Baseline-Profile対応動き検出プロセッサIP

  IINUMA Takahiro, MIYAKOSHI Junichi, MURACHI Yuichiro, MATSUNO Tetsuro, HAMANOTO Masaki, ISHIHARA Tomokazu, KAWAGUCHI Hiroshi, MIYAMA Masayuki, YOSHIMOTO Masahiko

  第10回システムLSIワークショップ ポスタセッション, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference

  Poster presentation


• Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications

  ONIZUKA Kohei, KAWAGUCHI Hiroshi, TAKAMIYA Makoto, T. KURODA, SAKURAI Takayasu

  Proceedings of IEEE Custom Integrated Circuits Conference (CICC), Sep. 2006, English, IEEE, San Jose, USA, International conference

  Oral presentation


• (Invited) Low Power and Flexible Braille Sheet Display with Organic FET's and Plastic Actuators

  TAKAMIYA Makoto, SEKITANI Takeshi, KATO Yusaku, KAWAGUCHI Hiroshi, SOMEYA Takao, SAKURAI Takayasu

  Proceedings of IEEE International Conference on IC Design and Technology (ICICDT), May 2006, English, Italy, International conference

  Oral presentation


• 動的電圧制御環境下における0.3-V 動作64-kb SRAM

  MORITA Yasuhiro, FUJIWARA Hidehiro, NOGUCHI Hiroki, KAWAKAMI Kentaro, MIYAKOSHI Junichi, MIKAMI Shinji, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  2006年電子情報通信学会総合大会;AS-2-2, Mar. 2006, Japanese, 電子情報通信学会, 東京都, Domestic conference

  Oral presentation


• 動的電圧制御環境下における0.3-V 動作64-kb SRAM

  森田 泰弘, 藤原 英弘, 野口 紘希, 川上 健太郎, 宮越 純一, 三上 真司, 新居 浩二, 川口 博, 吉本 雅彦

  電子情報通信学会総合大会, Mar. 2006, Japanese, 東京, Domestic conference

  Oral presentation


• センサノードの製造バラツキを考慮したネットワーク可用時間改善の一検討

  YOSHINO Hironori, AONISHI Takafumi, ICHIEN Masumi, MATSUDA Takashi, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  2006年電子情報通信学会総合大会;BS-10-5, Mar. 2006, Japanese, 電子情報通信学会, 東京都, Domestic conference

  Oral presentation


• Long-lived network by considering production trelance of sensor node

  YOSHINO Hironori, AONISHI Takafumi, ICHIEN Masumi, MATSUDA Takashi, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  電子情報通信学会総合大会, Mar. 2006, Japanese, Tokyo, Domestic conference

  Oral presentation


• Evaluation of GIT Routing Considering Aggregation Ratio in Sensor Networks

  AONISHI Takafumi, YOSHINO Hironori, MIKAMI Shinji, OHTA Chikara, KAWAGUCHI Hiroshi, YOHIMOTO Masahiko

  電子情報通信学会技術研究報告, Oct. 2005, Japanese, 新潟, Domestic conference

  Oral presentation


• Impact on impedance mismatch of output power control for wireless sensor nodes

  MIKAMI Shinji, TAKEUCHI Takashi, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  電子情報通信学会ソサイエティ大会, Sep. 2005, Japanese, 北海道大学, Domestic conference

  Oral presentation


• 二重ワード線と二重ビット線を用いた3次元積層シート型スキャナ

  川口 博, 伊庭 信吾, 加藤 祐作, 関谷 毅, 染谷 隆夫, 桜井 貴康

  電子情報通信学会技術研究報告, May 2005, Japanese, 神戸, Domestic conference

  Oral presentation

• ACM


• IEEE

• パイプラインバックプロパゲーションを用いたディープラーニングプロセッサ

  川口 博

  科学研究費補助金／基盤研究(B), Apr. 2018 - Mar. 2021, Principal investigator

  Competitive research funding


• 省電力AIエンジンと異種エンジン統合クラウドによる人工知能プラットフォーム

  川口 博

  国立研究開発法人産業技術総合研究所, IoT推進のための横断技術開発プロジェクト, 2017, Principal investigator

  Competitive research funding


• 省電力AIエンジンと異種エンジン統合クラウドによる人工知能プラットフォーム

  川口 博

  IoT推進のための横断技術開発プロジェクト, 2016, Principal investigator

  Competitive research funding


• ＦＤ－ＳＯＩのトータルばらつき抑制効果による超低電圧動作ディペンダブルＳＲＡＭ

  川口 博

  科学研究費補助金／基盤研究(B), 2008, Principal investigator

  Competitive research funding


• A research on silicon nano-devices for single-electron, quantum, CMOS integrated circuits operating at room temperature

  HIRAMOTO Toshiro, SAKURAI Takayasu, SARAYA Takuya

  Japan Society for the Promotion of Science, Grants-in-Aid for Scientific Research, Grant-in-Aid for Scientific Research (A), The University of Tokyo, 2004 - 2007

  This research aims at a new concept of integrate circuit in which new functional devices utilizing single-electron/quantum effect and conventional CMOS devices are merged operating at room temperature. At first, the fabrication process of single-electron transistors was developed. The world largest peak-to-valley current ratios of Coulomb blockade oscillations and negative differential conductance at room temperature were successfully obtained. Furthermore, the precise control of the peak position of the Coulomb blockade oscillations was achieved for the first time in single-hole transistors which have very small quantum dots. The unique characteristics originate from large quantum energy spacing in the quantum dot. Next, the integration of single-electron transistors operating at room temperature was pursued. The process conditions were finely tuned and finally, the single-electron transistors operating at room temperature were successfully integrated for the first time. Moreover, analog pattern matching circuits were fabricated by integrating single-electron transistors and their operations were demonstrated at room temperature.


• 有機トランジスタ駆動による点字ディスプレイの試作研究

  染谷 隆夫, 桜井 貴康, 関谷 毅, 川口 博

  日本学術振興会, 科学研究費助成事業, 萌芽研究, 東京大学, 2005 - 2006

  本研究は、有機トランジスタの駆動回路を用いた点字ディスプレイを試作することを目的としている。点字の表示部には導電性高分子のアクチュエータを活用し、オール・プラスティックの点字ディスプレイを実現することをねらいとしている。 今年度は、柔らかいアクチュエータと電気回路が同時にプラスティック・フィルム上に集積可能であることを世界に先駆けて示し、有機トランジスタで超薄型の点字ディスプレイを試作して、その動作原理実験に成功した。点字ディスプレイのプロトタイプは、実効表示面積が4x4平方センチメートル、1文字は合計6点(2x3)からなり、全部で24文字分の点字で構成される。有機トランジスタは、ポリエチレンナフタレート(PEN)もしくはポリイミドといったプラスティック・フィルムの上に製造されている。表示部の厚みは1mm、重さは5gである。 有機トランジスタ駆動回路の軽量性、可とう性、耐衝撃性を利用して、携帯性に優れる点字ディスプレイを実現し、目の不自由な方が電車で単庫本を広げて読むように手軽に読書ができる技術として供することをねらいとする。


• 次世代ウエアラブルコンピュータのための知覚認識モバイルプロセッサの垂直統合研究

  吉本 雅彦

  科学研究費補助金／基盤研究(A), 2006

  Competitive research funding


• 階層間協調設計による無線センサネットワークのための省電力通信プロトコルの開発

  太田 能

  科学研究費補助金／基盤研究(C), 2006

  Competitive research funding


• 物理的再構成可能なＳiＰを実現する電源と信号のミクロン距離無線伝送

  川口 博

  科学研究費補助金／若手研究(B), 2005, Principal investigator

  Competitive research funding

• 低電圧動作キャッシュメモリ

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 中田 洋平, 奥村 俊介, 鄭 晋旭

  特願2012-267445, 06 Dec. 2012, 大学長, 特許6024897, 21 Oct. 2016

  Patent right


• 半導体メモリおよびプログラム（韓国）

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 藤原 英弘, 奥村 俊介

  10-2010-7016180, 07 Jan. 2009, ＴＬＯ, 10-1569540, 10 Nov. 2015

  Patent right


• メモリセルアレイを用いたＩＤチップ

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 奥村 俊介

  特願2010-219910, 29 Sep. 2010, 大学長, 特許5499365, 20 Mar. 2014

  Patent right


• データ一括比較処理回路、データ一括比較処理方法およびデータ一括比較プログラム

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 奥村 俊介

  特願2010-219902, 29 Sep. 2010, 大学長, 特許5488920, 07 Mar. 2014

  Patent right


• キャッシュメモリとそのモード切替方法

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 中田 洋平

  特願2009-189603, 18 Aug. 2009, 大学長, 特許5397843, 01 Nov. 2013

  Patent right


• 共有キャッシュメモリとそのキャッシュ間のデータ転送方法

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 藤原 英弘, 奥村 俊介

  特願2009-082997, 30 Mar. 2009, 大学長, 特許5311309, 12 Jul. 2013

  Patent right


• 半導体メモリのハーフセレクト防止セル配置

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 藤原 英弘, 奥村 俊介

  特願2009-000012, 04 Jan. 2009, 大学長, 特許5298373, 28 Jun. 2013

  Patent right


• 画像処理用メモリ

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 宮越 純一, 村地勇一郎

  特願2007-298743, 18 Nov. 2007, 大学長, 特許5261694, 10 May 2013

  Patent right


• 半導体メモリのメモリセル間のデータコピー方法

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 藤原 英弘, 奥村 俊介

  特願2009-082996, 30 Mar. 2009, 大学長, 特許5256534, 02 May 2013

  Patent right


• 半導体メモリおよびプログラム

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 藤原 英弘, 奥村 俊介

  特願2009-548936, 07 Jan. 2009, ＴＬＯ, 特許5196449, 15 Feb. 2013

  Patent right


• 不良メモリセルの予知診断アーキテクチャーと予知診断方法

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 藤原 英弘, 奥村 俊介

  特願2009-082998, 30 Mar. 2009, 大学長, 特許5187852, 01 Feb. 2013

  Patent right


• 半導体記憶装置

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 藤原 英弘, 森田 泰弘

  特願2006-061644, 07 Mar. 2006, ＴＬＯ, 特許5119489, 02 Nov. 2012

  Patent right


• 半導体メモリおよびプログラム SEMICONDUCTOR MEMORY AND PROGRAM

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 藤原 英弘, 奥村 俊介

  US12,809,684, 07 Jan. 2009, ＴＬＯ, 8,238,140, 07 Aug. 2012

  Patent right


• 画像処理装置

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 宮越 純一, 村地 勇一郎, 濱本 真生, 飯沼 隆弘, 石原 朋和

  特願2007-298142, 16 Nov. 2007, 大学長, 特許5020029, 22 Jun. 2012

  Patent right


• センサネットワークにおける無線トランシーバー用電圧増幅器

  YOSHIMOTO MASAHIKO, OHTA CHIKARA, KAWAGUCHI HIROSHI, 三上 真司

  特願2007-035223, 15 Feb. 2007, 大学長, 特許5019362, 22 Jun. 2012

  Patent right


• センサネットワークシステム及びメディアアクセス制御方法

  YOSHIMOTO MASAHIKO, OHTA CHIKARA, KAWAGUCHI HIROSHI, 一圓 真澄

  特願2006-279761, 13 Oct. 2006, 大学長, 特許4919204, 10 Feb. 2012

  Patent right


• データ送信スケジューリング方法およびそれを用いたセンサネットワークシステム

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, OHTA CHIKARA, 三上 真司

  特願2006-279760, 13 Oct. 2006, 大学長, 特許4863069, 18 Nov. 2011

  Patent right