Research activity information

• 2018 電子情報通信学会, 電子情報通信学会ELEX Best Paper Award, A low power, VLSI object recognition processorusing Sparse FIND Feature for 60fps HDTV resolution video

  Matsukawa Go, Kodamda Taisuke, Nishizumi Yuri, Kajihara Koichi, Nakanishi Chikako, IZUMI Shintaro, KAWAGUCHI Hiroshi, Goto Toshio, Kato Takeo, YOSHIMOTO Masahiko

  Official journal


• Sep. 2017 IEEE International Workshop on Machine Learning for Signal Processing (MLSP), Sep. 2017., Best Student Paper Award, A Layer-Block-Wise Pipeline For Memory And Bandwidth Reduction In Distributed Deep Learning

  MORI Haruki, YOUKAWA Tetsuya, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, INOUE Atsuki

  International society


• Dec. 2016 IEEE International Conference on Electronics, Circuits, and Systems (ICECS), IEEE ICECS 2016 Best Paper Award, Dec. 2016, An Low-Energy 8T Dual-Port SRAM for Image Processor with Selective Sourceline Drive Scheme in 28-nm FD-SOI Process Technology

  MORI Haruki, NAKAGAWA Tomoki, KITAHARA Yuki, KAWAMOTO Yuta, TAKAGI Kenta, YOSHIMOTO Shusuke, IZUMI Shintaro, YOSHIMOTO Masahiko

  International society


• May 2016 電子情報通信学会集積回路研究専門委員会, LSIとシステムのワークショップ2016 優秀ポスター賞（学生部門）, プロセスばらつき耐性を有する低電圧動作STT-MRAM向けカウンターベース読出し回路

  UMEKI Yohei, YANAGIDA Kouji, YOSHIMOTO Shusuke, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, TSUNODA Koji, SUGII Toshihiro

  Japan society


• May 2014 電子情報通信学会集積回路研究専門委員会, 優秀ポスター賞, 38μAウェアラブル生体情報計測プロセッサ

  中井 陽三郎, IZUMI SHINTARO, 山下 顕, 中野 将尚, 藤井 貴英, 小西 恵大, KAWAGUCHI HIROSHI, 木村 啓明, 丸元 共治, 渕上 貴昭, 藤森 敬和, 中嶋 宏, 志賀 利一, YOSHIMOTO MASAHIKO

  Japan society


• Apr. 2008 財団法人 電気・電子学術振興財団, 第10回LSI IPデザイン・アワード 研究助成賞, 長波帯標準電波を用いた低電力センサノードの垂直統合設計

  OTAKE Yu, ICHIEN Masumi, TAKEUCHI Takashi, GION Akihiro, MIKAMI Shinji, FUJIWARA Hidehiro, KAWAGUCHI Hirosi, OHTA Chikara, YOSHIMOTO Masahiko


• Apr. 2008 財団法人 電気・電子学術振興財団, 第10回LSI IPデザイン・アワード IP賞 2, サブ100mW H.264/AVC MP@L4.1 HDTV 解像度対応整数画素精度動き検出プロセッサコア

  MIZUNO Kosuke, MIYAKOSHI Junichi, MURACHI Yuichiro, HAMAMOTO Masaki, IINUMA Takahiro, ISHIHARA Tomokazu, 印 芳, KAMINO Tetsuya, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko


• Apr. 2008 財団法人 電気・電子学術振興財団, 第10回LSI IPデザイン・アワード IP賞 1, VGA 30fps 実時間動画像認識応用オプティカルフロープロセッサコア

  MURACHI Yuichiro, FUKUYAMA Yuki, YAMANOTO Ryo, MIYAKOSHI Junichi, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, ISHIHARA Hajime, MIYAMA Masahiko, MATSUDA Yoshio


• Dec. 2007 IEEE, SENSORCOMM 2007 ENOPT 2008 Workshop Best Paper Award, Cross-Layer Design for Low-Power Wireless Sensor Node Using Long-Wave Standard Time Code

  OTAKE Yu, ICHIEN Masumi, TAKEUCHI Takashi, GION Akihiro, MIKAMI Shinji, FUJIWARA Hidehiro, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko


• Nov. 2007 電子情報通信学会, 第11回システムLSIワークショップ IEEEシステムLSI技術賞, DVS環境下での小面積・低電圧動作8T SRAMの設計-32nm世代以降で8Tセルが小面積・低電圧動作を同時に実現

  MORITA Yasuhiro, FUJIWARA Hidehiro, NOGUCHI Hiroki, IGUCHI Yusuke, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko


• Sep. 2007 東京大学大規模集積システム設計教育研究センター, IEEE SSCS Japan Chapter Outstanding Design Award, ビット線電力を削減する，動画像処理応用 10T 非プリチャージ 2-port SRAM

  IGUCHI Yusuke, NOGUCHI Hiroki, OKUMURA Syunsuke, FUJIWARA Hidehiro, MORITA Yasuhiro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko


• Apr. 2007 財団法人 電気・電子学術振興財団, 第9回LSI IPデザイン・アワード 開発奨励賞, 消費電力を50%削減する動的電圧/周波数スケーリング型H.264 Main Profile@Level 4ビデオデコーダLSI

  KAWAKAMI Kentaro, TAKEMURA Jun, KURODA Mitsuhiko, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko


• Apr. 2007 財団法人 電気・電子学術振興財団, 第9回LSI IPデザイン・アワード IP賞 2, ット線電力を53%削減できる実時間動画像処理応用2ポートSRAM

  FUJIWARA Hidehiro, NII Koji, MIYAKOSHI Junichi, MURACHI Yuichiro, MORITA Yasuhiro, NOGUCHI Hiroki, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko


• Apr. 2007 財団法人 電気・電子学術振興財団, 第9回LSI IPデザイン・アワード IP賞 1, 超並列画像処理のための，任意位置・水平垂直連続複数画素を同時アクセスできるメモリアーキテクチャ

  ISHIHARA Tokokazu, MIYAKOSHI Junichi, MURACHI Yuichiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

• Multimodal Cardiovascular Information Monitor Using Piezoelectric Transducers for Wearable Healthcare

  OKANO Takaaki, IZUMI Shintaro, KATSUURA Takumi, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Dec. 2018, Journal of Signal Processing Systems, 1 - 10, English

  [Refereed][Invited]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• Layer Skip Learning using LARS variables for 39% Faster Conversion Time and Lower Bandwidth

  MIYAUCHI Yuki, MORI Haruki, Tetsuya Youkawa, YAMADA Kazuki, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI

  Dec. 2018, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), English

  [Refereed]

  International conference proceedings


• 28-nm FD-SOI Dual-Port SRAM with MSB-Based Inversion Logic for Low-Power Deep Learning

  MORI Haruki, Tetsuya Youkawa, MIYAUCHI Yuki, YAMADA Kazuki, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI

  Dec. 2018, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), English

  [Refereed]

  International conference proceedings


• DELAYED WEIGHT UPDATE FOR FASTER CONVERGENCE IN DATA-PARALLEL DEEP LEARNING

  Tetsuya Youkawa, MORI Haruki, MIYAUCHI Yuki, YAMADA Kazuki, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI

  Nov. 2018, 2018 6th IEEE Global Conference on Signal and Information Processing, English

  [Refereed]

  International conference proceedings


• Hardware Implementation of Autoregressive Model Estimation Using Burg’s Method for Low-Energy Spectral Analysis

  NISHIKAWA Yuki, IZUMI Shintaro, YOSHIDA Seiya, YANO Yuji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Oct. 2018, IEEE Workshop on Signal Processing Systems 2018, English

  [Refereed]

  International conference proceedings


• Adaptive Learning Rate Adjustment with Short-Term Pre-Training in Data-Parallel Deep Learning

  YAMADA Kazuki, MORI Haruki, YOUKAWA Tetsuya, MIYAUCHI Yuki, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi

  This paper introduces a method to adaptively choose a learning rate (LR) with short-term pre-training (STPT). This is useful for quick model prototyping in data-parallel deep learning. For unknown models, it is necessary to tune numerous hyperparameters. The proposed method reduces computational time and increases efficiency in finding an appropriate LR; multiple LRs are evalua

  Oct. 2018, IEEE Workshop on Signal Processing Systems 2018, English

  [Refereed]

  International conference proceedings


• A 5-ms Error, 22-A Photoplethysmography Sensor Using Current Integration Circuit and Correlated Double Sampling

  WATANABE Kento, IZUMI Shintaro, YANO Yuji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jul. 2018, the 40th International Engineering in Medicine and Biology Conference, English

  [Refereed]

  International conference proceedings


• Sampling Rate Reduction for Wearable Heart Rate Variability Monitoring

  NISHIKAWA Yuki, IZUMI Shintaro, YANO Yuji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  May 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS), English

  [Refereed]

  International conference proceedings


• マイクロ波ドップラーセンサを用いた非接触生体認証

  OKANO Takaaki, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Mar. 2018, 信学技報, vol. 117, no. 511, MICT2017-54, pp. 17-20, 2018年3月, 17 - 20, Japanese

  Symposium


• Estimating metabolic equivalents for activities in daily life using acceleration and heart rate in wearable devices

  NAKANISHI Motofumi, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, SHIGA Toshikazu, ANDO Takafumi, NAKAE Satoshi, USUI Chiyoko, AOYAMA Tomoko, TANAKA Shigeho

  2018, BioMedical Engineering OnLine, English

  [Refereed]

  Scientific journal


• A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme

  MORI Haruki, NAKAGAWA Tomoki, KITAHARA Yuki, KAWAMOTO Yuta, TAKAGI Kenta, YOSHIMOTO Shusuke, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI

  2018, IEEE Trans. on Circuits and Systems I Reg. Papers), English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A 11.3-µA Physical Activity Monitoring System Using Acceleration and Heart Rate

  NAKANISHI Motofumi, IZUMI Shintaro, TSUKAHARA Mio, KAWAGUCHI Hiroshi, KIMURA Hiromitsu, MARUMOTO Kyoji, FUCHIKAMI Takaaki, FUJIMORI Yoshikazu, YOSHIMOTO Masahiko

  2018, IEICE Transactions on Electronics, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A Metabolic Equivalents Estimation Algorithm using Triaxial Accelerometer and Adaptive Sampling for Wearable Devices

  NAKANISHI Motofumi, IZUMI Shintaro, TSUKAHARA Mio, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Dec. 2017, The 1st IEEE Life Sciences Conference, Sydney, Australia, 13-15 Dec 2017, English

  [Refereed]

  International conference proceedings


• Wearable Pulse Wave Velocity Sensor Using Flexible Piezoelectric Film Array

  KATSUURA Takumi, IZUMI Shintaro, YOSHIMOTO Shusuke, SEKITANI Tsuyoshi, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi

  Oct. 2017, Proc. of IEEE Biomedical Circuits and Systems Conference (BioCAS), pp. 721–724, Oct. 2017, 721 - 724, English

  [Refereed]

  International conference proceedings


• Non-Contact Biometric Identification and Authentication Using Microwave Doppler Sensor

  OKANO Takaaki, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Oct. 2017, The 13th IEEE BioMedical Circuits and Systems Conference(BioCAS), pp.392-395, Oct. 2017., 392 - 395, English

  [Refereed]

  International conference proceedings


• Multimodal Cardiovascular Information Monitor using Piezoelectric Transducers for Wearable Healthcare

  OKANO Takaaki, IZUMI Shintaro, KATSUURA Takumi, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Oct. 2017, IEEE Workshop on Signal Processing Systems (SiPS), Oct. 2017., English

  [Refereed]

  International conference proceedings

  Link to Kobe Univ. Repository (Kernel)


• FPGA Implementation of Object Recognition Processor for HDTV Resolution Video Using Sparse FIND Feature

  NISHIZUMI Yuri, MATSUKAWA Go, KAJIHARA Koichi, KODAMA Taisuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, NAKANISHI Chikako, GOTO Toshio, KATO Takeo, YOSHIMOTO Masahiko

  Oct. 2017, IEEE Workshop on Signal Processing Systems (SiPS), Oct. 2017., English

  [Refereed]

  International conference proceedings


• Capacitively Coupled ECG Sensor System with Digitally Assisted Noise Cancellation for Wearable Application

  NAGASATO Yuki, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Oct. 2017, The 13th IEEE BioMedical Circuits and Systems Conference(BioCAS), pp.400-403, Oct. 2017., 400 - 403, English

  [Refereed]

  International conference proceedings


• A Layer-Block-Wise Pipeline For Memory And Bandwidth Reduction In Distributed Deep Learning

  MORI Haruki, YOUKAWA Tetsuya, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, INOUE Atsuki

  Sep. 2017, IEEE International Workshop on Machine Learning for Signal Processing (MLSP), Sep. 2017., English

  [Refereed]

  International conference proceedings


• A Wearable Biomedical Sensing System with Normally-off Computing Architecture

  YOSHIMOTO Masahiko

  Jul. 2017, invited to 17th INTERNATIONAL FORUM ON MPSoC, Annecy, July 2017., English

  [Invited]

  International conference proceedings


• A swallowable sensing device platform with wireless power feeding and chemical reaction actuator.

  Ryota Nakamura, Shintaro Izumi, Hiroshi Kawaguchi, Hidetoshi Ohta, Masahiko Yoshimoto

  This paper presents a swallowable sensor device that can be ingested orally, later passing to the stomach, where the device can indwell for long periods. Using wireless communication, it can be egested at any time after it is triggered. This device can indwell using a silicone balloon in the gastrointestinal tract. A chemical reaction inflates the balloon inside the stomach. Then it is deflated to egest the sensor device using an actuator with electrolysis of water. Energy for the actuator with electrolysis can be fed wirelessly. Near field communication and a flexible antenna are used for power feeding and wireless data communication. Because of the flexible balloon and the flexible antenna, the device size can be minimized without performance degradation.

  Jul. 2017, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2017, 3040 - 3043, English, International magazine

  [Refereed]

  Scientific journal


• A low power, VLSI object recognition processor using Sparse FIND Feature for 60fps HDTV resolution video

  MATSUKAWA Go, KODAMA Taisuke, NISHIZUMI Yuri, KAJIHARA Koichi, NAKANISHI Chikako, IZUMI Shintaro, KAWAGUCHI Hiroshi, GOTO Toshio, KATO Takeo, YOSHIMOTO Masahiko

  Jul. 2017, IEICE Electronics Express, Vol. 14, No. 15, pp.1-12, July. 2017., 1 - 12, English

  [Refereed]

  Scientific journal


• A contact-less heart rate sensor system for driver health monitoring

  IZUMI Shintaro, MATSUNAGA Daichi, NAKAMURA Ryota, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jul. 2017, The 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC’17), July. 2017, English

  International conference proceedings


• A Novel Test Scheme for Detecting Faulty Recall Margin Cells for6T-4C FeRAM,

  UMEKI Yohei, IZUMI Shintaro, KITAHARA Hiroto, NAKAGAWA Tomoki, YANAGIDA Kouji, YOSHIMOTO Shusuke, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, KIMURA Hiromitsu, MARUMOTO Kyoji, FUCHIKAMI Takaaki, FUJIMORI Yoshikazu

  Feb. 2017, Memoirs of the Graduate Schools of Engineering and SystemInformatics Kobe University, no. 8, pp. 5-8, Feb. 2017., English

  [Refereed]

  Research institution

  Link to Kobe Univ. Repository (Kernel)


• A 19-mu A Metabolic Equivalents Monitoring SoC using Adaptive Sampling

  Tsukahara, Mio, Izumi, Shintaro, Nakanashi, Motofumi, Kawaguchi, Hiroshi, Yoshimoto, Masahiko, Kimura, Hiromitsu, Maromoto, Kyoji, Fuchikami, Takaaki, Fujimori, Yoshikazu

  2017, 2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 37 - 38, English

  [Refereed]

  International conference proceedings


• Adaptive Noise Cancellation Method for Capacitively Coupled ECG Sensor using Single Insulated Electrode

  Tanaka Yoshito, IZUMI Shintaro, KAWAMOTO Yuta, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Oct. 2016, The 12th IEEE BioMedical Circuits and Systems Conference(BioCAS), pp.343-346, Oct. 2016, 343 - 346, English

  [Refereed]

  International conference proceedings


• 消化管内へ留置する飲み込型センサの検討

  NAKAMURA Ryota, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, OHTA Hidetoshi

  Sep. 2016, 電気学会C部門大会, 2016年9月1日，神戸, Japanese

  Symposium


• 加速度センサを用いた低消費電力運動強度推定アルゴリズム

  TSUKAHARA Mio, NAKANISHI Motofumi, IZUMI Shintaro, NAKAI Yozaburo, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Sep. 2016, 電気学会C部門大会, 2016年9月1日，神戸., Japanese

  Symposium


• 加速度センサを用いた低消費電力運動強度推定アルゴリズム

  TSUKAHARA Mio, NAKANISHI Motofumi, IZUMI Shintaro, NAKAI Yozaburo, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Sep. 2016, IEICEソサイエティ大会, 2016年9月21日，札幌, Japanese

  Symposium


• A Wearable Biomedical Sensing System with Normally-off Computing Architecture and Physical Activity Classification Algorithm

  YOSHIMOTO MASAHIKO

  Sep. 2016, invited to International Conference on Solid State Devices and Materials (SSDM2016), Sept. 2016, English

  [Invited]

  International conference proceedings


• Swallowable sensing device for long-term gastrointestinal tract monitoring.

  Ryota Nakamura, Shintaro Izumi, Hiroshi Kawaguchi, Hidetoshi Ohta, Masahiko Yoshimoto

  This paper presents a swallowable sensor device that can be ingested orally, later arriving to the stomach, where the device can indwell for a long term and can be egested at any time after it is triggered using wireless communication. This device can inflate a silicone balloon in the gastrointestinal tract using a chemical reaction. The balloon can be deflated later using electrolysis of water at the time of egestion. A motorless chemical-reaction-based egestion method is proposed to minimize the sensor device size. This device can achieve long-term monitoring in the gastrointestinal tract.

  Aug. 2016, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2016, 3039 - 3042, English, International magazine

  [Refereed]

  Scientific journal


• Low-Power Metabolic Equivalents Estimation Algorithm Using Adaptive Acceleration Sampling

  TSUKAHARA Mio, NAKANISHI Motofumi, IZUMI Shintaro, NAKAI Yozaburo, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Aug. 2016, 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society(EMBC),pp.1878-1881 ,Aug. 2016, English

  [Refereed]

  International conference proceedings


• A Counter-based Read Circuit Tolerant to ProcessVariation for 0.4-V Operating STT-MRAM,

  UMEKI Yohei, YANAGIDA Kouji, YOSHIMOTO Shusuke, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, TSUNODA Koji, SUGII Toshihiro

  Aug. 2016, IPSJ Transactions on System LSIDesign Methodology (TSLDM), vol. 9, pp. 79-83, English

  [Refereed]

  Scientific journal


• A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor

  MORI Haruki, UMEKI Yohei, YOSHIMOTO Shusuke, IZUMI Shintaro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Aug. 2016, IEICE Trans. Electron., Vol.E99-C, No.8, pp.901-908, Aug. 2016, 901 - 908, English

  [Refereed]

  Scientific journal


• An Soft Error Propagation Analysis Considering Logical Masking Effect on Re-convergent Path

  YOSHIDA Shuhei, MATSUKAWA Go, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jul. 2016, 22nd IEEE International Symposium on On-Line Testing and Robust System Design(IOLTS), Jul. 2016, English

  [Refereed]

  International conference proceedings


• Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-convergent Path

  MATSUKAWA Go, KIMI Yuta, YOSHIDA Shuhei, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jun. 2016, IEICE Trans. Electron., Vol.E99-A, No.6, pp.1198-1205, Jun. 2016, 1198 - 1205, English

  [Refereed]

  Scientific journal


• 298-fJ/writecycle 650-fJ/readcycle を実現する画像処理プロセッサ向け 28-nm FD-SOI 8T 3ポートSRAM

  MORI Haruki, NAKAGAWA Tomoki, KITAHARA Yuki, KAWAMOTO Yuta, TAKAGI Kenta, YOSHIMOTO Shusuke, IZUMI Shintaro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Apr. 2016, 信学技報, vol.116, no.3, pp.13-16, 2016年4月14日，東京., Japanese

  Symposium


• Process variation tolerant counter base read circuit for low-voltage operating STT-MRAM

  UMEKI Yohei, YANAGIDA Kouji, KUROTSU Hiroaki, KITAHARA Hiroto, MORI Haruki, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, YOSHIMOTO Shusuke, TSUNODA Koji, SUGII Toshihiro

  Mar. 2016, DATE EMS Workshop, Mar. 2016, English

  [Refereed]

  International conference proceedings


• Capacitively Coupled ECG Sensor using a Single Electrode with Adaptive Power-Line Noise Cancellation

  KAWAMOTO Yuta, IZUMI Shintaro, TANAKA Yoshito, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  in Proc. of IEEE International Conference on Biomedical and Health Informatics (BHI), Feb. 2016, in Proc. of IEEE International Conference on Biomedical and Health Informatics (BHI), pp.212 - 215, English

  [Refereed][Invited]

  International conference proceedings


• Non-Contact Instantaneous Heart Rate Monitoring using Microwave Doppler Sensor and Time-Frequency Domain Analysis

  Daichi Matsunaga, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2016, 2016 IEEE 16TH INTERNATIONAL CONFERENCE ON BIOINFORMATICS AND BIOENGINEERING (BIBE), 172 - 175, English

  [Refereed]

  International conference proceedings


• An Low-Energy 8T Dual-Port SRAM for Image Processor with Selective Sourceline Drive Scheme in 28-nm FD-SOI Process Technology

  Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2016, 23RD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS CIRCUITS AND SYSTEMS (ICECS 2016), 532 - 535, English

  [Refereed]

  International conference proceedings


• A 15-mu A Metabolic Equivalents Monitoring System using Adaptive Acceleration Sampling and Normally Off Computing

  Mio Tsukahara, Shintaro Izumi, Motofumi Nakanishi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori

  2016, 23RD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS CIRCUITS AND SYSTEMS (ICECS 2016), 61 - 64, English

  [Refereed]

  International conference proceedings


• A Fast Settling All Digital PLL using Temperature Compensated Oscillator Tuning Word Estimation Algorithm

  OKUNO Keisuke, IZUMI Shintaro, MASAKI Kana, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  IEICE, Dec. 2015, IEICE Trans. Fundamentals, Vol.E98-A(12) (12), pp.2590 - 2597, English

  [Refereed]

  Scientific journal


• Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector.

  Shintaro Izumi, Ken Yamashita, Masanao Nakano, Shusuke Yoshimoto, Tomoki Nakagawa, Yozaburo Nakai, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto

  This paper describes an electrocardiograph (ECG) monitoring SoC using a non-volatile MCU (NVMCU) and a noise-tolerant instantaneous heartbeat detector. The novelty of this work is the combination of the non-volatile MCU for normally off computing and a noise-tolerant-QRS (heartbeat) detector to achieve both low-power and noise tolerance. To minimize the stand-by current of MCU, a non-volatile flip-flop and a 6T-4C NVRAM are used. Proposed plate-line charge-share and bit-line non-precharge techniques also contribute to mitigate the active power overhead of 6T-4C NVRAM. The proposed accurate heartbeat detector uses coarse-fine autocorrelation and a template matching technique. Accurate heartbeat detection also contributes system-level power reduction because the active ratio of ADC and digital block can be reduced using heartbeat prediction. Measurement results show that the fully integrated ECG-SoC consumes 6.14 μ A including 1.28- μA non-volatile MCU and 0.7- μA heartbeat detector.

  IEEE, Oct. 2015, IEEE transactions on biomedical circuits and systems, 9(5) (5), 641 - 51, English, International magazine

  [Refereed]

  Scientific journal


• A Wearable Healthcare System With a 13.7 μA Noise Tolerant ECG Processor.

  Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto

  To prevent lifestyle diseases, wearable bio-signal monitoring systems for daily life monitoring have attracted attention. Wearable systems have strict size and weight constraints, which impose significant limitations of the battery capacity and the signal-to-noise ratio of bio-signals. This report describes an electrocardiograph (ECG) processor for use with a wearable healthcare system. It comprises an analog front end, a 12-bit ADC, a robust Instantaneous Heart Rate (IHR) monitor, a 32-bit Cortex-M0 core, and 64 Kbyte Ferroelectric Random Access Memory (FeRAM). The IHR monitor uses a short-term autocorrelation (STAC) algorithm to improve the heart-rate detection accuracy despite its use in noisy conditions. The ECG processor chip consumes 13.7 μA for heart rate logging application.

  IEEE, Oct. 2015, IEEE transactions on biomedical circuits and systems, 9(5) (5), 733 - 42, English, International magazine

  [Refereed]

  Scientific journal


• A Ferroelectric-Based Non-Volatile Flip-Flop for Wearable Healthcare Systems

  S. Izumi, H. Kawaguchi, M. Yoshimoto, KIMURA Hiromitsu, FUCHIKAMI Takaaki, MURAMOTO Kyoji, FUJIMORI Yoshikazu

  Proc. of IEEE Non-Volatile Memory Technology Symposium (NVMTS), Oct. 2015, Proc. of IEEE Non-Volatile Memory Technology Symposium (NVMTS), pp.1 - 4, English

  [Refereed][Invited]

  International conference proceedings


• Physical Activity Group Classification Algorithm using Triaxial Acceleration and Heart Rate

  NAKANISHI Motofumi, IZUMI Shintaro, NAGAYOSHI Sho, SATO Hironori, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, ANDO Takafumi, NAKAE Satoshi, USUI Chiyoko, AOYAMA Tomoko, TANAKA Shigeho

  37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society(EMBC), Aug. 2015, 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society(EMBC), pp.510 - 513, English

  [Refereed][Invited]

  International conference proceedings


• Non-contact and Noise Tolerant Heart Rate Monitoring using Microwave Doppler Sensor and Range Imagery

  MATSUNAGA Daichi, OKUNO Keisuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society(EMBC), Aug. 2015, 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society(EMBC), pp.6118 - 6121, English

  [Refereed][Invited]

  International conference proceedings


• Large Displacement Haptic Stimulus Actuator using Piezoelectric Pump for Wearable Devices

  KODAMA Taisuke, IZUMI Shintaro, MASAKI Kana, KAWAGUCHI Hiroshi, MAENAKA Kazusuke, YOSHIMOTO Masahiko

  37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society(EMBC), Aug. 2015, 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society(EMBC), pp.1172 - 1175, English

  [Refereed][Invited]

  International conference proceedings


• A moreacceptable endoluminal implantation for remotely monitoring ingestiblesensors anchored to the stomach wall

  OHTA Hidetoshi, IZUMI Shintaro, YOSHIMOTO Masahiko

  in Proc. of 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), Aug. 2015, in Proc. of 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), pp.4089 - 4092, English

  [Refereed][Invited]

  International conference proceedings


• Low-Jitter Design for Second-Order Time-to-Digital Converter Using Frequency Shift Oscillators

  OKUNO Keisuke, KONISHI Toshihiro, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi

  IEICE, Jul. 2015, IEICE Trans. Fundamentals, Vol.E98-A(7) (7), pp.1475 - 1481, English

  [Refereed]

  Scientific journal


• An Accurate Soft Error Propagation Analysis Technique Considering Temporal Masking Disablement

  KIMI Yuta, MATSUKAWA Go, YOSHIDA Shuhei, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Proc. of IEEE International On-Line Testing (IOLTS), Jul. 2015, Proc. of IEEE International On-Line Testing (IOLTS), pp.23 - 25, English

  [Refereed][Invited]

  International conference proceedings


• An I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter

  K. Okuno, KONISHI Toshihiro, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi

  IEICE, Jun. 2015, IEICE Trans. Electron, Vol.E98-C(6) (6), pp.489 - 495, English

  [Refereed]

  Scientific journal


• Noise Tolerant Heart Rate Extraction Algorithm Using Short-Term Autocorrelation for Wearable Healthcare Systems

  IZUMI Shintaro, Nakano Masanao, YAMASHITA Ken, NAKAI Yozaburo, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  IEICE, May 2015, IEICE Transactions on Information and Systems, Vol.E98-D(5) (5), pp.1095 - 1103, English

  [Refereed]

  Scientific journal


• A Low Power 6T-4C Non-volatile Memoly using Charge Sharing and Non-precharge Techniques

  NAKAGAWA Tomoki, IZUMI Shintaro, YANAGIDA Koji, KITAHARA Yuki, YOSHIMOTO Shusuke, UMEKI Yohei, MORI Haruki, KITAHARA Hiroto, KAWAGUCHI Hiroshi, KIMURA Hiromitsu, MARUMOTO Kyoji, FUCHIKAMI Takaaki, FUJIMORI Yoshikazu, YOSHIMOTO Masahiko

  IEEE International Symposium on Circuits and Systems (ISCAS), May 2015, IEEE International Symposium on Circuits and Systems (ISCAS), pp.2904 - 2907, English

  [Refereed][Invited]

  International conference proceedings


• A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme

  MATSUKAWA Go, Nakata Yohei, SUGURE Yasuo, OHO Shigeru, KIMI Yuta, SHIMOZAWA Masafumi, YOSHIDA Shuhei, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  IEICE, Apr. 2015, IEICE Trans. Electron, Vol.E98-C(4) (4), pp.333 - 339, English

  [Refereed]

  Scientific journal


• A Negative-Resistance Sense Amplifier for Low-Voltage Operating STT-MRAM

  Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, Koji Tsunoda, Toshihiro Sugii

  Jan. 2015, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) University LSI Design Contest, pp. 8 - 9, English

  [Refereed]

  International conference proceedings


• A 14μA ECG Processor with Noise Tolerant Heart Rate Extractor and FeRAM for Wearable Healthcare Systems

  Yozaburo Nakai, IZUMI Shintaro, Ken Yamashita, Masanao Nakano, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jan. 2015, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) University LSI Design Contest, pp. 16 - 17, English

  [Refereed]

  International conference proceedings


• 不揮発マイコンを用いたノーマリーオフ生体計測SoC

  松永 大地, 中井 陽三郎, 河本 優太, 中川 知己, 奥野 圭祐, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  Dec. 2014, 信学技報, vol. 114(no. 345) (no. 345), p. 49, Japanese

  Research society


• ウェアラブル生体センサのための心電計測方法

  田中 義人, 河本 優太, 中井 陽三郎, 奥野 圭祐, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  Dec. 2014, 信学技報, vol. 114(no. 345) (no. 345), p. 47, Japanese

  Research society


• STT-MRAM Operating at 0.38 V Using Negative-Resistance Sense Amplifier

  Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii

  Dec. 2014, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A(12) (12), 2411 - 2417, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• An 8-bit I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter

  OKUNO Keisuke, KONISHI Toshihiro, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi

  Dec. 2014, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 223 - 226, English

  [Refereed]

  International conference proceedings


• A 2.23 ps RMS Jitter 3 μs Fast Settling ADPLL using Temperature Compensation PLL Controller

  OKUNO Keisuke, MASAKI Kana, IZUMI Shintaro, KONISHI Toshihiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Dec. 2014, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 68 - 71, English

  [Refereed]

  International conference proceedings


• A 6.14μA Normally-Off ECG-SoC with Noise Tolerant Heart Rate Extractor for Wearable Healthcare Systems

  IZUMI Shintaro, YAMASHITA Ken, NAKANO Masanao, NAKAGAWA Tomoki, KITAHARA Yuki, YANAGIDA Koji, YOSHIMOTO Shusuke, KAWAGUCHI Hiroshi, H. Kimura, K. Marumoto, T. Fuchikami, H. Nakajima, T. Shiga, YOSHIMOTO Masahiko

  Oct. 2014, Proc. of IEEE BioCAS, pp. 280 - 283, English

  [Refereed]

  International conference proceedings


• Soft-Error Resilient and Margin-Enhanced N-P Reversed 6T SRAM Bitcell

  YOSHIMOTO Masahiko, S. Yoshimoto, KAWAGUCHI Hiroshi

  Sep. 2014, IEICE Trans. Fundamentals, Vol. E97-A(No. 9) (No. 9), pp. 1945 - 1951, English

  [Refereed]

  International conference proceedings

  Link to Kobe Univ. Repository (Kernel)


• A Real-time Scalable Object Detection System using Low-power HOG Accelerator VLSI

  K. Takagi, K. Tanaka, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO MASAHIKO

  Sep. 2014, Journal of Signal Processing Systems, Vol. 76(Issue 3) (Issue 3), pp. 261 - 274, English

  [Refereed]

  Scientific journal


• Noise Tolerant QRS Detection using Template Matching with Short-Term Autocorrelation

  NAKAI Yozaburo, IZUMI Shintaro, NAKANO Masanao, YAMASHITA Ken, FUJII Takahide, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Aug. 2014, 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society(EMBC), pp. 34 - 37, English

  [Refereed]

  International conference proceedings


• A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation

  Y. Nakata, Y. Kimi, S. Okumura, J. Jung, T. Sawada, T. Toshikawa, NAGATA Makoto, H. Nakano, M. Yabuuchi, H. Fujiwara, K. Nii, H. Kawai, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Apr. 2014, IEICE Trans. Electron, Vol. E97-C(No. 4) (No. 4), pp. 332 - 341, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance with Bit-Enhancing Memory and On-Chip Diagnosis Structures Delivering x91 Failure Rate Improvement

  Y. Nakata, Y. Kimi, S. Okumura, J. Jung, T. Sawada, T. Toshikawa, M. Nagata, H. nakano, M. Yabuuchi, H. Fujiwara, K. Nii, H. Kawai, H. Kawaguchi, YOSHIMOTO Masahiko

  Mar. 2014, IEEE International Symposium on Quality Electronic Design (ISQED), pp.16 - 23, English

  [Refereed]

  International conference proceedings


• A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM

  G.Matsukawa, Y.Nakata, Y.Kimi, Y.Sugure, M.Shimozawa, S.Oho, H.Kawaguchi, M.Yoshimoto

  Feb. 2014, ARCS VERFE Workshop, pp.1 - 5, English

  [Refereed]

  Symposium


• 動作環境の動的変動を考慮した動作マージン拡大機能を有する自律制御キャッシュ

  KIMI Yuta, NAKATA Yohei, OKUMURA Syunsuke, JUNG Jinwook, 沢田 卓也, 利川 托, 永田 真, 中野 博文, 薮内 誠, 藤原 英弘, 新居 浩二, 河合 浩行, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jan. 2014, 信学技報, vol. 113(no. 419) (no. 419), p. 59, Japanese

  Research society


• 磁性変化型メモリの書き込み速度を改善するメモリアーキテクチャ

  MORI Haruki, YANAGIDA Kouji, UMEKI Youhei, YOSHIMOTO Shusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, 角田 浩司, 杉井 寿博

  Jan. 2014, 信学技報, vol. 113(no. 419) (no. 419), p. 27, Japanese

  Research society


• 強誘電体メモリの高速回路技術

  NAKAGAWA Tomoki, YOSHIMOTO Shusuke, KITAHARA Yuki, YANAGIDA Kouji, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jan. 2014, 信学技報, vol. 113(no. 419) (no. 419), p. 39, Japanese

  Research society


• ディペンダブルメモリを用いた低遅延デュアルコアロックステップアーキテクチャ

  MATSUKAWA Go, NAKATA Yohei, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jan. 2014, 信学技報, vol. 113(no. 419) (no. 419), p. 57, Japanese

  Research society


• ウェアラブル生体センサのための心電図解析方法

  NAKAI Yozaburo, IZUMI Shintaro, NAKANO Masanao, YAMASHITA Ken, FUJI Takahide, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jan. 2014, 信学技報, vol. 113(no. 419) (no. 419), p. 61, Japanese

  Research society


• A 54-mW 3x-Real-Time 60-kWord Continuous Speech Recognition Processor VLSI

  G. He, Y. Miyamoto, K. Matsuda, S. Izumi, H. Kawaguchi, YOSHIMOTO Masahiko

  Jan. 2014, IEICE Electronics Express, Vol. 11(No. 2) (No. 2), pp. 1 - 9, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• 28nmFD-SOIを用いた画像処理プロセッサ向け低消費電力SRAM

  KAWAMOTO Yuta, YOSHIMOTO Shusuke, NAKAGAWA Tomoki, KITAHARA Yuki, MORI Haruki, TAKAGI Kenta, IZUMI Shintaro, 新居 浩二, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jan. 2014, 信学技報, vol. 113(no. 419) (no. 419), p. 41, Japanese

  Research society


• (Invited Paper) Normally-off Technologies for Healthcare Appliance,

  IZUMI Shintaro, H. Kawaguchi, M. Yoshimoto, Y. Fujimori

  Jan. 2014, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 17 - 20, English

  [Refereed]

  International conference proceedings


• A 6T-4C Shadow Memory using Plate Line and Word Line Boosting

  Nakagawa, Tomoki, Izumi, Shintaro, Yoshimoto, Shusuke, Yanagida, Koji, Kitahara, Yuki, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

  2014, 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2736 - 2739, English

  [Refereed]

  International conference proceedings


• A 2.4 pJ Ferroelectric-Based Non-Volatile Flip-Flop with 10-Year Data Retention Capability

  Kimura, Hiromitsu, Fuchikami, Takaaki, Marumoto, Kyoji, Fujimori, Yoshikazu, Izumi, Shintaro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

  2014, 2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 21 - 24, English

  [Refereed]

  International conference proceedings


• Low-power Hardware Implementation of Noise Tolerant Heart Rate Extractor for a Wearable Monitoring System

  IZUMI Shintaro, M. Nakano, K. Yamashita, T. Fujii, H. Kawaguchi, YOSHIMOTO Masahiko

  Nov. 2013, IEEE International Conference on BioInformatics and BioEngineering (BIBE), pp.1 - 4, English

  [Refereed]

  International conference proceedings


• A 0.38-V Operating STT-MRAM with Process Variation Tolerant Sense Amplifier

  Y. Umeki, K. Yanagida, S. Yoshimoto, S. Izumi, M. Yoshimoto, KAWAGUCHI Hiroshi, K. Tsunoda, T. Sugii

  Nov. 2013, IEEE Asian Solid-State Circuits Conference (A-SSCC), pp.249 - 252, English

  [Refereed]

  International conference proceedings


• A 40-nm 54-mW 3×-Real-time VLSI Processor for 60-KWORD Continuous Speech Recognition

  G. He, Y. Miyamoto, K. Matsuda, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Oct. 2013, IEEE Workshop on Signal Processing Systems (SiPS), pp.147 - 152, English

  [Refereed]

  International conference proceedings


• 3倍速実時間6万語彙連続音声認識のための40-nm, 54-mW音声認識専用プロセッサ

  HE Guangji, MIYAMOTO Yuki, MATSUDA Kumpei, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Oct. 2013, 信学技報, vol. 113(no. 235) (no. 235), pp. 29 - 34, Japanese

  Research society


• A 40-nm 8T SRAM with Selective Source Line Control of Read Bitlines and Address Preset Structure

  S. Yoshimoto, S. Miyano, M. Takamiya, H. Shinohara, H. Kawaguchi, YOSHIMOTO Masahiko

  Sep. 2013, IEEE Custom Integrated Circuits Conference (CICC), pp.1 - 4, English

  [Refereed]

  International conference proceedings


• Soft-Error Tolerant N-P Reversed 6T SRAM Cell

  S. Yoshimoto, S. Izumi, H. Kawaguchi, YOSHIMOTO Masahiko

  Jul. 2013, IEEE Nuclear and Space Radiation Effects Conference (NSREC), PG - 3, English

  [Refereed]

  International conference proceedings


• Noise Torelant Instantanous Heart Rate and R-peak Detection Using Short-term Autocorrelation for Wearable Healthcare Systems

  T. Fujii, M. Nakano, K. Yamashita, T. Konishi, S. Izumi, H. Kawaguchi, YOSHIMOTO Masahiko

  Jul. 2013, Annual International Conference IEEE Engineering in Medicine and Biology Society (EMBC), pp.7330 - 7333, English

  [Refereed]

  International conference proceedings


• Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout

  S. Yoshimoto, S. Okumura, K. Nii, H. Kawaguchi, YOSHIMOTO Masahiko

  Jul. 2013, IEICE Trans. Fundamentals, Vol. E96-A(No. 7) (No. 7), pp. 1579 - 1585, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• Temperature Compensation Using Least Mean Squares for Fast Settling All-Digital Phase-Locked Loop

  K. Okuno, S. Izumi, T. Konishi, S. Dae-Woo, M. Yoshimoto, KAWAGUCHI Hiroshi

  Jun. 2013, IEEE New Circuits and Systems Conference (NEWCAS), pp.1 - 4, English

  [Refereed]

  International conference proceedings


• Multiple-Cell-Upset Hardened 6T SRAM Using NMOS-Centered Layout

  S. Yoshimoto, K. Nii, H. Kawaguchi, YOSHIMOTO Masahiko

  Jun. 2013, IEEE International Meeting for Future of Electron Devices Kansai (IMFEDK), pp. 98 - 99, English

  [Refereed]

  International conference proceedings


• マルチビットアップセット耐性を有するNMOS内側レイアウトを用いた6T SRAM

  YOSHIMOTO Shusuke, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Apr. 2013, 信学技報, vol. 113(no. 1) (no. 1), pp.121 - 126, Japanese

  Research society


• ゼロデータフラグを用いた低エネルギーSTT-RAMキャッシュ

  KIMI Yuta, JUNG Jinwook, NAKATA Yohei, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi

  Apr. 2013, 信学技報, vol. 113(no. 1) (no. 1), pp.47 - 52, Japanese

  Research society


• Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM

  J. Jung, Y. Nakata, S. Okumura, S. Izumi, H. Kawaguchi, YOSHIMOTO Masahiko

  Apr. 2013, IEICE Trans. Electron, Vol. E96-C(No. 4) (No. 4), pp. 528 - 537, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A sub-100 mW Dual-Core HOG Accelerator VLSI for Parallel Feature Extraction Processing for HDTV Resolution Video

  K. Mizuno, K. Takagi, Y. Terauchi, S. Izumi, H. Kawaguchi, YOSHIMOTO Masahiko

  Apr. 2013, IEICE Trans. Electron, Vol. E96-C(No. 4) (No. 4), pp. 433 - 443, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops

  T. Konishi, K. Okuno, S. Izumi, M. Yoshimoto, KAWAGUCHI Hiroshi

  Apr. 2013, IEICE Trans. Electron, Vol. E96-C(No. 4) (No. 4), pp.546 - 552, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A 168-mW 2.4x-Real-Time 60-kWord Continuous Speech Recongnition Processor VLSI

  G. He, T. Sugahara, Y. Miyamoto, S. Izumi, H. Kawaguchi, YOSHIMOTO Masahiko

  Apr. 2013, IEICE Trans. Electron, Vol. E96-C(No. 4) (No. 4), pp. 444 - 453, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• SRAM Failure Injection to a Vehicle ECU and Its Behavior Evaluation

  Y. Takeuchi, Y. Nakata, Y. Ito, Y. Sugure, S. Oho, H. Kawaguchi, YOSHIMOTO MASAHIKO

  Mar. 2013, DATE RIIF Workshop, English

  [Refereed]

  International conference proceedings


• Model-Based Fault Injection for Large-Scale Failure Effect Analysis with 600-Node Cloud Computers

  Y. Nakata, Y. Ito, Y. Takeuchi, Y. Sugure, S. Oho, H. Kawaguchi, YOSHIMOTO MASAHIKO

  Mar. 2013, DATE RIIF Workshop, English

  [Refereed]

  International conference proceedings


• A Physical Unclonable Function Chip Exploiting Load Transistors’ Variation in SRAM Bitcells

  S. Okumura, S. Yoshimoto, H. Kawaguchi, YOSHIMOTO MASAHIKO

  Jan. 2013, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 79 - 80, English

  [Refereed]

  International conference proceedings


• A 40-nm 144-mW VLSI Processor for Real-time 60-kWord Continuous Speech Recognition

  Guangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2013, 2013 18TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 71 - 72, English

  [Refereed]

  International conference proceedings


• A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Power Disturb Mitigation Technique

  S. Yoshimoto, M. Terada, S. Okumura, T. Suzuki, S. Miyano, H. Kawaguchi, YOSHIMOTO MASAHIKO

  Jan. 2013, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 77 - 78, English

  [Refereed]

  International conference proceedings


• A SUB-100-MILLIWATT DUAL-CORE HOG ACCELERATOR VLSI FOR REAL-TIME MULTIPLE OBJECT DETECTION

  Kenta Takagi, Kosuke Mizuno, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2013, 2013 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING (ICASSP), 2533 - 2537, English

  [Refereed]

  International conference proceedings


• A 38 mu A Wearable Biosignal Monitoring System with Near Field Communication

  Yamashita, Ken, Izumi, Shintaro, Nakano, Masanao, Fujii, Takahide, Konishi, Toshihiro, Kawaguchi, Hiroshi, Kimura, Hiromitsu, Marumoto, Kyoji, Fuchikami, Takaaki, Fujimori, Yoshikazu, Nakajima, Hiroshi, Shiga, Toshikazu, Yoshimoto, Masahiko

  2013, 2013 IEEE 11TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), pp.1 - 4, English

  [Refereed]

  International conference proceedings


• A 14 μa ECG processor with robust heart rate monitor for a wearable healthcare system

  Shintaro Izumi, Ken Yamashita, Masanao Nakano, Toshihiro Konishi, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto

  2013, European Solid-State Circuits Conference, 145 - 148, English

  [Refereed]

  International conference proceedings


• Handsfree Voice Interface for Home Network Service using a Microphone Array Network

  S. Soda, M. Nakamura, S. Matsumoto, S. Izumi, H. Kawaguchi, YOSHIMOTO MASAHIKO

  Dec. 2012, In Proc. of Third International Conference on Networking and Computing, pp. 195 - 200, English

  [Refereed]

  International conference proceedings


• A 128-bit Chip Identification Generating Scheme Exploiting Load Transistor's Variation in SRAM Bitcells

  S. Okumura, S. Yoshimoto, H. Kawaguchi, YOSHIMOTO MASAHIKO

  Dec. 2012, IEICE Trans. Fundamentals, Vol. E95-A(No. 12) (No. 12), pp. 2226 - 2233, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure

  S. Yoshimoto, T. Amashita, S. Okumura, H Kawaguchi, YOSHIMOTO MASAHIKO

  Oct. 2012, IEICE Trans. Electron, Vol. E95-C(No. 10,) (No. 10,), pp. 1675 - 1681, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• Architectural Study on HOG Feature Extraction Processor for Real-Time Object Detection

  K. Mizuno, Y. Terachi, K. Takagi, S. Izumi, H. Kawaguchi, YOSHIMOTO MASAHIKO

  Sep. 2012, IEEE Workshop on Signal Processing Systems (SiPS), pp.197 - 202, English

  [Refereed]

  International conference proceedings


• A 40-nm 168-mW 2.4×-Real-Time VLSI Processor for 60-kWord Continuous Speech Recognition

  G. He, T. Sugahara, Y. Miyamoto, S. Izumi, H. Kawaguchi, YOSHIMOTO MASAHIKO

  Sep. 2012, IEEE Custom Integrated Circuits Conference(CICC), pp.1 - 4, English

  [Refereed]

  International conference proceedings


• Instantaneous Heart Rate Detection Using Short-Time Autocorrelation for Wearable Healthcare Systems

  M. Nakano, T. Konishi, S. Izumi, H. Kawaguchi, YOSHIMOTO MASAHIKO

  Aug. 2012, 34th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), pp.6703 - 6706, English

  [Refereed]

  International conference proceedings


• Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process

  S. Yoshimoto, T. Amashita, S. Okumura, K. Nii, M. Yoshimoto, KAWAGUCHI HIROSHI

  Aug. 2012, IEICE Trans. Fundamentals, Vol. E95-A(no. 8) (no. 8), pp. 1359 - 1365, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A 40 nm 144 mW VLSI Processor for Realtime 60 kWord Continuous Speech Recognition

  G. He, T. Sugahara, T. Fujinaga, Y. Miyamoto, H. Noguchi, S. Izumi, H. Kawaguchi, YOSHIMOTO MASAHIKO

  Aug. 2012, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59(no. 8) (no. 8), pp.1656 - 1666, English

  [Refereed]

  Scientific journal


• Trading off ECU Footprint for Reliability in X-by-Wire Application with Hybrid TMR Architecture

  Y. Nakata, S. Izumi, H. Kawaguchi, YOSHIMOTO MASAHIKO

  Jun. 2012, DAC International Workshop on System Level-Design of Automotive Electronics/Software (SLDAES),, English

  [Refereed]

  International conference proceedings


• Neutron-Induced Soft Error Rate Estimation for SRAM Using PHITS

  S. Yoshimoto, T. Amashita, M. Yoshimura, Y. Matsunaga, H. Yasuura, S. Izumi, H. Kawaguchi, YOSHIMOTO MASAHIKO

  Jun. 2012, IEEE International On-Line Testing Symposium (IOLTS), pp. 173 - 176, English

  [Refereed]

  International conference proceedings


• A Variation-Aware 0.57-V Set-Associative Cache with Mixed Associativity Using 7T/14T SRAM,

  J. Jung, Y. Nakata, S. Okumura, H Kawaguchi, YOSHIMOTO MASAHIKO

  Jun. 2012, IEEE Faible Tension Faible Consommation (FTFC), English

  [Refereed]

  International conference proceedings


• A 62-dB SNDR Second-Order Gated Ring Oscillator TDC with Two-Stage Dynamic D-Type Flipflops as A Quantization Noise Propagator

  K. Okuno, T. Konishi, M.Yoshimoto, KAWAGUCHI HIROSHI

  Jun. 2012, IEEE International New Circuits and Systems (NEWCAS),, IEEE International New Circuit, pp.289 - 292, English

  [Refereed]

  International conference proceedings


• A 61- dB SNDR 700 um2 Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops

  T. Konishi, K. Okuno, S. Izumi, M. Yoshimoto, KAWAGUCHI HIROSHI

  Jun. 2012, Symposium on VLSI Circuits, pp. 190 - 191, English

  [Refereed]

  International conference proceedings


• A 51- dB SNDR DCO-Based TDC Using Two-Stage Second-Order Noise Shaping

  T. Konishi, K. Okuno, S. Izumi, M. Yoshimoto, KAWAGUCHI HIROSHI

  May 2012, IEEE International Symposium on Circuits and Systems (ISCAS),, pp. 3170 - 3173, English

  [Refereed]

  International conference proceedings


• SRAMセルを用いたLow書込みによるチップID生成手法

  奥村俊介, 吉本秀輔, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  Apr. 2012, 信学技報, vol. 112(no. 15) (no. 15), pp. 97 - 102, Japanese

  Scientific journal


• NMOS-Inside 6T SRAM Layout Reducing Neutron-Induced Multiple Cell Upsets

  S. Yoshimoto, T. Amashita, S. Okumura, K. Nii, H. Kawaguchi, YOSHIMOTO MASAHIKO

  Apr. 2012, IEEE International Reliability Physics Symposium (IRPS),, pp. 5B.5.1 - 5, English

  [Refereed]

  International conference proceedings


• A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing

  Y. Nakata, H. Kawaguchi, YOSHIMOTO MASAHIKO

  IEICE, Apr. 2012, IEICE Trans. Electron, Vol. E95-C(No. 4,) (No. 4,), pp. 523 - 533, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme

  S. Yoshimoto, M. Terada, S. Okumura, T. Suzuki, S. Miyano, H. Kawaguchi, YOSHIMOTO MASAHIKO

  IEICE, Apr. 2012, IEICE Trans. Electron, Vol. E95-C(No. 4) (No. 4), pp. 572 - 578, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A 0.15-μm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme

  S. Okumura, H. Fujiwara, K. Yamaguchi, S. Yoshimoto, M. Yoshimoto, KAWAGUCHI HIROSHI

  Apr. 2012, IEICE Trans. Electron., Vol. E95-C(No. 4) (No. 4), pp. 579 - 585, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• Bit Error Rate Estimation in SRAM Considering Temperature Fluctuation

  Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, Syusuke Yoshimoto, Yohei Nakata, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Mar. 2012, Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), pp. 514-517, English

  [Refereed]

  Scientific journal


• A 40-nm 256-Kb 0.6-V Operation Half-Select Resilient 8T SRAM with Sequential Writing Technique Enabling 367-mV VDDmin Reduction

  Masaharu Terada, Syusuke Yoshimoto, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Mar. 2012, Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), pp. 487-490, English

  [Refereed]

  Scientific journal


• 0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme

  Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Feb. 2012, IPSJ Transactions on System LSI Design Methodology, vol. 5, pp.32-43, English

  [Refereed]

  Scientific journal


• 読出しビット線リミット機構を備えた40-nm 256-Kb サブ10pJ/access動作8T SRAM

  吉本 秀輔, 寺田 正治, 梅木 洋平, 奥村 俊介, 川澄 篤, 鈴木 利一, 森脇 真一, 宮野 信治, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  2012, 信学技報, vol. 112(no. 169) (no. 169), pp. 7 - 12, Japanese

  Scientific journal


• 低電力ディスターブ緩和技術を備えた40nm 12.9pJ/access 8T SRAM

  吉本 秀輔, 寺田 正治, 奥村 俊介, 鈴木 利一, 宮野 信治, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  2012, 信学技報, vol. 112(no. 15) (no. 15), pp. 67 - 72, Japanese

  Scientific journal


• 低エネルギ比較機能を有するDMR応用7T SRAM

  梅木 洋平, 奥村 俊介, 中田 洋平, 柳田 晃司, 鍵山 祐輝, 吉本 秀輔, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  2012, 信学技報, vol. 112(no. 15) (no. 15), pp. 85 - 90, Japanese

  Scientific journal


• 強誘電体キャパシタを用いた6T4CシャドウSRAMの高性能化技術

  中川 知己, 吉本 秀輔, 北原 佑起, 柳田 晃司, 梅木 洋平, 奥村 俊介, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  2012, 信学技報, vol. 112(no. 365) (no. 365), p. 41, Japanese

  Scientific journal


• プロセスばらつきを考慮した低電圧動作混合連想度キャッシュ構造

  鄭 晋旭, 中田 洋平, 奥村 俊介, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  2012, 信学技報, vol. 112(no. 170) (no. 170), pp. 1 - 6, Japanese

  Scientific journal


• ウェアラブル生体情報計測システムのための瞬時心拍検出アルゴリズム

  山下 顕, 中野 将尚, 小西 恵大, 和泉 慎太郎, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  2012, 信学技報, vol. 112(no. 365) (no. 365), p. 27, Japanese

  Scientific journal


• HOG特徴量による実時間物体検出プロセッサのFPGA実装

  高木 健太, 水野 孝祐, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  2012, 信学技報, vol. 112(no. 365) (no. 365), p. 61, Japanese

  Scientific journal


• 2.4倍速実時間6万語彙連続音声認識プロセッサの開発

  宮本 優貴, 何 光霽, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  2012, 信学技報, vol. 112(no. 365) (no. 365), pp. 49 - 53, Japanese

  Scientific journal


• Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes

  Takashi Matsuda, Shintaro Izumi, Yasuharu Sakai, Takashi Takeuchi, Hidehiro Fujiwara, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

  Jan. 2012, IEICE Transactions on Communications, vol. E95-B, no. 1, pp. 178-188, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique

  S. Yoshimoto, M. Terada, S. Okumura, T. Suzuki, S. Miyano, H. Kawaguchi, M. Yoshimoto

  2012, IEICE ELECTRONICS EXPRESS, 9(12) (12), 1023 - 1029, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme

  Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2012, Proceedings of the International Symposium on Low Power Electronics and Design, 85 - 90, English

  [Refereed]

  International conference proceedings


• チップ間ばらつき及びチップ内ばらつきを抑制する基板バイアス制御回路を備えた0.42-V 576-Kb 0.15-um FD-SOI 7T/14T SRAM

  吉本 秀輔, 山口 幸介, 奥村 俊介, 吉本 雅彦, 川口 博

  Dec. 2011, 信学技報, vol. 111, no. 352, ICD2011-133, Japanese

  Scientific journal


• A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output

  Toshihiro Konish, Hyeokjong Lee, Shintaro Izumi, Takashi Takeuchi, Masahiko YOSHIMOTO, Hiroshi KAWAGUCHI

  Dec. 2011, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E94-A, No.12, pp.2701-270, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• 7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory

  Shunsuke Okumura, Yuki Kagiyama, Yohei Nakata, Syusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Dec. 2011, IEICE Trans. Fundamentals, vol. E94-A, No. 12, pp. 2693-2, English

  [Refereed]

  Scientific journal


• 256-KB Associativity-Reconfigurable Cache with 7T/14T SRAM for Aggressive DVS Down to 0.57 V

  Jung Jin-Wook, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Dec. 2011, Proceedings of 18th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 524-527, English

  [Refereed]

  Scientific journal


• A Low-Power Multi Resolution Spectrum Sensing Architecture for a Wireless Sensor Network with Cognitive Radio

  Toshihiro Konish, Shintaro IZUMI, Ko Tsuruda, Hyeokjong Lee, Takashi Takeuchi, Masahiko YOSHIMOTO, Hiroshi KAWAGUCHI

  Nov. 2011, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E94-A, No.11, pp.2287-229, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• Low-Power Block-Level Instantaneous Comparison 7T SRAM for Dual Modular Redundancy

  Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Syusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Sep. 2011, Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4, English

  [Refereed]

  Scientific journal


• A 40 nm 144 mW VLSI Processor for Realtime 60 kWord Continuous Speech Recognition

  Guangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Sep. 2011, Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4, English

  [Refereed]

  Scientific journal


• A 128-bit Chip Identification Generating Scheme Exploiting SRAM Bitcells with Failure Rate of 4.45 � 10-19

  Shunsuke Okumura, Syusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Sep. 2011, Proceedings of IEEE European Solid-State Circuits Research Conference (ESSCIRC), pp. 527-530, English

  [Refereed]

  Scientific journal


• A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Router

  Yohei Nakata, Yusuke Takeuchi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Aug. 2011, 14th Euromicro Conference on Digital System Design (DSD), pp. 801-804, English

  [Refereed]

  Scientific journal


• Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure

  Syusuke Yoshimoto, Takro Amashita, Daisuke Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Jul. 2011, IEEE International On-Line Testing Symposium (IOLTS), pp.151-156, English

  [Refereed]

  Scientific journal


• Data Aggregation Protocol for Multiple Sound Sources Acquisition with Microphone Array Network

  Shintaro Izumi, Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shimpei Soda, Masahiko YOSHIMOTO, Hiroshi KAWAGUCHI

  Jul. 2011, Proceedings of 20th International Conference on Computer Communications and Networks (ICCCN), English

  [Refereed]

  Scientific journal


• Model-Based Fault Injection for Failure Effect Analysis -Evaluation of Dependable SRAM for Vehicle Control Units-

  Yohei Nakata, Yasuhiro Ito, Yasuo Sugure, Shigeru Oho, Yusuke Takeuchi, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Jun. 2011, 5th Workshop on Dependable and Secure Nanocomputing (WDSN), in conjunction with the 41st International Conference on Dependable Systems and Networks (DSN), pp. 91-96, English

  [Refereed]

  Scientific journal


• A 40-nm 0.5-V 20.1-uW/MHz 8T SRAM with Low-Energy Disturb Mitigation Scheme,

  Syusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Jun. 2011, Digest of Technical Papers 2011 Symposium on VLSI Circuits, pp. 72-73, English

  [Refereed]

  Scientific journal


• Positioning System for Mobile Terminals Using a Microphone Array Network as an Intuitive Interface

  Shimpei Soda, Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Shintaro Izumi, Masahiko YOSHIMOTO, Hiroshi KAWAGUCHI

  May 2011, The Third Joint Workshop on Hands-free Speech Communication and Microphone Arrays(HSCMA), English

  [Refereed]

  Scientific journal


• A 40-nm 640-μm2 45-dB Opampless All-Digital Second-Order MASH ΔΣ ADC

  Toshihiro Konish, Hyeokjong Lee, Shintaro Izumi, Masahiko YOSHIMOTO, Hiroshi KAWAGUCHI

  May 2011, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 518-521, English

  [Refereed]

  Scientific journal


• VLSI Architecture of GMM Processing and Viterbi Decoder for 60,000-Word Real-Time Continuous Speech Recognition

  Hiroki Noguchi, Kazuo Miura, Tsuyoshi Fujinaga, Takanobu Sugahara, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Apr. 2011, IEICE Trans. Electron, vol. E94-C, no. 4, pp. 458-467, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• Bit Error and Soft Error Hardenable 7T/14T SRAM with 150-nm FD-SOI Process

  Shusuke Yoshimoto, Takuro Amashita, Kosuke Yamaguchi, Shunsuke Okumura, Masahiko YOSHIMOTO, Hiroshi KAWAGUCHI

  Apr. 2011, IEEE International Reliability Phisics Symposium (IRPS), pp. 876-881, English

  [Refereed]

  Scientific journal


• A Low-power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition

  Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Tsuyoshi Fujinaga, Shintaro Izumi, Yasuo Ariki, Hiroshi Kawaguchi, Masahiko Yoshimoto

  Apr. 2011, IEICE Trans. Electron, vol. E94-C, no. 4, pp. 448-457, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• Data-Intensive Sound Acquisition System with Large-Scale Microphone Array,

  H. Noguchi, T. Takagi, K. Kugata, S. Izumi, M. Yoshimoto, H. Kawaguch

  Mar. 2011, Journal of Information Processing Society of Japan (IPSJ), vol. 19, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• 0.45-V Operating Vt-Variation Tolerant 9T/18T Dual-Port SRAM

  H. Noguchi, S. Okumura, T. Takagi, K. Kugata, M. Yoshimoto, H. Kawaguch

  Mar. 2011, Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 219-222, English

  [Refereed]

  Scientific journal


• 0.42-V 576-kb 0.15-um FD-SOI SRAM with 7T/14T Bit Cells and Substrate Bias Control Circuits for Intra-Die and Inter-Die Variability Compensation

  K. Yamaguchi, S. Okumura, M. Yoshimoto, H. Kawaguchi

  Jan. 2011, Proceedings of 7th Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EUROSOI), pp. 37-38, English

  [Refereed]

  Scientific journal


• A 75-variable MIQP solver processor for real-time autonomous robot control

  Masanori Nishino, Hiroki Noguchi, Yusuke Shimai, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

  2011, 2011 IEEE/SICE International Symposium on System Integration, SII 2011, pp. 469-472, 469 - 472, English

  [Refereed]

  International conference proceedings


• システムレベル故障注入技術を用いたディペ ンダブルプロセッサアーキテクチャの評価・ 検証

  Y. Nakata, ITO Hiroaki, SUGURE Yasuo, OHO Shigeru, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Nov. 2010, 電子情報通信学会技術研究報告, vol. 110, no. 317, VLD2010-74,, Japanese

  Scientific journal


• The Area Criteria of 6T and 8T SRAM Cells,

  S. Yoshimoto, S. Okumura, H. Kawaguchi, M. Yoshimoto

  Nov. 2010, EEE/ACM Workshop on Variability Modeling and Characterization (VMC), p.4, English

  Scientific journal


• ブロック一括コピー機能を有する7T SRAM

  S. Okumura, Y. Kagiyama, S. Yoshimoto, K. Yamaguchi, Y. Nakata, H. Kawaguchi, M. Yoshimoto

  Oct. 2010, 電子情報通信学会CEATEC JAPAN 2010 連携企画研究報告 （Digital Harmony を支えるプロ セッサとDSP，画像処理の最先 端）, pp.49-54 (2010), Japanese

  Scientific journal


• ネットワーク型マイクロホンアレイ間のデー タ集約による音声信号ビームフォーミング

  IZUMI Shintaro, NOGUCHI Hiroki, TAKAGI Tomoya, KUGATA Koji, SODA Shinpei, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi

  Oct. 2010, 電子情報通信学会CEATEC JAPAN 2010 連携企画研究報告 （Digital Harmony を支えるプロ セッサとDSP、画像処理の最先 端）, pp.95-100 (2010), Japanese

  Scientific journal


• A Low-Traffic and Low-Power Data-Intensive Sound Acquisition System with Perfect Aggregation Scheme Specialized for Microphone Array Network

  H. Noguchi, T. Takagi, K. Kugata, M. Yoshimoto, H. Kawaguchi

  Jul. 2010, Proceedings of International Conference on Sensor Technologies and Applications (SENSORCOMM 2010), pp. 157-162, English

  [Refereed]

  Scientific journal


• Live demonstration: Intelligent ubiquitous sensor network for sound acquisition,

  K. Kugata, T. Takagi, H. Noguchi, M. Yoshimoto, H. Kawaguchi

  May 2010, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS),, p. 1413, English

  [Refereed]

  Scientific journal


• Intelligent ubiquitous sensor network for sound acquisition

  K. Kugata, T. Takagi, H. Noguchi, M. Yoshimoto, H. Kawaguchi

  May 2010, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS, pp. 1414-1417, English

  [Refereed]

  Scientific journal


• A power-variation model fo r sensor node and the impact against life time of wireless sensor networks

  Takashi Matsuda, Takashi Takeuchi, Takefumi Aonishi, Masumi Ichien, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

  Mar. 2010, IEICE Electron. Express, Vol. 7, No. 3, pp.197-202, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A 58-uW Single-Chip Sensor Node Processor with Communication Centric Design

  S. Izumi, T. Takeuchi, T. Matsuda, H. Lee, T. Konishi, K. Tsuruda, Y. Sakai, H. Kawaguchi, C. Ohta, M. Yoshimoto

  Mar. 2010, IEICE Transactions on Electronics, vol. E93-C, no. 3, pp.261-269, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• "Microphone Array Network for Ubiquitous Sound Acquisition,"

  Tomoya Takagi, Hiroki Noguchi, Kouji Kugata, Masahiko Yoshimoto, Hiroshi Kawaguchi

  Mar. 2010, Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp. 1474-1477, English

  [Refereed]

  Scientific journal


• Design Choice in 45-nm Dual-Port SRAM – 8T, 10T Single End, and 10T Differential –

  H. Noguchi, Y. Iguchi, H. Fujiwara, S. Okumura, K. Nii, H. Kawaguchi, M. Yoshimoto

  Feb. 2010, IPSJ Transactions on System LSI Design Methodology, vol. 4, pp. 80-90, English

  [Refereed]

  Scientific journal

  Link to Kobe Univ. Repository (Kernel)


• A Single-Chip Sensor Node LSI with Synchronous MAC Protocol and Divided Data-Buffer SRAM

  T. Takeuchi, S. Izumi, T. Matsuda, H. Lee, T. Konishi, K. Tsuruda, Y. Sakai, H. Kawaguchi, M. Yoshimoto

  Nov. 2009, International SoC Design Conference 2009, English

  [Refereed]

  Scientific journal


• "An Ultra-Low-Power VAD Hardware Implementation for Intelligent Ubiquitous Sensor Networks,"

  Hiroki Noguchi, Tomoya Takagi, Masahiko Yoshimoto, Hiroshi Kawaguchi

  Oct. 2009, Proceedings of IEEE Workshop on Signal Processing Systems (SiPS), pp. 214-219, English

  [Refereed]

  Scientific journal


• Parallelized Viterbi Processor for 5,000-Word Large-Vocabulary Real-Time Continuous Speech Recognition FPGA System

  T. Fujinaga, K. Miura, H. Noguchi, H. Kawaguchi, M. Yoshimoto

  Sep. 2009, ISCA Annual Conference of International Speech Communication Association (Interspeech), pp.1483-1486, English

  [Refereed]

  Scientific journal


• A 60-dB Image Rejection Filter Using Δ-Σ Modulation and Frequency Shifting,

  T. Konishi, K. Tsuruda, S. Izumi, H. Lee, H. Fujiwara, T. Takeuchi, H. Kawaguchi, M. Yoshimoto

  Aug. 2009, 2009 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Victoria, B.C., Canada, pp. 565-570, English

  [Refereed]

  Scientific journal


• A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks,

  T. Takeuchi, S. Mikami, H. Lee, H. Kawaguchi, C. Ohta, M. Yoshimoto

  Jun. 2009, IEICE Transactions on Communications, vol. E92-C, no. 6, pp. 815-821, English

  [Refereed]

  Scientific journal


• 58-uW Single-Chip Sensor Node Processor Using Synchronous MAC Protocol,

  T. Takeuchi, S. Izumi, T. Matsuda, H. Lee, Y. Otake, T. Konishi, K. Tsuruda, Y. Sakai, H. Fujiwara, C. Ohta, H. Kawaguchi, M. Yoshimoto

  Jun. 2009, Digest of Technical Papers2009 Symposium on VLSI Circuits, pp. 290- 291, English

  [Refereed]

  Scientific journal


• A Dependable SRAM with 7T/14T Memory Cells

  H. Fujiwara, S. Okumura, Y. Iguchi, H. Noguchi, H. Kawaguchi, M. Yoshimoto

  Apr. 2009, IEICE Transactions on Electronics, vol. E92-C, no. 4, pp. 423-432, English

  [Refereed]

  Scientific journal


• 低消費電力センサノードVLSIのための時刻同期型MACプロトコルの研究

  IZUMI Shintaro, MATSUDA Takashi, TAKEUCHI Takashi, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  Mar. 2009, 電子情報通信学会技術研究報告(信学技報), vol. 108, no. 457, NS2008-174,, Japanese

  International conference proceedings


• A 0.56-V 128kb 10T SRAM Using Column Line Assist (CLA) Scheme

  OKUMURA Syunsuke, IGUCHI Yusuke, YOSHIMOTO Shusuke, FUJIWARA Hidehiro, NOGUCHI Hiroki, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Mar. 2009, International Symposium on Quality Electronic Design 2009, 0, English

  [Refereed]

  International conference proceedings


• 7T/14TディペンダブルSRAMおよびそのセル配置構造

  FUJIWARA Hidehiro, OKUMURA Syunsuke, IGUCHI Yusuke, NOGUCHI Hiroki, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Mar. 2009, 電子情報通信学会総合大会, 0, Japanese

  International conference proceedings


• A 7T 14T Dependable SRAM and Its Array Structure to Avoid Half Selection,

  FUJIWARA Hidehiro, OKUMURA Syunsuke, IGUCHI Yusuke, NOGUCHI Hiroki, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jan. 2009, International Conference on VLSI Design, pp. 295-300, English

  [Refereed]

  International conference proceedings


• チップ間ばらつき 補正機能を有する基板バイアス制御を用いた0.42V動作486kb FD-SOI SRAM

  山口 幸介, 藤原 英弘, 竹内 隆, 大竹 優, 吉本 雅彦, 川口 博

  Dec. 2008, 電子情 報通信学会技術研究報告(信学技報), vol. 108, no. 347, ICD2008-127, Japanese

  Scientific journal


• A Low Memory Bandwidth Gaussian Mixture Model (GMM) Processor for 20,000-Word Real-Time Speech Recognition FPGA System

  MIURA Kazuo, NOGUCHI Hiroki, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Dec. 2008, International Conference on Field-Programmable Technology 2008, 0, English

  [Refereed]

  International conference proceedings


• A Flexible Baseband Processor with Multi-Resolution Spectrum-Sensing Functionality,

  TSURUDA Koh, IZUMI Shintaro, Hyeokjong Lee, Takashi Takeuchi, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Dec. 2008, International Symposium on Information Theory and its Applications, pp. 1423-1428, English

  [Refereed]

  International conference proceedings


• Cross-Layer Design for Low-Power Wireless Sensor Node Using Wave Clock,

  TAKEUCHI Takashi, OTAKE Yu, ICHIEN Masumi, GION Akihiro, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  Nov. 2008, IEICE Transactions on Communications, vol. E91-B, no. 11, pp. 3480-3, English

  [Refereed]

  Scientific journal


• Counter-based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks

  IZUMI Shintaro, TAKEUCHI Takashi, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko, MATSUDA Takashi

  Nov. 2008, IEICE Transactions on Communications,, vol. E91-B, no. 11, pp. 3489-3, English

  [Refereed]

  Scientific journal


• 全整数計画問題ソルバーのFPGA実装,

  TANI Junichi, NOGUCHI Hiroki, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Oct. 2008, 情報処理学会関西支部大会,, D-05, Japanese

  International conference proceedings


• コグニティブ無線向け可変帯域ディジタルバンドパスフィルタの設計

  TSURUTA Koh, IZUMI Shintaro, LEE Hyeokjong, TAKEUCHI Takashi, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Oct. 2008, 電子情報通信学会技術研究報告(信学技報),, vol. 108, no. 253, ICD2008-82,, Japanese

  International conference proceedings


• An Inter-Die Variability Compensation Scheme for 0.42-V 486-kb FD-SOI SRAM using Substrate Control,

  H. Fujiwara, T. Takeuchi, Y. Otake, M. Yoshimoto, H. Kawaguchi

  Oct. 2008, Proceedings of IEEE International SOI Conference, pp. 93-94, English

  [Refereed]

  International conference proceedings


• ワイヤレスセンサネットワークのためのデータ集約を考慮した部分起動メモリの電力削減効果に関する研究

  SAKAI Yasuharu, MATSUDA Takashi, IZUMI Shintaro, TAKEUCHI Takashi, FUJIWARA Hidehiro, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  Sep. 2008, 電子情報通信学会ソサイエティ大会, B-20-10, pp. 346, Japanese

  International conference proceedings


• An H.264 AVC MP@L4.1 Quarter-Pel Motion Estimation Processor VLSI for Real-Time MBAFF Encoding

  Kosuke Mizuno, Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Sep. 2008, IEEE International Conference on Electronics, Circuits, and Systems(ICECS 2008),, 0, English

  [Refereed]

  International conference proceedings


• Which is the Best Dual-Port SRAM in 45-nm Process Technology? - 8T, 10T Single End, and 10T Differential -,

  NOGUCHI Hiroki, OKUMURA Syunsuke, IGUCHI Yusuke, FUJIWARA Hidehiro, MORITA Yasuhiro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jun. 2008, Proc. International Conference on IC Design and Technology, pp.55-58,, English

  [Refereed]

  International conference proceedings


• Novel Video Memory Reduces 45% of Bitline Power using Majority Logic and Data-Bit Reordering

  FUJIWARA Hidehiro, NII Koji, NOGUCHI Hiroki, MIYAKOSHI Junichi, MURACHI Yuichiro, MORITA Yasuhiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jun. 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 6, pp. 620-627, English

  [Refereed]

  Scientific journal


• 高信頼性モードと高速アクセスモードを有するディペンダブルSRAM

  OKUMURA Syunsuke, FUJIWARA Hidehiro, IGUCHI Yusuke, NOGUCHI Hiroki, MORITA Yasuhiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  May 2008, 電子情報通信学会技術研究報告,, VLD2008-12, pp.31-36, Japanese

  International conference proceedings


• サブ 100mW H.264 AVC MP@L4.1 HDTV 解像度対応整数画素精度動き検出プロセッサコア

  MIZUNO Kosuke, MIYAKOSHI Junichi, MURACHI Yuichiro, HAMAMOTO Masaki, IINUMA Takahiro, ISHIHARA Tomokazu, YIN Fang, LEE Jangchung, KAMINO Tetsuya, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  May 2008, 電子情報通信学会技術研究報告, VLD2008-12, pp.25-30, Japanese

  International conference proceedings


• A Sub 100 mW H.264 AVC MP@L4.1 Integer-Pel Motion Estimation Processor VLSI for MBAFF Encoding

  Yuichiro Murachi, Kosuke Mizuno, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  May 2008, International Symposium on Circuits and Systems(ISCAS), 0, English

  [Refereed]

  International conference proceedings


• Impact of Random Access Memory aware Data Aggregation for Wireless Sensor Network

  MATSUDA Takashi, IZUMI Shintaro, TAKEUCHI Takashi, FUJIWARA Hidehiro, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  Apr. 2008, Asia-Pacific Symposium on Information and Telecommunication Technologies (APSITT), pp. 130-134, English

  [Refereed]

  International conference proceedings


• Hop Count Aware Broadcast Algorithm with Random Assessment Delay Extension for Wireless Sensor Networks

  IZUMI Shintaro, MATSUDA Takashi, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  Apr. 2008, Asia-Pacific Symposium on Information and Telecommunication Technologies (APSITT), pp. 30-35, English

  [Refereed]

  International conference proceedings


• A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition

  MURACHI Yuichiro, FUKUYAMA Yuki, YAMAMOTO Ryo, MIYAKOSHI Junichi, KAWAGUCHI Hiroshi, ISHIHARA Hajime, MIYAMA Masayuki, MATSUDA Yoshio, YOSHIMOTO Masahiko

  Apr. 2008, IEICE Trans. Electron, 0, English

  [Refereed]

  Scientific journal


• A sub 100 mW H.264 MP@L4.1 Integer-pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-connected Systolic Array and Segmentation-free, Rectangle-access Search-window Buffer

  MURACHI Yuichiro, MIYAKOSHI Junichi, HAMAMOTO Masaki, IINUMA Takahiro, ISHIHARA Tomokazu, YIN Fang, LEE Jangchung, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Apr. 2008, IEICE Trans. Electron, 0, English

  [Refereed]

  Scientific journal


• A Power-Efficient SRAM Core Architecture with Segmentation-Free and Rectangular Accessibility for Super-Parallel Video Processing

  MURACHI Yuichiro, KAMINO Tetsuya, MIYAKOSHI Junichi, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Apr. 2008, 2008 International Symposium on VLSI Design, Automation & Test (VLSI-DAT), pp. 63-66, English

  [Refereed]

  International conference proceedings


• A 10T Non-Precharge Two-Port SRAM Reducing Readout Power for Video Processing

  NOGUCHI Hiroki, IGUCHI Yusuke, FUJIWARA Hidehiro, OKUMURA Syunsuke, MORITA Yasuhiro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Apr. 2008, IEICE Trans. Electron., vol. E91-C, no. 4, pp. 543-552, English

  [Refereed]

  Scientific journal


• Quality of a Bit (QoB): A New Concept in Dependable SRAM

  FUJIWARA Hidehiro, OKUMURA Syunsuke, IGUCHI Yusuke, NOGUCHI Hiroki, MORITA Yasuhiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Mar. 2008, 9th International Symposium on Quality Electronic Design (ISQED 2008), pp. 98-102, English

  [Refereed]

  International conference proceedings


• 超並列画像処理応用 任意位置任意サイズ矩形画素の1サイクルアクセスが可能なブロックアクセスメモリアーキテクチャ

  MURACHI Yuichiro, MIYAKOSHI Junichi, KAMINO Tetsuya, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Dec. 2007, 電子情報通信学会技術研究報告,ICD2007-128, Vol.107,No.382,pp.47-52, Japanese

  International conference proceedings


• Data Transmission Scheduling based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks

  MATSUDA Takashi, ICHIEN Mashumi, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  Dec. 2007, IEICE Trans. Communications, vol.E90-B, vol.12, pp.3410-341, English

  [Refereed]

  Scientific journal


• Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme

  MORITA Yasuhiro, FUJIWARA Hidehiro, NOGUCHI Hiroki, IGUCHI Yusuke, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Dec. 2007, IEICE Trans. Fundamentals, vol. E90-A, No. 12, pp. 2695-2, English

  [Refereed]

  Scientific journal


• Multipath Routing using Isochronous Medium Access Control with Multi Wakeup Period for Wireless Sensor Networks,

  MATSUDA Takashi, AONISHI Takafumi, TAKEUCHI Takashi, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  Oct. 2007, Proc. 4th IEEE International Symposium on Wireless Communication Systems 2007 (ISWCS 2007), pp.718-721, English

  [Refereed]

  International conference proceedings


• Improvement of Counter-based Broadcasting by Random Assessment Delay Extension for Wireless Sensor Networks

  IZUMI Shintaro, MATSUDA Takashi, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  Oct. 2007, Proc. International Conference on Sensor Technologies and Applications (SENSORCOMM 2007), pp.76-81, English

  [Refereed]

  International conference proceedings


• Cross-Layer Design for Low-Power Wireless Sensor Node using Long-Wave Standard Time Code

  OTAKE Yu, ICHIEN Mashumi, TAKEUCHI Takashi, GION Akihiro, MIKAMI Shinji, FUJIWARA Hidehiro, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  Oct. 2007, Proc. International Conference on Sensor Technologies and Applications (SENSORCOMM 2007), pp.341-346, English

  [Refereed]

  International conference proceedings


• Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes

  MORITA Yasuhiro, FUJIWARA Hidehiro, NOGUCHI Hiroki, IGUCHI Yusuke, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Oct. 2007, IEICE Trans. Electron, vol.E90-C, No.10, pp.1949-1956, English

  [Refereed]

  Scientific journal


• An elastic pipeline architecture for dynamic voltage scaling and its application to low-power portable H.264/AVC decoder with embedded frame buffer SRAM

  SAKATA Yoshinori, KAWAKAMI Kentaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Sep. 2007, EUROPEAN COMPUTING CONFERENCE, pp.00-00, English

  [Refereed]

  International conference proceedings


• DVS環境下での小面積・低電圧動作8T SRAMの設計

  MORITA Yasuhiro, FUJIWARA Hidehiro, NOGUCHI Hiroki, IGUCHI Yusuke, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Aug. 2007, 電子情報通信学会技術研究報告,ICD2007-95, Vol.107,No.195,pp.139-144, Japanese

  International conference proceedings


• 電源電圧と周波数の動的制御によるH.264/AVC デコーダの低消費電力化

  SAKATA Yoshinori, 川上 健太郎, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jul. 2007, 電子情報通信学会技術研究報告,ICD2007-52, Vol.107,No.163,pp.89-94, Japanese

  International conference proceedings


• 長波帯標準電波を用いた低電力センサーノードのための垂直統合設計

  OTAKE Yu, ICHIEN Masumi, TAKEUCHI Takashi, GION Akihiro, MIKAMI Shinji, FUJIWARA Hidehiro, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  Jul. 2007, 電子情報通信学会技術研究報告,ICD2007-49, Vol.107,No.163,pp.71-76, Japanese

  International conference proceedings


• ワイヤレスセンサーネットワーク応用キャリアセンス機能を持つ433MHz帯、356-uW電圧増幅器

  LEE Hyeokjong, MIKAMI Shinji, TAKEUCHI Takashi, ICHIEN Masumi, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  Jul. 2007, 電子情報通信学会技術研究報告,ICD2007-50, Vol.107,No.163,pp.77-82, Japanese

  International conference proceedings


• ビット線電力を74%削減する動画像処理応用 10T 非プリチャージ 2-port SRAMの設計

  OKUMURA Syunsuke, NOGUCHI Hiroki, IGUCHI Yusuke, FUJIWARA Hidehiro, MORITA Yasuhiro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jul. 2007, 電子情報通信学会技術研究報告,ICD2007-53, Vol.107,No.163,pp.95-100, Japanese

  International conference proceedings


• An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment

  MORITA Yasuhiro, FUJIWARA Hidehiro, NOGUCHI Hiroki, IGUCHI Yusuke, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jun. 2007, 2007 Symposium on VLSI Circuits Digest of Technical Papers, pp.256-257, English

  [Refereed]

  International conference proceedings


• A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing

  NOGUCHI Hiroki, IGUCHI Yusuke, FUJIWARA Hidehiro, MORITA Yasuhiro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  May 2007, Proc. IEEE Computer Society Annual Symposium on VLSI 2007 (ISVLSI 2007), pp.107-112, English

  [Refereed]

  International conference proceedings


• ビット線の電力を削減する実時間動画像処理応用2-port SRAM

  FUJIWARA Hidehiro, NII Koji, NOGUCHI Hiroki, MIYAKOSHI Junichi, MURACHI Yuichiro, MORITA Yasuhiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Apr. 2007, 電子情報通信学会技術研究報告,ICD2007-7, Vol.107,No.1,pp.35-40, Japanese

  International conference proceedings


• Delay Guarantee Service Interval Optimization for HCCA in IEEE 802.11e WLANs

  HIGUCHI Yuhi, Augusto FORONDA, OHTA Chikara, YOSHIMOTO Masahiko, OKADA Y

  Mar. 2007, Proc. IEEE Wireless Communications Networking Conference (WCNC 2007), pp.00-00, English

  [Refereed]

  International conference proceedings


• Power Memory Bwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture

  KAWAKAMI Kentaro, KURODA Mitsuhiko, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jan. 2007, Proc. 12th Asia South Pacific Design Automation Conference (12th ASP-DAC), pp.292-297, English

  [Refereed]

  International conference proceedings


• An Efficiency Degradation Model of Power Amplifier the Impact against Transmission Power Control

  MIKAMI Shinji, TAKEUCHI Takashi, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  Jan. 2007, Proc. IEEE 2007 Radio Wireless Symposium (RWS 2007), pp.447-450, English

  [Refereed]

  International conference proceedings


• A 356-�W 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks

  MIKAMI Shinji, ICHIEN Mashumi, TAKEUCHI Takashi, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  Jan. 2007, Proc. IEEE 2007 Radio Wireless Symposium (RWS 2007), pp.451-454, English

  [Refereed]

  International conference proceedings


• A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy SIMD/Systolic-Array Architecture

  MIYAKOSHI Junichi, MURACHI Yuichiro, MATSUNO Tetsuro, HAMAMOTO Masaki, IINUMA Takahiro, ISHIHARA Tomokazu, KAWAGUCHI Hiroshi, MIYAMA Masayuki, YOSHIMOTO Masahiko

  Dec. 2006, IEICE Trans. Fundamentals, Vol.E89-A No.12 pp.3623-3633, English

  [Refereed]

  Scientific journal


• A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline

  KAWAKAMI Kentaro, TAKEMURA Jun, KURODA Mitsuhiko, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Dec. 2006, IEICE Trans. Fundamentals, Vol.E89-A No.12 pp.3642-3651, English

  [Refereed]

  Scientific journal


• A 0.3-V Operating Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era Beyond

  MORITA Yasuhiro, FUJIWARA Hidehiro, NOGUCHI Hiroki, KAWAKAMI Kentaro, MIYAKOSHI Junichi, MIKAMI Shinji, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Dec. 2006, IEICE Trans. Fundamentals, Vol.E89-A No.12 pp.3634-3641, English

  [Refereed]

  Scientific journal


• A Power- Area-Efficient SRAM Core Architecture with Segmentation-Free Horizontal/Vertical Accessibility for Super-Parallel Video Processing

  MIYAKOSHI Junichi, MURACHI Yuichiro, ISHIHARA Tomokazu, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Nov. 2006, IEICE Trans. Electronics, Vol.E89-C No.11 pp.1629-1636, English

  [Refereed]

  Scientific journal


• An 800-�W H.264 Baseline-Profile Motion Estimation Processor Core

  IINUMA Takahiro, MIYAKOSHI Junichi, MURACHI Yuichiro, MATSUNO Tetsuro, HAMAMOTO Masaki, ISHIHARA Tomokazu, KAWAGUCHI Hiroshi, MIYAMA Masayuki, YOSHIMOTO Masahiko

  Nov. 2006, 2006 IEEE Asian Solid-State Circuits Conference Proceedings, pp.99-102, English

  [Refereed]

  International conference proceedings


• 画像符号化SoCの低消費電力化のための垂直統合設計研究

  YOSHIMOTO Masahiko

  Oct. 2006, 電子情報通信学会技術研究報告, ICD2006-122Vol.106No.316pp.75-, Japanese

  International conference proceedings


• Isochronous MAC using Low Frequency Radio Wave Time Synchronization for Wireless Sensor Networks

  ICHIEN Mashumi, TAKEUCHI Takashi, MIKAMI Shinji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Oct. 2006, Proc. First International Conference on Communications Electronics (ICCE 2006), p.172-177, English

  [Refereed]

  International conference proceedings


• Data Transmission Scheduling based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks

  MATSUDA Takashi, ICHIEN Mashumi, MIKAMI Shinji, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  Oct. 2006, First International Conference on Communications Electronics (ICCE 2006), pp.00-00, English

  [Refereed]

  International conference proceedings


• A Two-Port SRAM for Real-Time Video Processor Saving 53% of Bitline Power with Majority Logic Data-Bit Reordering

  FUJIWARA Hidehiro, NII Koji, MIYAKOSHI Junichi, MURACHI Yuichiro, MORITA Yasuhiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Oct. 2006, Proc. International Symposium on Low Power Electronics Design (ISLPED), pp.61-66, English

  [Refereed]

  International conference proceedings


• A Power-Variation Model for Sensor Node the Impact against Life Time of Wireless Sensor Networks

  MATSUDA Takashi, TAKEUCHI Takashi, YOSHINO Hironori, ICHIEN Mashumi, MIKAMI Shinji, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  Oct. 2006, Proc. First International Conference on Communications Electronics (ICCE 2006), pp.106-111, English

  [Refereed]

  International conference proceedings


• A Power- Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing

  MIYAKOSHI Junichi, MURACHI Yuichiro, MATSUNO Tetsuro, HAMAMOTO Masaki, IINUMA Takahiro, ISHIHARA Tomokazu, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Oct. 2006, Proc. 14th IFIP International Conference on Very Large Scale Integration (VLSI-SoC 2006), pp.192-197, English

  [Refereed]

  International conference proceedings


• Aggregation Efficient-Aware Greedy Incremental Tree Routing for Wireless Sensor Networks

  MIKAMI Shinji, AONISHI Takafumi, YOSHINO Hironori, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Oct. 2006, IEICE Trans. Communications, Vol.E89-B No.10 pp.2741-2751, English

  [Refereed]

  Scientific journal


• しきい値電圧ばらつきを克服したDVS環境下における0.3V動作SRAMの開発

  NOGUCHI Hiroki, MORITA Yasuhiro, FUJIWARA Hidehiro, KAWAKAMI Kentaro, MIYAKOSHI Junichi, MIKAMI Shinji, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Aug. 2006, 電子情報通信学会技術研究報告, ICD2006-106Vol.106No.206pp.155, Japanese

  International conference proceedings


• Impact of Aggregation Efficiency on GIT Routing for Wireless Sensor Networks

  AONISHI Takafumi, MATSUDA Takashi, MIKAMI Shinji, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Aug. 2006, Proc. International Workshop on Wireless Sensor Networks Columbus, pp.00-00, English

  [Refereed]

  International conference proceedings


• AVC HDTVデコーダアーキテクチャ

  KAWAKAMI Kentaro, TAKEMURA Jun, KURODA Mitsuhiko, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jun. 2006, 電子情報通信学会技術研究報告, ICD-2006-45 Vol.106 No.92 pp.3, Japanese

  International conference proceedings


• A Vth-Variation-Tolerant SRAM with 0.3-V Minimum Operation Voltage for Memory-Rich SoC under DVS Environment

  MORITA Yasuhiro, FUJIWARA Hidehiro, NOGUCHI Hiroki, KAWAKAMI Kentaro, MIYAKOSHI Junichi, MIKAMI Shinji, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Jun. 2006, 2006 Symposium on VLSI Circuits Digest of Technical Papers, pp.16-17, English

  [Refereed]

  International conference proceedings


• A New Scheduler to Guarantee Delay Bound with Bwidth Optimization for HCCA in IEEE 802.11e WLANs

  HIGUCHI Yuhi, OHTA Chikara, OKADA Youji, YOSHIMOTO Masahiko

  Jun. 2006, 電子情報通信学会技術研究報告, IN2006-28Vol.106 No.118pp.67-7, Japanese

  International conference proceedings


• An Energy-Harvesting Wireless-Interface SoC for Short-Range Data Communication

  MIKAMI Shinji, MATSUNO Tetsuro, MIYAMA Masayuki, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, ONO Hiroaki

  May 2006, IEEJ Trans. Electronics Information Systems, Vol.126 No.5 pp.565-570, English

  [Refereed]

  Scientific journal


• 定期情報収集型センサネットワークのためのRTS/CTS交換に基づくデータ送信スケジューリング

  MATSUDA Takashi, ICHIEN Masumi, MIKAMI Shinji, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Apr. 2006, 電子情報通信学会技術研究報告, NS2006-7Vol.106No.14pp.25-28, Japanese

  International conference proceedings


• 送信電力制御による効率劣化の影響

  MIKAMI Shinji, TAKEUCHI Takashi, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  Apr. 2006, 電子情報通信学会技術研究報告, NS2006-4Vol.106No.14pp.13-16, Japanese

  International conference proceedings


• 製造ばらつきを考慮したセンサネットワークノード消費電力モデルの提案と評価

  TAKEUCHI Takashi, YOSHINO Hironori, ICHIEN Masumi, MATSUDA Takashi, MIKAMI Shinji, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Apr. 2006, 電子情報通信学会技術研究報告, NS2006-6Vol.106No.14pp.21-24, Japanese

  International conference proceedings


• センサネットワークのための長波帯標準電波時刻同期を用いた周期起動型MACの提案

  ICHIEN Masumi, TAKEUCHI Takashi, MIKAMI Shinji, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  Apr. 2006, 電子情報通信学会技術研究報告, NS2006-8Vol.106No.14pp.29-32, Japanese

  International conference proceedings


• センサネットワークのための集約率を考慮したGIT経路制御の評価

  AONISHI Takafumi, YOSHINO Hironori, MIKAMI Shinji, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Apr. 2006, 電子情報通信学会技術研究報告, NS2006-9Vol.106No.14pp.33-36, Japanese

  International conference proceedings


• An Architecture Study of Scalable Optical-Flow Processor for Real-Time Video Segmentation

  YAMAMOTO Ryo, FUKAYAMA Yuuki, KATAGIRI Tadayoshi, MIYAKOSHI Junichi, KURODA Yuki, MINEGISHI Noriyuki, MIYAMA Masayuki, KAWAGUCHI Hiroshi, IMAMURA Kosuke, HASHIMOTO Hideo, YOSHIMOTO Masahiko

  Apr. 2006, Proc. IEEE Symposium on Low-Power High-Speed Chips (COOL Chips IX), pp. 225-240, English

  [Refereed]

  International conference proceedings


• VLSI Architecture Study of a Read-Time Scalable Optical Flow Processor for Video Segmentation

  MINEGISHI Noriyuki, MIYAKOSHI Junichi, KURODA Yuki, KATAGIRI Tadayoshi, FUKUYAMA Yuuki, YAMAMOTO Ryo, MIYAMA Masayuki, IMAMURA Kosuke, HAMAMOTO Masaki, YOSHIMOTO Masahiko

  Mar. 2006, IEICE Trans. Electronics, Vol.E89-C; No.3; pp.230-242, English

  [Refereed]

  Scientific journal


• A Feed-Forward Dynamic VDD-VBB-Frequency Management for Low Power Motion Video Compression on 90nm RISC Processor

  KAWAKAMI Kentaro, KANOMORI Miwako, MORITA Yasuhiro, TAKEMURA Jun, OHIRA Hideo, MIYAMA Masayuki, YOSHIMOTO Masahiko

  2006, Intelligent Automation Soft Computing, Vol.12 No.3 pp.283-298, English

  [Refereed]

  Scientific journal


• Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-dominant Technology Era

  KAWAKAMI Kentaro, KANAMORI Miwako, MORITA Yasuhiro, TAKEMURA Jun, MIYAMA Masayuki, YOSHIMOTO Masahiko

  Dec. 2005, IEICE Trans. Fundamentals, Vol.E88-A; No.12; pp.3290-3297, English

  [Refereed]

  Scientific journal


• A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application

  MURACHI Yuichiro, HAMAMOTO Masaki, MATSUNO Tetsuro, MIYAKOSHI Junichi, MIYAMA Masayuki, YOSHIMOTO Masahiko

  Dec. 2005, IEICE Trans. Fundamentals, Vol.E88-A; No.12; pp.3492-3499, English

  [Refereed]

  Scientific journal


• モバイル応用H.264コーデックLSI向け低消費電力動き検出アルゴリズム

  HAMAMOTO Masaki, NAGAI Kenichi, MATSUNO Tetsuro, MURACHI Yuichiro, MIYAKOSHI Junichi, MIYAMA Masayuki, YOSHIMOTO Masahiko

  Nov. 2005, 第9回システムLSIワークショップ, pp.215-218, Japanese

  International conference proceedings


• A Wireless-Interface SoC Powered by Energy Harvesting for Short-range Data Communication

  MIKAMI Shinji, MATSUNO Tetsuro, MIYAMA Masayuki, YOSHIMOTO Masahiko, ONO Hiroaki

  Nov. 2005, 2005 IEEE Asian Solid-State Circuits Conference Proceedings;, pp.241-244; Hsinchu;, English

  [Refereed]

  International conference proceedings


• モバイル応用H.264コーデックLSI向け低消費電力動き検出アルゴリズム

  HAMAMOTO Masaki, NAGAI Kenichi, MATSUNO Tetsuro, MURACHI Yuichiro, MIYAKOSHI Junichi, MIYAMA Masayuki, YOSHIMOTO Masahiko

  Oct. 2005, 電子情報通信学会技術研究報告;SIP2005-107, Vol.105;No.349;pp.67-72, Japanese

  International conference proceedings


• センサネットワークのための集約率を考慮したGIT経路制御の評価

  AONISHI Takafumi, YOSHINO Hironori, MIKAMI Shinji, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Oct. 2005, 電子情報通信学会技術研究報告;NS2005-108, Vol.105; No.357; pp.37-40, Japanese

  International conference proceedings


• ワイヤレスセンサノードのための送信電力制御におけるインピーダンス不整合の影響

  MIKAMI Shinji, TAKEUCHI Takashi, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Sep. 2005, 2005年電子情報通信学会ソサイエティ大会;B-5-148, p.148, Japanese

  International conference proceedings


• 携帯機器応用 95mW MPEG2 MP@HL 動き検出プロセッサコア

  MURACHI Yuichiro, HAMANO Koji, MATSUNO Tetsuro, MIYAKOSHI Junichi, MIYAMA Masayuki, YOSHIMOTO Masahiko

  Aug. 2005, 電子情報通信学会技術研究報告;SDM2005-128, Vol.105;No.232;pp.1-6, Japanese

  International conference proceedings


• A 95mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High Resolution Video Application

  MURACHI Yuichiro, HAMAMOTO Masaki, MATSUNO Tetsuro, MIYAKOSHI Junichi, MIYAMA Masayuki, YOSHIMOTO Masahiko

  Jun. 2005, 2005 Symposium on VLSI Circuits Dig. Tech. Papers, pp.212-215, English

  [Refereed]

  International conference proceedings


• 動画像符号化動きベクトル検出のための低消費電力シストリックアレイアーキテクチャの研究

  MIYAKOSHI Junichi, MURACHI Yuichiro, HAMANO Koji, MATSUNO Tetsuro, MIYAMA Masayuki, YOSHIMOTO Masahiko

  May 2005, 電子情報通信学会技術研究報告;ICD2005-20, Vol.105; No.95; pp.1-6, Japanese

  International conference proceedings


• 近距離データ通信用超低消費電力ワイヤレスインターフェースLSI技術

  MIKAMI Shinji, MATSUNO Tetsuro, MIYAMA Masayuki, YOSHIMOTO Masahiko

  May 2005, 電子情報通信学会第4回シリコンアナログRF研究会, p.3, Japanese

  International conference proceedings


• A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation

  MIYAKOSHI Junichi, MURACHI Yuichiro, HAMAMOTO Masaki, MATSUNO Tetsuro, MIYAMA Masayuki, YOSHIMOTO Masahiko

  Apr. 2005, IEICE Trans. Electoronics, Vol.E88-C; No.4; pp.559-569, English

  [Refereed]

  Scientific journal


• A 400�W MPEG-4 Motion Estimation Processor Core for Mobile Video Application

  MIYAKOSHI Junichi, KURODA Yuki, MIYAMA Masayuki, IMAMURA Kosuke, HASHIMOTO Hideo, YOSHIMOTO Masahiko

  Dec. 2004, Proc. IP-Based SoC Design Forum Exhibition (IP/SoC 2004);Grenoble, vol. pp, English

  [Refereed]

  International conference proceedings


• 携帯機器応用低消費電力MPEG2 MP@HL動き検出プロセッサの開発

  MURACHI Yuichiro, HAMANO Koji, MIYAKOSHI Junichi, MIYAMA Masayuki, YOSHIMOTO Masahiko

  Nov. 2004, 第8回システムLSIワークショップ, pp.299-302, Japanese

  International conference proceedings


• ワイヤレス近距離データ通信システムLSIの設計

  MIKAMI Shinji, MATSUNO Tetsuro, MIYAMA Masayuki, YOSHIMOTO Masahiko

  Nov. 2004, 第8回システムLSIワークショップ, pp.215-218, Japanese

  International conference proceedings


• リーク電力を考慮した周波数-電圧協調制御型プロセッサの消費電力最小化スケジューリング

  KAWAKAMI Kentaro, KANAMORI Miwako, MORITA Yasuhiro, TAKEMURA Jun, MIYAMA Masayuki, YOSHIMOTO Masahiko

  Oct. 2004, 電子情報通信学会技術研究報告;ICD2004-114, Vol.104;No.363;pp.37-42, Japanese

  International conference proceedings


• A Feed-Foreward Dynamic Voltage Frequency Management by Workload Prediction for a Low Power Motion Video Compression

  YOSHIMOTO Masahiko, KAWAKAMI Kentaro

  Oct. 2004, Proc. Workshop on Synthesis System Integration of Mixed Information Technologies (SASIMI), pp. 365-370, English

  [Refereed]

  International conference proceedings


• A sub-mW MPEG-4 motion estimation processor core for mobile video application

  MIYAMA Masayuki, MIYAKOSHI Junichi, KURODA Yuki, IMAMURA Kosuke, HASHIMOTO Hideo, YOSHIMOTO Masahiko

  Sep. 2004, IEEE J. Solid-State Circuits, Vol.39;No.9;pp.1562-1570, English

  [Refereed]

  Scientific journal


• A Feed-Forward Dynamic Voltage Frequency Management for Power-Minimum Motion Video Compression in Sub-Decimicron Era

  KAWAKAMI Kentaro, KANAMORI Miwako, MORITA Yasuhiro, TAKEMURA Jun, MIYAKOSHI Junichi, OHIRA Hideo, MIYAMA Masayuki, YOSHIMOTO Masahiko

  Jun. 2004, Sixth Biannual World Automation Congress (WAC 2004) Proceedings, Vol.18;pp.279-284, English

  [Refereed]

  International conference proceedings


• 携帯機器応用低消費電力MPEG2 MP@HL動き検出プロセッサの開発

  MURACHI Yuichiro, HAMANO Koji, MIYAKOSHI Junichi, MIYAMA Masayuki, YOSHIMOTO Masahiko

  May 2004, 電子情報通信学会技術研究報告;ICD2004-24, Vol.104;No.67;pp.7-12, Japanese

  International conference proceedings


• VLSI-Oriented Motion Estimation Using a Steepest Descent Method in Mobile Video Coding

  MIYAMA Masayuki, MIYAKOSHI Junichi, IMAMURA Kosuke, HASHIMOTO Hideo, YOSHIMOTO Masahiko

  Apr. 2004, IEICE Trans. Electron, Vol.E87-C;No.4;pp.466-474, English

  [Refereed]

  Scientific journal


• A Feed-Forward Dynamic Voltage Control Algorithm for Low Power MPEG4 on Multi-Regulated Voltage CPU

  OHIRA Hideo, KAWAKAMI Kentaro, KANAMORI Miwako, MORITA Yasuhiro, MIYAMA Masayuki, YOSHIMOTO Masahiko

  Apr. 2004, IEICE Trans. Electron, Vol.E87-C;No.4;pp.457-465, English

  [Refereed]

  Scientific journal


• 低消費電力VLSI向けMPEG2 MP@HL動き検出アルゴリズムの開発(3) : 内蔵メモリ容量とデータ転送量の削減

  MIYAKOSHI Junichi, MURACHI Yuichiro, MIYAMA Masayuki, YOSHIMOTO Masahiko

  Mar. 2004, 2004年電子情報通信学会総合大会;C-12-15, p.117, Japanese

  International conference proceedings


• 低消費電力VLSI向けMPEG2 MP@HL動き検出アルゴリズムの開発(2) : 演算と制御の簡単化

  MURACHI Yuichiro, MIYAKOSHI Junichi, MIYAMA Masayuki, YOSHIMOTO Masahiko

  Mar. 2004, 2004年電子情報通信学会総合大会;C-12-14, p.116, Japanese

  International conference proceedings


• 低消費電力VLSI向けMPEG2 MP@HL動き検出アルゴリズムの開発(1) : アルゴリズムの提案

  MIYAMA Masayuki, MIYAKOSHI Junichi, MURACHI Yuichiro, YOSHIMOTO Masahiko

  Mar. 2004, 2004年電子情報通信学会総合大会;C-12-13, p.115, Japanese

  International conference proceedings


• A sub-mW MPEG-4 motion estimation processor core for mobile video application

  KURODA Yuki, MIYAKOSHI Junichi, MIYAMA Masayuki, IMAMURA Kosuke, HASHIMOTO Hideo, YOSHIMOTO Masahiko

  Jan. 2004, Proc. Asia South Pasific Design Automation Conference 2004, pp.527-528, English

  [Refereed]

  International conference proceedings


• 破綻回避を考慮したフィードフォワード型動的電圧制御によるMPEG4低消費電力アルゴリズム

  KANAMORI Miwako, KAWAKAMI Kentaro, MORITA Yasuhiro, OHIRA Hideo, MIYAMA Masayuki, YOSHIMOTO Masahiko

  Nov. 2003, 第7回システムLSIワークショップ, pp.255-258, Japanese

  International conference proceedings


• 携帯動画像端末応用サブmW・MPEG4動き検出プロセッサコアIPの開発

  KURODA Yuki, MIYAKOSHI Junichi, MIYAMA Masayuki, IMAMURA Kosuke, HASHIMOTO Hideo, YOSHIMOTO Masahiko

  Nov. 2003, 第7回システムLSIワークショップ, pp.251-254, Japanese

  International conference proceedings


• 携帯動画像端末応用サブmW・MPEG4動き検出プロセッサコアIP

  MIYAKOSHI Junichi, KURODA Yuki, MIYAMA Masayuki, IMAMURA Kosuke, HASHIMOTO Hideo, YOSHIMOTO Masahiko

  Oct. 2003, 電子情報通信学会技術研究報告;ICD2003‐132, Vol.103;No.382;pp.59-64, Japanese

  International conference proceedings


• ヒトゲノム解析アクセラレータLSIアーキテクチャ

  SASAKI Masamitsu, AKITA Junichi, MIYAMA Masayuki, YOSHIMOTO Masahiko

  Oct. 2003, 電子情報通信学会論文誌, Vol.J86-C;No.10;pp.1079-1085, Japanese

  [Refereed]

  Scientific journal


• A Sub-mW MPEG-4 Motion Estimation Processor Core for Mobile Video Application

  MIYAKOSHI Junichi, KURODA Yuki, MIYAMA Masayuki, IMAMURA Kosuke, HASHIMOTO Hideo, YOSHIMOTO Masahiko

  Sep. 2003, Proc. IEEE 2003 Custom Integrated Circuit Conference (CICC), pp.181-184, English

  [Refereed]

  International conference proceedings


• フィードフォワード型動的電圧制御によるMPEG4低消費電力化アルゴリズム

  KAWAKAMI Kentaro, OHIRA Hideo, KANAMORI Miwako, MIYAMA Masayuki, YOSHIMOTO Masahiko

  May 2003, 電子情報通信学会技術研究報告;ICD2003-30, Vol.103;No.89;pp.25-30, Japanese

  International conference proceedings


• An Ultra Low Power Motion Estimation Processor for MPEG2 HDTV Resolution Video

  MIYAMA Masayuki, O. Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, MIYAKOSHI Junichi, HASHIMOTO Hideo, S. Komatsu, M. Yagi, K. Taki, YOSHIMOTO Masahiko

  Apr. 2003, IEICE Trans. Electron, Vol.E86-C;No.4;pp.561-569, English

  [Refereed]

  Scientific journal


• A Feed-Forward Dynamic Voltage Control Algorithm for Low Power/High Quality MPEG4 on Multi-regulated Voltage CPU

  KAWAKAMI Kentaro, OHIRA Hideo, KANAMORI Miwako, MIYAMA Masayuki, YOSHIMOTO Masahiko

  Apr. 2003, Proc. IEEE Symposium on Low-Power High-Speed Chips (COOL Chips VI), Vol. 1;pp. 87-101, English

  [Refereed]

  International conference proceedings

• 超低消費電力貼り付け型心電・心拍SoC

  IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  応用物理学会, Apr. 2016, 応用物理, 85(4) (4), 301 - 305, Japanese

  [Refereed][Invited]

  Introduction scientific journal


• マイクアレイネットワークを用いたホームネットワークサービス向けハンズフリー音声インタフェース

  SODA Shimpei, NAKAMURA Masahide, MATSUMOTO Shinsuke, MATSUBARA Noriyuki, KUGATA Kouji, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  Mar. 2012, 電子情報通信学会技術研究報告, Vol. 111, No. 481, pp.73-78, Japanese

  Report scientific journal


• マイクアレイネットワークを用いた宅内サービス実現可能性の検討

  SODA Shimpei, MATSUMOTO Shinsuke, NAKAMURA Masahide, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO MASAHIKO

  Oct. 2011, 電子情報通信学会技術研究報告 CPSY2011-36, pp.61-66, Japanese

  Report scientific journal


• Multiple-Bit- Upset Tolerant 8T SRAM Cell Layout with Divided Wordline Structure

  S. Yoshimoto, T. Amashita, D. Kozuwa, T. Takata, M. Yoshimura, Y. Matsunaga, H. Yasuura, H. Kawaguchi, M. Yoshimoto

  Mar. 2011, Proceedings of Silicon Errors in Logic - System Effects (SELSE), pp. 106 -111, English

  [Refereed]

  Others


• Block-Basis On-Line BIST Architecture for Embedded SRAM Using Wordline and Bitcell Voltage Optimal Control

  M. Yoshikawa, S. Okumura, Y. Nakata, Y. Kagiyama, H. Kawaguchi, M. Yoshimoto

  Mar. 2011, Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 322- 325, English

  [Refereed]

  Others


• A 58-uW Sensor Node LSI with Synchronous MAC Protocol

  S. Izumi, T. Takeuchi, T. Matsuda, H. Lee, T. Konishi, K. Tsuruda, Y. Sakai, C. Ohta, H. Kawaguchi, M. Yoshimoto

  Sep. 2010, Proceedings of Asia-aPacific Radio Science Conference (AP-RASC), English

  [Refereed]

  Others


• A 34.7-mW Quad-Core MIQP Solver Processor for Robot Control

  H. Noguchi, J. Tani, Y. Shimai, M. Nishino, S. Izumi, H. Kawaguchi, M. Yoshimoto

  Sep. 2010, Proceedings of IEEE Custom Integrated Circuits Conference (CICC), English

  [Refereed]

  Others


• 7T SRAM Enabling Low-Energy Simultaneous Block Copy

  S. Okumura, S. Yoshimoto, K. Yamaguchi, Y. Nakata, H. Kawaguchi, M. Yoshimoto

  Sep. 2010, Proceedings of IEEE Custom Integrated Circuits Conference (CICC), Dig. Tech. Papers, English

  [Refereed]

  Others


• Scalable Parallel Processing for H.264 Encoding Application to Multi/Many-core Processor

  Y. Takeuchi, Y. Nakata, H. Kawaguchi, M. Yoshimoto

  Aug. 2010, Proceedings of the International Conference on Intelligent Control and Information Processing (ICICIP), pp. 163-170, English

  [Refereed]

  Others


• Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video

  K. Mizuno, H. Noguchi, G. He, Y. Terachi, T. Kamino, H. Kawaguchi, M. Yoshimoto

  Aug. 2010, Proceedings of 20th International Conference on Field Programmable Logic and Applications (FPL), pp608-611, English

  [Refereed]

  Others


• 0.5-V Operation Variation-Aware Word-Enhancing Cache Architecture Using 7T/14T hybrid SRAM

  Y. Nakata, S. Okumura, H. Kawaguchi, M. Yoshimoto

  Aug. 2010, Proceedings of International Symposium on Low Power Electronics and Design (ISLPED), pp. 219-224, English

  [Refereed]

  Others


• A Low-Power Multi Resolution Spectrum Sensing (MRSS) Architecture for a Wireless Sensor Network with Cognitive Radio

  S. Izum, K. Tsuruda, T. Takeuchi, H. Lee, H. Kawaguchi, M. Yoshimoto

  Jul. 2010, Proceedings of International Conference on Sensor Technologies and Applications (SENSORCOMM 2010), pp. 39-44, English

  [Refereed]

  Others


• Parallel-Processing VLSI Architecture for Mixed Integer Linear Programming

  H. Noguchi, J. Tani, Y. Shimai, H. Kawaguchi, M. Yoshimoto

  May 2010, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2362-2365, English

  [Refereed]

  Others


• FPGA Implementation of Mixed Integer Quadratic Programming Solver for Mobile Robot Control

  Y. Shimai, J. Tani, H. Noguchi, H. Kawaguchi, M. Yoshimoto

  Dec. 2009, Proceedings of IEEE International Conference on Field-Programmable Technology (FPT), pp. 447-450, English

  Others

• OHM大学テキスト・集積回路工学

  YOSHIMOTO Masahiko

  Joint work, オーム社, Mar. 2014, Japanese

  Textbook


• Image LSI System Design Technology

  ENOMOTO Tadayoshi, UCHIYAMA Kunio, KASAI Ryouta, YOSHIMOTO Masahiko, ONOE Takao, ABE Masahide, SEKI Masahiko, HAMAMOTO Takayuki

  Joint work, 株式会社コロナ社, Sep. 2003, Japanese

  General book

• 光電式容積脈波法による脈拍測定の低消費電力化手法

  WATANABE Kento, IZUMI Shintaro, YANO Yuji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  ヘルスケア・医療情報通信技術研究会（MICT）, Jan. 2019, Japanese, 電子情報通信学会, 東京都千代田区明治大学駿河台キャンパス, Domestic conference

  Oral presentation


• ウェアラブルデバイスのための心拍変動モニタリングにおけるサンプリングレート低減手法

  NISHIKAWA Yuki, IZUMI Shintaro, YANO Yuji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  第35回「センサ・マイクロマシンと応用システム」シンポジウム, Oct. 2018, Japanese, 電気学会 センサ・マイクロマシン部門, 北海道札幌市 札幌市民交流プラザ, Domestic conference

  Poster presentation


• ウェアラブルデバイスのための圧電素子を用いたマルチモーダルな心血管情報の計測

  OKANO Takaaki, IZUMI Shintaro, KATSUURA Takumi, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  第34回「センサ・マイクロマシンと応用システム」シンポジウム，01am2-PS-135，広島，2017年11月1日, Nov. 2017, Japanese, Domestic conference

  Oral presentation


• 消化管内への留置を目的とした飲み込み型デバイスの検討

  NAKAMURA Ryota, IZUMI Shintaro, KAWAGUCHI Hiroshi, OHTA Hidetoshi, YOSHIMOTO Masahiko

  第34回「センサ・マイクロマシンと応用システム」シンポジウム，31pm3-PS-46，広島，2017年10月31日, Oct. 2017, Japanese, Domestic conference

  Oral presentation


• ノイズフィードバック技術を用いたウェアラブル向け容量結合型心電センサ

  NAGASATO Yuki, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  IEICEソサイエティ大会, 2017年9月12-15日，東京, Sep. 2017, Japanese, Domestic conference

  Oral presentation


• 選択的ソース線駆動方式を用いた画像処理プロセッサ向け低消費電力28nm FD-SOI 8TデュアルポートSRAM

  MORI Haruki, NAKAGAWA Tomoki, KITAHARA Yuki, KAWAMOTO Yuta, TAKAGI Kenta, YOSHIMOTO Shusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  LSIとシステムのワークショップ2017 ポスターセッション, 東京, 2017年5月, May 2017, Japanese, Domestic conference

  Oral presentation


• マイクロ波ドップラーセンサを用いた車両走行中の心拍計測手法

  MATSUNAGA DAICHI, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  電子情報通信学会総合大会，B-20-10, 名古屋, 2017年3月22日., Mar. 2017, Japanese, 名古屋, Domestic conference

  Oral presentation


• プロセスばらつき耐性を有する低電圧動作STT-MRAM向けカウンターベース読出し回路

  UMEKI YOHEI, YANAGIDA KOUJI, YOSHIMOTO SHUSUKE, IZUMI SHINTARO, YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, TSUNODA KOJI, SUGII TOSHIHIRO

  LSIとシステムのワークショップ2016, May 2016, Japanese, Domestic conference

  Poster presentation


• 消化管内に留置可能な飲み込み型生体センサー

  IZUMI Shintaro, NAKAMURA Ryota, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  電子情報通信学会総合大会, Mar. 2016, Japanese, 福岡, Domestic conference

  Oral presentation


• Process variation tolerant counter base read circuit for low-voltage operating STT-MRAM

  UMEKI Yohei, YANAGIDA Koji, KUROTSU Hiroaki, KITAHARA Hiroto, MORI Haruki, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, YOSHIMOTO Shusuke, TSUNODA Koji, SUGII Toshihiro

  DATE EMS Workshop, Mar. 2016, English, Dresden,Germany, International conference

  Poster presentation


• Analysis of Soft Error Propagation considering Masking Effects on Re-convergent Path

  KIMI Yuta, MATSUKAWA Go, YOSHIDA Shuhei, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  IEEE Asian Test Symposium (ATS), Nov. 2015, English, International conference

  Oral presentation


• A 298-fJ/writecycle 650-fJ/readcycle 8T Three-Port SRAM in 28-nm FD-SOI Process Technology for Image Processor

  MORI Haruki, NAKAGAWA Tomoki, KITAHARA Yuki, KAWAMOTO Yuta, TAKAGI Kenta, YOSHIMOTO Shusuke, IZUMI Shintaro, Nii Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  IEEE Custom Integrated Circuits Conference (CICC), Sep. 2015, English, International conference

  Oral presentation


• 低SNR環境向け心拍抽出アルゴリズム

  MATSUNAGA Daichi, KAWAMOTO Yuta, NAKAI Yozaburo, OKUNO Keisuke, IZUMI Shintaro, YOSHIMOTO Masahiko

  LSIとシステムのワークショップ2015, May 2015, Japanese, 小倉, Domestic conference

  Poster presentation


• 時間デジタル変換器を用いたIOサイズ8bitAD変換器

  OKUNO Keisuke, 小西恵大, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi

  LSIとシステムのワークショップ2015 ポスターセッション, May 2015, Japanese, 小倉, Domestic conference

  Poster presentation


• ウェアラブル心電図計測SoC

  TANAKA Yoshito, NAKAI Yozaburo, KAWAMOTO Yuta, OKUNO Keisuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, KIMURA Hiromitsu, MURAMOTO Kyoji, FUCHIKAMI Takaaki, FUJIMORI Yoshikazu, YOSHIMOTO Masahiko

  LSIとシステムのワークショップ2015, May 2015, Japanese, 小倉, Domestic conference

  Poster presentation


• 6T4C型低消費電力不揮発メモリ

  KITAHARA Hiroto, NAKAGAWA Tomoki, IZUMI Shintaro, TANAGIDA Kouji, KITAHARA Yuki, YOSHIMOTO Shusuke, UMEKI Yohei, MORI Haruki, KAWAGUCHI Hiroshi, KIMURA Hiromitsu, MURAMOTO Kyoji, FUCHIKAMI Takaaki, FUJIMORI Yoshikazu, YOSHIMOTO Masahiko

  LSIとシステムのワークショップ2015, May 2015, Japanese, 小倉, Domestic conference

  Poster presentation


• 温度補償回路を用いた高速セットリングADPLL

  奥野 圭祐, 正木 何奈, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  第37回アナログRF研究会, Dec. 2014, Japanese, Domestic conference

  Oral presentation


• 低消費電力貼り付け型センサのためのテンプレートマッチングを用いたロバスト心拍抽出手法の開発

  中井 陽三郎, IZUMI SHINTARO, 中野 将尚, 山下 顕, 藤井 貴英, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  第31回「センサ・マイクロマシンと応用システム」シンポジウム, Oct. 2014, Japanese, Domestic conference

  Oral presentation


• 動作環境変動に応じて動的に動作マージンを拡大する自律制御キャッシュ

  KIMI YUTA, NAKATA YOHEI, OKUMURA SYUNSUKE, JUNG Jinwook, 澤田 卓也, 利川 托, NAGATA MAKOTO, 中野 博文, 藪内 誠, 藤原 英弘, 新居 浩二, 河合 浩行, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  LSIとシステムのワークショップ2014 ポスターセッション, May 2014, Japanese, 小倉, Domestic conference

  Poster presentation


• 磁性変化型メモリの書き込み高速化メモリアーキテクチャ

  森 陽紀, 柳田 晃司, 梅木 洋平, 吉本秀輔, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO, 角田 浩司, 杉井 寿博

  LSIとシステムのワークショップ2014 ポスターセッション, May 2014, Japanese, 電子情報通信学会集積回路研究専門委員会, 小倉, Domestic conference

  Poster presentation


• 温度補償回路を用いた高速セットリングADPLL

  正木 何奈, 奥野 圭祐, IZUMI SHINTARO, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  LSIとシステムのワークショップ2014 ポスターセッション, May 2014, Japanese, 電子情報通信学会集積回路研究専門委員会, 小倉, Domestic conference

  Poster presentation


• 一括コピー・比較が可能なSRAMを用いた低遅延デュアルコアロックステップアーキテクチャ

  吉田 周平, 松川 豪, 中田 洋平, 木美 雄太, 勝 康夫, 下澤 晶史, 於保 茂, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

  LSIとシステムのワークショップ2014 ポスターセッション, May 2014, Japanese, 電子情報通信学会集積回路研究専門委員会, 小倉, Domestic conference

  Poster presentation


• 38μAウェアラブル生体情報計測プロセッサ

  中井 陽三郎, IZUMI SHINTARO, 山下 顕, 中野 将尚, 藤井 貴英, 小西 恵大, KAWAGUCHI HIROSHI, 木村 啓明, 丸元 共治, 渕上 貴昭, 藤森 敬和, 中嶋 宏, 志賀 利一, YOSHIMOTO MASAHIKO

  LSIとシステムのワークショップ2014 ポスターセッション, May 2014, Japanese, Domestic conference

  Poster presentation


• ロバストな瞬時心拍抽出機能を有する低消費電力ウェアラブルヘルスケアシステム

  IZUMI Shintaro, NAKANO Masanao, YAMASHITA Ken, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  第14回計測自動制御学会システムインテグレーション部門講演会SI2013, Dec. 2013, Japanese, 神戸市, Domestic conference

  [Invited]

  Invited oral presentation


• 読出しビット線振幅制限機構及び読み出し加速回路を備えた8T SRAM

  UMEKI Yohei, YOSHIMOTO Shusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference

  Poster presentation


• 車載ECUのSRAMへの故障注入による自動車制御システムの挙動評価

  FUJIKAWA Asuka, TAKEUCHI Yusuke, NAKATA Yohei, 伊藤 康宏, 勝 康夫, 於保 茂, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference

  Poster presentation


• 核反応シミュレータを用いたソフトエラー率導出ツール及び耐マルチビットエラー6T SRAM

  YOSHIMOTO Shusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference

  Poster presentation


• ラウドコンピュータを用いたディペンダブルプロセッサの大規模故障注入評価

  MATSUKAWA Go, NAKATA Yohei, 伊藤 康宏, TAKEUTCI Yusuke, 勝 康夫, 於保 茂, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference

  Poster presentation


• ゼロデータを利用したSTT-RAMキャッシュの低エネルギー化設計

  KIMI Yuta, JUNG Jinwook, NAKATA Yohei, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi

  LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference

  Poster presentation


• HDTV解像度対応 実時間HOG特徴量抽出と複数物体検出を実現する43mWデュアルコアプロセッサ

  TKAGI Kenta, MIZUNO Kosuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference

  Poster presentation


• 65nm 700-μm2 61-dB 低ジッター2次ΔΣT-D変換器

  OKUNO Keisuke, KONISHI Toshihiro, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi

  LSIとシステムのワークショップ2013, May 2013, Japanese, 北九州市, Domestic conference

  Poster presentation


• ウェアラブルヘルスケアシステムのための 短時間自己相関を用いた瞬時心拍検出手法

  中野将尚, 小西恵大, 和泉慎太郎, 川口博, YOSHIMOTO MASAHIKO

  電気学会センサ・マイクロマシン部門大会, Oct. 2012, Japanese, 北九州, Domestic conference

  Public symposium


• 低電圧動作マージン拡大機能を有する連想度可変キャッシュ

  鄭晋旭, 中田洋平, 奥村俊介, 川口博, YOSHIMOTO MASAHIKO

  LSIとシステムのワークショップ 2012, May 2012, Japanese, 北九州, Domestic conference

  Poster presentation


• プロセスばらつきを考慮したNoCアーキテクチャ

  中田洋平, 川口博, YOSHIMOTO MASAHIKO

  LSIとシステムのワークショップ 2012, May 2012, Japanese, 北九州, Domestic conference

  Poster presentation


• 6万語彙実時間連続音声認識のための40nm, 144mW音声認識専用プロセッサの開発

  何光霽, 菅原隆伸, 藤永剛史, 宮本優貴, 野口紘希, 和泉慎太郎, 川口博, YOSHIMOTO MASAHIKO

  LSIとシステムのワークショップ 2012, May 2012, Japanese, 北九州, Domestic conference

  Poster presentation


• 40nm 640μm2 7.2bit プロセススケーラブル・オペアンプレス時間演算型AD変換器

  小西恵大, 奥野圭祐, 和泉慎太郎, 吉本雅彦, KAWAGUCHI HIROSHI

  LSIとシステムのワークショップ 2012, May 2012, Japanese, 北九州, Domestic conference

  Poster presentation


• 0.5V 12.9pJ/accessを実現する低電力ライトバック技術を備えた40nm 8T SRAM

  吉本秀輔, 寺田正治, 奥村俊介, 鈴木利一, 宮野信治, 川口博, YOSHIMOTO MASAHIKO

  LSIとシステムのワークショップ 2012, May 2012, Chinese, 北九州, Domestic conference

  Poster presentation


• 温度変化を考慮したSRAMのBER導出手法の検討

  KITAHARA Yuki, KAGIYAMA Yuki, OKUMURA Shunsuke, YANAGIDA Koji, YOSHIMOTO Syusuke, NAKATA Yohei, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  電子情報通信学会総合大会, Mar. 2012, Japanese, 電子情報通信学会, 岡山市, Domestic conference

  Oral presentation


• マイクアレイネットワークを用いたホームネットワークサービス向けハンズフリー音声インタフェース

  SODA_Shinpei, NAKAMURA_Masahide, MAtSUMOTO_Shinsuke, MATSUBARA_Noriyuki, KUGATA_Koji, 和泉 慎太郎_IZUMI_Shintaro, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  電子情報通信学会研究会, Mar. 2012, Japanese, 電子情報通信学会集積回路研究専門委員会, 那覇市, Domestic conference

  Oral presentation


• ディペンダブルSRAMのためのオンライン故障診断技術の開発

  FUJIKAWA Asuka, YOSHIKAWA Masahiro, OKUMURA Shunsuke, NAKATA Yohei, KAGIYAMA Yuki, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  電子情報通信学会総合大会, Mar. 2012, Japanese, 電子情報通信学会, 岡山市, Domestic conference

  Oral presentation


• 0.6V動作可能なハーフセレクト耐性を向上させる差動書込み技術を用いた40-nm 8T SRAM

  UMEKI_Yohei, TERADA_Masaharu, YOSHIMOTO_Syusuke, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  電子情報通信学会総合大会, Mar. 2012, Japanese, 電子情報通信学会, 岡山市, Domestic conference

  Oral presentation


• 低電圧動作におけるマージン拡大機能を有する連想度可変キャッシュ

  JUNG_JinWook, NAKATA_Yohei, OKUMURA_Shunsuke, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  電子情報通信学会研究会, Jan. 2012, Japanese, 電子情報通信学会集積回路研究専門委員会, 東京, Domestic conference

  Oral presentation


• 実時間ロボット制御のための75変数MIQP問題ソルバープロセッサ

  NISHINO Masanori, NOGUCHI Hiroki, SHIMAI Yusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  電子情報通信学会研究会, Jan. 2012, Japanese, 電子情報通信学会集積回路研究専門委員会, 東京, Domestic conference

  Oral presentation


• 低電力20相出力発振回路

  OKUNO_Keisuke, KONISHI_Toshihiro, LEE_Hyeokjong, 和泉 慎太郎_IZUMI_Shintaro, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  電子情報通信学会研究会, Dec. 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 大阪, Domestic conference

  Oral presentation


• マルチビットアップセット耐性及びシングルビットアップセット耐性を備えた8T SRAM セルレイアウト

  UMEKI_Yohei, YOSHIMOTO_Syusuke, AMASHITA_Takro, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  電子情報通信学会研究会, Dec. 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 大阪, Domestic conference

  Oral presentation


• チップ間ばらつき及びチップ内ばらつきを抑制する基板バイアス制御回路を備えた0.42-V 576-Kb 0.15-um FD-SOI 7T/14T SRAM

  YOSHIMOTO Syusuke, YAMAGUCHI Kosuke, OKUMURA Shunsuke, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi

  電子情報通信学会研究会 (2011), Dec. 2011, Japanese, Domestic conference

  Poster presentation


• 6万語彙実時間連続音声認識のための40nm,144mW音声認識専用プロセッサの開発

  SUGAHARA_Takanobu, HE_Guangji, FUJINAGA_Tsuyoshi, MIYAMOTO_Yuki, NOGUCHI_Hiroki, 和泉 慎太郎_IZUMI_Shintaro, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  デザインガイア2011, Nov. 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 宮崎市, Domestic conference

  Oral presentation


• 故障注入技術を用いたディペンダブルSRAMを搭載するプロセッサの信頼性評価・検証

  TAKEUCHI_Yusuke, NAKATA_Yohei, ITO_Yasuhiro, SUGURE_Yasuo, OHO_Shigeru, OKUMURA_Shunsuke, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  コンピュータシステム研究会, Oct. 2011, Japanese, 電子情報通信学会, 神戸市, Domestic conference

  Oral presentation


• マイクアレイネットワークを用いた宅内サービス実現可能性の検討

  SODA_Shinpei, NAKAMURA_Masahide, MAtSUMOTO_Shinsuke, MATSUBARA_Noriyuki, KUGATA_Koji, 和泉 慎太郎_IZUMI_Shintaro, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  コンピュータシステム研究会, Oct. 2011, Japanese, 電子情報通信学会, 神戸市, Domestic conference

  Oral presentation


• 低電力20相出力発振回路

  OKUNO_Keisuke, KONISHI_Toshihiro, 和泉 慎太郎_IZUMI_Shintaro, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  LSIとシステムのワークショップ 2011, May 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference

  Poster presentation


• 次世代知能ロボット制御のための混合整数2次計画問題(MIQP)ソルバーコアプロセッサ

  NISHINO Masanori, NOGUCHI Hiroki, TANI Junichi, SHIMAI Yusuke, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  LSIとシステムのワークショップ 2011, May 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference

  Poster presentation


• マルチビットアップセット耐性を備えた8T SRAMセルレイアウト

  AMASHITA_Takro, YOSHIMOTO_Syusuke, KOZUWA_Daisuke, TAKATA_Taiga, YOSHIMURA_Masayoshi, MATSUNAGA_Yusuke, YASUURA_Hiroto, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  LSIとシステムのワークショップ 2011, May 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference

  Poster presentation


• ブロックデータ一括コピー機能を有する7T SRAM

  KAGIYAMA_Yuki, OKUMURA_Shunsuke, YOSHIMOTO_Syusuke, NAKATA_Yohei, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  LSIとシステムのワークショップ 2011, May 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference

  Poster presentation


• フルHDTV実時間動画像認識のための低消費電力SIFT特徴量抽出プロセッサ

  TERACHI_Yosuke, MIZUNO_Kosuke, HE_Guangji, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  LSIとシステムのワークショップ 2011, May 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference

  Poster presentation


• ビットエラー耐性及びソフトエラー耐性を備えたFD-SOI 7T/14T SRAM

  吉本 秀輔, 天下 卓郎, 奥村 俊介, 山口 幸介, 吉本 雅彦, 川口 博

  LSIとシステムのワークショップ 2011, May 2011, Japanese, 北九州市, Domestic conference

  Poster presentation


• システムレベル故障注入技術によるディペンダブルメモリを搭載したプロセッサの評価・検証

  TAKEUCHI_Yusuke, NAKATA_Yohei, ITO_Yasuhiro, SUGURE_Yasuo, OHO_Shigeru, KAWAGUCHI_Hiroshi, YOSHIMOTO_Masahiko

  LSIとシステムのワークショップ 2011, May 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference

  Poster presentation


• 18TデュアルポートSRAM

  YANAGIDA Koji, NOGUCHI Hiroki, OKUMURA Shunsuke, TAKAGI Tomoya, KUGATA Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  LSIとシステムのワークショップ 2011, May 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference

  Poster presentation


• 7T/14T SRAMの細粒度制御による低電圧動作キャッシュアーキテクチャ

  JUNG JinWook, NAKATA Yohei, OKUMURA Shunsuke, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  LSIとシステムのワークショップ 2011, May 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference

  Poster presentation


• 18TデュアルポートSRAM

  YANAGIDA Koji, NOGUCHI Hiroki, OKUMURA Shunsuke, TAKAGI Tomoya, KUGATA Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  電子情報通信学会研究会, Apr. 2011, Japanese, 電子情報通信学会集積回路研究専門委員会, 神戸市, Domestic conference

  Poster presentation


• プロセスばらつきを考慮したNoCアーキテクチャの検討

  中田 洋平, 竹内 幸大, 川口 博, 吉本 雅彦

  情報処理学会研究報告 計算機アーキテクチャ(ARC), Oct. 2010, Japanese, Domestic conference

  Others


• 分散処理を用いた超低消費電力 ネットワーク型マイクロホンアレーの研究

  祖田 心平, 久賀田 耕史, 高木 智也, 和泉 慎太郎, 野口 紘希, 吉本 雅彦, 川口 博

  日本音響学会2010年秋季研究発表会, Sep. 2010, Japanese, 関西大学, Domestic conference

  Poster presentation


• マルチコアプロセッサにおけるH.264/AVC符号化処理の並列度とメモリアクセスに関する高効率実装

  中田 洋平, 竹内 幸大, 川口 博, 吉本 雅彦

  DAシンポジウム2010, Sep. 2010, Japanese, 豊橋市, Domestic conference

  Poster presentation


• 高精度音源定位および音源分離機能を有する低消費電力ユビキタス・センサネットの開発

  TAKAGI Tomoya, 川口 博, 吉本 雅彦

  STARCフォーラム/シンポジウム2009, Aug. 2010, Japanese, Domestic conference

  Poster presentation


• ネットワーク分散処理を用いた超低消費電力音声信号処理プロセッサ

  久賀田 耕史, 野口 紘希, 高木 智也, 祖田 心平, 吉本 雅彦, 川口 博

  STARC フォーラム/シンポジウム２０１０, Aug. 2010, Japanese, 横浜市, Domestic conference

  Poster presentation


• 分散処理型ユビキ タスセンサネットワークのための超低消費電力音声処理プロセッサ

  高木 智也, 野口 紘希, 久賀田 耕史, 吉本 雅彦, 川口 博

  LSIとシステムのワークショップ 2010, May 2010, Japanese, 北九州市, Domestic conference

  Poster presentation


• 知能ロボットのためのマルチコアMIQPソルバープロセッサのFPGA実装

  嶋井 優介, 谷 純一, 野口 紘輝, H. Kawaguchi, M. Yoshimoto

  LSIとシステムのワークショップ 2010, May 2010, Japanese, 北九州, Domestic conference

  Poster presentation


• 大語彙連続音声認識のための並列Viterbiプロセッサアーキテクチャ

  藤永 剛史, 三浦 和夫, 野口 紘輝, 川口 博, M. Yoshimoto

  LSIとシステムのワークショップ 2010, May 2010, Japanese, 北九州, Domestic conference

  Poster presentation


• ワイヤレスセンサネットワークのためのΔ-Σ変調とデジタルアシストを用いたイメージ信号除去に関する研究

  小西 恵大, 李 赫鍾, 和泉 慎太郎, 竹内 隆, H. Kawaguchi, 吉本 雅彦

  LSIとシステムのワークショップ 2010, May 2010, Japanese, 北九州市, Domestic conference

  Poster presentation


• 7T/14T SRAMを内部メモリに用いたマルチコアプロセッサアーキテクチャ

  中田 洋平, 川口 博, 吉本 雅彦

  LSIとシステムのワークショップ 2010, May 2010, Japanese, 北九州市, Domestic conference

  Poster presentation


• "時刻同期型MACプロトコルを用いる6.4μWシングルチップセンサーノードLSI,

  和泉 慎太郎, 李 赫鍾, 小西 恵大, 岡 顕久, 松田 隆志, 竹内 隆, 太田 能, 川口 博, 吉本 雅彦

  LSIとシステムのワークショップ 2010, May 2010, Japanese, 北九州市, Domestic conference

  Poster presentation


• 時刻同期型MACプロトコルを用いる58-uWワンチップセンサノードプロセッサ

  和泉 慎太郎, 竹内 隆, 松田 隆志, 李 赫鍾, 小西 恵大, 鶴田 嵩, 酒井 康晴, 川口 博, 太田 能, 吉本 雅彦

  電子情報通信学会技術研究報告, Oct. 2009, Japanese, 電子情報通信学会, Domestic conference

  Poster presentation


• 7T/14T SRAMを内部メモリに用いたマルチコアプロセッサアーキテクチャの検討

  中田 洋平, 川口 博, 吉本 雅彦

  DAシンポジウム2009, Aug. 2009, Japanese, 情報処理学会 システムLSI設計技術研究会, 石川, Domestic conference

  Poster presentation


• 全整数計画問題のソルバーのFPGA実装

  谷 純一, 野口 紘希, 嶋井 優介, 川口 博, 吉本 雅彦

  LSIとシステムのワークショップ2009 ポスターセッション, May 2009, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, Domestic conference

  Poster presentation


• 時間同期型MACプロトコルの垂直統合設計によるセンサノードVLSIの低消費電力化

  和泉 慎太郎, 松田 隆志, 竹内 隆, 川口 博, 太田 能, 吉本 雅彦

  LSIとシステムのワークショップ2009 ポスターセッション, May 2009, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, Domestic conference

  Poster presentation


• 高信頼性モードを有する7T/14TディペンダブルSRAM,

  奥村 俊介, 藤原 英弘, 井口 友輔, 野口 紘希, 川口 博, 吉本 雅彦

  LSIとシステムのワークショップ2009 ポスターセッション, May 2009, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, Domestic conference

  Poster presentation


• リアルタイム20,000語彙連続音声認識のためのGMMプロセッサのFPGA実装

  三浦 和夫, 野口 紘希, 藤永 剛史, 川口 博, 吉本 雅彦

  LSIとシステムのワークショップ2009 ポスターセッション, May 2009, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, Domestic conference

  Poster presentation


• マイクロホンアレイ・センサネットワークによるインテリジェント・ユビキタス音声処理システムと，その低消費電力LSIの提案,

  高木 智也, 野口 紘希, 吉本 雅彦, 川口 博

  LSIとシステムのワークショップ2009 ポスターセッション, May 2009, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, Domestic conference

  Poster presentation


• チップ間ばらつき補正機能を有する基板バイアス制御を用いた0.42V動作486-kb FD-SOI SRAM,

  山口 幸介, 藤原 英弘, 竹内 隆, 大竹 優, 吉本 雅彦, 川口 博

  LSIとシステムのワークショップ2009 ポスターセッション, May 2009, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, Domestic conference

  Poster presentation


• カラム線制御回路を用いた0.56V動作128-kb10T小面積SRAM,

  吉本 秀輔, 井口 友輔, 奥村 俊介, 藤原 英弘, 野口 紘希, 新居 浩二, 川口 博, 吉本 雅彦

  LSIとシステムのワークショップ2009 ポスターセッション, May 2009, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, Domestic conference

  Poster presentation


• 動的電源電圧/周波数制御によるフレームバッファSRAM内蔵型H.264 AVCデコーダの低消費電力化

  SAKATA Yoshinori, NAKATA Youhei, KAWAKAMI Kentaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  第11回システムLSIワークショップ ポスタセッション, Nov. 2007, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, Domestic conference

  Poster presentation


• 長波帯標準電波を用いた低電力センサノードのための垂直統合設計

  OTAKE Yu, ICHIEN Masumi, TAKEUCHI Takashi, GION Akihiro, MIKAMI Shinji, FUJIWARA Hidehiro, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  第11回システムLSIワークショップ ポスタセッション, Nov. 2007, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, Domestic conference

  Poster presentation


• 超並列画像処理プロセッサ応用任意位置任意サイズ矩形データの1サイクルアクセスが可能なメモリアーキテクチャ

  KAMINO Tetsuya, MIYAKOSHI Junichi, MURACHI Yuichiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  第11回システムLSIワークショップ ポスタセッション, Nov. 2007, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, Domestic conference

  Poster presentation


• サブ100mW H.264 MP@L4.1 HDTV解像度対応 整数画素精度動き検出プロセッサコア

  MIZUNO Kosuke, MIYAKOSHI Junichi, MURACHI Yuichiro, HAMAMOTO Masaki, IINUMA Takahiro, ISHIHARA Tomokazu, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  第11回システムLSIワークショップ ポスタセッション, Nov. 2007, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, Domestic conference

  Poster presentation


• VGA 30fps実時間動画像認識応用オプティカルフロープロセッサコア

  MURACHI Yuichiro, FUKUYAMA Yuki, YAMAMOTO Ryo, MIYAKOSHI Junichi, KAWAGUCHI Hiroshi, ISHIHARA Hajime, MIYAMA Masayuki, MATSUDA Yoshio, 吉本 雅彦

  第11回システムLSIワークショップ ポスタセッション, Nov. 2007, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, Domestic conference

  Poster presentation


• H.264 MP@L4.1エンコーダLSIのためのHDTV解像度対応適応的階層探索動き検出アルゴリズム

  印 芳, MURACHI Yuichiro, HAMAMOTO Masaki, IINUMA Takahiro, ISHIHARA Tomokazu, 李 将充, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  第11回システムLSIワークショップ ポスタセッション, Nov. 2007, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, Domestic conference

  Poster presentation


• DVS環境下での小面積・低電圧動作8T SRAMの設計-32nm世代以降で8Tセルが小面積・低電圧動作を同時に実現

  MORITA Yasuhiro, FUJIWARA Hidehiro, NOGUCHI Hiroki, IGUCHI Yusuke, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  第11回システムLSIワークショップ ポスタセッション, Nov. 2007, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, Domestic conference

  Poster presentation


• ビット線電力を削減する;動画像処理応用 10T 非プリチャージ 2-port SRAM

  IGUCHI Yusuke, NOGUCHI Hiroki, OKUMURA Syunsuke, FUJIWARA Hidehiro, MORITA Yasuhiro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  VDEC LSIデザイナーフォーラム2007(若手の会)ポスターセッション, Sep. 2007, Japanese, 東京大学大規模集積システム設計教育研究センター, 北海道, Domestic conference

  Poster presentation


• ワイヤレスセンサネットワークのためのタイマ制御によるカウンターベースブロードキャスティング方式の改良

  IZUMI Shintaro, MATSUDA Takashi, MIKAMI Shinji, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  2007年電子情報通信学会総合大会, Mar. 2007, Japanese, 電子情報通信学会, 名古屋, Domestic conference

  Oral presentation


• ビット線電力を8割削減する動画像処理応用 10T非プリチャージ2-port SRAM

  IGUCHI Yusuke, NOGUCHI Hiroki, FUJIWARA Hidehiro, MORITA Yasuhiro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  2007年電子情報通信学会総合大会, Mar. 2007, Japanese, 電子情報通信学会, 名古屋, Domestic conference

  Oral presentation


• 低消費電力SoCの垂直統合研究事例 -H.264ベースラインプロファイル動き検出プロセッサコアIP-

  YOSHIMOTO Masahiko

  第10回システムLSIワークショップ 招待講演, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference

  Invited oral presentation


• 超並列画像処理のための、任意位置・水平垂直連続複数画素を同時アクセスできるメモリアーキテクチャ

  ISHIHARA Tomokazu, MIYAKOSHI Junichi, MURACHI Yuichiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  第10回システムLSIワークショップ ポスタセッション, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference

  Poster presentation


• 消費電力を50%削減する動的電圧/周波数スケーリング型H.264 Main Profile@Level 4ビデオデコーダLSI

  KAWAKAMI Kentaro, KURODA Mitsuhiko, SAKATA Yoshinori, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  第10回システムLSIワークショップ ポスタセッション, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference

  Poster presentation


• 実時間動画像認識応用スケーラブルオプティカルフロープロセッサ

  FUKUYAMA Yuuki, YAMAMOTO Ryo, MIYAKOSHI Junichi, KATAGIRI Tadayoshi, MINEGISHI Noriyuki, KAWAGUCHI Hiroshi, MIYAMA Masayuki, IMAMURA Kosuke, HASHIMOTO Hideo, YOSHIMOTO Masahiko

  第10回システムLSIワークショップ ポスタセッション, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference

  Poster presentation


• ワイヤレスセンサーネットワーク応用キャリアセンス機能を持つ433MHz帯、356-uW電圧増幅器

  OTAKE Yu, MIKAMI Shinji, TAKEUCHI Takashi, ICHIEN Masumi, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  第10回システムLSIワークショップ ポスタセッション, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference

  Poster presentation


• ワイヤレスセンサーネットワークにおける送信電力制御による送信効率劣化が消費電力モデルに与えるネガティブインパクト

  MIKAMI Shinji, TAKEUCHI Takashi, OTAKE Yu, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  第10回システムLSIワークショップ ポスタセッション, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference

  Poster presentation


• ビット線電力を53%削減できる実時間動画像処理応用2ポートSRAM

  FUJIWARA Hidehiro, NII Koji, MIYAKOSHI Junichi, MURACHI Yuichiro, MORITA Yasuhiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  第10回システムLSIワークショップ ポスタセッション, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference

  Poster presentation


• しきい値電圧ばらつきを克服したDVS環境下における0.3V動作SRAMの開発

  NOGUCHI Hiroki, MORITA Yasuhiro, FUJIWARA Hidehiro, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  第10回システムLSIワークショップ ポスタセッション, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference

  Poster presentation


• 800-μW H.264 Baseline-Profile対応動き検出プロセッサIP

  IINUMA Takahiro, MIYAKOSHI Junichi, MURACHI Yuichiro, MATSUNO Tetsuro, HAMANOTO Masaki, ISHIHARA Tomokazu, KAWAGUCHI Hiroshi, MIYAMA Masayuki, YOSHIMOTO Masahiko

  第10回システムLSIワークショップ ポスタセッション, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, Domestic conference

  Poster presentation


• 動的電圧制御環境下における0.3-V 動作64-kb SRAM

  MORITA Yasuhiro, FUJIWARA Hidehiro, NOGUCHI Hiroki, KAWAKAMI Kentaro, MIYAKOSHI Junichi, MIKAMI Shinji, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  2006年電子情報通信学会総合大会;AS-2-2, Mar. 2006, Japanese, 電子情報通信学会, 東京都, Domestic conference

  Oral presentation


• 動的電圧制御環境下における0.3-V 動作64-kb SRAM

  森田 泰弘, 藤原 英弘, 野口 紘希, 川上 健太郎, 宮越 純一, 三上 真司, 新居 浩二, 川口 博, 吉本 雅彦

  電子情報通信学会総合大会, Mar. 2006, Japanese, 東京, Domestic conference

  Oral presentation


• 動画像認識応用VLSIオプティカルフロープロセッサ(2)-オプティカルフロープロセッサアーキテクチャ-

  YAMAMOTO Ryo, FUKUYAMA Yuuki, KATAGIRI Tadayoshi, MIYAKOSHI Junichi, MINEGISHI Noriyuki, MIYAMA Masayuki, IMAMURA Kosuke, HASHIMOTO Hideo, YOSHIMOTO Masahiko

  2006年電子情報通信学会総合大会;D-12-78, Mar. 2006, Japanese, 電子情報通信学会, 東京都, Domestic conference

  Oral presentation


• 動画像認識応用VLSIオプティカルフロープロセッサ(2)-オプティカルフロープロセッサアーキテクチャ-

  山本 亮, 福山 祐貴, 片桐 忠義, 宮越 純一, 峯岸 孝行, 深山 正幸, 今村 幸祐, 橋本 秀雄, 吉本 雅彦

  電子情報通信学会総合大会, Mar. 2006, Japanese, 東京, Domestic conference

  Oral presentation


• 動画像認識応用VLSIオプティカルフロープロセッサ(1)-アルゴリズムのVLSI向き最適化-

  FUKUYAMA Yuuki, YAMAMOTO Ryo, KATAGIRI Tadayoshi, MIYAKOSHI Junichi, MINEGISHI Noriyuki, MIYAMA Masayuki, IMAMURA Kosuke, HASHIMOTO Hideo, YOSHIMOTO Masahiko

  2006年電子情報通信学会総合大会;D-12-77, Mar. 2006, Japanese, 電子情報通信学会, 東京都, Domestic conference

  Oral presentation


• 動画像認識応用VLSIオプティカルフロープロセッサ(1)-アルゴリズムのVLSI向き最適化-

  福山 祐貴, 山本 亮, 片桐 忠義, 宮越 純一, 峯岸 孝行, 深山 正幸, 今村 幸祐, 橋本 秀雄, 吉本 雅彦

  電子情報通信学会総合大会, Mar. 2006, Japanese, 東京, Domestic conference

  Oral presentation


• センサノードの製造バラツキを考慮したネットワーク可用時間改善の一検討

  YOSHINO Hironori, AONISHI Takafumi, ICHIEN Masumi, MATSUDA Takashi, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  2006年電子情報通信学会総合大会;BS-10-5, Mar. 2006, Japanese, 電子情報通信学会, 東京都, Domestic conference

  Oral presentation


• Long-lived network by considering production trelance of sensor node

  YOSHINO Hironori, AONISHI Takafumi, ICHIEN Masumi, MATSUDA Takashi, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  電子情報通信学会総合大会, Mar. 2006, Japanese, Tokyo, Domestic conference

  Oral presentation


• モバイル応用H.264コーデックLSI向け低消費電力動き検出アルゴリズム

  濱本 真生, 長井 健一, 松野 哲郎, 村地 勇一郎, 宮越 純一, 深山 正幸, 吉本 雅彦

  システムLSIワークショップ, Nov. 2005, Japanese, 北九州, Domestic conference

  Poster presentation


• モバイル応用H.264コーデックLSI向け低消費電力動き検出アルゴリズム

  濱本 真生, 長井 健一, 松野 哲郎, 村地 勇一郎, 宮越 純一, 深山 正幸, 吉本 雅彦

  電子情報通信学会技術研究報告, Oct. 2005, Japanese, 青森, Domestic conference

  Oral presentation


• Evaluation of GIT Routing Considering Aggregation Ratio in Sensor Networks

  AONISHI Takafumi, YOSHINO Hironori, MIKAMI Shinji, OHTA Chikara, KAWAGUCHI Hiroshi, YOHIMOTO Masahiko

  電子情報通信学会技術研究報告, Oct. 2005, Japanese, 新潟, Domestic conference

  Oral presentation


• Impact on impedance mismatch of output power control for wireless sensor nodes

  MIKAMI Shinji, TAKEUCHI Takashi, OHTA Chikara, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

  電子情報通信学会ソサイエティ大会, Sep. 2005, Japanese, 北海道大学, Domestic conference

  Oral presentation


• 携帯機器応用 95mW MPEG2 MP@HL 動き検出プロセッサコア

  村地 勇一郎, 浜野 康司, 松野 哲郎, 宮越 純一, 深山 正幸, 吉本 雅彦

  電子情報通信学会技術研究報告, Aug. 2005, Japanese, 北見, Domestic conference

  Oral presentation


• 動画像符号化動きベクトル検出のための低消費電力シストリックアレイアーキテクチャの研究

  宮越 純一, 村地 勇一郎, 浜野 康司, 松野 哲郎, 深山 正幸, 吉本 雅彦

  電子情報通信学会技術研究報告, May 2005, Japanese, 神戸, Domestic conference

  Oral presentation


• 近距離データ通信用超低消費電力ワイヤレスインターフェースLSI技術

  三上 真司, 松野 哲郎, 深山 正幸, 吉本 雅彦

  電子情報通信学会シリコンアナログRF研究会, May 2005, Japanese, 神戸, Domestic conference

  Oral presentation


• 携帯機器応用 95mW MPEG2 MP@HL 動き検出プロセッサコア IP (2)‐低消費電力全探索向けシストリックアレイアーキテクチャ‐

  MURACHI Yuichiro, HAMANO Koji, MATSUNO Tetsuro, MIYAKOSHI Junichi, MIYAMA Masayuki, YOSHIMOTO Masahiko

  2005年電子情報通信学会総合大会, Mar. 2005, Japanese, 電子情報通信学会, 大阪府, Domestic conference

  Oral presentation


• 携帯機器応用 95mW MPEG2 MP@HL 動き検出プロセッサコア IP (1)-アルゴリズム;アーキテクチャ;VLSI実装-

  MATSUNO Tetsuro, MURACHI Yuichiro, HAMANO Koji, MIYAKOSHI Junichi, MIYAMA Masayuki, YOSHIMOTO Masahiko

  2005年電子情報通信学会総合大会, Mar. 2005, Japanese, 電子情報通信学会, 大阪府, Domestic conference

  Oral presentation


• サブ100mW・MPEG2 MP@HL動きベクトル検出プロセッサ

  MURACHI Yuichiro, HAMANO Koji, MIYAKOSHI Junichi, MIYAMA Masayuki, YOSHIMOTO Masahiko

  2004 STARCシンポジウムポスターセッション, Sep. 2004, Japanese, 半導体理工学研究センター, 神奈川県, Domestic conference

  Poster presentation


• HDTV対応動き検出LSIの機能検証

  HAMANO Koji, MURACHI Yuichiro, MIYAKOSHI Junichi, MIYAMA Masayuki, YOSHIMOTO Masahiko

  平成16年度電気関係学会北陸支部連合大会, Sep. 2004, Japanese, 社団法人照明学会北陸支部, 石川県, Domestic conference

  Oral presentation


• H.264/MPEG4 AVC復号化処理における演算処理量の調査

  TAKEMURA Jun, KAWAKAMI Kentaro, KANAMORI Miwako, MORITA Yasuhiro, MIYAMA Masayuki, YOSHIMOTO Masahiko

  平成16年度電気関係学会北陸支部連合大会, Sep. 2004, Japanese, 社団法人照明学会北陸支部, 石川県, Domestic conference

  Oral presentation


• 携帯動画像端末応用サブmW・MPEG4動き検出プロセッサコアIP -試作と評価-

  KURODA Yuki, MIYAKOSHI Junichi, MIYAMA Masayuki, IMAMURA Kosuke, HASHIMOTO Yukio, YOSHIMOTO Masahiko

  平成15年度電気関係学会北陸支部連合大会;D-21, Sep. 2003, Japanese, 電気学会・電子情報通信学会・照明学会・映像情報メディア学会・日本ME学会・ 情報処理学会・計測自動制御学会各北陸支部, 富山県, Domestic conference

  Oral presentation


• 携帯動画像応用サブmW・MPEG4 動き検出プロセッサコアIP

  KURODA Yuki, MIYAKOSHI Junichi, MIYAMA Masayuki, IMAMURA Kosuke, HASHIMOTO Hideo, YOSHIMOTO Masahiko

  2003 STARCシンポジウムポスターセッション, Sep. 2003, Japanese, 株)半導体理工学研究センター, 大阪府豊中市, Domestic conference

  Poster presentation


• フィードフォワード制御を用いたMPEG4 低消費電力化アルゴリズム(2) -2段階動作電圧/周波数制御適用時の消費電力削減効果の見積もり-

  MORITA Yasuhiro, KAWAKAMI Kentaro, KANAMORI Miwako, OHIRA Hideo, MIYAMA Masayuki, YOSHIMOTO Masahiko

  平成15年度電気関係学会北陸支部連合大会;D-23, Sep. 2003, Japanese, 電気学会・電子情報通信学会・照明学会・映像情報メディア学会・日本ME学会・ 情報処理学会・計測自動制御学会各北陸支部, 富山県, Domestic conference

  Oral presentation


• フィードフォワード制御を用いたMPEG4 低消費電力化アルゴリズム(1) -符号化処理周波数予測に用いるパラメータと予測精度の検討-

  KANAMORI Miwako, KAWAKAMI Kentaro, MORITA Yasuhiro, OHIRA Hideo, MIYAMA Masayuki, YOSHIMOTO Masahiko

  平成15年度電気関係学会北陸支部連合大会;D-22, Sep. 2003, Japanese, 電気学会・電子情報通信学会・照明学会・映像情報メディア学会・日本ME学会・ 情報処理学会・計測自動制御学会各北陸支部, 富山県, Domestic conference

  Oral presentation

• 【NEDO】超低消費電力データ収集システムの研究開発

  吉本 雅彦

  国立研究開発法人新エネルギー・産業技術総合開発機構, IoT推進のための横断技術開発プロジェクト, 2017, Principal investigator

  Competitive research funding


• 【NEDO】超低消費電力データ収集システムの研究開発

  吉本 雅彦

  IoT推進のための横断技術開発プロジェクト, 2016, Principal investigator

  Competitive research funding


• 最先端のシステム情報学に関する国際学生交流

  吉本 雅彦

  科学技術振興機構, 日本・アジア青少年サイエンス交流事業（さくらサイエンスプラン）, 2015, Principal investigator

  Competitive research funding


• CREST「微細化SRAMのマージン不良最少化技術、不良予知診断、不良回避技術および統合化システムの開発」

  吉本 雅彦

  戦略的創造研究推進事業 チーム型研究CREST, 2013, Principal investigator

  Competitive research funding


• CREST「微細化SRAMのマージン不良最少化技術、不良予知診断、不良回避技術および統合化システムの開発」

  吉本 雅彦

  戦略的創造研究推進事業 チーム型研究CREST, 2012, Principal investigator

  Competitive research funding


• CREST「微細化SRAMのマージン不良最少化技術、不良予知診断、不良回避技術および統合化システムの開発」

  吉本 雅彦

  戦略的創造研究推進事業 チーム型研究CREST, 2011, Principal investigator

  Competitive research funding


• 階層間協調設計によるセンサネットワークノード用超低消費電力LSI設計技術に関する研究

  吉本 雅彦

  2007, Principal investigator

  Competitive research funding


• 次世代ウエアラブルコンピュータのための知覚認識モバイルプロセッサの垂直統合研究

  吉本 雅彦

  科学研究費補助金／基盤研究(A), 2006, Principal investigator

  Competitive research funding


• 階層間協調設計による無線センサネットワークのための省電力通信プロトコルの開発

  太田 能

  科学研究費補助金／基盤研究(C), 2006

  Competitive research funding

• 低電圧動作キャッシュメモリ

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 中田 洋平, 奥村 俊介, 鄭 晋旭

  特願2012-267445, 06 Dec. 2012, 大学長, 特許6024897, 21 Oct. 2016

  Patent right


• 半導体メモリおよびプログラム（韓国）

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 藤原 英弘, 奥村 俊介

  10-2010-7016180, 07 Jan. 2009, ＴＬＯ, 10-1569540, 10 Nov. 2015

  Patent right


• メモリセルアレイを用いたＩＤチップ

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 奥村 俊介

  特願2010-219910, 29 Sep. 2010, 大学長, 特許5499365, 20 Mar. 2014

  Patent right


• データ一括比較処理回路、データ一括比較処理方法およびデータ一括比較プログラム

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 奥村 俊介

  特願2010-219902, 29 Sep. 2010, 大学長, 特許5488920, 07 Mar. 2014

  Patent right


• キャッシュメモリとそのモード切替方法

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 中田 洋平

  特願2009-189603, 18 Aug. 2009, 大学長, 特許5397843, 01 Nov. 2013

  Patent right


• 共有キャッシュメモリとそのキャッシュ間のデータ転送方法

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 藤原 英弘, 奥村 俊介

  特願2009-082997, 30 Mar. 2009, 大学長, 特許5311309, 12 Jul. 2013

  Patent right


• 半導体メモリのハーフセレクト防止セル配置

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 藤原 英弘, 奥村 俊介

  特願2009-000012, 04 Jan. 2009, 大学長, 特許5298373, 28 Jun. 2013

  Patent right


• 画像処理用メモリ

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 宮越 純一, 村地勇一郎

  特願2007-298743, 18 Nov. 2007, 大学長, 特許5261694, 10 May 2013

  Patent right


• 半導体メモリのメモリセル間のデータコピー方法

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 藤原 英弘, 奥村 俊介

  特願2009-082996, 30 Mar. 2009, 大学長, 特許5256534, 02 May 2013

  Patent right


• 半導体メモリおよびプログラム

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 藤原 英弘, 奥村 俊介

  特願2009-548936, 07 Jan. 2009, ＴＬＯ, 特許5196449, 15 Feb. 2013

  Patent right


• 不良メモリセルの予知診断アーキテクチャーと予知診断方法

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 藤原 英弘, 奥村 俊介

  特願2009-082998, 30 Mar. 2009, 大学長, 特許5187852, 01 Feb. 2013

  Patent right


• 半導体記憶装置

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 藤原 英弘, 森田 泰弘

  特願2006-061644, 07 Mar. 2006, ＴＬＯ, 特許5119489, 02 Nov. 2012

  Patent right


• デジタルＶＬＳＩ回路およびそれを組み込んだ画像処理システム（米国）

  YOSHIMOTO MASAHIKO, 川上 健太郎, 竹村 淳

  12/278015, 05 Feb. 2007, 大学長, 8291256, 16 Oct. 2012

  Patent right


• 半導体メモリおよびプログラム SEMICONDUCTOR MEMORY AND PROGRAM

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 藤原 英弘, 奥村 俊介

  US12,809,684, 07 Jan. 2009, ＴＬＯ, 8,238,140, 07 Aug. 2012

  Patent right


• 画像処理装置

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, 宮越 純一, 村地 勇一郎, 濱本 真生, 飯沼 隆弘, 石原 朋和

  特願2007-298142, 16 Nov. 2007, 大学長, 特許5020029, 22 Jun. 2012

  Patent right


• センサネットワークにおける無線トランシーバー用電圧増幅器

  YOSHIMOTO MASAHIKO, OHTA CHIKARA, KAWAGUCHI HIROSHI, 三上 真司

  特願2007-035223, 15 Feb. 2007, 大学長, 特許5019362, 22 Jun. 2012

  Patent right


• 動き探索方法Ｂ

  YOSHIMOTO MASAHIKO, 濱本 真生, 村地 勇一郎, 宮越 純一, 松野 哲郎

  特願2005-284117, 29 Sep. 2005, 大学長, 特許5013041, 15 Jun. 2012

  Patent right


• 動き探索方法

  YOSHIMOTO MASAHIKO, 濱本 真生, 村地 勇一郎, 宮越 純一, 松野 哲郎

  特願2005-284116, 29 Sep. 2005, 大学長, 特許5013040, 15 Jun. 2012

  Patent right


• 動き探索方法

  YOSHIMOTO MASAHIKO, 濱本 真生, 宮越 純一, 村地 勇一郎, 飯沼 隆弘, 石原 朋和, 印 芳, 李 将充

  特願2008-000620, 07 Jan. 2008, 大学長, 特許4961236, 23 Mar. 2012

  Patent right


• センサネットワークシステム及びメディアアクセス制御方法

  YOSHIMOTO MASAHIKO, OHTA CHIKARA, KAWAGUCHI HIROSHI, 一圓 真澄

  特願2006-279761, 13 Oct. 2006, 大学長, 特許4919204, 10 Feb. 2012

  Patent right


• データ送信スケジューリング方法およびそれを用いたセンサネットワークシステム

  YOSHIMOTO MASAHIKO, KAWAGUCHI HIROSHI, OHTA CHIKARA, 三上 真司

  特願2006-279760, 13 Oct. 2006, 大学長, 特許4863069, 18 Nov. 2011

  Patent right


• デジタルＶＬＳＩ回路およびそれを組み込んだ画像処理システム

  Masahiko Yoshimoto, Kentarou Kawakami, Jun Takemura

  特願2007-556947, 05 Feb. 2007, 大学長, 特許4521508, 04 Jun. 2010

  Patent right