研究者紹介システム

川口 博
カワグチ ヒロシ
大学院科学技術イノベーション研究科 科学技術イノベーション専攻
教授
電気通信工学関係
Last Updated :2021/07/25

研究者情報

所属

  • 【主配置】

    大学院科学技術イノベーション研究科 科学技術イノベーション専攻
  • 【配置】

    工学部 情報知能工学科, 大学院工学研究科 情報知能学専攻, 大学院システム情報学研究科 情報科学専攻, 数理・データサイエンスセンター

学位

  • 博士(工学), 東京大学

授業科目

ジャンル

  • 情報・通信・メディア / ウェアラブルコンピューティング

コメントテーマ

  • ウェアラブル生体情報センサーLSI
  • 低消費電力メモリ
  • 画像処理プロセッサ
  • 音声認識プロセッサ

研究活動

研究分野

  • 情報通信 / 計算機システム

委員歴

  • 情報処理学会システムLSI設計技術研究運営委員会, 運営委員

受賞

  • 2018年 電子情報通信学会, 電子情報通信学会ELEX Best Paper Award, A low power, VLSI object recognition processorusing Sparse FIND Feature for 60fps HDTV resolution video

    松川 豪, 児玉 泰佑, 西住 友里, 梶原 弘一, 中西 知嘉子, 和泉 慎太郎, 川口 博, Goto Toshio, Kato Takeo, 吉本 雅彦

    学会誌・学術雑誌による顕彰

  • 2017年09月 IEEE International Workshop on Machine Learning for Signal Processing (MLSP), Sep. 2017., Best Student Paper Award, A Layer-Block-Wise Pipeline For Memory And Bandwidth Reduction In Distributed Deep Learning

    森 陽紀, 陽川 哲也, 和泉 慎太郎, 吉本 雅彦, 川口 博, 井上 淳樹

    国際学会・会議・シンポジウム等の賞

  • 2016年05月 電子情報通信学会集積回路研究専門委員会, LSIとシステムのワークショップ2016 優秀ポスター賞(学生部門), プロセスばらつき耐性を有する低電圧動作STT-MRAM向けカウンターベース読出し回路

    梅木 洋平, 柳田 晃司, 吉本秀輔, 和泉 慎太郎, 吉本 雅彦, 川口 博, 角田 浩司, 杉井 寿博

    国内学会・会議・シンポジウム等の賞

  • 2014年05月 電子情報通信学会集積回路研究専門委員会, 優秀ポスター賞, 38μAウェアラブル生体情報計測プロセッサ

    中井 陽三郎, 和泉 慎太郎, 山下 顕, 中野 将尚, 藤井 貴英, 小西 恵大, 川口 博, 木村 啓明, 丸元 共治, 渕上 貴昭, 藤森 敬和, 中嶋 宏, 志賀 利一, 吉本 雅彦

    日本国

    国内学会・会議・シンポジウム等の賞

  • 2008年07月 株式会社 半導体理工学研究センター, 優秀ポスター賞, 発話推定を用いたインテリジェント認識システムの低消費電力化技術

    野口紘希, 川口 博

  • 2008年07月 STARC, STARCフォーラム/シンポジウム2008 学生ポスターセッション 優秀ポスター賞受賞, 発話推定を用いたインテリジェント認識システムの低消費電力化技術

    野口 紘希, 川口 博

  • 2008年04月 財団法人 電気・電子学術振興財団, 第10回LSI IPデザイン・アワード 研究助成賞, 長波帯標準電波を用いた低電力センサノードの垂直統合設計

    大竹 優, 一圓 真澄, 竹内 隆, 祗園 昭宏, 三上 真司, 藤原 英弘, 川口 博, 太田 能, 吉本 雅彦

  • 2008年04月 財団法人 電気・電子学術振興財団, 第10回LSI IPデザイン・アワード IP賞 2, サブ100mW H.264/AVC MP@L4.1 HDTV 解像度対応整数画素精度動き検出プロセッサコア

    水野 孝祐, 宮越 純一, 村地 勇一郎, 濱本 真生, 飯沼 隆弘, 石原 朋和, 印 芳, 上農 哲也, 川口 博, 吉本 雅彦

  • 2008年04月 財団法人 電気・電子学術振興財団, 第10回LSI IPデザイン・アワード IP賞 1, VGA 30fps 実時間動画像認識応用オプティカルフロープロセッサコア

    村地 勇一郎, 福山 祐貴, 山本 亮, 宮越 純一, 川口 博, 吉本 雅彦, 石原 一, 深山 正幸, 松田 吉雄

  • 2007年12月 IEEE, SENSORCOMM 2007 ENOPT 2008 Workshop Best Paper Award, Cross-Layer Design for Low-Power Wireless Sensor Node Using Long-Wave Standard Time Code

    OTAKE Yu, ICHIEN Masumi, TAKEUCHI Takashi, GION Akihiro, MIKAMI Shinji, FUJIWARA Hidehiro, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

  • 2007年11月 電子情報通信学会, 第11回システムLSIワークショップ IEEEシステムLSI技術賞, DVS環境下での小面積・低電圧動作8T SRAMの設計-32nm世代以降で8Tセルが小面積・低電圧動作を同時に実現

    森田泰弘, 藤原英弘, 野口紘希, 井口友輔, 新居浩二, 川口 博, 吉本 雅彦

  • 2007年09月 東京大学大規模集積システム設計教育研究センター, IEEE SSCS Japan Chapter Outstanding Design Award, ビット線電力を削減する,動画像処理応用 10T 非プリチャージ 2-port SRAM

    井口友輔, 野口紘希, 奥村俊介, 藤原英弘, 森田泰弘, 新居浩二, 川口 博, 吉本 雅彦

  • 2007年04月 財団法人 電気・電子学術振興財団, 第9回LSI IPデザイン・アワード 開発奨励賞, 消費電力を50%削減する動的電圧/周波数スケーリング型H.264 Main Profile@Level 4ビデオデコーダLSI

    川上健太郎, 竹村淳, 黒田光彦, 川口 博, 吉本 雅彦

  • 2007年04月 財団法人 電気・電子学術振興財団, 第9回LSI IPデザイン・アワード IP賞 2, ット線電力を53%削減できる実時間動画像処理応用2ポートSRAM

    藤原英弘, 新居浩二, 宮越純一, 村地 勇一郎, 森田泰弘, 野口紘希, 川口 博, 吉本 雅彦

  • 2007年04月 財団法人 電気・電子学術振興財団, 第9回LSI IPデザイン・アワード IP賞 1, 超並列画像処理のための,任意位置・水平垂直連続複数画素を同時アクセスできるメモリアーキテクチャ

    石原朋和, 宮越純一, 村地 勇一郎, 川口 博, 吉本 雅彦

  • 2007年02月 IEEE, IEEE Kansai Section 2006 Gold Award, 低電力回路技術によるIEEEへの貢献

    川口 博

  • 2005年02月 IEEE International Solid-State Circuits Conference, IEEE International Solid-State Circuits Conference Takuo Sugano Outstanding Paper Award, Cut-and-Paste Organic FET Customized ICs for Application to Artificial Skin

    SOMEYA Takao, KAWAGUCHI Hiroshi, SAKURAI Takayasu

論文

  • Daisuke Watanabe, Yuji Yano, Shintaro Izumi, Hiroshi Kawaguchi, Kiyoshi Takeuchi, Toshiro Hiramoto, Shoichi Iwai, Masami Murakata, Masahiko Yoshimoto

    2020年, 305 - 309

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Reiya Kawamoto, Masakazu Taichi, Masaya Kabuto, Daisuke Watanabe, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi

    2020年, 203 - 207

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Yuji Yano, Seiya Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Tetsuya Hirose, Masaya Miyahara, Teruki Someya, Kenichi Okada, Ippei Akita, Yoshihiko Kurui, Hideyuki Tomizawa, Masahiko Yoshimoto

    2019年, 267 - 270

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Seiya Yoshida, Shintaro Izumi, Yuki Nishikawa, Kento Watanabe, Kana Sasai, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto

    2019年, 1 - 4

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Seiya Yoshida, Shintaro Izumi, Koichi Kajihara, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper presents an energy-efficient spectral analysis method for the Internet of Things (IoT). The objective of this paper is to reduce the energy consumption of edge devices. The proposed method uses an autoregressive (AR) model for spectral analysis instead of the discrete Fourier transform, and its calculation process is distributed to the edge device and a base station by considering the energy consumption tradeoff of the data processing and the data communication. In this paper, the Yule-Walker method is employed for the AR coefficient calculation. The calculation process of Yule-Walker method can be divided into two parts: an autocorrelation calculation and an AR coefficient calculation. The autocorrelation calculation is implemented in the edge devices, and its dedicated hardware is designed using Verilog HDL. Meanwhile, the AR coefficient is calculated in the base station and is used for the spectral analysis. According to this distributed processing approach, the energy consumption of the edge device can be reduced compared with conventional DFT approaches using the fast Fourier transform (FFT). The system level energy consumption is evaluated assuming the IoT edge device, which has a wireless transceiver using Bluetooth low energy. The evaluation results show that the proposed method can reduce 79% of the edge device energy consumption for spectral analysis in a practical application.

    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2019年, IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (10), 3896 - 3905, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Takaaki Okano, Shintaro Izumi, Takumi Katsuura, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This article describes a multimodal cardiovascular information measurement method using a wearable device composed of piezoelectric transducers. Cardiovascular diseases are increasing with the aging population, and they constitute a significant portion of the causes of death and long-term care. In recent years, daily-life monitoring using wearable sensor devices has attracted particular attention for the prevention and early detection of cardiovascular diseases. However, recent wearable devices can only measure limited cardiovascular information such as the heart rate. In contrast, the proposed method can simultaneously measure heart rate variability, pulse wave propagation velocity, and blood flow velocity using only a piezoelectric transducer array.

    SPRINGER, 2019年, J. Signal Process. Syst., 91 (9), 1053 - 1062, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Shintaro Izumi, Takaaki Okano, Daichi Matsunaga, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper describes a non-contact and noise-tolerant heart rate monitoring system using a 24-GHz microwave Doppler sensor. The microwave Doppler sensor placed at some distance from the user's chest detects the small vibrations of the body surface due to the heartbeats. The objective of this work is to detect the instantaneous heart rate (IHR) using this non-contact system in a car, because the possible application of the proposed system is a driver health monitoring based on heart rate variability analysis. IHR can contribute to preventing heart-triggered disasters and to detect mental stress state. However, the Doppler sensor system is very sensitive and it can be easily contaminated by motion artifacts and road noise especially while driving. To address this problem, time-frequency analysis using the parametric method and template matching method are employed. Measurement results show that the Doppler sensor, which is pasted on the clothing surface, can successfully extract the heart rate through clothes. The proposed method achieves 13.1-ms RMS error in IHR measurements conducted on 11 subjects in a car on an ordinary road.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2019年, IEICE Trans. Commun., 102-B (6), 1088 - 1096, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Kento Watanabe, Shintaro Izumi, Kana Sasai, Yuji Yano, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This study designs a low-power photoplethysmography (PPG) sensor based on the error compensation method for heartbeat interval acquisition. To perform heartbeat monitoring in daily life, it is necessary to obtain long-term and accurate heartbeat interval data with low power consumption, because of the limited size and battery capacity of the PPG sensor. Effective reduction in the power consumption of the sensor requires the duty-cycled LEDs and lowering pulse repetition frequency (PRF), i.e., decreasing the sampling rate. However, these methods reduce the accuracy of the heartbeat interval measurement because of signal-to-noise ratio (SNR) degradation and sampling errors. We propose an algorithm for heartbeat interval error compensation and incorporate a low-noise readout circuit to improve SNR. The readout circuit uses current integration to achieve low duty-cycle LED driving. A correlated double sampling (CDS) is introduced to minimize the random noise arising from the switching operation of the integration circuit. An error compensation method based on the PPG waveform similarity is also introduced using the autocorrelation and linear interpolation. The measurement results obtained from nine subjects show that a total current consumption of 28.2A is achieved with a 20-Hz PRF and 0.3 LED duty cycle. The proposed design effectively reduces the mean absolute error (MAE) of the heartbeat interval to an average of 6.2 ms.

    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2019年, IEEE Trans. Biomed. Circuits and Systems, 13 (6), 1552 - 1562, 英語, 国際誌

    [査読有り]

    研究論文(学術雑誌)

  • Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper presents a low-energy 64-Kb eighttransistor (8T) one-read/one-write dual-port image memory with a 28-nm fully depleted SOI (FD-SOI) process technology. Our proposed SRAM adopts a selective sourceline drive (SSD) scheme and a consecutive data write technique for improving active energy efficiency at low voltage. The novel SSD scheme controls sourceline voltage and eliminates leakage energy at unselected columns in read operations. We fabricated a 64-Kb 8T dual-port SRAM in the 28-nm FD-SOI process technology. The 81 SRAM cell size is 0.291 x 1.457 mu m(2). The test chip exhibits 0A8-V operation at an access time of 135 ns. The energy minimum point is at a supply voltage of 0.56 V and an access time of 35 ns, where 265.0 fJ/cycle in write operations and 389.6 fJ/cycle in read operations are achieved. These factors are, respectively, 30% and 26% smaller than those of the 8T dual-port SRAM with the conventional scheme.

    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2019年, IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (4), 1442 - 1453, 英語

    [査読有り]

    研究論文(学術雑誌)

  • 中西 基文, 和泉 慎太郎, 川口 博, 吉本 雅彦, SHIGA Toshikazu, ANDO Takafumi, NAKAE Satoshi, USUI Chiyoko, AOYAMA Tomoko, TANAKA Shigeho

    BACKGROUND: Herein, an algorithm that can be used in wearable health monitoring devices to estimate metabolic equivalents (METs) based on physical activity intensity data, particularly for certain activities in daily life that make MET estimation difficult. RESULTS: Energy expenditure data were obtained from 42 volunteers using indirect calorimetry, triaxial accelerations and heart rates. The proposed algorithm used the percentage of heart rate reserve (%HRR) and the acceleration signal from the wearable device to divide the data into a middle-intensity group and a high-intensity group (HIG). The two groups were defined in terms of estimated METs. Evaluation results revealed that the classification accuracy for both groups was higher than 91%. To further facilitate MET estimation, five multiple-regression models using different features were evaluated via leave-one-out cross-validation. Using this approach, all models showed significant improvements in mean absolute percentage error (MAPE) of METs in the HIG, which included stair ascent, and the maximum reduction in MAPE for HIG was 24% compared to the previous model (HJA-750), which demonstrated a 70.7% improvement ratio. The most suitable model for our purpose that utilized heart rate and filtered synthetic acceleration was selected and its estimation error trend was confirmed. CONCLUSION: For HIG, the MAPE recalculated by the most suitable model was 10.5%. The improvement ratio was 71.6% as compared to the previous model (HJA-750C). This result was almost identical to that obtained from leave-one-out cross-validation. This proposed algorithm revealed an improvement in estimation accuracy for activities in daily life; in particular, the results included estimated values associated with stair ascent, which has been a difficult activity to evaluate so far.

    2018年07月28日, BioMedical Engineering OnLine, 17 (1), 100 - 100, 英語, 国際誌

    [査読有り]

    研究論文(学術雑誌)

  • 渡辺 健斗, 和泉 慎太郎, 矢野 祐二, 川口 博, 吉本 雅彦

    This paper presents a low-power Photoplethysmography (PPG) sensing method. The PPG is commonly used in recent wearable devices to detect cardiovascular information including heartbeat. The heartbeat is useful for physical activity and stress monitoring. However, the PPG circuit consumes large power because it consists of LED and photodiode. To reduce its power consumption without accuracy degradation, a cooperative design of circuits and algorithms is proposed in this work. A straightforward way to reduce the power is intermittent driving of LED, but there is a disadvantage that the signal is contaminated by a noise while circuit switching. To overcome this problem, we introduce correlated double sampling (CDS) method, which samples an integration circuit output twice with short intervals after the LED turns on and uses the difference of these voltage. Furthermore, an up-conversion method using linear interpolation, and an error correction using autocorrelation are introduced. The proposed PPG sensor, which consists of the LED, the photodiode, the current integration circuit, a CMOS switch, an A/D converter, and an MCU, is prototyped. It is evaluated by actual measurement with 22-year-old subject. The measurement results show that 22-μA total current consumption is achieved with 5-ms mean absolute error.

    2018年07月, the 40th International Engineering in Medicine and Biology Conference, 2018, 5566 - 5569, 英語, 国際誌

    [査読有り]

    研究論文(学術雑誌)

  • 中西 基文, 和泉 慎太郎, 塚原 美緒, 川口 博, KIMURA Hiromitsu, MARUMOTO Kyoji, FUCHIKAMI Takaaki, FUJIMORI Yoshikazu, 吉本 雅彦

    This paper presents an algorithm for a physical activity (PA) classification and metabolic equivalents (METs) monitoring and its System-on-a-Chip (SoC) implementation to realize both power reduction and high estimation accuracy. Long-term PA monitoring is an effective means of preventing lifestyle-related diseases. Low power consumption and long battery life are key features supporting the wider dissemination of the monitoring system. As described herein, an adaptive sampling method is implemented for longer battery life by minimizing the active rate of acceleration without decreasing accuracy. Furthermore, advanced PA classification using both the heart rate and acceleration is introduced. The proposed algorithms are evaluated by experimentation with eight subjects in actual conditions. Evaluation results show that the root mean square error with respect to the result of processing with fixed sampling rate is less than 0.22 [METs], and the mean absolute error is less than 0.06 [METs]. Furthermore, to minimize the system-level power dissipation, a dedicated SoC is implemented using 130-nm CMOS process with FeRAM. A nonvolatile CPU using non-volatile memory and a flip-flop is used to reduce the stand-by power. The proposed algorithm, which is implemented using dedicated hardware, reduces the active rate of the CPU and accelerometer. The current consumption of the SoC is less than 3-mu A. And the evaluation system using the test chip achieves 74% system-level power reduction. The total current consumption including that of the accelerometer is 11.3-mu A on average.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2018年04月, IEICE Transactions on Electronics, E101C (4), 233 - 242, 英語

    [査読有り]

    研究論文(学術雑誌)

  • マイクロ波ドップラーセンサを用いた非接触生体認証 (ヘルスケア・医療情報通信技術)

    岡野 孝昭, 和泉 慎太郎, 川口 博, 吉本 雅彦

    電子情報通信学会, 2018年03月16日, 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 117 (511), 17 - 20, 日本語

    研究論文(研究会,シンポジウム資料等)

  • Tetsuya Youkawa, Haruki Mori, Yuki Miyauchi, Kazuki Yamada, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi

    This paper presents a proposal of a data-parallel stochastic gradient descent (SGD) using delayed weight update. A large-scale neural network appears to solve advanced problems, but its processing time increases concomitantly with the network scale. For conventional data parallelism, workers must wait for data communication to and from a server during weight updating. Using the proposed data-parallel method, the network weight has a delay. It is therefore stale. Nevertheless, it gives faster convergence time by hiding the latency of the weight communication for the server. The server concurrently carries out the weight communication and weight update while workers calculate their gradients. The experimentally obtained results demonstrate that, in the proposed data parallel method, the final accuracy converges within degradation of 1.5% compared with the conventional method in both VGG and ResNet At maximum, the convergence speedup factor theoretically reaches double that of conventional data parallelism.

    IEEE, 2018年, 2018 IEEE GLOBAL CONFERENCE ON SIGNAL AND INFORMATION PROCESSING (GLOBALSIP 2018), 663 - 667, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Go Matsukawa, Taisuke Kodama, Yuri Nishizumi, Koichi Kajihara, Chikako Nakanishi, Shintaro Izumi, Hiroshi Kawaguchi, Toshio Goto, Takeo Kato, Masahiko Yoshimoto

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2018年, IEICE Electronic Express, 15 (12), 20188003 - 20188003, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Layer Skip Learning using LARS variables for 39% Faster Conversion Time and Lower Bandwidth

    宮内 勇貴, 森 陽紀, 陽川 哲也, 山田 和樹, 和泉 慎太郎, 吉本 雅彦, 川口 博

    In this paper, a method for the improvement of the relationship between calculation time and recognition accuracy in deep learning is proposed. A major problem with respect to deep learning is that a large calculation time is required for higher recognition accuracy. Because of this problem, the implementation of deep learning in hardware and its application to real problems are limited. In this study, layer-wise adaptive rate scaling (LARS) variables are adopted to evaluate the necessity of the learning of each layer. When the variable of a certain convolution layer exceeds the threshold value, the learning for that layer is considered unnecessary; thus, the layer is skipped. When a layer recognized as the layer that does not require learning, only the lower layers below than that layer are learned in the next epoch. By adaptively skipping the layer, the calculation time is reduced. Furthermore, the recognition accuracy is improved. Consequently, the proposed methods accelerate the calculation time in VGG-F to achieve the highest accuracy for the top1 and top5 test accuracy by a speed up factor of 2.14, and 2.25, respectively. Moreover, the respective topl and top5 test accuracy was improved by 3.0 %, and 2.8% which obtained as the final accuracy. In addition, the operation process was reduced by approximately 39.0 %, and required bandwidth was reduced by 38.9 %, when compared with the case of conventional full layer learning.

    IEEE, 2018年, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 673 - 676, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Sampling Rate Reduction for Wearable Heart Rate Variability Monitoring

    Nishikawa, Yuki, Izumi, Shintaro, Yano, Yuji, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

    This report describes a sampling rate reduction method for heart rate variability monitoring with a wearable device. This work was conducted to realize low-power measurement of biological signals necessary for heart rate variability (HRV) analysis. Continuous operation of the wearable device is an important factor for daily life monitoring. Therefore, the active time of the measuring circuit must be minimized. To reduce the required sampling rate, we propose a sampling error reduction method using interpolation and correlation of the heartbeat waveform. The proposed method is evaluated using measured electrocardiograms from five subjects. Evaluation results demonstrate that the sampling rate can be reduced to 32 Hz with 1 ms RMS error in heartbeat interval and 1.04% LF/HF degradation in HRV analysis.

    IEEE, 2018年, 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Hardware Implementation of Autoregressive Model Estimation Using Burg’s Method for Low-Energy Spectral Analysis

    西河 有貴, 和泉 慎太郎, 吉田 聖也, 矢野 祐二, 川口 博, 吉本 雅彦

    We present a hardware implementation of Burg's method, which is used for autoregressive (AR) model estimation. The AR model is a linear predictive modeling technique. It assumes that the current value of a signal can be described by a finite linear aggregate of the previous values. The AR model can be used for spectral analysis as an alternative to the Fourier transform. This approach is a parametric method, and it can yield higher resolutions than nonparametric methods in cases when the signal length is short. Although Burg's method requires a large computational capacity, especially with higher model orders, a fast Burg's method has been proposed for improving this draw back. In this study, we evaluate the influence of the order and the data length of Burg's method on the computational capacity. The hardware implementation method of the fast Burg's method including a two-stage pipeline architecture and a parallelization technique for autocorrelation calculations is proposed. The proposed method is implemented using Verilog HDL and its energy consumption is estimated with the 65-nm CMOS process. The evaluation result shows that the proposed method achieves an energy consumption of 21.6-361.4 nJ for the spectral estimation with a data length of 128-2048 points when the model order is 5.

    IEEE, 2018年, IEEE Workshop on Signal Processing Systems 2018, 199 - 204, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Adaptive Learning Rate Adjustment with Short-Term Pre-Training in Data-Parallel Deep Learning

    Yamada, Kazuki, Mori, Haruki, Youkawa, Tetsuya, Miyauchi, Yuki, Izumi, Shintaro, Yoshimoto, Masahiko, Kawaguchi, Hiroshi

    This paper introduces a method to adaptively choose a learning rate (LR) with short-term pre-training (STPT). This is useful for quick model prototyping in data-parallel deep learning. For unknown models, it is necessary to tune numerous hyperparameters. The proposed method reduces computational time and increases efficiency in finding an appropriate LR; multiple LRs are evaluated by STPT in data-parallel deep learning. STPT means training only with the beginning iterations in an epoch. When eight LRs are evaluated using eight parallel workers, the proposed method can easily reduce the computational time by 87.5% in comparison with the conventional method. The accuracy is also improved by 4.8% in comparison with the conventional method with a reference LR of 0.1; thus, no deterioration in accuracy is observed. For an unknown model, this method shows a better training curve trend than other cases with fixed LRs.

    IEEE, 2018年, PROCEEDINGS OF THE 2018 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), 100 - 105, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • 28-nm FD-SOI Dual-Port SRAM with MSB-Based Inversion Logic for Low-Power Deep Learning

    Mori, Haruki, Izumi, Shintaro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

    This paper presents low-power and low-energy 8T dual-port SRAM with a novel MSB-based (most-significant-bit-based) inversion logic for an image processor such a deep learning processor. Our proposed SRAM is suitable for real-time and low-power image processing, in which data have statistical correlation and data bit reordering are exploited. The proposed MSB-based inversion logic eliminates an additional flag bit in a majority logic; the MSB digit in an input datum judges whether or not to invert the datum. Thus, the area overhead of 12.5 % for the 8-bit conventional majority logic is dramatically saved. The area overhead of the proposed SRAM is merely 0.6% for the MSB-based inversion logic. We verified that, with the proposed technique, 14.76 % of total energy can be saved in a 28-nm 64-kb FD-SOI SRAM when a set of images are read out. Furthermore, the saving factor is extended to 17.31 % when image processing in the VGG-F convolutional neural network (CNN) is considered, where 304.81 fJ/cycle in the read operation is achieved.

    IEEE, 2018年, 2018 25TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 161 - 164, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Non-Contact Biometric Identification and Authentication Using Microwave Doppler Sensor

    岡野 孝昭, 和泉 慎太郎, 川口 博, 吉本 雅彦

    2017年10月, The 13th IEEE BioMedical Circuits and Systems Conference(BioCAS), pp.392-395, Oct. 2017., 392 - 395, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Ryota Nakamura, Shintaro Izumi, Hiroshi Kawaguchi, Hidetoshi Ohta, Masahiko Yoshimoto

    This paper presents a swallowable sensor device that can be ingested orally, later passing to the stomach, where the device can indwell for long periods. Using wireless communication, it can be egested at any time after it is triggered. This device can indwell using a silicone balloon in the gastrointestinal tract. A chemical reaction inflates the balloon inside the stomach. Then it is deflated to egest the sensor device using an actuator with electrolysis of water. Energy for the actuator with electrolysis can be fed wirelessly. Near field communication and a flexible antenna are used for power feeding and wireless data communication. Because of the flexible balloon and the flexible antenna, the device size can be minimized without performance degradation.

    2017年07月, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2017, 3040 - 3043, 英語, 国際誌

    [査読有り]

    研究論文(学術雑誌)

  • A contact-less heart rate sensor system for driver health monitoring

    和泉 慎太郎, 松永 大地, 中村 亮太, 川口 博, 吉本 雅彦

    2017年07月, The 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC’17), July. 2017, 英語

    研究論文(国際会議プロシーディングス)

  • Matsukawa, Go, Kodama, Taisuke, Nishizumi, Yuri, Kajihara, Koichi, Nakanishi, Chikako, Izumi, Shintaro, Kawaguchi, Hiroshi, Goto, Toshio, Kato, Takeo, Yoshimoto, Masahiko

    This paper describes a low-power object recognition processor VLSI for HDTV resolution video at 60 frames per second (fps) using an object recognition algorithm with Sparse FIND features. The VLSI processor features two-stage feature extraction processing by HOG and Sparse FIND, a highly parallel classification in the support vector machine (SVM), and a block-parallel processing for RAM access cycle reduction. Compared to the accuracy by the original Sparse FIND algorithm, the two-stage object detection demonstrates insignificant accuracy degradation. Using this architectural design, a 60 fps performance for object recognition of HDTV resolution video was attained at an operating frequency of 130 MHz. This 3.35 x 3.35 mm(2) chip, designed with 40 nm CMOS technology, contains 8.22 M gates and 5 Mb SRAM in the chip of 3.35 x 3.35 mm(2). The simulated power consumption at 133 MHz were 528 mW and 702 mW at the slow process condition (SS, 0.81 V, -40 degrees C) and typical process condition (TT, 0.9 V, 25 degrees C), respectively.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2017年04月, IEICE ELECTRONICS EXPRESS, 14 (15), 1 - 12, 英語

    [査読有り]

    研究論文(学術雑誌)

  • A Novel Test Scheme for Detecting Faulty Recall Margin Cells for6T-4C FeRAM,

    梅木 洋平, 和泉 慎太郎, 北原 弘登, 中川 知己, 柳田 晃司, 吉本秀輔, 川口 博, 吉本 雅彦, 木村 啓明, 丸元 共治, 渕上 貴昭, 藤森 敬和

    2017年02月, Memoirs of the Graduate Schools of Engineering and SystemInformatics Kobe University, no. 8, pp. 5-8, Feb. 2017., 英語

    [査読有り]

    研究論文(大学,研究機関等紀要)

  • A 19-μA Metabolic Equivalents Monitoring SoC Using Adaptive Sampling

    塚原 美緒, 和泉 慎太郎, 中西 基文, 川口 博, 木村啓明, 丸元共治, 渕上貴昭, 藤森敬和, 吉本 雅彦

    This paper presents a low-power metabolic equivalents (METs) estimation SoC for monitoring physical activity with wearable sensor. Long-term continuous METs monitoring can contribute to detection of non-communicable diseases. The proposed SoC consists of a non-volatile CPU and a dedicated hardware for heart rate extraction and METs estimation to reduce the power consumption. A test chip is fabricated in a 130-nm CMOS process. Evaluation results show that the proposed system, which consists of the test chip and an accelerometer, consumes about 19-mu A on average.

    IEEE, 2017年, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) University LSI Design Contest, pp. 37-38, Jan. 2017, 37 - 38, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A LAYER-BLOCK-WISE PIPELINE FOR MEMORY AND BANDWIDTH REDUCTION IN DISTRIBUTED DEEP LEARNING

    Mori, Haruki, Youkawa, Tetsuya, Izumi, Shintaro, Yoshimoto, Masahiko, Kawaguchi, Hiroshi, Inoue, Atsuki

    This paper describes a pipelined stochastic gradient descent (SGD) algorithm and its hardware architecture with a memory distributed structure. In the proposed architecture, a pipeline stage takes charge of multiple layers: a "layer block." The layer-block-wise pipeline has much less weight parameters for network training than conventional multithreading because weight memory is distributed to workers assigned to pipeline stages. The memory capacity of 2.25 GB for the four-stage proposed pipeline is about half of the 3.82 GB for multithreading when a batch size is 32 in VGG-F. Unlike multithreaded data parallelism, no parameter server for weight update or shared I/O data bus is necessary. Therefore, the memory bandwidth is drastically reduced. The proposed four-stage pipeline only needs memory bandwidths of 36.3 MB and 17.0 MB per batch, respectively, for forward propagation and backpropagation processes, whereas four-thread multithreading requires a bandwidth of 974 MB overall for send and receive processes to unify its weight parameters. At the parallelization degree of four, the proposed pipeline maintains training convergence by a factor of 1.12, compared with the conventional multithreaded architecture although the memory capacity and the memory bandwidth are decreased.

    IEEE, 2017年, 2017 IEEE 27TH INTERNATIONAL WORKSHOP ON MACHINE LEARNING FOR SIGNAL PROCESSING, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Takumi Katsuura, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Shusuke Yoshimoto, Tsuyoshi Sekitani

    2017年, Proc. of IEEE Biomedical Circuits and Systems Conference (BioCAS), pp. 721–724, Oct. 2017, 1 - 4, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Multimodal Cardiovascular Information Monitor using Piezoelectric Transducers for Wearable Healthcare

    Okano, Takaaki, Izumi, Shintaro, Katsuura, Takumi, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

    This report describes a multimodal cardiovascular information measurement method using a wearable sensor device. With the progress of aging populations worldwide, cardiovascular diseases are increasing. Such diseases account for a large share of causes of death and constitute the main cause of long-term care. Along with the miniaturization and longer life of measuring instruments in recent years, constant monitoring of biological information using a wearable biosensor has attracted attention for the prevention and early detection of cardiovascular diseases. However, today's wearable devices can only measure limited cardiovascular information such as the heart rate. Therefore, we propose a method that can simultaneously measure heart rate variation, pulse wave propagation velocity, and blood flow velocity with a single device equipped with a piezoelectric transducer array.

    IEEE, 2017年, 2017 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • FPGA Implementation of Object Recognition Processor for HDTV Resolution Video Using Sparse FIND Feature

    Nishizumi, Yuri, Matsukawa, Go, Kajihara, Koichi, Kodama, Taisuke, Izumi, Shintaro, Kawaguchi, Hiroshi, Nakanishi, Chikako, Goto, Toshio, Kato, Takeo, Yoshimoto, Masahiko

    This paper describes FPGA implementation of object recognition processor for HDTV resolution 30 fps video using the Sparse FIND feature. Two-stage feature extraction processing by HOG and Sparse FIND, a highly parallel classification in the support vector machine (SVM), and a block-parallel processing for RAM access cycle reduction are proposed to perform a real time object recognition with enormous computational complexity. From implementation of the proposed architecture in the FPGA, it was confirmed that detection using the Sparse FIND feature was performed for HDTV images at 47.63 fps, on average, at 90 MHz. The recognition accuracy degradation from the original Sparse FIND-base object detection algorithm implemented on software was 0.5%, which shows that the FPGA system provides sufficient accuracy for practical use.

    IEEE, 2017年, 2017 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Yuki Nagasato, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    2017年, The 13th IEEE BioMedical Circuits and Systems Conference(BioCAS), pp.400-403, Oct. 2017., 1 - 4, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A METABOLIC EQUIVALENTS ESTIMATION ALGORITHM USING TRIAXIAL ACCELEROMETER AND ADAPTIVE SAMPLING FOR WEARABLE DEVICES

    Nakanishi, Motofumi, Izumi, Shintaro, Tsukahara, Mio, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

    This study describes a low-power metabolic equivalents estimation method. Low-power consumption is a key feature of wearable devices because it requires longer battery-life with small battery capacity. The proposed algorithm employs adaptive sampling for reducing the energy consumed by an accelerometer and by signal processing. The sampling frequency is adaptively changed according to an estimated physical activity group. Evaluation of the results shows that the sampling rate can be reduced by 86%, and there is 0.1 metabolic equivalents RMS error compared with a reference values. And it is seen that there is no significant error compared with other prediction methods in spite of very low average sampling frequency with proposed algorithm.

    IEEE, 2017年, 2017 IEEE LIFE SCIENCES CONFERENCE (LSC), 107 - 110, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Multimodal Cardiovascular Information Monitor using Piezoelectric Transducers for Wearable Healthcare

    Okano, Takaaki, Izumi, Shintaro, Katsuura, Takumi, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

    This report describes a multimodal cardiovascular information measurement method using a wearable sensor device. With the progress of aging populations worldwide, cardiovascular diseases are increasing. Such diseases account for a large share of causes of death and constitute the main cause of long-term care. Along with the miniaturization and longer life of measuring instruments in recent years, constant monitoring of biological information using a wearable biosensor has attracted attention for the prevention and early detection of cardiovascular diseases. However, today's wearable devices can only measure limited cardiovascular information such as the heart rate. Therefore, we propose a method that can simultaneously measure heart rate variation, pulse wave propagation velocity, and blood flow velocity with a single device equipped with a piezoelectric transducer array.

    IEEE, 2017年, 2017 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), 1 - 10, 英語

    [査読有り][招待有り]

    研究論文(国際会議プロシーディングス)

  • 消化管内へ留置する飲み込型センサの検討

    中村 亮太, 和泉 慎太郎, 川口 博, 吉本 雅彦, 太田 英敏

    2016年09月, 電気学会C部門大会, 2016年9月1日,神戸, 日本語

    研究論文(研究会,シンポジウム資料等)

  • 加速度センサを用いた低消費電力運動強度推定アルゴリズム

    塚原 美緒, 中西 基文, 和泉 慎太郎, 中井 陽三郎, 川口 博, 吉本 雅彦

    2016年09月, 電気学会C部門大会, 2016年9月1日,神戸., 日本語

    研究論文(研究会,シンポジウム資料等)

  • 加速度センサを用いた低消費電力運動強度推定アルゴリズム

    塚原 美緒, 中西 基文, 和泉 慎太郎, 中井 陽三郎, 川口 博, 吉本 雅彦

    2016年09月, IEICEソサイエティ大会, 2016年9月21日,札幌, 日本語

    研究論文(研究会,シンポジウム資料等)

  • Ryota Nakamura, Shintaro Izumi, Hiroshi Kawaguchi, Hidetoshi Ohta, Masahiko Yoshimoto

    This paper presents a swallowable sensor device that can be ingested orally, later arriving to the stomach, where the device can indwell for a long term and can be egested at any time after it is triggered using wireless communication. This device can inflate a silicone balloon in the gastrointestinal tract using a chemical reaction. The balloon can be deflated later using electrolysis of water at the time of egestion. A motorless chemical-reaction-based egestion method is proposed to minimize the sensor device size. This device can achieve long-term monitoring in the gastrointestinal tract.

    2016年08月, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2016, 3039 - 3042, 英語, 国際誌

    [査読有り]

    研究論文(学術雑誌)

  • Mio Tsukahara, Motofumi Nakanishi, Shintaro Izumi, Yozaburo Nakai, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper describes a proposed low-power metabolic equivalent estimation algorithm that can calculate the value of metabolic equivalents (METs) from triaxial acceleration at an adaptively changeable sampling rate. This algorithm uses four rates of 32, 16, 8 and 4 Hz. The mode of switching them is decided from synthetic acceleration. Applying this proposed algorithm to acceleration measured for 1 day, we achieved the low root mean squared error (RMSE) of calculated METs, with current consumption that was 41.5 % of the value at 32 Hz, and 75.4 % of the value at 16 Hz.

    2016年08月, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2016, 1878 - 1881, 英語, 国際誌

    [査読有り]

    研究論文(学術雑誌)

  • A Counter-based Read Circuit Tolerant to ProcessVariation for 0.4-V Operating STT-MRAM,

    梅木 洋平, 柳田 晃司, 吉本秀輔, 和泉 慎太郎, 吉本 雅彦, 川口 博, 角田 浩司, 杉井 寿博

    2016年08月, IPSJ Transactions on System LSIDesign Methodology (TSLDM), vol. 9, pp. 79-83, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Haruki Mori, Yohei Umeki, Shusuke Yoshimoto, Shintaro Izumi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using 28-nm FD-SOI process technology. Our proposed SRAM accommodates eight-transistor bit cells comprising one-write/two-read ports and a majority logic circuit to save active energy. The test chip operates at a supply voltage of 0.46V and access time of 140 ns. The minimum energy point is a supply voltage of 0.54V and an access time of 55 ns (= 18.2 MHz), at which 484 fJ/cycle in a write operation and 650 fJ/cycle in a read operation are achieved assisted by majority logic. These factors are 69% and 47% smaller than those in a conventional 6T SRAM using the 28-nm FD-SOI process technology.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2016年08月, IEICE TRANSACTIONS ON ELECTRONICS, E99C (8), 901 - 908, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Go Matsukawa, Yuta Kimi, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    As technology nodes continue to shrink, the impact of radiation-induced soft error on processor reliability increases. Estimation of processor reliability and identification of vulnerable flip-flops requires accurate soft error rate (SER) analysis techniques. This paper presents a proposal for a soft error propagation analysis technique. We specifically examine single event upset (SEU) occurring at a flip-flop in sequential circuits. When SEUs propagate in sequential circuits, the faults can be masked temporally and logically. Conventional soft error propagation analysis techniques do not consider error convergent timing on re-convergent paths. The proposed technique can analyze soft error propagation while considering error-convergent timing on a re-convergent path by combinational analysis of temporal and logical effects. The proposed technique also considers the case in which the temporal masking is disabled with an enable signal of the erroneous flip-flop negated. Experimental results show that the proposed technique improves inaccuracy by 70.590, on average, compared with conventional techniques using ITC 99 and ISCAS 89 benchmark circuits when the enable probability is 1/3, while the runtime overhead is only 1.79( on average.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2016年06月, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E99A (6), 1198 - 1205, 英語

    [査読有り]

    研究論文(学術雑誌)

  • 298-fJ/writecycle 650-fJ/readcycleを実現する画像処理プロセッサ向け28-nm FD-SOI 8T 3ポートSRAM (集積回路)

    森 陽紀, 中川 知己, 北原 佑起, 河本 優太, 高木 健太, 吉本 秀輔, 和泉 慎太郎, 新居 浩二, 川口 博, 吉本 雅彦

    電子情報通信学会, 2016年04月14日, 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 116 (3), 13 - 16, 日本語

    研究論文(研究会,シンポジウム資料等)

  • Process variation tolerant counter base read circuit for low-voltage operating STT-MRAM

    梅木 洋平, 柳田 晃司, 黒津 弘明, 北原 弘登, 森 陽紀, 和泉 慎太郎, 吉本 雅彦, 川口 博, 吉本秀輔, 角田 浩司, 杉井 寿博

    2016年03月, DATE EMS Workshop, Mar. 2016, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Capacitively Coupled ECG Sensor using a Single Electrode with Adaptive Power-Line Noise Cancellation

    Yuta Kawamoto, Shintaro Izumi, Yoshito Tanaka, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This report describes a small heartbeat monitoring system using capacitively coupled ECG sensors. Capacitively coupled sensors using an insulated electrode have been proposed to obtain ECG signals without pasting electrodes directly onto the skin. Although the sensors have better usability than conventional ECG sensors, it is difficult to remove noise contamination. Power-line noise can be a severe noise source that increases when only a single electrode is used. However, a multiple electrode system degrades usability. To address this problem, we propose a noise cancellation technique using an adaptive noise feedback approach, which can improve the availability of the capacitive ECG sensor using a single electrode. An instrumental amplifier is used in the proposed method for the first stage amplifier instead of voltage follower circuits. A microcontroller predicts the noise waveform from an ADC output. To avoid saturation caused by power-line noise, the predicted noise waveform is fed back to an amplifier input through a DAC. We implemented the prototype sensor system to evaluate the noise reduction performance. Measurement results using a prototype board show that the proposed method can suppress 28-dB power-line noise.

    IEEE, 2016年, 2016 3RD IEEE EMBS INTERNATIONAL CONFERENCE ON BIOMEDICAL AND HEALTH INFORMATICS, 212 - 215, 英語

    [査読有り][招待有り]

    研究論文(国際会議プロシーディングス)

  • An Soft Error Propagation Analysis Considering Logical Masking Effect on Re-convergent Path

    Shuhei Yoshida, Go Matsukawa, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper presents an accurate soft error propagation analysis technique. Especially, we focus on Single Event Upset (SEU) in flip-flop. The proposed technique can calculate the accurate error propagation probability considering logical masking on re-convergent paths with SAT solver efficiently. Experimental result shows that the proposed technique improves the computation time by 94.6% compared with the method with only SAT solver and the accuracy by 93.3% compared with the conventional method respectively.

    IEEE, 2016年, 2016 IEEE 22ND INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS), 13 - 16, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Adaptive Noise Cancellation Method for Capacitively Coupled ECG Sensor using Single Insulated Electrode

    Yoshito Tanaka, Shintaro Izumi, Yuta Kawamoto, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper describes a noise reduction method for capacitively coupled ECG sensors. Capacitively coupled sensors using an insulated electrode have been proposed to obtain ECG signals without pasting electrodes directly onto the skin. It can achieve better usability than conventional ECG sensors. However, it is difficult to remove noise contamination, because the high input impedance and low input capacitance are required to realize the capacitively coupled ECG sensor. Especially, base-line drift and power-line noise are more serious problem when using a single electrode structure. To address this problem, we propose a noise cancellation technique using an adaptive noise feedback approach, which can improve the availability of the capacitive ECG sensor using a single electrode. An instrumental amplifier is used in the proposed method for the first stage amplifier instead of voltage follower circuits. A microcontroller predicts the noise waveform from an ADC output. To avoid saturation caused by base-line drift and power-line noise, the predicted noise waveform is fed back to an amplifier input through a DAC. We implemented the prototype sensor system to evaluate the noise reduction performance. Measurement results show that the proposed method can suppress both of base-line drift and power-line noise simultaneously.

    IEEE, 2016年, PROCEEDINGS OF 2016 IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE (BIOCAS), 296 - 299, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Daichi Matsunaga, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper describes a non-contact heart rate monitoring system using a microwave Doppler sensor. It can achieve better usability than conventional heart rate sensors, which require direct skin contact. The objective of this work is to detect an instantaneous heart rate using this non-contact system. The instantaneous heart rate can contribute to prevent heart disasters and to detect mental stress state. However, the Doppler sensor system is very sensitive and it can be easily contaminated by a body motion artifact including breathing. To address this problem, we introduce time frequency analysis with short window length. The heart rate extraction performance with various parameters is evaluated using a measured Doppler sensor output with 4 subjects. The proposed method achieves 4.5-ms RMS error with 50-cm distance for heart rate extraction from 60 s duration data.

    IEEE, 2016年, 2016 IEEE 16TH INTERNATIONAL CONFERENCE ON BIOINFORMATICS AND BIOENGINEERING (BIBE), 172 - 175, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • An Low-Energy 8T Dual-Port SRAM for Image Processor with Selective Sourceline Drive Scheme in 28-nm FD-SOI Process Technology

    Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper presents a low-energy and low-voltage 64-kb 8T dual-port image memory in a 28-nm FD-SOI process technology. Our proposed SRAM adopts the selective sourceline drive (SSD) scheme and the consecutive data write technique for improving active energy efficiency at the low voltage. We fabricated a 64-Kb 8T dual-port SRAM in the 28-nm FD-SOI process technology; the test chip exhibits 0.48 V operation and an access time of 135 ns. The energy minimum point is at a supply voltage of 0.56 V and an access time of 35 ns, where 265.0 fJ/cycle in write operation and 389.6 fJ/cycle in read operation are achieved; these factors are 30% and 26% smaller than those in the 8T dual-port SRAM with the conventional selective sourceline control (SSLC) scheme, respectively.

    IEEE, 2016年, 23RD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS CIRCUITS AND SYSTEMS (ICECS 2016), 532 - 535, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A 15-mu A Metabolic Equivalents Monitoring System using Adaptive Acceleration Sampling and Normally Off Computing

    Mio Tsukahara, Shintaro Izumi, Motofumi Nakanishi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori

    This paper describes a low-power metabolic equivalents (METs) estimation method for monitoring physical activity. Long-term continuous METs monitoring can contribute to detection of non-communicable diseases. The proposed system consists of dedicated METs estimation hardware and a nonvolatile CPU. A test is fabricated in a 130-nm CMOS with a ferroelectric capacitor process. Evaluation results show that the proposed system, which consists of the test chip and an accelerometer, requires about 15-A on average.

    IEEE, 2016年, 23RD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS CIRCUITS AND SYSTEMS (ICECS 2016), 61 - 64, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A. Tanaka, T. Douseki, Y. Umeki, H. Kawaguchi, M. Yoshimoto, K. Tsunoda, T. Sugii

    A batteryless sensorless bicycle speed recorder system with a hub dynamo that functions as both a power source and a speed sensor has been developed. The hub dynamo produces a voltage waveform with more than ten AC cycles per rotation of the bicycle wheel, which enables precise determination of speed and acceleration. The data is stored in a spin-transfer-torque magnetoresistive random-access memory (STT-MRAM) that has perpendicular magnetic tunnel junctions (MTJs) and an infinite rewriting capability. For writing operation, the MRAM employs an intermittent write operation, which involves high-speed writing with a duty cycle of less than 0.01%. This reduces the average power dissipation of the MRAM to that of the standby mode. A road test showed that a fabricated speed recorder mounted on a bicycle stored and reproduced accurate values of a large acceleration and its duration when the brakes were suddenly applied while the bicycle was being ridden.

    Institute of Electrical and Electronics Engineers Inc., 2015年12月31日, 2015 IEEE SENSORS - Proceedings, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Keisuke Okuno, Shintaro Izumi, Kana Masaki, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This report describes an all-digital phase-locked loop (ADPLL) using a temperature compensated settling time reduction technique. The novelty of this work is autonomous oscillation control word estimation without a look-up table or memory circuits. The proposed ADPLL employs a multi-phase digitally controlled oscillator (DCO). In the proposed estimation method, the optimum oscillator tuning word (OTW) is estimated from the DCO frequency characteristic in the setup phase of ADPLL. The proposed ADPLL, which occupies 0.27 x 0.36mm(2), is fabricated by a 65 nm CMOS process. The temperature compensation PLL controller (TCPC) is implemented using an FPGA. Although the proposed method has 20% area overhead, measurement results show that the 47% settling time is reduced. The average settling time at 25 degrees C is 3 mu s. The average reduction energy is at least 42% from 0 degrees C to 100 degrees C.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2015年12月, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E98A (12), 2592 - 2599, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Shintaro Izumi, Ken Yamashita, Masanao Nakano, Shusuke Yoshimoto, Tomoki Nakagawa, Yozaburo Nakai, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto

    This paper describes an electrocardiograph (ECG) monitoring SoC using a non-volatile MCU (NVMCU) and a noise-tolerant instantaneous heartbeat detector. The novelty of this work is the combination of the non-volatile MCU for normally off computing and a noise-tolerant-QRS (heartbeat) detector to achieve both low-power and noise tolerance. To minimize the stand-by current of MCU, a non-volatile flip-flop and a 6T-4C NVRAM are used. Proposed plate-line charge-share and bit-line non-precharge techniques also contribute to mitigate the active power overhead of 6T-4C NVRAM. The proposed accurate heartbeat detector uses coarse-fine autocorrelation and a template matching technique. Accurate heartbeat detection also contributes system-level power reduction because the active ratio of ADC and digital block can be reduced using heartbeat prediction. Measurement results show that the fully integrated ECG-SoC consumes 6.14 μ A including 1.28- μA non-volatile MCU and 0.7- μA heartbeat detector.

    IEEE, 2015年10月, IEEE transactions on biomedical circuits and systems, 9 (5), 641 - 51, 英語, 国際誌

    [査読有り]

    研究論文(学術雑誌)

  • IZUMI Shintaro, YAMASHITA Ken, NAKANO Masanao, KAWAGUCHI Hiroshi, KIMURA Hiromitsu, MARUMOTO Kyoji, FUCHIKAMI Takaaki, FUJIMORI Yoshikazu, NAKAJIMA Hiroshi, SHIGA Toshikazu, YOSHIMOTO Masahiko

    To prevent lifestyle diseases, wearable bio-signal monitoring systems for daily life monitoring have attracted attention. Wearable systems have strict size and weight constraints, which impose significant limitations of the battery capacity and the signal-to-noise ratio of bio-signals. This report describes an electrocardiograph (ECG) processor for use with a wearable healthcare system. It comprises an analog front end, a 12-bit ADC, a robust Instantaneous Heart Rate (IHR) monitor, a 32-bit Cortex-M0 core, and 64 Kbyte Ferroelectric Random Access Memory (FeRAM). The IHR monitor uses a short-term autocorrelation (STAC) algorithm to improve the heart-rate detection accuracy despite its use in noisy conditions. The ECG processor chip consumes 13.7 μA for heart rate logging application.

    IEEE, 2015年10月, IEEE Transactions on Biomedical Circuits and Systems, 9 (5), 733 - 42, 英語, 国際誌

    [査読有り]

    研究論文(学術雑誌)

  • Motofumi Nakanishi, Shintaro Izumi, Sho Nagayoshi, Hironori Sato, Hiroshi Kawaguchi, Masahiko Yoshimoto, Takafumi Ando, Satoshi Nakae, Chiyoko Usui, Tomoko Aoyama, Shigeho Tanaka

    As described in this paper, a physical activity classification algorithm is proposed for energy expenditure estimation. The proposed algorithm can improve the classification accuracy using both the triaxial acceleration and heart rate. The optimal classification also contributes to improvement of the accuracy of the energy expenditures estimation. The proposed algorithm employs three indices: the heart rate reserve (%HRreserve), the filtered triaxial acceleration, and the ratio of filtered and unfiltered acceleration. The percentage HRreserve is calculated using the heart rate at rest condition and the maximum heart rate, which is calculated using Karvonen Formula. Using these three indices, a decision tree is constructed to classify physical activities into five classes: sedentary, household, moderate (excluding locomotive), locomotive, and vigorous. Evaluation results show that the average classification accuracy for 21 activities is 91%.

    37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society(EMBC), 2015年08月, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2015, 510 - 3, 英語, 国際誌

    [査読有り][招待有り]

    研究論文(国際会議プロシーディングス)

  • Taisuke Kodama, Shintaro Izumi, Kana Masaki, Hiroshi Kawaguchi, Kazusuke Maenaka, Masahiko Yoshimoto

    Recently, given Japan's aging society background, wearable healthcare devices have increasingly attracted attention. Many devices have been developed, but most devices have only a sensing function. To expand the application area of wearable healthcare devices, an interactive communication function with the human body is required using an actuator. For example, a device must be useful for medication assistance, predictive alerts of a disease such as arrhythmia, and exercise. In this work, a haptic stimulus actuator using a piezoelectric pump is proposed to realize a large displacement in wearable devices. The proposed actuator drives tactile sensation of the human body. The measurement results obtained using a sensory examination demonstrate that the proposed actuator can generate sufficient stimuli even if adhered to the chest, which has fewer tactile receptors than either the fingertip or wrist.

    37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society(EMBC), 2015年08月, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2015, 1172 - 5, 英語, 国際誌

    [査読有り][招待有り]

    研究論文(学術雑誌)

  • Tomoki Nakagawa, Shintaro Izumi, Koji Yanagida, Yuki Kitahara, Shusuke Yoshimoto, Yohei Umeki, Haruki Mori, Hiroto Kitahara, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Masahiko Yoshimoto

    This report describes a low power 6T-4C nonvolatile memory design using a bit-line non-precharge and plate-line charge-share techniques. Two proposed techniques contribute to decrease energy consumption. The bit-line non-precharge technique can reduce 73% of write energy consumption and 76% of read energy consumption. The plate-line charge-share technique can reduce 22% of store energy consumption and 11% of recall energy consumption.

    Institute of Electrical and Electronics Engineers Inc., 2015年07月27日, Proceedings - IEEE International Symposium on Circuits and Systems, 2015-, 2904 - 2907, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi

    We present a low-jitter design for a 10-bit second-order frequency shift oscillator time-to-digital converter (FSOTDC). As described herein, we analyze the relation between performance and FSOTDC parameters and provide insight to support the design of the FSOTDC. Results show that an oscillator jitter limits the FSOTDC resolution, particularly during the first stage. To estimate and design an FSOTDC, the frequency shift oscillator requires an inverter of a certain size. In a standard 65-nm CMOS process, an SNDR of 64 dB is achievable at an input signal frequency of 10 kHz and a sampling clock of 2MHz. Measurements of the test chip confirmed that the measurements match the analyses.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2015年07月, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E98A (7), 1475 - 1481, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi

    We present an I/O-size second-order analog to digital converter (ADC) combined with a time-to-digital converter (TDC) and a voltage-to-time converter (VTC). Our proposed VTC is optimized for metal-oxide-metal (MOM) capacitances, and is charged to the MOM capacitances by an input voltage. In a standard 65-nm CMOS process, a signal to noise and distortion ratio (SNDR) of 50 dB (8 bits) is achievable at an input signal frequency of 78 kHz and a sampling rate of 20 MHz, where the respective area and power are 6468 mm(2) and 509 mu W. The measured maximum integral nonlinearity (INL) of the proposed ADC is 1.41 LSBs. The active area of the proposed ADC is smaller than an I/O buffer. The proposed ADC is useful as an ADC I/O.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2015年06月, IEICE TRANSACTIONS ON ELECTRONICS, E98C (6), 489 - 495, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Shintaro Izumi, Masanao Nakano, Ken Yamashita, Yozaburo Nakai, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This report describes a robust method of instantaneous heart rate (IHR) extraction from noisy electrocardiogram (ECG) signals. Generally, R-waves are extracted from ECG using a threshold to calculate the IHR from the interval of R-waves. However, noise increases the incidence of misdetection and false detection in wearable healthcare systems because the power consumption and electrode distance are limited to reduce the size and weight. To prevent incorrect detection, we propose a short-time autocorrelation (STAC) technique. The proposed method extracts the IHR by determining the search window shift length which maximizes the correlation coefficient between the template window and the search window. It uses the similarity of the QRS complex waveform beat-by-beat. Therefore, it has no threshold calculation process. Furthermore, it is robust against noisy environments. The proposed method was evaluated using MIT-BIH arrhythmia and noise stress test databases. Simulation results show that the proposed method achieves a state-of-the-art success rate of IHR extraction in a noise stress test using a muscle artifact and a motion artifact.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2015年05月, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E98D (5), 1095 - 1103, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Go Matsukawa, Yohei Nakata, Yasuo Sugure, Shigeru Oho, Yuta Kimi, Masafumi Shimozawa, Shuhei Yoshida, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper presents a novel architecture for a fault-tolerant and dual modular redundancy (DMR) system using a checkpoint recovery approach. The architecture features exploitation of SRAM with simultaneous copy and instantaneous compare function. It can perform low-latency data copying between dual cores. Therefore, it can carry out fast backup and rollback. Furthermore, it can reduce the power consumption during data comparison process compared to the cyclic redundancy check (CRC). Evaluation results show that, compared with the conventional checkpoint/restart DMR, the proposed architecture reduces the cycle overhead by 97.8% and achieves a 3.28% low-latency execution cycle even if a one-time fault occurs when executing the task. The proposed architecture provides high reliability for systems with a real-time requirement.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2015年04月, IEICE TRANSACTIONS ON ELECTRONICS, E98C (4), 333 - 339, 英語

    [査読有り]

    研究論文(学術雑誌)

  • A 298-fJ/writecycle 650-fJ/readcycle 8T Three-Port SRAM in 28-nm FD-SOI Process Technology for Image Processor

    Haruki Mori, T. Nakagawa, Y. Kitahara, Y. Kawamoto, K. Takagi, S. Yoshimoto, S. Izumi, K. Nii, H. Kawaguchi, M. Yoshimoto

    This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using a 28-nm FD-SOI process technology. Our proposed SRAM accommodates eight-transistor bitcells comprising one-write/two-read ports and a majority logic circuit to save active energy. The test chip can operate at a supply voltage of 0.46 V and an access time of 140 ns. The energy minimum point is a supply voltage of 0.54 V and an access time of 55 ns (= 18.2 MHz), at which 298 fJ/cycle in a write operation and 650 fJ/cycle in a read operation are achieved with the help of the majority logic; these factor are 87% and 52% smaller than those in a 28-nm FD-SOI 6T SRAM.

    IEEE, 2015年, 2015 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Kimi, Yuta, Matsukawa, Go, Yoshida, Shuhei, Izumi, Shintaro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

    As technology nodes continue to shrink, the impact of radiation-induced soft error on processor reliability increases. Estimation of processor reliability and identification of vulnerable flip-flops requires accurate soft error rate (SER) analysis techniques. This paper presents a proposal for a soft error propagation analysis technique. We specifically examine single event upset (SEU) occurring at a flip-flop in sequential circuits. When SEUs propagate in sequential circuits, the faults can be masked temporally and logically. Conventional soft error propagation analysis techniques do not consider error convergent timing on re-convergent paths. The proposed technique can analyze soft error propagation while considering error-convergent timing on a re-convergent path by combinational analysis of temporal and logical effects. The proposed technique also considers the case in which the temporal masking is disabled with an enable signal of the erroneous flip-flop negated. Experimental results show that the proposed technique improves inaccuracy by 70.5%, on average, compared with conventional techniques using ITC 99 and ISCAS 89 benchmark circuits when the enable probability is 1/3, while the runtime overhead is only 1.7% on average.

    IEEE COMPUTER SOC, 2015年, 2015 IEEE 24TH ASIAN TEST SYMPOSIUM (ATS), 139 - 144, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance with Bit-Enhancing Memory and On-Chip Diagnosis Structures Delivering x91 Failure Rate Improvement

    Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper presents a resilient cache memory for dynamic variation tolerance in a 40-nm CMOS. The cache can perform sustained operations under a large-amplitude voltage droop. To realize sustained operation, the resilient cache exploit 7T/14T bit-enhancing SRAM and on-chip voltage/temperature monitoring circuit. 7T/14T bitenhancing SRAM can reconfigure itself dynamically to a reliable bit-enhancing mode. An on-chip monitoring circuit can sense a precise supply voltage level of a power rail of the cache. The proposed cache can dynamically change its operation mode using the voltage/temperature monitoring result and can operate reliably under a large-amplitude voltage droop. Experimental result shows that it does not fail with 25% and 30% droop of Vdd and it provides 91 times better failure rate with a 35% droop of Vdd compared with the conventional design. The processor simulator shows that the proposed cache running in the bit-enhancing mode results in 2.88% IPC loss on average.

    IEEE, 2015年, PROCEEDINGS OF THE FIFTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2014), 16 - +, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A Negative-Resistance Sense Amplifier for Low-Voltage Operating STT-MRAM

    Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, Koji Tsunoda, Toshihiro Sugii

    2015年01月, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) University LSI Design Contest, pp. 8 - 9, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A 14μA ECG Processor with Noise Tolerant Heart Rate Extractor and FeRAM for Wearable Healthcare Systems

    Yozaburo Nakai, IZUMI Shintaro, Ken Yamashita, Masanao Nakano, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

    This report describes an electrocardiograph (ECG) processor for use with a wearable healthcare system. It comprises an analog front end, a 12-bit ADC, a robust Instantaneous Heart Rate (IHR) monitor, a 32-bit Cortex-M0 core, and 64 Kbyte Ferroelectric Random Access Memory (FeRAM). The IHR monitor uses a short-term autocorrelation (STAC) algorithm to improve the heart-rate detection accuracy despite its use in noisy conditions. The ECG processor chip consumes 13.7 mu A for heart rate logging application.

    IEEE, 2015年, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) University LSI Design Contest, 16 - 17, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A Low Power 6T-4C Non-volatile Memory using Charge Sharing and Non-precharge Techniques

    Tomoki Nakagawa, Shintaro Izumi, Koji Yanagida, Yuki Kitahara, Shusuke Yoshimoto, Yohei Umeki, Haruki Mori, Hiroto Kitahara, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Masahiko Yoshimoto

    This report describes a low power 6T-4C nonvolatile memory design using a bit-line non-precharge and plate-line charge-share techniques. Two proposed techniques contribute to decrease energy consumption. The bit-line non-precharge technique can reduce 73% of write energy consumption and 76% of read energy consumption. The plate-line charge-share technique can reduce 22% of store energy consumption and 11% of recall energy consumption.

    IEEE, 2015年, 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2904 - 2907, 英語

    [査読有り][招待有り]

    研究論文(国際会議プロシーディングス)

  • An Accurate Soft Error Propagation Analysis Technique Considering Temporal Masking Disablement

    Yuta Kimi, Go Matsukawa, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper presents an accurate soft error propagation analysis technique for processor SER evaluation. Especially, we focus on Single Event Upset (SEU) in flip-flop which is a main contributor of processor SER. SEUs in flip-flops propagate combinational circuits with temporal masking and logical masking effects. The temporal masking is disabled when the erroneous flip-flop is disabled. The proposed technique is able to evaluate temporal masking disablement by combined analysis of temporal and logical effects. Experimental result shows that the proposed technique reduces 49.87% inaccuracy in average compared with the technique ignoring temporal masking disablement when the enabled probability of the erroneous flip-flop is 0.1.

    IEEE, 2015年, 2015 IEEE 21ST INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), 23 - 25, 英語

    [査読有り][招待有り]

    研究論文(国際会議プロシーディングス)

  • Daichi Matsunag, Shintaro Izumi, Keisuke Okuno, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper describes a non-contact and noise-tolerant heart beat monitoring system. The proposed system comprises a microwave Doppler sensor and range imagery using Microsoft Kinect™. The possible application of the proposed system is a driver health monitoring. We introduce the sensor fusion approach to minimize the heart beat detection error. The proposed algorithm can subtract a body motion artifact from Doppler sensor output using time-frequency analysis. The body motion artifact is a crucially important problem for biosignal monitoring using microwave Doppler sensor. The body motion speed is obtainable from range imagery, which has 5-mm resolution at 30-cm distance. Measurement results show that the success rate of the heart beat detection is improved about 75% on average when the Doppler wave is degraded by the body motion artifact.

    37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society(EMBC), 2015年, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2015, 6118 - 21, 英語, 国際誌

    [査読有り][招待有り]

    研究論文(学術雑誌)

  • A Ferroelectric-Based Non-Volatile Flip-Flop for Wearable Healthcare Systems

    Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Hiromitsu Kimura, Takaaki Fuchikami, Kyoji Marumoto, Yoshikazu Fujimori

    The low-power FE-based NVFF is developed by reduction of FE capacitor size. In the proposed NVFF, coupled FE capacitors with complementary data storage are introduced. The use of complementarily stored data in coupled FE capacitors achieves 88% FE capacitor size reduction while maintaining a wide read voltage margin of 240 mV (minimum) at 1.5 V, which results in 2.4 pJ low access energy with 10-year, 85 degrees C data retention capability. An access speed of FE capacitors can be adaptively changed according to required retention time, which becomes 1.6 mu s for 10-year data retention, and 170 ns for 10-hour data retention. Especially, short-term data retention is suitable for power gating implementation. As a design example, the proposed NVFF is applied to 32-bit CPU in a vital sensor LSI for wearable healthcare applications. The vital sensor LSI consists of an electrocardiogram (ECG) sensor, the 32-bit CPU core with NVFF, and a 16-Kbyte FE-based non-volatile memory (NVRAM) for data and instruction. Because the frequency range of vital signals is low, both the standby power reduction and sleep time maximization is important to system level power reduction. Its standby current can be cut when the state of CPU core transits to deep sleep. Then the data in the memory and register values of CPU core in the NVFF are stored sequentially to ferroelectric capacitors. The implementation result demonstrates that 87% of total power dissipation during measurement of the heart rate can be reduced with 64% area overhead using 130-nm CMOS with Pb(Zr,Ti)O-3(PZT) thin films.

    IEEE, 2015年, 2015 15TH NON-VOLATILE MEMORY TECHNOLOGY SYMPOSIUM (NVMTS), pp.1 - 4, 英語

    [査読有り][招待有り]

    研究論文(国際会議プロシーディングス)

  • 不揮発マイコンを用いたノーマリーオフ生体計測SoC

    松永 大地, 中井 陽三郎, 河本 優太, 中川 知己, 奥野 圭祐, 和泉 慎太郎, 川口 博, 吉本 雅彦

    2014年12月, 信学技報, vol. 114 (no. 345), p. 49, 日本語

    研究論文(その他学術会議資料等)

  • ウェアラブル生体センサのための心電計測方法

    田中 義人, 河本 優太, 中井 陽三郎, 奥野 圭祐, 和泉 慎太郎, 川口 博, 吉本 雅彦

    2014年12月, 信学技報, vol. 114 (no. 345), p. 47, 日本語

    研究論文(その他学術会議資料等)

  • Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii

    This paper reports a 65 nm 8 Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at a single supply voltage with a process-variation-tolerant sense amplifier. The proposed sense amplifier comprises a boosted-gate nMOS and negative-resistance pMOSs as loads, which maximizes the readout margin at any process corner. The STT-MRAM achieves a cycle time of 1.9 mu s (= 0.526 MHz) at 0.38 V. The operating power is 1.70 mu W at this voltage. The minimum energy per access is 1.12 pJ/bit when the supply voltage is 0.44 V. The proposed STT-MRAM operates at a lower energy than an SRAM when the utilization of the memory bandwidth is 14% or less.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2014年12月, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A (12), 2411 - 2417, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper describes a soft-error tolerant and margin-enhanced nMOS-pMOS reversed 6T SRAM cell. The 6T SRAM bitcell comprises pMOS access and driver transistors, and nMOS load transistors. Therefore, the nMOS and pMOS masks are reversed in comparison with those of a conventional bitcell. In scaled process technology, The pMOS transistors present advantages of small random dopant fluctuation, strain-enhanced saturation current, and small soft-error sensitivity. The four-pMOS and two-nMOS structure improves the soft-error rate plus operating margin. We conduct SPICE and neutron-induced soft-error simulations to evaluate the n-p reversed 6T SRAM bitcell in 130-nm to 22-nm processes. At the 22-nm node, a multiple-cell-upset and single-bit-upset SERs are improved by 34% and 51% over a conventional 6T cell. Additionally, the static noise margin and read cell current are 2.04x and 2.81x improved by leveraging the pMOS benefits.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2014年09月, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E97A (9), 1945 - 1951, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Takagi, Kenta, Tanaka, Kotaro, Izumi, Shintaro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

    As described in this paper, a real-time object detection system using a Histogram of Oriented Gradients (HOG) feature extraction accelerator VLSI is presented. The VLSI [1, 2] enables the system to achieve real-time performance and scalability for multiple object detection under limited power condition. The VLSI employs three techniques: a VLSI-oriented HOG algorithm with early classification in Support Vector Machine (SVM) classification, a dual-core architecture for parallel feature extraction, and a detection-window-size scalable architecture with a reconfigurable MAC array for processing objects of different shapes. The test chip was fabricated using 65 nm CMOS technology. The measurement result shows that the VLSI consumes 43 mW at 42.9 MHz and 1.1 V to process HDTV (1920 x 1080 pixels) at 30 frames per second (fps). A multiple object detection system and a multiple scale object detection system are presented to demonstrate the system flexibility and scalability realized by VLSI and applicability for versatile application of object detection. On the multiple object detection system, a real-time object detection for HDTV resolution video is achieved with 84 mW of power consumption on a task to detect 2 types of targets while keeping comparable detection accuracy as software-based system. On the multiple scale object detection system, a task to detect 5 scales of a target is accomplished using a single VLSI. The power consumption of the VLSI is estimated to 102 mW on the task.

    SPRINGER, 2014年09月, JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 76 (3), 261 - 274, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Y. Nakata, Y. Kimi, S. Okumura, J. Jung, T. Sawada, T. Toshikawa, NAGATA Makoto, H. Nakano, M. Yabuuchi, H. Fujiwara, K. Nii, H. Kawai, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

    This paper presents a resilient cache memory for dynamic variation tolerance in a 40-nm CMOS. The cache can perform sustained operations under a large-amplitude voltage droop. To realize sustained operation, the resilient cache exploits 7T/14T bit-enhancing SRAM and on-chip voltage/temperature monitoring circuit. 7T/14T bit-enhancing SRAM can reconfigure itself dynamically to a reliable bit-enhancing mode. The on-chip voltage/temperature monitoring circuit can sense a precise supply voltage level of a power rail of the cache. The proposed cache can dynamically change its operation mode using the voltage/temperature monitoring result and can operate reliably under a large-amplitude voltage droop. Experimental result shows that it does not fail with 25% and 30% droop of V-dd and it provides 91 times better failure rate with a 35% droop of V-dd compared with the conventional design.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2014年04月, IEICE Trans. Electron, E97C (4), 332 - 341, 英語

    [査読有り]

    研究論文(学術雑誌)

  • A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM

    G.Matsukawa, Y.Nakata, Y.Kimi, Y.Sugure, M.Shimozawa, S.Oho, H.Kawaguchi, M.Yoshimoto

    2014年02月, ARCS VERFE Workshop, pp.1 - 5, 英語

    [査読有り]

    研究論文(研究会,シンポジウム資料等)

  • 28nmFD-SOIを用いた画像処理プロセッサ向け低消費電力SRAM(ポスターセッション,学生・若手研究会)

    河本 優太, 吉本 秀輔, 中川 知己, 北原 佑起, 森 陽紀, 高木 健太, 和泉 慎太郎, 新居 浩二, 川口 博, 吉本 雅彦

    一般社団法人電子情報通信学会, 2014年01月21日, 電子情報通信学会技術研究報告. ICD, 集積回路, 113 (419), 41 - 41, 日本語

    研究論文(その他学術会議資料等)

  • Tomoki Nakagawa, Shintaro Izumi, Shusuke Yoshimoto, Koji Yanagida, Yuki Kitahara, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This report describes a high speed 6T-4C shadow memory design using a word line boosting and a plate line driver boosting. The proposed methods utilize a characteristic of ferroelectric capacitor. The word line and the plate line boosting method respectively reduce 21% write time and 33% plate line charging time. © 2014 IEEE.

    Institute of Electrical and Electronics Engineers Inc., 2014年, Proceedings - IEEE International Symposium on Circuits and Systems, 2736 - 2739, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • 動作環境の動的変動を考慮した動作マージン拡大機能を有する自律制御キャッシュ

    木美 雄太, 中田 洋平, 奥村 俊介, 鄭 晋旭, 沢田 卓也, 利川 托, 永田 真, 中野 博文, 薮内 誠, 藤原 英弘, 新居 浩二, 河合 浩行, 川口 博, 吉本 雅彦

    2014年01月, 信学技報, vol. 113 (no. 419), p. 59, 日本語

    研究論文(その他学術会議資料等)

  • 磁性変化型メモリの書き込み速度を改善するメモリアーキテクチャ

    森 陽紀, 柳田 晃司, 梅木 洋平, 吉本 秀輔, 和泉 慎太郎, 川口 博, 吉本 雅彦, 角田 浩司, 杉井 寿博

    2014年01月, 信学技報, vol. 113 (no. 419), p. 27, 日本語

    研究論文(その他学術会議資料等)

  • 強誘電体メモリの高速回路技術

    中川 知己, 吉本 秀輔, 北原 佑起, 柳田 晃司, 和泉 慎太郎, 川口 博, 吉本 雅彦

    2014年01月, 信学技報, vol. 113 (no. 419), p. 39, 日本語

    研究論文(その他学術会議資料等)

  • ディペンダブルメモリを用いた低遅延デュアルコアロックステップアーキテクチャ

    松川 豪, 中田 洋平, 川口 博, 吉本 雅彦

    2014年01月, 信学技報, vol. 113 (no. 419), p. 57, 日本語

    研究論文(その他学術会議資料等)

  • ウェアラブル生体センサのための心電図解析方法

    中井 陽三郎, 和泉 慎太郎, 中野 将尚, 山下 顕, 藤井 貴英, 川口 博, 吉本 雅彦

    2014年01月, 信学技報, vol. 113 (no. 419), p. 61, 日本語

    研究論文(その他学術会議資料等)

  • Guangji He, Yuki Miyamoto, Kumpei Matsuda, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition. We implement parallel and pipelined architecture for GMM computation and Viterbi processing. It includes a 8-path Viterbi transition architecture to maximize the processing speed and adopts tri-gram language model to improve the recognition accuracy. A two-level cache architecture is implemented for the demo system. Measured results show that our implementation achieves 25% required frequency reduction (62.5 MHz) and 26% power consumption reduction (54.8mW) for 60 k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 3.02x and 2.25x times faster than real-time at 200MHz using the bigram and trigram language models, respectively.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2014年, IEICE ELECTRONICS EXPRESS, 11 (2), pp. 1 - 9, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Normally-Off Technologies for Healthcare Appliance

    Izumi, Shintaro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko, Fujimori, Yoshikazu

    Battery mass and power consumption of wearable system must be reduced because the key factors affecting wearable system usability are miniaturization and weight reduction. This report describes a wearable biosignal monitoring system using normally-off technologies to minimize the power consumption. Especially we focused on daily-life monitoring and electrocardiograph (ECG) processor. Our system employs Ferroelectric Random Access Memory (FeRAM) and Near Field Communication (NFC) for normally-off data logging and normally-off data communication. A robust heart rate monitor and Cortex M0 core are used to on-node processing for logging data reduction.

    IEEE, 2014年, 2014 19TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 17 - 20, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A 6T-4C Shadow Memory using Plate Line and Word Line Boosting

    Nakagawa, Tomoki, Izumi, Shintaro, Yoshimoto, Shusuke, Yanagida, Koji, Kitahara, Yuki, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

    This report describes a high speed 6T-4C shadow memory design using a word line boosting and a plate line driver boosting. The proposed methods utilize a characteristic of ferroelectric capacitor. The word line and the plate line boosting method respectively reduce 21% write time and 33% plate line charging time.

    IEEE, 2014年, 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2736 - 2739, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Yozaburo Nakai, Shintaro Izumi, Masanao Nakano, Ken Yamashita, Takahide Fujii, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper describes a robust method for heart beat detection from noisy electrocardiogram (ECG) signals. Generally, the QRS-complex of heart beat is extracted from the ECG using a threshold. However, in a noisy condition such a mobile and wearable bio-signal monitoring system, noise increases the incidence of misdetection and false detection of QRS-complex. To prevent incorrect detection, we introduce a novel template matching algorithm. The template waveform can be generated autonomously using a short-term autocorrelation method, which leverages the similarity of QRS-complex waveforms. Simulation results show the proposed method achieves state-of-the-art noise tolerance of heart beat detection.

    2014年, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2014, 34 - 7, 英語, 国際誌

    [査読有り]

    研究論文(学術雑誌)

  • A 6.14μA Normally-Off ECG-SoC with Noise Tolerant Heart Rate Extractor for Wearable Healthcare Systems

    IZUMI Shintaro, YAMASHITA Ken, NAKANO Masanao, NAKAGAWA Tomoki, KITAHARA Yuki, YANAGIDA Koji, YOSHIMOTO Shusuke, KAWAGUCHI Hiroshi, H. Kimura, K. Marumoto, T. Fuchikami, H. Nakajima, T. Shiga, YOSHIMOTO Masahiko

    This paper describes an electrocardiograph (ECG) monitoring SoC using a non-volatile MCU (NVMCU) and a noise tolerant instantaneous heart rate (IHR) monitor. The novelty of this work is the combination of the non-volatile MCU for normally-off computing and a noise-tolerant-QRS (heart beat) detection algorithm to achieve both low-power and noise tolerance. To minimize the stand-by current of MCU, a nonvolatile flip-flop and a 6T-4C NVRAM are employed. Proposed plate-line charge-share and bit-line non-precharge techniques also contribute to mitigate the active power overhead of 6T-4C NVRAM. The proposed accurate heart beat detector employs a coarse-fine autocorrelation and a template matching technique. Accurate heart beat detection also contributes system level power reduction because the active ratio of ADC and digital block can be reduced using a heart beat prediction. Then, at least 25% active time can be reduced. Measurement results show the fully integrated ECG-SoC consumes 6.14 mu A including 1.28-mu A nonvolatile MCU and 0.7-mu A heart rate extractor.

    IEEE, 2014年, Proc. of IEEE BioCAS, 280 - 283, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A 2.4 pJ Ferroelectric-Based Non-Volatile Flip-Flop with 10-Year Data Retention Capability

    Kimura, Hiromitsu, Fuchikami, Takaaki, Marumoto, Kyoji, Fujimori, Yoshikazu, Izumi, Shintaro, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

    A ferroelectric-based (FE-based) non-volatile flip-flop (NVFF) is proposed for low-power LSI. Since leakage current in a logic circuit can be cut off by non-volatile storage capability of NVFFs, the standby power is reduced to zero. The use of complementarily stored data in coupled FE capacitors makes it possible to achieve 88% reduction of FE capacitor size while maintaining a wide read voltage margin of 240mV (minimum) at 1.5V, which results in 2.4pJ low access energy with 10-year, 85 degrees C data retention capability. An access speed of FE capacitors can be adaptively changed according to required retention time, which becomes 1.6 mu s for 10-year data retention, and 170ns for 10-hour data retention. Especially, short-term data retention is suitable for power gating implementation. Applying the proposed circuitry in 32bit CPU of a vital sensor LSI, its power consumption becomes 13% of that of conventional one with area overhead of 64% using 130nm CMOS with Pb(Zr,Ti)O-3(PZT) thin films.

    IEEE, 2014年, 2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 21 - 24, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • An 8-bit I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter

    Okuno, Keisuke, Konishi, Toshihiro, Izumi, Shintaro, Yoshimoto, Masahiko, Kawaguchi, Hiroshi

    We present an I/O-sized second-order analog to digital converter (ADC) combined with a time-to-digital converter (TDC) and a voltage-to-time converter (VTC). Our proposed VTC is optimized for metal-oxide-metal (MOM) capacitances, and is charged to the MOM capacitances by an input voltage. In a standard 65-nm CMOS process, an SNR of 50 dB (8 bits) is achievable at an input signal frequency of 78 kHz and a sampling rate of 20 MHz, where the respective area and power are 6468 mm(2) and 509 mu W. The active area of the proposed ADC is smaller than an I/O buffer. The proposed ADC is useful as an ADC I/O.

    IEEE, 2014年, 2014 21ST IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 223 - 226, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A 2.23 ps RMS Jitter 3 μs Fast Settling ADPLL using Temperature Compensation PLL Controller

    OKUNO Keisuke, MASAKI Kana, IZUMI Shintaro, KONISHI Toshihiro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

    This report describes an all-digital phase-locked loop (ADPLL) with temperature-compensated settling time reduction. The novelty of this work is autonomous oscillation control word estimation without a look-up table or memory circuits. The proposed ADPLL includes a multi-phase oscillator as a digitally controlled oscillator (DCO). Digital timing error correction circuits are integrated to minimize the settling time that is degraded by phase conversion error. The ADPLL is fabricated using a 65 nm CMOS process. The test chip occupies 0.27 x 0.36 mm(2). It achieves 2.23 ps RMS jitter and -224 dB FoM at 2.4 GHz output frequency with 8.85 mW power dissipation. Measurement results show that the 47% settling time is reduced by the proposed estimation block. The average settling time at 25 degrees C is 3 mu s.

    IEEE, 2014年, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 68 - 71, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • 3×倍速実時間6万語彙連続音声認識のための40-nm,54-mW音声認識専用プロセッサ (集積回路)

    何 光霽, 宮本 優貴, 松田 薫平, 和泉 慎太郎, 川口 博, 吉本 雅彦

    本稿では,6万語彙の実時間連続音声認識のための低消費電力VLSIチップについて説明する.高速,高精度,低消費電力で6万語彙連続音声認識を実現するために,以前試作した音声認識プロセッサの提案手法を用いた上で,高並列な8-pass Viterbi遷移アーキテクチャを実装することで,全体処理速度のネックとなっているViterbi部分をさらに高速化させた.また,探索処理において第2パスにtri-gramを用いることで,認識精度をbi-gramのみの場合より約2%向上できた. 回路規模2.98MTr,オンチップ SRAM容量4.29Mbitsの6万語彙連続音声認識のための専用プロセッサを設計し,40nmプロセスで試作した. bi-gramのみを使う場合,実時間処理に必要な62.5MHz動作時の消費電力は54.8 mWであった.標準電圧(1.1V)で最大200MHz (177.4 mW) 動作が確認され, 3倍速動作を実現できた.また,tri-gramを使う場合,200MHzで最高処理速度は2.25倍速であり,消費電力は174.56 mWであった.

    一般社団法人電子情報通信学会, 2013年10月07日, 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 113 (236), 29 - 34, 日本語

    研究論文(その他学術会議資料等)

  • Soft-Error Tolerant N-P Reversed 6T SRAM Cell

    S. Yoshimoto, S. Izumi, H. Kawaguchi, M. Yoshimoto

    2013年07月, IEEE Nuclear and Space Radiation Effects Conference (NSREC), PG - 3, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Shusuke Yoshimoto, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper presents a proposed NMOS-centered 6T SRAM cell layout that reduces a neutron-induced multiple-cell-upset (MCU) SER on a same wordline. We implemented an 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67-98% compared with a general macro that has PMOS-centered 6T SRAM cells.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2013年07月, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E96A (7), 1579 - 1585, 英語

    [査読有り]

    研究論文(学術雑誌)

  • マルチビットアップセット耐性を有するNMOS内側レイアウトを用いた6T SRAM (集積回路)

    吉本 秀輔, 和泉 慎太郎, 川口 博, 吉本 雅彦

    本論文では,マルチビットアップセット耐性を有するNMOS内側レイアウトを有する6T SRAMセルレイアウトを提案する.提案レイアウトは,ソフトエラー耐性の低いNMOSを内側に配置することにより,MCUを低減出来る.65-nmプロセスを用いて1Mb SRAMを試作し中性子線照射試験を行った所,67-98%のMCUソフトエラーレートを削減出来る事を示した.

    一般社団法人電子情報通信学会, 2013年04月11日, 電子情報通信学会技術研究報告 : 信学技報, 113 (1), 121 - 126, 日本語

    研究論文(その他学術会議資料等)

  • ゼロデータフラグを用いた低エネルギーSTT-RAMキャッシュ

    木美 雄太, 鄭 晋旭, 中田 洋平, 吉本 雅彦, 川口 博

    2013年04月, 信学技報, vol. 113 (no. 1), pp.47 - 52, 日本語

    研究論文(その他学術会議資料等)

  • Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper presents an adaptive cache architecture for wide-range reliable low-voltage operations. The proposed associativity-reconfigurable cache consists of pairs of cache ways so that it can exploit the recovery feature of the novel 7T/14T SRAM cell. Each pair has two operating modes that can be selected based upon the required voltage level of current operating conditions: normal mode for high performance and dependable mode for reliable low-voltage operations. We can obtain reliable low-voltage operations by application of the dependable mode to weaker pairs that cannot operate reliably at low voltages. Meanwhile leaving stronger pairs in the normal mode, we can minimize performance losses. Our chip measurement results show that the proposed cache can trade off its associativity with the minimum operating voltage. Moreover, it can decrease the minimum operating voltage by 140 mV achieving 67.48% and 26.70% reduction of the power dissipation and energy per instruction. Processor simulation results show that designing the on-chip caches using the proposed scheme results in 2.95% maximum IPC losses, but it can be chosen various performance levels. Area estimation results show that the proposed cache adds area overhead of 1.61% and 5.49% in 32-KB and 256-KB caches, respectively.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2013年04月, IEICE TRANSACTIONS ON ELECTRONICS, E96C (4), 528 - 537, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Kosuke Mizuno, Kenta Takagi, Yosuke Terachi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper describes a Histogram of Oriented Gradients (HOG) feature extraction accelerator that features a VLSI-oriented HOG algorithm with early classification in Support Vector Machine (SVM) classification, dual core architecture for parallel feature extraction and multiple object detection, and detection-window-size scalable architecture with reconfigurable MAC array for processing objects of several shapes. To achieve low-power consumption for mobile applications, early classification reduces the amount of computations in SVM classification efficiently with no accuracy degradation. The dual core architecture enables parallel feature extraction in one frame for high-speed or low-power computing and detection of multiple objects simultaneously with low power consumption by HOG feature sharing. Objects of several shapes, a vertically long object, a horizontally long object, and a square object, can be detected because of cooperation between the two cores. The proposed methods provide processing capability for HDTV resolution video (1920 x 1080 pixels) at 30 frames per second (fps). The test chip, which has been fabricated using 65 nm CMOS technology, occupies 4.2 x 2.1 mm(2) containing 502 Kgates and 1.22 Mbit on-chip SRAMs. The simulated data show 99.5 mW power consumption at 42.9 MHz and 1.1 V.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2013年04月, IEICE TRANSACTIONS ON ELECTRONICS, E96C (4), 433 - 443, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi

    We present a small-area second-order all-digital time-to-digital converter (TDC) with two frequency shift oscillators (FSOs) comprising inverter chains and dynamic flipflops featuring low jitter. The proposed FSOs can maintain their phase states through continuous oscillation, unlike conventional gated ring oscillators (GROs) that are affected by transistor leakage. Our proposed FSOTDC is more robust and is eligible for all-digital TDC architectures in recent leaky processes. Low-jitter dynamic flipflops are adopted as a quantization noise propagator (QNP). A frequency mismatch occurring between the two FSOs can be canceled out using a least mean squares (LMS) filter so that second-order noise shaping is possible. In a standard 65-nm CMOS process, an SNDR of 61 dB is achievable at an input bandwidth of 500 kHz and a sampling rate of 16 MHz, where the respective area and power are 700 mu m(2) and 281 mu W.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2013年04月, IEICE TRANSACTIONS ON ELECTRONICS, E96C (4), 546 - 552, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Guangji He, Takanobu Sugahara, Yuki Miyamoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). It features a compression-decoding scheme to reduce the external memory bandwidth for Gaussian Mixture Model (GMM) computation and multi-path Viterbi transition units. We optimize the internal SRAM size using the max-approximation GMM calculation and adjusting the number of look-ahead frames. The test chip, fabricated in 40 nm CMOS technology, occupies 1.77 mm x 2.18 mm containing 2.52 M transistors for logic and 4.29 Mbit on-chip memory. The measured results show that our implementation achieves 34.2% required frequency reduction (83.3 MHz), 48.5% power consumption reduction (74.14 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work while 30% of the area is saved with recognition accuracy of 90.9%. This chip can maximally process 2.4x faster than real-time at 200 MHz and 1.1 V with power consumption of 168 mW. By increasing the beam width, better recognition accuracy (91.45%) can be achieved. In that case, the power consumption for real-time processing is increased to 97.4 mW and the max-performance is decreased to 2.08x because of the increased computation workload.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2013年04月, IEICE TRANSACTIONS ON ELECTRONICS, E96C (4), 444 - 453, 英語

    [査読有り]

    研究論文(学術雑誌)

  • SRAM Failure Injection to a Vehicle ECU and Its Behavior Evaluation

    Y. Takeuchi, Y. Nakata, Y. Ito, Y. Sugure, S. Oho, H. Kawaguchi, M. Yoshimoto

    2013年03月, DATE RIIF Workshop, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Model-Based Fault Injection for Large-Scale Failure Effect Analysis with 600-Node Cloud Computers

    Y. Nakata, Y. Ito, Y. Takeuchi, Y. Sugure, S. Oho, H. Kawaguchi, M. Yoshimoto

    2013年03月, DATE RIIF Workshop, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Kosuke Mizuno, Yosuke Terachi, Kenta Takagi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper describes a Histogram of Oriented Gradients (HOG)-based object detection processor. It features a simplified HOG algorithm with cell-based scanning and simultaneous Support Vector Machine (SVM) calculation, cell-based pipeline architecture, and parallelized modules. To evaluate the effectiveness of our approach, the proposed architecture is implemented onto a FPGA prototyping board. Results show that the proposed architecture can generate HOG features and detect objects with 40MHz for SVGA resolution video (800 × 600 pixels) at 72 frames per second (fps). © 2013 Information Processing Society of Japan.

    2013年02月, IPSJ Transactions on System LSI Design Methodology, 6, 42 - 51, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Konishi, Toshihiro, Okuno, Keisuke, Izumi, Shintaro, Yoshimoto, Masahiko, Kawaguchi, Hiroshi

    This paper presents a second-order Delta Sigma analog-to-digital converter (ADC) operating in a time domain. In the proposed ADC architecture, a voltage-controlled delay unit (VCDU) converts an input analog voltage to a delay time. Then, the clocks outputs from a gated ring oscillator (GRO) are counted during the delay time. No switched capacitor or opamp is used. Therefore, the proposed ADC can be implemented in a small area and with low power. For that reason, it has process scalability: it can keep pace with Moore's law. A time error is propagated to the second GRO by a multi-stage noise-shaping (MASH) topology, which provides second-order noise-shaping. In a standard 40-nm CMOS process, a SNDR of 45 dB is achievable at input bandwidth of 16 kHz and a sampling rate of 8 MHz, where the power is 408.5 mu W. Its area is 608 mu m(2).

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2013年02月, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E96A (2), 434 - 442, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Yasuo Sugure, Yasuhiro Ito, Yohei Nakata, Yusuke Takeuchi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Shigeru Oho

    We propose a virtual prototyping system that can evaluate failure mode and effect analysis (FMEA). The virtual prototyping system which consists of co-simulation environment between mechanics model and microcontroller model is integrated a fault-injection system that can inject faults into SRAM. This approach was applied to a validation of vehicle engine control. We observed that an abnormal system behavior occurred by SRAM fault. Thus the virtual prototyping system with faultinjection system can be performed a vehicle engine control behavior without actual components when fault occurred.

    2013年, IFAC Proceedings Volumes (IFAC-PapersOnline), 7 (1), 562 - 563, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Takahide Fujii, Masanao Nakano, Ken Yamashita, Toshihiro Konishi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper describes a robust method of Instantaneous Heart Rate (IHR) and R-peak detection from noisy electrocardiogram (ECG) signals. Generally, the IHR is calculated from the R-wave interval. Then, the R-waves are extracted from the ECG using a threshold. However, in wearable bio-signal monitoring systems, noise increases the incidence of misdetection and false detection of R-peaks. To prevent incorrect detection, we introduce a short-term autocorrelation (STAC) technique and a small-window autocorrelation (SWAC) technique, which leverages the similarity of QRS complex waveforms. Simulation results show that the proposed method improves the noise tolerance of R-peak detection.

    2013年, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2013, 7330 - 3, 英語, 国際誌

    [査読有り]

    研究論文(学術雑誌)

  • A Physical Unclonable Function Chip Exploiting Load Transistors’ Variation in SRAM Bitcells

    S. Okumura, S. Yoshimoto, H. Kawaguchi, M. Yoshimoto

    We propose a chip identification (ID) generating scheme with random variation of transistor characteristics in SRAM bitcells. In the proposed scheme, a unique fingerprint is generated by grounding both bitlines. It has high speed, and it can be implemented in a very small area overhead. We fabricated test chips in a 65-nm process and obtained 12,288 sets of unique 128-bit fingerprints, which are evaluated in this paper. The failure rate of the IDs is found to be 2.1 x 10(-12).

    IEEE, 2013年, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), 79 - 80, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A 40-nm 144-mW VLSI Processor for Real-time 60-kWord Continuous Speech Recognition

    Guangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    We have developed a low-power VLSI chip for 60- kWord real-time continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). Our implementation includes a cache architecture using locality of speech recognition, beam pruning using a dynamic threshold, two-stage language model searching, highly parallel Gaussian Mixture Model (GMM) computation based on the mixture level, a variable-frame look-ahead scheme, and elastic pipeline operation between the Viterbi transition and GMM processing. Results show that our implementation achieves 95% bandwidth reduction (70.86 MB/s) and 78% required frequency reduction (126.5 MHz). The test chip, fabricated using 40 nm CMOS technology, contains 1.9 M transistors for logic and 7.8 Mbit on-chip memory. It dissipates 144 mW at 126.5 MHz and 1.1 V for 60 kWord real-time continuous speech recognition.

    IEEE, 2013年, 2013 18TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 71 - 72, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Power Disturb Mitigation Technique

    S. Yoshimoto, M. Terada, S. Okumura, T. Suzuki, S. Miyano, H. Kawaguchi, M. Yoshimoto

    2013年01月, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 77 - 78, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Energy-Efficient Spin-Transfer Torque RAM Cache Exploiting Additional All-Zero-Data Flags

    Jinwook Jung, Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi

    Large on-chip caches account for a considerable fraction of the total energy consumption in modern microprocessors. In this context, emerging Spin-Transfer Torque RAM (STT-RAM) has been regarded as a promising candidate to replace large on-chip SRAM caches in virtue of its nature of the zero leakage. However, large energy requirement of STT-RAM on write operations, resulting in a huge amount of dynamic energy consumption, precludes it from application to on-chip cache designs. In order to reduce the write energy of the STT-RAM cache thereby the total energy consumption, this paper provides an architectural technique which exploits the fact that many applications process a large number of zero data. The proposed design appends additional flags in cache tag arrays and set these additional bits if the corresponding data in the cache line is the zero-valued data in which all data bits are zero. Our experimental results show that the proposed cache design can reduce 73.78% and 69.30% of the dynamic energy on write operations at the byte and word granularities, respectively; total energy consumption reduced by 36.18% and 42.51%, respectively. In addition to the energy reduction, performance evaluation results indicate that the proposed cache improves the processor performance by 5.44% on average.

    IEEE, 2013年, PROCEEDINGS OF THE FOURTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2013), 216 - 222, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A SUB-100-MILLIWATT DUAL-CORE HOG ACCELERATOR VLSI FOR REAL-TIME MULTIPLE OBJECT DETECTION

    Kenta Takagi, Kosuke Mizuno, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    In this paper, a Histogram of Oriented Gradients (HOG) feature extraction accelerator for real-time multiple object detection is presented. The processor employs three techniques: a VLSI-oriented HOG algorithm with early classification in Support Vector Machine (SVM) classification, a dual core architecture for parallel feature extraction, and a detection-window-size scalable architecture with a reconfigurable MAC array for processing objects of different shapes. Early classification reduces the number of computations in SVM classification. The dual core architecture and the detection-window-size scalable architecture enable the processor to operate in several modes: highspeed mode, low-power mode, multiple object detection mode, and multiple shape object detection mode. These techniques expand the processor flexibility required for versatile application. The test chip was fabricated using 65 nm CMOS technology. The proposed architecture is designed to process HDTV resolution video (1920 x 1080 pixels) at 30 frames per second (fps). The performance of this accelerator is demonstrated on a pedestrian detection system.

    IEEE, 2013年, 2013 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING (ICASSP), 2533 - 2537, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Temperature Compensation using Least Mean Squares for Fast Settling All-Digital Phase-Locked Loop

    Keisuke Okuno, Shintaro Izumi, Toshihiro Konishi, Song Dae-Woo, Masahiko Yoshimoto, Hiroshi Kawaguchi

    This paper presents a temperature compensation technique for a digitally controlled oscillator (DCO) using least means square (LMS) filtering. The proposed scheme contributes to reduction of the start-up settling time of all-digital phase-locked loop (ADPLL). The proposed method estimates the temperature using the output frequency of DCO because it is affected by temperature fluctuation. An optimal value of oscillation tuning word (OTW) for DCO can be estimated using the LMS algorithm because a linear relation exists between the output frequency of maximum OTW and the output frequency of other OTWs. These characteristics are confirmed using measurement results of the DCO, which is fabricated in 65-nm CMOS process. We modeled the ADPLL with the proposed temperature compensator in MATLAB using the measurement results of DCO. The simulation results show that the ADPLL with proposed temperature compensator achieves more than 53% settling time reduction and less than 10-MHz frequency error.

    IEEE, 2013年, 2013 IEEE 11TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), pp.1 - 4, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Multiple-Cell-Upset Hardened 6T SRAM Using NMOS-Centered Layout

    S. Yoshimoto, K. Nii, H. Kawaguchi, M. Yoshimoto

    This paper presents a proposed NMOS-centered 6T SRAM cell layout that reduces a neutron-induced multiple-cell-upset (MCU) SER on a same wordline. We implemented an 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67-98% compared with a general macro that has PMOS-centered 6T SRAM cells.

    IEEE, 2013年, 2013 IEEE INTERNATIONAL MEETING FOR FUTURE OF ELECTRON DEVICES, KANSAI (IMFEDK2013), pp. 98 - 99, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A 38 mu A Wearable Biosignal Monitoring System with Near Field Communication

    Yamashita, Ken, Izumi, Shintaro, Nakano, Masanao, Fujii, Takahide, Konishi, Toshihiro, Kawaguchi, Hiroshi, Kimura, Hiromitsu, Marumoto, Kyoji, Fuchikami, Takaaki, Fujimori, Yoshikazu, Nakajima, Hiroshi, Shiga, Toshikazu, Yoshimoto, Masahiko

    This paper presents a low-power wearable biosignal monitoring system. The proposed system can communicate with smartphones using Near Field Communication (NFC) to check vital signs easily at any time. It comprises a battery, electrodes, a triaxial accelerometer IC, an NFC tag IC, and a biosignal processor LSI. The proposed biosignal processor LSI, fabricated using a 130-nm CMOS process, comprises heart rate monitoring circuits, a 32-kbyte ferroelectric random access memory (FeRAM), an accelerometer interface, and an NFC interface. The proposed system consumes 38.1 mu A for logging application at 32-kHz operating frequency, with 3.0-V supply voltage.

    IEEE, 2013年, 2013 IEEE 11TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), pp.1 - 4, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Takahide Fujii, Masanao Nakano, Ken Yamashita, Toshihiro Konishi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper describes a robust method of Instantaneous Heart Rate (IHR) and R-peak detection from noisy electrocardiogram (ECG) signals. Generally, the IHR is calculated from the R-wave interval. Then, the R-waves are extracted from the ECG using a threshold. However, in wearable bio-signal monitoring systems, noise increases the incidence of misdetection and false detection of R-peaks. To prevent incorrect detection, we introduce a short-term autocorrelation (STAC) technique and a small-window autocorrelation (SWAC) technique, which leverages the similarity of QRS complex waveforms. Simulation results show that the proposed method improves the noise tolerance of R-peak detection.

    2013年, Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference, 2013, 7330 - 3, 英語, 国際誌

    [査読有り]

    研究論文(学術雑誌)

  • A 40-nm 8T SRAM with Selective Source Line Control of Read Bitlines and Address Preset Structure

    S. Yoshimoto, S. Miyano, M. Takamiya, H. Shinohara, H. Kawaguchi, M. Yoshimoto

    This paper presents a 40-nm 8T SRAM in which bitlines are partially discharged by a selective source line control (SSLC) for low-power operation. The proposed SSLC scheme reduces a read bitline voltage swing in an unselected column with a floating source line (SL) of dedicated read ports. The SL is controlled by an additional NMOS switch that is turned on in a selected column, but the switch is kept off in the remaining unselected columns. The proposed scheme is effective for power reduction in successive address readouts through a single column. Furthermore, this paper introduces an address preset structure. The preset address enables the SRAM to be read out with no access time penalty for preferred use of the SSLC scheme. We fabricated a 16-Kb 8T SRAM test chip in a 40-nm CMOS process and observed that the proposed SSLC scheme with the address preset structure saves 38.1% of the readout power on average.

    IEEE, 2013年, 2013 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), pp.1 - 4, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Shintaro Izumi, Ken Yamashita, Masanao Nakano, Toshihiro Konishi, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto

    This report describes an electrocardiograph (ECG) processor for use with a wearable healthcare system. It comprises an analog front end, a 12-bit ADC, a robust Instantaneous Heart Rate (IHR) monitor, a 32-bit Cortex-M0 core, and 64 Kbyte Ferroelectric Random Access Memory (FeRAM). The IHR monitor uses a short-term autocorrelation (STAC) algorithm to improve the heart-rate detection accuracy despite its use in noisy conditions. The ECG processor chip consumes 13.7 μA for heart rate logging application. © 2013 IEEE.

    2013年, European Solid-State Circuits Conference, 145 - 148, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A 40-nm 54-mW 3×-Real-time VLSI Processor for 60-KWORD Continuous Speech Recognition

    G. He, Y. Miyamoto, K. Matsuda, S. Izumi, H. Kawaguchi, M. Yoshimoto

    This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). We implement parallel and pipelined architecture for GMM computation and Viterbi processing. It includes a 8-path Viterbi transition architecture to maximize the processing speed and adopts tri-gram language model to improve the recognition accuracy. A two-level cache architecture is implemented for the demo system. The test chip, fabricated in 40 nm CMOS technology, occupies 1.77 mm x 2.18 mm containing 2.98 M transistors for logic and 4.29 Mbit on-chip memory. The measured results show that our implementation achieves 25% required frequency reduction (62.5 MHz) and 26% power consumption reduction (54.8 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 3.02x and 2.25x times faster than real-time at 200 MHz using the bigram and trigram language models, respectively.

    IEEE, 2013年, IEEE Workshop on Signal Processing Systems (SiPS), 147 - 152, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Low-power Hardware Implementation of Noise Tolerant Heart Rate Extractor for a Wearable Monitoring System

    Shintaro Izumi, Masanao Nakano, Ken Yamashita, Takahide Fujii, Hiroshi Kawaguchi, Masahiko Yoshimoto

    To prevent lifestyle diseases, wearable bio-signal monitoring systems for daily life monitoring have attracted attention. Wearable systems have strict size and weight constraints, which impose significant limitations of the battery capacity and the signal-to-noise ratio of bio-signals. The novelty of this work is the hardware implementation of a noise-tolerant heart rate extraction algorithm that can achieve low-power performance with high reliability. This report describes comparisons of the heart rate extraction algorithm performance and the dedicated hardware implementation of short-term autocorrelation ( STAC) method. The proposed heart rate extractor, implemented in 65-nm CMOS process using Verilog-HDL, consumes 1.65 mu A at 32.768-kHz operating frequency with 1.1 V supply voltage.

    IEEE, 2013年, 2013 IEEE 13TH INTERNATIONAL CONFERENCE ON BIOINFORMATICS AND BIOENGINEERING (BIBE), pp.1 - 4, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A 0.38-V Operating STT-MRAM with Process Variation Tolerant Sense Amplifier

    Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii

    This paper exhibits a 65-nm 8-Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at a single supply voltage with a process-variation tolerant sense amplifier. The proposed sense amplifier comprises a boosted-gate nMOS and negative-resistance pMOSes as loads, which maximizes the readout margin in any process corner. The STT-MRAM achieves a cycle time of 1.9 mu s (=0.526 MHz) at 0.38 V. The operating power is 6.15 mu W at that voltage. The minimum energy per access is 3.89 pJ/bit when the supply voltage is 0.44 V. The proposed STT-MRAM operates at lower energy than SRAM when a utilization of a memory bandwidth is 14% or less.

    IEEE, 2013年, PROCEEDINGS OF THE 2013 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 249 - 252, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • 2.4倍速実時間6万語彙連続音声認識プロセッサの開発 (集積回路)

    宮本 優貴, 何 光霽, 和泉 慎太郎, 川口 博, 吉本 雅彦

    本稿では,6万語彙の実時間連続音声認識のための低消費電力VLSIチップについて説明する.GMM演算時の外部メモリ帯域削減用圧縮デコーダ,VITERBI並列アーキテクチャを実装した.内部SRAM容量を最適化するために,近似GMM演算アルゴリズムの導入,先読みフレーム数の調整を行った.その結果,実時間処理時において従来研究より必要動作周波数を34.2%削減し83.3MHz,消費電力を48.5%削減し74.14mWを実現した.また,標準電圧(1.1 V)で最大200MHz (168 mW) 動作を確認し,2.4倍速で動作することを確認出来た.

    一般社団法人電子情報通信学会, 2012年12月17日, 電子情報通信学会技術研究報告 : 信学技報, 112 (365), 49 - 53, 日本語

    研究論文(学術雑誌)

  • 強誘電体キャパシタを用いた6T4CシャドウSRAMの高性能化技術

    中川 知己, 吉本 秀輔, 北原 佑起, 柳田 晃司, 梅木 洋平, 奥村 俊介, 和泉 慎太郎, 川口 博, 吉本 雅彦

    近年,農業・医療・防災といった分野において,実フィールドの情報を広範囲にカバー可能な,センサネットワーク技術が注目されている.各センサノードはバッテリの交換が困難なため,極低電力な動作が求められる.
    中でも,待機時電力の大きなメモリの低消費電力化技術が重要視されている.

    本研究では,6T4Cシャドウメモリにおける高性能化回路技術の提案を行う.強誘電体キャパシタを用いた6T4C SRAMは,アクティブ時に高速なSRAMとして動作し,スリープ時にはFe素子にデータをストアし不揮発メモリとして動作出来る.従来6T4C SRAMではFe素子の追加により,SRAM動作時の消費電力・サイクルタイムが劣化するという問題があった.本論文では,シミュレーションにより提案技術の有効性を示す.

    一般社団法人電子情報通信学会, 2012年12月10日, 電子情報通信学会技術研究報告. ICD, 集積回路, 112 (365), 41 - 41, 日本語

    研究論文(学術雑誌)

  • ウェアラブル生体情報計測システムのための瞬時心拍検出アルゴリズム(ポスターセッション)

    山下 顕, 中野 将尚, 小西 恵大, 和泉 慎太郎, 川口 博, 吉本 雅彦

    重要な生体基礎データのひとつに瞬時心拍がある.瞬時心拍とは,心電図における直近のR波間距離のことである.活動量計算や行動分類,心拍変動解析による心疾患の検出など,ヘルスケア・メディカル用途で瞬時心拍を用いた応用技術が多数提案されている.本研究では,消費電力や電極サイズに対して厳しい制約を持つ貼り付け型生体情報計測システムのための,ロバストな瞬時心拍検出アルゴリズムを提案する. 従来の心拍抽出手法では,Root Mean Squareや標準偏差などを用いて何らかの閾値を設定し,心電波形からR波を検出していた.しかし,従来の方法では心電図に混入したノイズ(筋電ノイズ,電極アーチファクト等)による誤検出・未検出が問題となる.これに対して提案手法では,得られた心電波形から短時間自己相関を求めることで,SNRの低い心電図からでも高精度に心拍を抽出できる.また,提案手法はA/D変換後のデジタル信号処理によって実現されるため,消費電力削減の難しいアナログフロントエンドや,ノードサイズを決める電極の性能要件を緩和することができる.

    一般社団法人電子情報通信学会, 2012年12月10日, 電子情報通信学会技術研究報告. ICD, 集積回路, 112 (365), 27 - 27, 日本語

    研究論文(学術雑誌)

  • HOG特徴量による実時間物体検出プロセッサのFPGA実装

    高木 健太, 水野 孝祐, 和泉 慎太郎, 川口 博, 吉本 雅彦

    Histogram of Oriented Gradients (HOG)特徴量は,歩行者を始めとする様々な物体の検出に高い性能を有するため,近年広く用いられている画像特徴量である.物体検出の技術は,自動車等への実用が始まっており重要度を増している.また,近年の汎用プロセッサの性能向上により,HOG特徴量等の計算コストの高い処理を実装し,実時間で動画像を処理することも可能となってきた.一方で,これらの汎用プロセッサは膨大な電力を消費するため,モバイル用途への適用は困難である.そこで本研究では,HOG特徴量を用いた実時間物体検出のためのプロセッサを提案する.提案するプロセッサは,画像中の局所領域であるセルに着目したHOGアルゴリズムの簡略化と,サポートベクターマシーンでの同時計算,セルベースのパイプラインアーキテクチャ及び高並列な各演算モジュールを用いたアーキテクチャを有する.本アーキテクチャの有効性を評価するため,FPGAにて実装を行った.その結果,SVGA解像度(800x600ピクセル)の画像から,HOG特徴量の生成及び物体検出を72fpsで実現できることを確認した.

    一般社団法人電子情報通信学会, 2012年12月10日, 電子情報通信学会技術研究報告. ICD, 集積回路, 112 (365), 61 - 61, 日本語

    研究論文(学術雑誌)

  • Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto

    We propose a chip identification (ID) generating scheme with random variation of transistor characteristics in SRAM bitcells. In the proposed scheme, a unique fingerprint is generated by grounding both bitlines in write operations. Through minor modifications, this scheme can be implemented for existing SRAMs. It has high speed, and it can be implemented in a very small area overhead. The generated fingerprint mainly reflects threshold voltages of load transistors in the bitcells. We fabricated test chips in a 65-nm process and obtained 12,288 sets of unique 128-bit fingerprints, which are evaluated in this paper. The failure rate of the IDs is found to be 2.1 x 10(-12).

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2012年12月, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E95A (12), 2226 - 2233, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper presents a new 8T (8-transistor) SRAM cell layout mitigating multiple-bit upset (MBU) in a divided wordline structure. Because bitlines along unselected columns are not activated, the divided wordline structure eliminates a half-select problem and achieves low-power operation, which is often preferred for low-power/low-voltage applications. However, the conventional 81 SRAM with the divided wordline structure engenders MBUs because all bits in the same word are physically adjoining. Consequently, it is difficult to apply an error correction coding (ECC) technique to it. In this paper, we propose a new 81 cell layout pattern that separates internal latches in SRAM cells using both an n-well and a p-substrate. We saw that a SEU cross section of nMOS is 3.5-4.5 times higher than that of pMOS (SEU: single event upset; a cross section signifies a sensitive area to soft error effects). By using a soft-error simulator, iRoC TFIT, we confirmed that the proposed 81 cell has better neutron-induced MBU tolerance. The simulator includes soft-error measurement data in a commercial 65-nm process. The MBU in the proposed 81 SRAM is improved by 90.70% and the MBU soft error rate (SER) is decreased to 3.46 FIT at 0.9 V when ECC is implemented (FIT: failure in time). Additionally, we conducted Synopsys 3-0 TCAD simulation, which indicates that the linear energy transfer (LET) threshold in SEU is also improved by 66% in the proposed 81 SRAM by a common-mode effect.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2012年10月, IEICE TRANSACTIONS ON ELECTRONICS, E95C (10), 1675 - 1681, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Guangji He, Takanobu Sugahara, Yuki Miyamoto, Tsuyoshi Fujinaga, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    We have developed a low-power VLSI chip for 60-kWord real-time continuous speech recognition based on a context-dependent hidden Markov model (HMM). Our implementation includes a cache architecture using locality of speech recognition, beam pruning using a dynamic threshold, two-stage language model searching, highly parallel Gaussian mixture model (GMM) computation based on the mixture level, a variable-frame look-ahead scheme, and elastic pipeline operation between the Viterbi transition and GMM processing. The accuracy degradation of the important parameters in Viterbi computation is strictly discussed. Results show that our implementation achieves 95% bandwidth reduction (70.86 MB/s) and 78% required frequency reduction (126.5 MHz) comparing to the referential Julius [1] system. The test chip, fabricated using 40 nm CMOS technology, contains 1.9 M transistors for logic and 7.8 Mbit on-chip memory. It dissipates 144 mW at 126.5 MHz and 1.1 V for 60-kWord real-time continuous speech recognition.

    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2012年08月, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 59 (8), 1656 - 1666, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Koji Nii, Masahiko Yoshimoto, Hiroshi Kawaguchi

    This paper presents measurement results of bit error rate (BER) and soft error rate (SER) improvement on 150-nm FD-SOI 7T/14T (7-transistor/14-transistor) SRAM test chips. The reliability of the 7T/14T SRAM can be dynamically changed by a control signal depending on an operating condition and application. The 14T dependable mode allocates one bit in a 14T cell and improves the BER in a read operation and SER in a retention state, simultaneously. We investigate its error rate mitigating mechanisms using Synopsys TCAD simulator. In our measurements, the minimum operating voltage was improved by 100 mV, the alpha-induced SER was suppressed by 80.0%, and the neutron-induced SER was decreased by 34.4% in the 14T dependable mode over the 7T normal mode.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2012年08月, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E95A (8), 1359 - 1365, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Trading off ECU Footprint for Reliability in X-by-Wire Application with Hybrid TMR Architecture

    Y. Nakata, S. Izumi, H. Kawaguchi, M. Yoshimoto

    2012年06月, DAC International Workshop on System Level-Design of Automotive Electronics/Software (SLDAES),, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A Variation-Aware 0.57-V Set-Associative Cache with Mixed Associativity Using 7T/14T SRAM,

    J. Jung, Y. Nakata, S. Okumura, H Kawaguchi, 吉本 雅彦

    2012年06月, IEEE Faible Tension Faible Consommation (FTFC), 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A 61- dB SNDR 700 um2 Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops

    T. Konishi, K. Okuno, S. Izumi, M. Yoshimoto, H. Kawaguchi

    2012年06月, Symposium on VLSI Circuits, pp. 190 - 191, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • SRAMセルを用いたLow書込みによるチップID生成手法

    奥村俊介, 吉本秀輔, 川口 博, 吉本 雅彦

    2012年04月, 信学技報, vol. 112 (no. 15), pp. 97 - 102, 日本語

    研究論文(学術雑誌)

  • Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto

    As process technology is scaled down, a typical system on a chip (SoC) becomes denser. In scaled process technology, process variation becomes greater and increasingly affects the SoC circuits. Moreover, the process variation strongly affects network-on-chips (NoCs) that have a synchronous network across the chip. Therefore, its network frequency is degraded. We propose a process-variation-adaptive NoC with a variation-adaptive variable-cycle router (VAVCR). The proposed VAVCR can configure its cycle latency adaptively on a processor core basis, corresponding to the process variation. It can increase the network frequency, which is limited by the process variation in a conventional router. Furthermore, we propose a variable-cycle pipeline adaptive routing (VCPAR) method with VAVCR; the proposed VCPAR can reduce packet latency and has tolerance to network congestion. The total execution time reduction of the proposed VAVCR with VCPAR is 15.7%, on average, for five task graphs.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2012年04月, IEICE TRANSACTIONS ON ELECTRONICS, E95C (4), 523 - 533, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper presents a novel disturb mitigation scheme which achieves low-energy operation for a deep sub-micron 8T SRAM macro. The classic write-back scheme with a dedicated read port overcame both half-select and read-disturb problems. Moreover, it improved the yield, particularly in the low-voltage range. The conventional scheme, however, consumed more power because of charging and discharging all write bitlines in a sub-block. Our proposed scheme reduces the power overhead of the write-back scheme using a floating write bitline technique and a low-swing bitline driver (LSBD). The floating bitline and the LSBD respectively consist of a precharge-less CMOS equalizer (transmission gate) and an nMOS write-back driver. The voltage on the floating write bitline is at an intermediate voltage between the ground and the supply voltage before a write cycle. The write target cells are written by normal CMOS drivers, whereas the write bitlines in half-selected columns are driven by the LSBDs in the write cycle, which suppresses the write bitline voltage to VDD - V-tn and therefore saves the active power in the half-selected columns (where V-tn is a threshold voltage of an nMOS). In addition, the proposed scheme reduces a leakage current from the write bitline because of the floating write bitline. The active leakage is reduced by 33% at the FF corner, 125 degrees C. The active energy in the write operation is reduced by 37% at the FF corner. In other process corners, more writing power reduction can be expected because it depends on the V-tn in the LSBD. We fabricated a 512-Kb 8T SRAM test chip that operates at a single 0.5-V supply voltage. The test chip with the proposed scheme respectively achieves 1.52-mu W/MHz writing energy and 72.8-mu W leakage power, which are 59.4% and 26.0% better than those of the conventional write-back scheme. The total energy is 12.9 mu W/MHz (12.9 pJ/access) at a supply voltage of 0.5 V and operating frequency of 6.25 MHz in a 50%-read/50%-write operation.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2012年04月, IEICE TRANSACTIONS ON ELECTRONICS, E95C (4), 572 - 578, 英語

    [査読有り]

    研究論文(学術雑誌)

  • S. Okumura, H. Fujiwara, K. Yamaguchi, S. Yoshimoto, M. Yoshimoto, H. Kawaguchi

    We propose a novel substrate-bias control scheme for an FD-SOI SRAM that suppresses inter-die variability. The proposed circuits detect inter-die threshold-voltage variation automatically, and then maximize read/write margins of memory cells to supply the substrate bias. We confirmed that a 486-kb 61 SRAM operates at 0.42 V, in which an FS corner can be compared as much as 0.14 V or more.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2012年04月, IEICE Trans. Electron., E95C (4), 579 - 585, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy

    Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper proposes a 7T SRAM that realizes a block-level instantaneous comparison feature. The proposed SRAM is useful for operation results comparison in dual modular redundancy (DMR). The data size that can be instantaneously compared is scalable using the proposed structure. The 1-Mb SRAM comprises 16-Kb blocks in which 8-Kb data can be compared in 130.0 ns. The proposed scheme reduces energy consumption in data comparison to 1/418, compared to that of a parallel cyclic redundancy check (CRC) circuit.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2012年03月, IEICE ELECTRONICS EXPRESS, 9 (6), 470 - 476, 英語

    [査読有り]

    研究論文(学術雑誌)

  • 0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme

    Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto

    2012年02月, IPSJ Transactions on System LSI Design Methodology, vol. 5, pp.32-43, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Kosuke Mizuno, Yosuke Terachi, Kenta Takagi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper describes a Histogram of Oriented Gradients (HOG) feature extraction processor for HDTV resolution video (1920 × 1080 pixels). It features a simplified HOG algorithm with cell-based scanning and simultaneous Support Vector Machine (SVM) calculation, cell-based pipeline architecture, and parallelized modules. To evaluate the effectiveness of our approach, the proposed architecture is implemented onto a FPGA prototyping board. Results show that the proposed architecture can generate HOG features and detect objects with 40 MHz for SVGA resolution video (800 × 600 pixels) at 72 frames per second (fps). The proposed schemes are easily expandable to HDTV resolution video at 30 fps with 76.2 MHz if a highresolution camera and higher operating frequency are available. © 2012 IEEE.

    2012年, IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, 197 - 202, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • M. Nakano, T. Konishi, S. Izumi, H. Kawaguchi, M. Yoshimoto

    This report describes a robust method of Instantaneous Heart Rate (IHR) detection from noisy electrocardiogram (ECG) signals. Generally, the IHR is calculated from the interval of R-waves. Then, the R-waves are extracted from the ECG using a threshold. However, in wearable biosignal monitoring systems, various noises (e.g. muscle artifacts from myoelectric signals, electrode motion artifacts) increase incidences of misdetection and false detection because the power consumption and electrode distance of the wearable sensor are limited to reduce its size and weight. To prevent incorrect detection, we use a short-time autocorrelation technique. The proposed method uses similarity of the waveform of the QRS complex. Therefore, it has no threshold calculation Process and it is robust for noisy environment. Simulation results show that the proposed method improves the success rate of IHR detection by up to 37%.

    IEEE, 2012年, 34th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2012, 6703 - 6706, 英語, 国際誌

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Shimpei Soda, Masahide Nakamura, Shinsuke Matsumoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    We have been developing a hands-free voice controller for a home network system (HNS) by using microphone arrays. In our current implementation, however, all human-HNS interactions are performed by voice only. Hence, the interactions tend to be mechanical, dreary and uninformative. To achieve richer interactions, we try to introduce the virtual agent technology as a feedback interface of the HNS. In this paper, we implement the virtual agent as a Web service, by using MMDAgent Toolkit extensively. The agent is then integrated with the HNS and microphone arrays in a service-oriented fashion. Finally, we conduct a user experiment with three versions of virtual agents. In the experiment, we evaluate how the virtual agent can enrich the interactions. © 2012 IEEE.

    IEEE Computer Society, 2012年, Proceedings - Asia-Pacific Software Engineering Conference, APSEC, 1, 342 - 345, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • 読出しビット線リミット機構を備えた40-nm 256-Kb サブ10pJ/access動作8T SRAM

    吉本 秀輔, 寺田 正治, 梅木 洋平, 奥村 俊介, 川澄 篤, 鈴木 利一, 森脇 真一, 宮野 信治, 川口 博, 吉本 雅彦

    2012年, 信学技報, vol. 112 (no. 169), pp. 7 - 12, 日本語

    研究論文(学術雑誌)

  • 低電力ディスターブ緩和技術を備えた40nm 12.9pJ/access 8T SRAM

    吉本 秀輔, 寺田 正治, 奥村 俊介, 鈴木 利一, 宮野 信治, 川口 博, 吉本 雅彦

    2012年, 信学技報, vol. 112 (no. 15), pp. 67 - 72, 日本語

    研究論文(学術雑誌)

  • 低エネルギ比較機能を有するDMR応用7T SRAM

    梅木 洋平, 奥村 俊介, 中田 洋平, 柳田 晃司, 鍵山 祐輝, 吉本 秀輔, 川口 博, 吉本 雅彦

    2012年, 信学技報, vol. 112 (no. 15), pp. 85 - 90, 日本語

    研究論文(学術雑誌)

  • プロセスばらつきを考慮した低電圧動作混合連想度キャッシュ構造

    鄭 晋旭, 中田 洋平, 奥村 俊介, 川口 博, 吉本 雅彦

    2012年, 信学技報, vol. 112 (no. 170), pp. 1 - 6, 日本語

    研究論文(学術雑誌)

  • Takashi Matsuda, Shintaro Izumi, Yasuharu Sakai, Takashi Takeuchi, Hidehiro Fujiwara, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

    One of the most challenging issues in wireless sensor networks is extension of the overall network lifetime. Data aggregation is one promising solution because it reduces the amount of network traffic by eliminating redundant data. In order to aggregate data, each sensor node must temporarily store received data, which requires a specific amount of memory. Most sensor nodes use static random access memory (SRAM) or flash memory for storage. SRAM can be implemented in a one-chip sensor node at low cost; however, SRAM requires standby energy, which consumes a lot of power, especially because the sensor node spends most of its time sleeping, i.e. its radio circuits are quiescent. This study proposes two types of divided SRAM: equal-size divided SRAM and equal-ratio divided SRAM. Simulations show that both proposed SRAM types offer reduced power consumption in various situations.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2012年01月, IEICE TRANSACTIONS ON COMMUNICATIONS, E95B (1), 178 - 188, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Bit Error Rate Estimation in SRAM Considering Temperature Fluctuation

    Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, Shusuke Yoshimoto, Yohei Nakata, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    SRAM performance varies depending on the operating environment. This study specifically examines the bit error rate (BER) when considering temperature fluctuation. The SRAM performance is generally determined using a read margin because a half-select issue must be considered even in a write operation. As a metric of the SRAM's performance, we also adopt a static noise margin (SNM) with which we evaluate three methods to estimate the BER considering temperature fluctuation. Method 1 iterates calculations for the SNM many times with Monte Carlo simulation. BER is defined as the number of cells that have no margin. Method 2 includes the assumption that SNM forms a normal distribution. Its BER is defined as a probability distribution function. Method 3 includes the assumption that SNM is determined as either square but not the smaller one of the two squares. The BER estimations are compared with a test chip result implemented in a 65-nm CMOS technology: Method 2 has 11.10% and Method 3 has 4.09% difference (unfortunately, Method 1 has no data missing because of a lack of simulations). The shift of the minimum operating voltage between the low and high temperatures is 0.04 V at a 128-Kb capacity when the temperature fluctuates from 25 degrees C to 100 degrees C.

    IEEE, 2012年, 2012 13TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), pp. 514-517, 516 - 519, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A 40-nm 256-Kb 0.6-V Operation Half-Select Resilient 8T SRAM with Sequential Writing Technique Enabling 367-mV VDDmin Reduction

    M. Terada, S. Yoshimoto, S. Okumura, T. Suzuki, S. Miyano, H. Kawaguchi, M. Yoshimoto

    This paper introduces a novel half-select resilient dual write wordline 8T (DW8T) SRAM with a sequential writing technique. The process scaling increases random variation that degrades SRAM operating margins, for which the proposed DW8T cell presents two features: half-VDD precharging write bitlines and dual write wordlines. The dual write wordlines are sequentially activated in a write cycle, and its combination with the half-VDD precharge suppresses the half-select problem. The DW8T SRAM with the sequential writing technique improve a half-select bit error rate by 71% at the disturb worst corner (FS, 125 degrees C) and by 79% at a typical corner (CC, 25 degrees C) over the conventional 8T, respectively. We implemented a 256-Kb DW8T SRAM and a half-VDD generator on a single chip in a 40-nm CMOS process. The measurement results of the seven samples show that the proposed DW8T SRAM achieves a VDDmin of 600 mV and improves the average VDDmin by 367 mV compared to the conventional 8T SRAM. The measured leakage power can be reduced by 25%.

    IEEE, 2012年, 2012 13TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), pp. 487-490, 489 - 492, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • NMOS-Inside 6T SRAM Layout Reducing Neutron-Induced Multiple Cell Upsets

    Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper presents a novel NMOS-inside 6T SRAM cell layout that reduces a neutron-induced MCU SER on a same wordline. We implemented a 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER The proposed 6T SRAM macro improves the horizontal MCU SER by 67-98% compared with a general macro that has PMOS-inside 6T SRAM cells.

    IEEE, 2012年, 2012 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), pp. 5B.5.1 - 5, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A 51-dB SNDR DCO-Based TDC Using Two-Stage Second-Order Noise Shaping

    Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi

    This paper presents a two-stage second-order noise shaping time-to-digital converter (TDC) using a one-bit digitally-controlled oscillator (DCO). The clocks output from DCOs are counted and digitized as in a conventional gated ring oscillator (GRO) TDC. A time error is propagated to the second DCO, which provides second-order noise shaping. In the conventional GROTDC, internal oscillators must maintain their phase state. However, because of the leak current, the stored phase states are degraded or even lost. In our proposed architecture, the DCOs always oscillate and need not maintain their phase state. Therefore, our proposed TDC is more suitable in leaky recent process than a GROTDC is. Because no switched capacitor or opamp is used, the proposed TDC can be implemented in a small area and with low power. Mismatches in the oscillation frequency between the DCOs might occur. However, error detection and correction can be performed using a first-order least mean square (LMS) filter. In a standard 65-nm CMOS process, an SNDR of 51 dB is achievable at an input bandwidth of 3 MHz and a sampling rate of 65 MHz, where the power is 271 mu W.

    IEEE, 2012年, 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), pp. 3170 - 3173, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Neutron-Induced Soft Error Rate Estimation for SRAM Using PHITS

    Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper presents a novel neutron-induced soft-error-rate (SER) estimation tool with a particle transport code: PHITS. The proposed tool can calculate the SER according to various data patterns and the layout of the memory cells in an SRAM. As layouts, two kinds of an NMOS-PMOS-NMOS 6T and an inside-out PMOS-NMOS-PMOS versions are considered. The proposed tool distinguishes a single-event-upset (SEU) SER, a horizontal multiple-cell-upset (MCU) SER, and a vertical MCU SER using an extracting function. The horizontal MCU SER in the inside-out version of the PMOS-NMOS-PMOS 6T SRAM cell layout was expected to be 26-41% less than that of the general NMOS-PMOS-NMOS 6T cell layout.

    IEEE, 2012年, 2012 IEEE 18TH INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), 138 - 141, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A 62-dB SNDR Second-Order Gated Ring Oscillator TDC with Two-Stage Dynamic D-Type Flipflops as A Quantization Noise Propagator

    Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi

    This paper presents a second-order noise shaping time-to-digital converter (TDC) with two gated ring oscillators (GROs). The oscillating outputs from the GROs are counted and digitized. As a quantization noise propagator (QNP) between the two GROs, two-stage dynamic d-type flipflops (DDFFs) and a NOR gate are adopted. The proposed QNP does not propagate a time error caused by flipflop's metastability to the next GRO, and thus improves its linearity over the conventional masterslave d-type flipflop. In a standard 65-nm CMOS process, an SNDR of 62-dB is achievable at a sampling rate of 65MS/s.

    IEEE, 2012年, 2012 IEEE 10TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), IEEE International New Circuit, 289 - 292, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • S. Yoshimoto, M. Terada, S. Okumura, T. Suzuki, S. Miyano, H. Kawaguchi, M. Yoshimoto

    This paper introduces a novel half-select resilient dual write wordline 8T (DW8T) SRAM with a sequential writing technique. The dual write wordlines are sequentially activated in a write cycle, and its combination with the half-VDD precharge suppresses the half-select problem. We implemented a 256-Kb DW8T SRAM and a half-VDD generator with a 40-nm CMOS process. The measurement results of the seven samples show that the proposed DW8T SRAM achieves a VDDmin of 600mV and improves the average VDDmin by 367mV compared to the conventional 8T SRAM. The measured leakage power can be reduced by 25%.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2012年, IEICE ELECTRONICS EXPRESS, 9 (12), 1023 - 1029, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper presents a novel read-bitline amplitude limiting (RBAL) scheme which suppresses dynamic energy dissipation caused by random variation. In addition, a discharge acceleration (DA) circuit is proposed to decrease delay overhead of RBAL. The proposed scheme improves the active energy dissipation in a read cycle by 22% at the center-center (CC) corner and 25°C. The maximum delay overhead is 32% at the fast-slow (FS) corner and -40°C. The circuits have been implemented using the 40-nm bulk CMOS process. The implemented 256-Kb 8T SRAM works fine with energy dissipation of sub-10 pJ / access from 0.5-0.7 V. © 2012 ACM.

    2012年, Proceedings of the International Symposium on Low Power Electronics and Design, 85 - 90, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A 40-nm 168-mW 2.4x-Real-Time VLSI Processor for 60-kWord Continuous Speech Recognition

    Guangji He, Takanobu Sugahara, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). Our implementation includes a compression-decoding scheme to reduce the external memory bandwidth for Gaussian Mixture Model (GMM) computation and multi-path Viterbi transition units. We optimize the internal SRAM size using the max-approximation GMM calculation and adjusting the number of look-ahead frames. The test chip, fabricated in 40 nm CMOS technology, occupies 1.77 mm x 2.18 mm containing 2.52 M transistors for logic and 4.29 Mbit on-chip memory. The measured results show that our implementation achieves 34.2% required frequency reduction (83.3 MHz) and reduces 48.5% power consumption (74.14 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 2.4x faster than real-time at 200 MHz and 1.1 V with power consumption of 168 mW.

    IEEE, 2012年, 2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), vol. 59 (no. 8), pp.1656 - 1666, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Kosuke Mizuno, Yosuke Terachi, Kenta Takagi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper describes a Histogram of Oriented Gradients (HOG) feature extraction processor for HDTV resolution video (1920 x 1080 pixels). It features a simplified HOG algorithm with cell-based scanning and simultaneous Support Vector Machine (SVM) calculation, cell-based pipeline architecture, and parallelized modules. To evaluate the effectiveness of our approach, the proposed architecture is implemented onto a FPGA prototyping board. Results show that the proposed architecture can generate HOG features and detect objects with 40 MHz for SVGA resolution video (800 x 600 pixels) at 72 frames per second (fps). The proposed schemes are easily expandable to HDTV resolution video at 30 fps with 76.2 MHz if a high-resolution camera and higher operating frequency are available.

    IEEE, 2012年, 2012 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), 197 - 202, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A 40-nm 168-mW 2.4×-Real-Time VLSI Processor for 60-kWord Continuous Speech Recognition

    G. He, T. Sugahara, Y. Miyamoto, S. Izumi, H. Kawaguchi, M. Yoshimoto

    This paper describes a low-power VLSI chip for speaker-independent 60-kWord continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). Our implementation includes a compression-decoding scheme to reduce the external memory bandwidth for Gaussian Mixture Model (GMM) computation and multi-path Viterbi transition units. We optimize the internal SRAM size using the max-approximation GMM calculation and adjusting the number of look-ahead frames. The test chip, fabricated in 40 nm CMOS technology, occupies 1.77 mm x 2.18 mm containing 2.52 M transistors for logic and 4.29 Mbit on-chip memory. The measured results show that our implementation achieves 34.2% required frequency reduction (83.3 MHz) and reduces 48.5% power consumption (74.14 mW) for 60 k-Word real-time continuous speech recognition compared to the previous work. This chip can maximally process 2.4x faster than real-time at 200 MHz and 1.1 V with power consumption of 168 mW.

    IEEE, 2012年, IEEE Custom Integrated Circuits Conference(CICC), pp.1 - 4, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Shimpei Soda, Masahide Nakamura, Shinsuke Matsumoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    The voice control is a promising user interface for the home network system (HNS). In our previous interface, a user had to be equipped with an actual microphone device, which imposed a burden on the user. This paper presents a hands-free voice interface using a microphone array network. The microphone array network enables voice quality enhancement, as well as sound source localization, by networking multiple microphone arrays. Attaching the arrays to the walls or ceiling, users can input voice operations to the HNS from anywhere in the room, without being aware of the microphone devices. We implement a prototype system with a 16ch microphone array, and evaluate the speech recognition rate and the accuracy of sound source localization in a real home network environment. A hands-free operation service and an automatic speech logging service are implemented.

    IEEE, 2012年, 2012 THIRD INTERNATIONAL CONFERENCE ON NETWORKING AND COMPUTING (ICNC 2012), 195 - 200, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • チップ間ばらつき及びチップ内ばらつきを抑制する基板バイアス制御回路を備えた0.42-V 576-Kb 0.15-um FD-SOI 7T/14T SRAM

    吉本 秀輔, 山口 幸介, 奥村 俊介, 吉本 雅彦, 川口 博

    2011年12月, 信学技報, vol. 111, no. 352, ICD2011-133, 日本語

    研究論文(学術雑誌)

  • Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Takashi Takeuchi, Masahiko Yoshimoto, Hiroshi Kawaguchi

    We propose a transfer gate phase coupler for a low-power multi-phase oscillator (MPOSC). The phase coupler is an nMOS transfer gate, which does not waste charge to the ground and thus achieves low power. The proposed MPOSC can set the number of outputs to an arbitrary number. The test circuit in a 180-nm process and a 65-nm process exhibits 20 phases, including 90 degrees different angles. The designs in a 180-nm CMOS process and a 65-nm CMOS process were fabricated to confirm its process scalability; in the respective designs, we observed 36.6% and 38.3% improvements in a power-delay products, compared with the conventional MPOSCs using inverters and nMOS latches. In a 65-nm process, the measured DNL and 3 sigma period jitter are, respectively, less than +/- 1.22 degrees and 5.82 ps. The power is 284 mu W at 1.85 GHz.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2011年12月, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E94A (12), 2701 - 2708, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Shunsuke Okumura, Yuki Kagiyama, Yohei Nakata, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper proposes 7T SRAM which realizes block-level simultaneous copying feature. The proposed SRAM can be used for data transfer between local memories such as checkpoint data storage and transactional memory. The 1-Mb SRAM is comprised of 32-kb blocks, in which 16-kb data can be copied in 33.3 ns at 1.2 V. The proposed scheme reduces energy consumption in copying by 92.7% compared to the conventional read-modify-write manner. By applying the proposed scheme to transactional memory, the number of write back cycles is possibly reduced by 98.7% compared with the conventional memory system.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2011年12月, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E94A (12), 2693 - 2700, 英語

    [査読有り]

    研究論文(学術雑誌)

  • 256-KB Associativity-Reconfigurable Cache with 7T/14T SRAM for Aggressive DVS Down to 0.57 V

    Jung Jin-Wook, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto

    2011年12月, Proceedings of 18th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 524-527, 英語

    [査読有り]

    研究論文(学術雑誌)

  • 6万語彙実時間連続音声認識のための40nm,144mW音声認識専用プロセッサの開発 (集積回路)

    菅原 隆伸, 何 光霽, 藤永 剛史, 宮本 優貴, 野口 紘希, 和泉 慎太郎, 川口 博, 吉本 雅彦

    本研究では,6万語彙の実時間連続音声認識の実現を目指すために新たなアーキテクチャを設計した.提案アーキテクチャでは,音声認識に特化したキャッシュ,言語モデルの粗密探索,閾値カットの導入,GMM演算とViterbi演算の2ステージパイプラインの導入,GMM演算の50先読み・高並列化を行った.その結果,必要メモリ帯域を97.94%削減し,70.86MB/sの低メモリ帯域を達成することが出来た.また,必要動作周波数を78%削減し126.5MHzで6万語彙実時間音声認識を行うことが出来た.尚,今回の試作では,40nmCMOSプロセスで試作を行い,ロジック部分が1.9Mトランジスタ,内部メモリが7.8Mbitとなっている.この試作チップを測定した結果,126.5MHz,1.1Vの条件下で144mWもの低消費電力で動作することが分かった.

    一般社団法人電子情報通信学会, 2011年11月28日, 電子情報通信学会技術研究報告 : 信学技報, 111 (327), 79 - 84, 日本語

    [査読有り]

    研究論文(学術雑誌)

  • Toshihiro Konishi, Shintaro Izumi, Koh Tsuruda, Hyeokjong Lee, Takashi Takeuchi, Masahiko Yoshimoto, Hiroshi Kawaguchi

    Concomitantly with the progress of wireless communications, cognitive radio has attracted attention as a solution for depleted frequency bands. Cognitive radio is suitable for wireless sensor networks because it reduces collisions and thereby achieves energy-efficient communication. To make cognitive radio practical, we propose a low-power multi-resolution spectrum sensing (MRSS) architecture that has flexibility in sensing frequency bands. The conventional MRSS scheme consumes much power and can be adapted only slightly to process scaling because it comprises analog circuits. In contrast, the proposed architecture carries out signal processing in a digital domain and can detect occupied frequency bands at multiple resolutions and with low power. Our digital MRSS module can be implemented in 180-nm and 65-nm CMOS processes using Verilog-HDL. We confirmed that the processes respectively dissipate 9.97 mW and 3.45 mW

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2011年11月, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E94A (11), 2287 - 2294, 英語

    [査読有り]

    研究論文(学術雑誌)

  • A 128-bit Chip Identification Generating Scheme Exploiting SRAM Bitcells with Failure Rate of 4.45 � 10-19

    Shunsuke Okumura, Syusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto

    2011年09月, Proceedings of IEEE European Solid-State Circuits Research Conference (ESSCIRC), pp. 527-530, 英語

    [査読有り]

    研究論文(学術雑誌)

  • A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Router

    Yohei Nakata, Yusuke Takeuchi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    2011年08月, 14th Euromicro Conference on Digital System Design (DSD), pp. 801-804, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Model-Based Fault Injection for Failure Effect Analysis -Evaluation of Dependable SRAM for Vehicle Control Units-

    Yohei Nakata, Yasuhiro Ito, Yasuo Sugure, Shigeru Oho, Yusuke Takeuchi, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto

    2011年06月, 5th Workshop on Dependable and Secure Nanocomputing (WDSN), in conjunction with the 41st International Conference on Dependable Systems and Networks (DSN), pp. 91-96, 英語

    [査読有り]

    研究論文(学術雑誌)

  • A 40-nm 0.5-V 20.1-uW/MHz 8T SRAM with Low-Energy Disturb Mitigation Scheme,

    Syusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto

    2011年06月, Digest of Technical Papers 2011 Symposium on VLSI Circuits, pp. 72-73, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Positioning System for Mobile Terminals Using a Microphone Array Network as an Intuitive Interface

    Shimpei Soda, Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Shintaro Izumi, Masahiko YOSHIMOTO, Hiroshi KAWAGUCHI

    2011年05月, The Third Joint Workshop on Hands-free Speech Communication and Microphone Arrays(HSCMA), 英語

    [査読有り]

    研究論文(学術雑誌)

  • Hiroki Noguchi, Kazuo Miura, Tsuyoshi Fujinaga, Takanobu Sugahara, Hiroshi Kawaguchi, Masahiko Yoshimoto

    We propose a low-memory-bandwidth, high-efficiency VLSI architecture for 60-k word real-time continuous speech recognition. Our architecture includes a cache architecture using the locality of speech recognition, beam pruning using a dynamic threshold, two-stage language model searching, a parallel Gaussian Mixture Model (GMM) architecture based on the mixture level and frame level, a parallel Viterbi architecture, and pipeline operation between Viterbi transition and GMM processing. Results show that our architecture achieves 88.24% required frequency reduction (66.74 MHz) and 84.04% memory bandwidth reduction (549.91 MB/s) for real-time 60-k word continuous speech recognition.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2011年04月, IEICE TRANSACTIONS ON ELECTRONICS, E94C (4), 458 - 467, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Tsuyoshi Fujinaga, Shintaro Izumi, Yasuo Ariki, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper describes a SIFT (Scale Invariant Feature Transform) descriptor generation engine which features a VLSI oriented SIFT algorithm, three-stage pipelined architecture and novel systolic array architectures for Gaussian filtering and key-point extraction. The ROI-based scheme has been employed for the VLSI oriented algorithm. The novel systolic array architecture drastically reduces the number of operation cycle and memory access. The cycle counts of Gaussian filtering module is reduced by 82%, compared with the SIMD architecture. The number of memory accesses of the Gaussian filtering module and the key-point extraction module are reduced by 99.8% and 66% respectively, compared with the results obtained assuming the SIMD architecture. The proposed schemes provide processing capability for HDTV resolution video (1920 x 1080 pixels) at 30 frames per second (fps). The test chip has been fabricated in 65 nm CMOS technology and occupies 4.2 x 4.2 mm(2) containing 1.1M gates and 1.38 Mbit on-chip memory. The measured data demonstrates 38.2 mW power consumption at 78 MHz and 1.2 V.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2011年04月, IEICE TRANSACTIONS ON ELECTRONICS, E94C (4), 448 - 457, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Data-Intensive Sound Acquisition System with Large-Scale Microphone Array,

    H. Noguchi, T. Takagi, K. Kugata, S. Izumi, M. Yoshimoto, H. Kawaguch

    2011年03月, Journal of Information Processing Society of Japan (IPSJ), vol. 19, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi

    This paper presents a second-order ΔΣ analog to digital converter (ADC) operating in a time domain. In the proposed ADC architecture, a voltage-controlled delay unit (VCDU) converts an input analog voltage to a delay time. Then the number of clocks output from a gated ring oscillator (GRO) is counted up during the delay time. Because no switched capacitor or opamp is used, the proposed ADC can be implemented in a small area and at low power. For the same reason, it has process scalability: it can be in keeping with Moore's law. A time error is propagated to the second GRO by a multi-stage noise-shaping (MASH) topology, which provides second-order noise-shaping. In a standard 40-nm CMOS process, a SNDR of 45 dB is achievable at an input bandwidth of 3 MHz and a sampling rate of 100 MHz, where the power is 583.2 μW. Its area is 640 μm2. © 2011 IEEE.

    2011年, Proceedings - IEEE International Symposium on Circuits and Systems, 518 - 521, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • 0.42-V 576-kb 0.15-um FD-SOI SRAM with 7T/14T Bit Cells and Substrate Bias Control Circuits for Intra-Die and Inter-Die Variability Compensation

    K. Yamaguchi, S. Okumura, M. Yoshimoto, H. Kawaguchi

    2011年01月, Proceedings of 7th Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EUROSOI), pp. 37-38, 英語

    [査読有り]

    研究論文(学術雑誌)

  • 0.45-V Operating V-t-Variation Tolerant 9T/18T Dual-Port SRAM

    Hiroki Noguchi, Shunsuke Okumura, Tomoya Takagi, Koji Kugata, Masahiko Yoshimoto, Hiroshi Kawaguchi

    This paper proposes a dependable dual-port SRAM with 9T/18T bitcell structure. The proposed SRAM has two operating modes: a 9T normal mode and an 18T dependable mode. The 9T bitcell has an outside single-ended bitline as a dedicated read port along with a pair of conventional differential inside bitlines. Therefore, the 18T bitcell has two differential pairs of the outside bitlines and inside bitlines. For the dedicated read port, the 18T bitcell can exploit a differential sense amplifier operating at low voltage, but the 9T bitcell must have a single-ended readout inverter at high voltage. To achieve the 9T/18T SRAM architecture, an interleaved bitline scheme is incorporated for the dedicated read port. The 9T/18T dual-port SRAM can scale its speed, operating voltage, and power dynamically by combining two bitcells for one-bit information. We designed and fabricated the proposed SRAM using a 65-nm process. The measurement results show that the dependable read mode using the pair of the single-ended bitlines can reduce the operation voltage to 0.45 V at a frequency of 1 MHz because of the disturb-free read port, although the dependable read mode using the inside bitlines needs 0.54 V at the same frequency.

    IEEE, 2011年, 2011 12TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), pp. 219-222, 225 - 228, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Bit Error and Soft Error Hardenable 7T/14T SRAM with 150-nm FD-SOI Process

    Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Kosuke Yamaguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi

    This paper presents measurement results of bit error rate (BER) and soft error rate (SER) improvement on 150-nm FD-SOI 7T/14T (7-transistor / 14-transistor) SRAM test chips. The reliability of the 7T/14T SRAM can be dynamically changed by a control signal depending on an operating condition and application. The 14T dependable mode allocates one bit in a 14T cell and improves the BER in a read operation and SER in a retention state, simultaneously. We investigate its error rate mitigating mechanisms using Synopsys TCAD simulator. In our measurements, the minimum operating voltage was improved by 100 mV, the alpha-induced SER was suppressed by 80.0%, and the neutron-induced SER was decreased by 34.4% in the 14T dependable mode over the 7T normal mode.

    IEEE, 2011年, 2011 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), pp. 876-881, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A 40-nm 640-μm2 45-dB Opampless All-Digital Second-Order MASH ΔΣ ADC

    Toshihiro Konish, Hyeokjong Lee, Shintaro Izumi, Masahiko YOSHIMOTO, Hiroshi KAWAGUCHI

    This paper presents a second-order Delta Sigma analog to digital converter (ADC) operating in a time domain. In the proposed ADC architecture, a voltage-controlled delay unit (VCDU) converts an input analog voltage to a delay time. Then the number of clocks output from a gated ring oscillator (GRO) is counted up during the delay time. Because no switched capacitor or opamp is used, the proposed ADC can be implemented in a small area and at low power. For the same reason, it has process scalability: it can be in keeping with Moore's law. A time error is propagated to the second GRO by a multi-stage noise-shaping (MASH) topology, which provides second-order noise-shaping. In a standard 40-nm CMOS process, a SNDR of 45 dB is achievable at an input bandwidth of 3 MHz and a sampling rate of 100 MHz, where the power is 583.2 mu W. Its area is 640 mu m(2).

    IEEE, 2011年, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 518-521, 518 - 521, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure

    S. Yoshimoto, T. Amashita, D. Kozuwa, T. Takata, M. Yoshimura, Y. Matsunaga, H. Yasuura, H. Kawaguchi, M. Yoshimoto

    This paper presents a new 8T (8-transistor) SRAM cell layout mitigating multiple-bit upset (MBU) in a divided wordline structure. Because bitlines along unselected columns are not activated, the divided wordline structure eliminates a half-select problem and achieves low-power operation, which is often preferred for low-power / low-voltage applications. However, the conventional 8T SRAM with the divided wordline structure engenders MBUs because all bits in the same word are physically adjoining. Consequently, error correction coding (ECC) techniques are difficult to apply. This paper presents a new 8T cell layout pattern that separates internal latches in SRAM cells using both an n-well and a p-substrate. We investigated an SEU cross section of nMOS that is 3.5-4.5 times higher than that of pMOS. Using an iRoC TFIT simulator, we confirmed that the proposed 8T cell has better neutron-induced MBU tolerance. The MBU in the proposed 8T SRAM is improved by 90.70% and the MBU soft error rate (SER) is decreased to 3.46 FIT at 0.9 V when ECC is implemented. Additionally, we conducted Synopsys 3-D TCAD simulation, which indicates that the LET threshold (LETth) in single-event upset (SEU) is also improved by 66.47% in the proposed 8T SRAM by a common-mode effect.

    IEEE COMPUTER SOC, 2011年, 2011 IEEE 17TH INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), pp.151-156, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Data Aggregation Protocol for Multiple Sound Sources Acquisition with Microphone Array Network

    Shintaro Izumi, Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shimpei Soda, Masahiko Yoshimoto, Hiroshi Kawaguchi

    In this paper, we propose a microphone array network that realizes ubiquitous sound acquisition for multiple sound sources. Several nodes with 16 microphones are connected to form a huge sound acquisition system, which carries out voice activity detection (VAD), sound source localization, and enhancement. The three operations are distributed among nodes with multi-hop data communication. Using the distributed network, we produce a low-traffic data-intensive array network. In the sound-source enhancement, we combine the delay-and-sum beam-forming algorithm with network data aggregation. The prototype of microphone array node is implemented in SUZAKU FPGA boards, which demonstrates a real-time multiple-sound-source enhancement operation.

    IEEE, 2011年, 2011 20TH INTERNATIONAL CONFERENCE ON COMPUTER COMMUNICATIONS AND NETWORKS (ICCCN), 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Low-Power Block-Level Instantaneous Comparison 7T SRAM for Dual Modular Redundancy

    Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper proposes a 7T SRAM that realizes a block-level instantaneous comparison feature. The proposed SRAM is useful for operation results comparison in dual modular redundancy (DMR). The data size that can be instantaneously compared is scalable using the proposed structure. The 1-Mb SRAM comprises 16-kb blocks in which 8-kb data can be compared in 130.0ns. The proposed scheme reduces power consumption in data comparison by 92.3%, compared to that of a parallel cyclic redundancy check (CRC) circuit.

    IEEE, 2011年, 2011 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), pp. 1-4, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Masanori Nishino, Hiroki Noguchi, Yusuke Shimai, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper describes a low-power eight-core Mixed Integer Quadric Programming (MIQP) solver processor VLSI for real-time autonomous robot control. It features an eight-core architecture with operation-level and task-level parallel processing using speculative execution to solve a 75-variable MIQP problem within 100 ms. The VLSI, containing 12.2 M transistors and occupying 2.7 × 3.0 mm 2 area, was designed and fabricated using 40-nm CMOS technology. It consumes 568 mW with 135 MHz operation, allowing real-time, low-power capability for a 75-variable MIQP solver. © 2011 IEEE.

    2011年, 2011 IEEE/SICE International Symposium on System Integration, SII 2011, pp. 469-472, 469 - 472, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure

    S. Yoshimoto, T. Amashita, D. Kozuwa, T. Takata, M. Yoshimura, Y. Matsunaga, H. Yasuura, H. Kawaguchi, M. Yoshimoto

    This paper presents a new 8T (8-transistor) SRAM cell layout mitigating multiple-bit upset (MBU) in a divided wordline structure. Because bitlines along unselected columns are not activated, the divided wordline structure eliminates a half-select problem and achieves low-power operation, which is often preferred for low-power / low-voltage applications. However, the conventional 8T SRAM with the divided wordline structure engenders MBUs because all bits in the same word are physically adjoining. Consequently, error correction coding (ECC) techniques are difficult to apply. This paper presents a new 8T cell layout pattern that separates internal latches in SRAM cells using both an n-well and a p-substrate. We investigated an SEU cross section of nMOS that is 3.5-4.5 times higher than that of pMOS. Using an iRoC TFIT simulator, we confirmed that the proposed 8T cell has better neutron-induced MBU tolerance. The MBU in the proposed 8T SRAM is improved by 90.70% and the MBU soft error rate (SER) is decreased to 3.46 FIT at 0.9 V when ECC is implemented. Additionally, we conducted Synopsys 3-D TCAD simulation, which indicates that the LET threshold (LETth) in single-event upset (SEU) is also improved by 66.47% in the proposed 8T SRAM by a common-mode effect.

    IEEE COMPUTER SOC, 2011年, 2011 IEEE 17TH INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), Vol. E95-C (No. 10,), pp. 1675 - 1681, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • システムレベル故障注入技術を用いたディペ ンダブルプロセッサアーキテクチャの評価・ 検証

    中田 洋平, 伊藤 康宏, 勝 康夫, 於保 茂, 川口 博, 吉本 雅彦

    2010年11月, 電子情報通信学会技術研究報告, vol. 110, no. 317, VLD2010-74,, 日本語

    研究論文(学術雑誌)

  • The Area Criteria of 6T and 8T SRAM Cells,

    S. Yoshimoto, S. Okumura, H. Kawaguchi, M. Yoshimoto

    2010年11月, EEE/ACM Workshop on Variability Modeling and Characterization (VMC), p.4, 英語

    研究論文(学術雑誌)

  • ブロック一括コピー機能を有する7T SRAM

    奥村 俊介, 鍵山 祐輝, 吉本 秀輔, 山口 幸介, 中田 洋平, 川口 博, 吉本 雅彦

    2010年10月, 電子情報通信学会CEATEC JAPAN 2010 連携企画研究報告 (Digital Harmony を支えるプロ セッサとDSP,画像処理の最先 端), pp.49-54 (2010), 日本語

    研究論文(学術雑誌)

  • ネットワーク型マイクロホンアレイ間のデー タ集約による音声信号ビームフォーミング

    和泉 慎太郎, 野口 紘希, 高木 智也, 久賀田 耕史, 祖田 心平, 吉本 雅彦, 川口 博

    2010年10月, 電子情報通信学会CEATEC JAPAN 2010 連携企画研究報告 (Digital Harmony を支えるプロ セッサとDSP、画像処理の最先 端), pp.95-100 (2010), 日本語

    研究論文(学術雑誌)

  • A power-variation model fo r sensor node and the impact against life time of wireless sensor networks

    Takashi Matsuda, Takashi Takeuchi, Takefumi Aonishi, Masumi Ichien, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

    2010年03月, IEICE Electron. Express, Vol. 7, No. 3, pp.197-202, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Shintaro Izumi, Takashi Takeuchi, Takashi Matsuda, Hyeokjong Lee, Toshihiro Konishi, Koh Tsuruda, Yasuharu Sakai, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

    This paper presents an ultra-low-power single-chip sensor-node VLSI for wireless-sensor-network applications A communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system. through a vertical cooperative design among circuits. architecture, and communication protocols The sensor-node LSI features a synchronous media access control (MAC) protocol and integrates a transceiver. 18051 microcontroller. and dedicated MAC processor The test chip occupies 3 x 3 mm(2) in a 180-nm CMOS process. including 1 38 M transistors It dissipates 58 0 mu W under a network environment

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2010年03月, IEICE TRANSACTIONS ON ELECTRONICS, E93C (3), 261 - 269, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Design Choice in 45-nm Dual-Port SRAM – 8T, 10T Single End, and 10T Differential –

    H. Noguchi, Y. Iguchi, H. Fujiwara, S. Okumura, K. Nii, H. Kawaguchi, M. Yoshimoto

    2010年02月, IPSJ Transactions on System LSI Design Methodology, vol. 4, pp. 80-90, 英語

    [査読有り]

    研究論文(学術雑誌)

  • A 284-mu W 1.85-GHz 20-Phase Oscillator Using Transfer Gate Phase Couplers

    Hyeokjong Lee, Takashi Takeuchi, Masahiko Yoshimoto, Hiroshi Kawaguchi

    We propose a transfer gate phase coupler for a low-power multi-phase oscillator (MPOSC). The phase coupler is an nMOS transfer gate, which does not waste charge to the ground and thus achieves low power. The proposed MPOSC can set the number of outputs to an arbitrary number. The test circuit in a 180-nm process and a 65-nm process exhibits 20 phases, including 90 different angles. In a 65-nm process, the measured peak DNL and 3 sigma period jitter are, respectively, less than +/- 1.2 degrees and 5.82 ps. The minimum I/Q angle error is 0.019 degrees. The power is 284 mu W at 1.85 GHz.

    IEEE, 2010年, 2010 ASIA-PACIFIC MICROWAVE CONFERENCE, 594 - 597, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Intelligent Ubiquitous Sensor Network for Sound Acquisition

    Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi

    We propose a microphone array network that realizes ubiquitous sound acquisition. Nodes with 16 microphones are connected to form a large sound acquisition system that carries out voice activity detection (VAD), sound source localization and sound source separation. The three operations are distributed among nodes using network. Because the VAD is implemented to manage power consumption, the system consumes little power when speech is not active. The power of the VAD module is only 2.1 mW on an FPGA. The system can improve an SNR by 7.75 dB using 112 microphones.

    IEEE, 2010年, 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 1414 - 1417, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • MICROPHONE ARRAY NETWORK FOR UBIQUITOUS SOUND ACQUISITION

    Tomoya Takagi, Hiroki Noguchi, Koji Kugata, Masahiko Yoshimoto, Hiroshi Kawaguchi

    We propose a microphone array network that realizes ubiquitous sound acquisition. Nodes with 16 microphones are connected to form a huge sound acquisition system that carries out VAD, sound source localization and separation. The three operations are distributed among nodes. The VAD is implemented to manage power consumption. Consequently, the system consumes little power when speech is not active. The VAD module uses only 2.1 mW. The system can improve an SNR by 7.75 dB using 112 microphones.

    IEEE, 2010年, 2010 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, pp. 1474-1477, 1474 - 1477, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Live Demonstration: Intelligent Ubiquitous Sensor Network for Sound Acquisition

    Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi

    We propose a microphone array network that realizes ubiquitous sound acquisition. Nodes with 16 microphones are connected to form a large sound acquisition system that carries out voice activity detection (VAD), sound source localization and sound source separation. The three operations are distributed among nodes using network. Because the VAD is implemented to manage power consumption, the system consumes little power when speech is not active. The power of the VAD module is only 2.1 mW on an FPGA. The system can improve an SNR by 7.75 dB using 112 microphones.

    IEEE, 2010年, 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, p. 1413, 1413 - 1413, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Live Demonstration: Intelligent Ubiquitous Sensor Network for Sound Acquisition

    Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi

    We propose a microphone array network that realizes ubiquitous sound acquisition. Nodes with 16 microphones are connected to form a large sound acquisition system that carries out voice activity detection (VAD), sound source localization and sound source separation. The three operations are distributed among nodes using network. Because the VAD is implemented to manage power consumption, the system consumes little power when speech is not active. The power of the VAD module is only 2.1 mW on an FPGA. The system can improve an SNR by 7.75 dB using 112 microphones.

    IEEE, 2010年, 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, pp. 1414-1417, 1413 - 1413, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Takashi Takeuchi, Shinji Mikami, Hyeokjong Lee, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

    In this paper we propose a novel functional amplifier suitable for low-power wireless receivers in a wireless sensor network. This amplifier can change input threshold level as carrier sensing level, since it has a minimum input amplitude to be amplified. A simple rail-to-rail output is suitable for a subsequent digital interface. The target frequency is 433 MHz, and the maximum voltage gain is 11 dB. The standby power is 39.5 nW, and the active power is 352 mu W. The chip area is 82 x 24 mu m(2).

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2009年06月, IEICE TRANSACTIONS ON ELECTRONICS, E92C (6), 815 - 821, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper proposes a novel dependable SRAM with 7T/14T memory cells, and introduces a new concept, "quality of a bit (QoB)" for it. The proposed SRAM has three modes: a normal mode, highspeed mode, and dependable mode, and dynamically scales its reliability, power and speed by combining two memory cells for one-bit information (i.e. 14T/bit). By carrying out Monte Carlo simulation in a 65-nm process technology, the minimum voltages in read and write operations are improved by 0.21 V and 0.26 V, respectively, with a bit error rate of 10(-8) kept. In addition, we confirm that the dependable mode achieves a lower bit error rate than the error correction code (ECC) and multi module redundancy (MMR). Furthermore, we propose a new memory array structure to avoid the half-selection problem in a write operation. The respective cell area overheads in the normal mode are 26% and 11% in the cases where additional transistors are pMOSes and nMOSes, compared to the conventional 6T memory cell.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2009年04月, IEICE TRANSACTIONS ON ELECTRONICS, E92C (4), 423 - 432, 英語

    [査読有り]

    研究論文(学術雑誌)

  • 低消費電力センサノードVLSIのための時刻同期型MACプロトコルの研究

    和泉慎太郎, 松田隆志, 竹内 隆, 川口 博, 太田 能, 吉本雅彦

    2009年03月, 電子情報通信学会技術研究報告(信学技報), vol. 108, no. 457, NS2008-174,, 日本語

    研究論文(国際会議プロシーディングス)

  • 7T/14TディペンダブルSRAMおよびそのセル配置構造

    藤原 英弘, 奥村 俊介, 井口 友輔, 野口 紘希, 川口 博, 吉本 雅彦

    2009年03月, 電子情報通信学会総合大会, 0, 日本語

    研究論文(国際会議プロシーディングス)

  • Yoshinori Sakata, Kentaro Kawakami, Hiroshi Kawaguchi, Masahiko Yoshimoto

    We propose an elastic pipeline architecture that can apply dynamic voltage scaling (DVS) to a dedicated hardware, and implement the elastic pipeline to a portable H.264/AVC decoder LSI with embedded frame buffer SRAM. A supply voltage and operating frequency are decreased by a feedback-type voltage/frequency control algorithm. In a portable H.264/AVC decoder, embedded SARM can be utilized as frame buffer since the frame buffer is not so large that an external DRAM is required. In the proposed pipeline architecture, the power in the embedded SRAM and even in a local bus connecting with the frame buffer SRAM can be controlled by dynamic voltage scaling (DVS). We carried out simulation in the 320 × 180 pixels baseline profile and 320 × 240 pixels mail profile. The total power reduction in 320 × 180 pixels and 320 × 240 pixels are 30 and 31%, respectively. © 2009 Springer Science+Business Media, LLC.

    2009年, Lecture Notes in Electrical Engineering, 28 (2), 25 - 32, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A 58-mu W Single-Chip Sensor Node Processor Using Synchronous MAC Protocol

    Takeuchi, Takashi, Izumi, Shintaro, Matsuda, Takashi, Lee, Hyeokjong, Otake, Yu, Konishi, Toshihiro, Tsuruda, Koh, Sakai, Yasuharu, Fujiwara, Hidehiro, Ohta, Chikara, Kawaguchi, Hiroshi, Yoshimoto, Masahiko

    We propose a single-chip ultralow-power sensor node processor with a synchronous media access control (MAC). It is comprised of a transceiver, i8051 micro processor, and dedicated MAC processor. The test chip occupies 3 x 3 mm(2) in a 180-nm CMOS process, including 1.38 M transistors. The power is 58.0 mu W under a network environment.

    JAPAN SOCIETY APPLIED PHYSICS, 2009年, 2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 290 - 291, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    We propose a novel dependable SRAM with 7T cells and their array structure that avoids a half-selection problem. In addition, we introduce a new concept, "quality of a bit (QoB)" for it. The dependable SRAM has three modes (normal mode, high-speed mode, and dependable mode), and dynamically scales its reliability and speed by combining two memory cells for one-bit information (i.e. 14T/bit). Monte Carlo simulation demonstrates that, in a 65-nm process technology, the minimum voltages in read and write operations are improved by 0.20V and 0.26V, respectively, with a bit error rate of 10(-8) kept. The cell area overhead is 11%, compared to the conventional 6T cell in the normal mode.

    IEEE COMPUTER SOC, 2009年, 22ND INTERNATIONAL CONFERENCE ON VLSI DESIGN HELD JOINTLY WITH 8TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS, pp. 295-300, 295 - 300, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A 0.56-V 128kb 10T SRAM Using Column Line Assist (CLA) Scheme

    Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

    We present a small-area 10T SRAM cell without half selection problem. As well, the proposed 10T cell achieves a faster access time and low voltage operation. The cell area is reduced by 25%, and the cell current is increased by 21%, compared with the prior 10T cell. The minimum operating voltage is lowered by the column line assist (CLA) scheme that suppresses write margin degradation. By measurement, we confirmed that the proposed 128-kb SRAM works at 0.56 V.

    IEEE, 2009年, ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2, 0, 659 - +, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • 和泉 慎太郎, 吉本 雅彦, 竹内 隆, 松田 隆志, 李 赫鍾, 小西 恵大, 鶴田 嵩, 酒井 康晴, 川口 博, 太田 能

    本研究では,時刻同期型MACプロトコル(I-MAC)を用いる1-chipセンサノードSoCの垂直統合設計を行った.提案するセンサノードはトランシーバ,通信制御用マイクロコントローラ,電源管理モジュールから構成される.CMOS 180nmプロセスでの試作を行い,コアサイズ3mmx3mm,1.38MトランジスタのセンサノードLSIを実現した.また,データ収集型のネットワーク環境において,ノード全体で58.0μWの平均消費電力を達成した.

    一般社団法人 映像情報メディア学会, 2009年, 映像情報メディア学会技術報告, 33 (0), 141 - 145, 日本語

    [査読有り]

    研究論文(学術雑誌)

  • A 60-dB Image Rejection Filter Using Δ-Σ Modulation and Frequency Shifting,

    T. Konishi, K. Tsuruda, S. Izumi, H. Lee, H. Fujiwara, T. Takeuchi, H. Kawaguchi, M. Yoshimoto

    We propose a novel image rejection scheme for a low-IF (low intermediate frequency,) receiver. A Delta-Sigma modulator converts I/Q signals to digital values, and then they are digitally processed. The Delta-Sigma modulator is a second-order complex band-pass type; the proposed architecture is suitable for various multi-channel communications and/or cognitive radio. As the first step in the digital signal processing, a spectrum is shifted so that the desired signal band is centered at 0 Hz. Next, by LPFs (low-pass filters), an image signal and the quantization noise of the Delta-Sigma modulator are removed. These LPFs also function as a decimation filter; thus a dedicated decimation filter is not needed, and an extra area and power for it are saved. The test chip occupies 0.75 mm2 in a 180-nm mixed-signal process. The power is 6.0 mW at 1.8 V. The IRR (image rejection ratio) achieves 60 dB.

    IEEE, 2009年, 2009 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Victoria, B.C., Canada, pp. 565-570, 565 - 570, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Parallelized Viterbi Processor for 5,000-Word Large-Vocabulary Real-Time Continuous Speech Recognition FPGA System

    Tsuyoshi Fujinaga, Kazuo Miura, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    We propose a novel Viterbi processor for the large vocabulary real-time continuous speech recognition. This processor is built with multi Viterbi cores. Since each core can independently compute, these cores reduce the cycle times very efficiently. To verify the effect of utilizing multi cores, we implement a dual-core Viterbi processor in an FPGA and achieve 49% cycle-time reduction, compared to a single-core processor. Our proposed dual-core Viterbi processor achieves the 5,000-word real-time continuous speech recognition at 65.175 MHz. In addition, it is easy to implement scalable increases in the number of cores, which leads to achievement of the larger vocabulary.

    ISCA-INST SPEECH COMMUNICATION ASSOC, 2009年, INTERSPEECH 2009: 10TH ANNUAL CONFERENCE OF THE INTERNATIONAL SPEECH COMMUNICATION ASSOCIATION 2009, VOLS 1-5, pp.1483-1486, 1495 - 1498, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • AN ULTRA-LOW-POWER VAD HARDWARE IMPLEMENTATION FOR INTELLIGENT UBIQUITOUS SENSOR NETWORKS

    Hiroki Noguchi, Tomoya Takagi, Masahiko Yoshimoto, Hiroshi Kawaguchi

    We propose a power management method using a digital voice activity detection (VAD) module for intelligent ubiquitous sensor systems. When this VAD module detects a speech signal, a main signal processing circuit is connected to a power source. When no speech signal is detected, most circuits except VAD are blocked off, thereby reducing stand-by power for the specialized sensor nodes used for speech signal processing. We implemented the VAD algorithm, using zero crossing of input signals to an FPGA, thereby achieving 2.10 mW operation. We synthesized this VAD module using CMOS 0.18-mu m process, achieving 3.49 mu W power consumption for operation at 1.8 V and 100 kHz.

    IEEE, 2009年, SIPS: 2009 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS, pp. 214-219, 214 - 219, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A Single-Chip Sensor Node LSI with Synchronous MAC Protocol and Divided Data-Buffer SRAM

    Takashi Takeuchi, Shintaro Izumi, Takashi Matsuda, Hyeokjong Lee, Toshihiro Konishi, Koh Tsuruda, Yasuhiro Sakai, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

    This paper presents an ultra-low-power single-chip sensor-node VLSI with a synchronous MAC protocol and divided data-buffer SRAM for wireless-sensor-network applications. One of the most challenging issues in wireless sensor networks is extension of the overall network lifetime. So a communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system, through a vertical cooperative design among circuits, architecture, and communication protocols. A transceiver, i8051 microcontroller, and dedicated MAC processor with divided SRAM are integrated in a single chip. The test chip occupies 3.0 x 1.7 mm(2) in a 180-nm CMOS process, including 0.63 M transistors. Divided data-buffer reduces 18.6% of average power and the LSI consumes 6.34 mu W under a network environment.

    IEEE, 2009年, 2009 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2009), 202 - 207, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • チップ間ばらつき 補正機能を有する基板バイアス制御を用いた0.42V動作486kb FD-SOI SRAM

    山口 幸介, 藤原 英弘, 竹内 隆, 大竹 優, 吉本 雅彦, 川口 博

    2008年12月, 電子情 報通信学会技術研究報告(信学技報), vol. 108, no. 347, ICD2008-127, 日本語

    研究論文(学術雑誌)

  • Takashi Takeuchi, Yu Otake, Masumi Ichien, Akihiro Gion, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

    We propose Isochronous-MAC (I-MAC) using the Long-Wave Standard Time Code (so called "wave clock"), and introduce cross-layer design for a low-power wireless sensor node with I-MAC. I-MAC has a periodic wakeup time synchronized with the actual time, and thus we take the wave clock. However, a frequency of a crystal oscillator varies along with temperature, which incurs a time difference among nodes. We present a time correction algorithm to address this problem, and shorten the time difference. Thereby, the preamble length in I-MAC can be minimized, which saves communication power. For further power reduction. a low-power crystal oscillator is also proposed. as a physical-layer design. We implemented I-MAC oil an off-the-shelf sensor node to estimate the power saving, and verified that the proposed cross-layer design reduces 81% of the total power, compared to Low Power Listening.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2008年11月, IEICE TRANSACTIONS ON COMMUNICATIONS, E91B (11), 3480 - 3488, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Shintaro Izumi, Takashi Takeuchi, Takashi Matsuda, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

    Broadcasting is an elementary operation in wireless multihop networks. Flooding is a simple broadcast protocol but it frequently causes serious redundancy. contention and collisions. Probability based methods are promising because they can reduce broadcast messages without additional hardware and control packets. In this paper, the counter-based scheme which is one of the probability based methods is focused on as a broadcast protocol, and the RAD (Random Assessment Delay) Extension is proposed to improve the original counter-based scheme. The RAD Extension can be implemented without additional hardware, so that the strength of the counter-based scheme can be preserved. In addition, we propose the additional algorithm called Hop Count Aware RAD Extension to establish shorter path from the source node. Simulation results show that both of the RAD Extension and the Hop Count Aware RAD Extension reduce the number of retransmitting nodes by about 10% compared with the original scheme. Furthermore. the Hop Count Aware RAD Extension call establish almost the same path length as the counter-based scheme.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2008年11月, IEICE TRANSACTIONS ON COMMUNICATIONS, E91B (11), 3489 - 3498, 英語

    [査読有り]

    研究論文(学術雑誌)

  • 全整数計画問題ソルバーのFPGA実装,

    谷 純一, 野口 紘希, 川口 博, 吉本 雅彦

    2008年10月, 情報処理学会関西支部大会,, D-05, 日本語

    研究論文(国際会議プロシーディングス)

  • ワイヤレスセンサネットワークのためのデータ集約を考慮した部分起動メモリの電力削減効果に関する研究

    酒井 康晴, 松田 隆志, 和泉 慎太郎, 竹内 隆, 藤原 英弘, 川口 博, 太田 能, 吉本 雅彦

    2008年09月, 電子情報通信学会ソサイエティ大会, B-20-10, pp. 346, 日本語

    研究論文(国際会議プロシーディングス)

  • Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto

    We propose a low-power two-port SRAM for real-time video processing that exploits statistical similarity in images. To-minimize the discharge power on a read bitline, a majority-logic circuit decides if input data should be inverted in a write cycle, so that "1"s are in the majority. In addition, for further power reduction, write-in data are reordered into digit groups from the most significant bit group to the least significant bit group. The measurement result of a 68-kbit video memory in a 90-nm process demonstrates that a 45% power saving is achieved on the read bitline. The speed and area overheads are 4% and 7%, respectively.

    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2008年06月, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 16 (6), 620 - 627, 英語

    [査読有り]

    研究論文(学術雑誌)

  • 高信頼性モードと高速アクセスモードを有するディペンダブルSRAM

    奥村俊介, 藤原英弘, 井口友輔, 野口紘希, 森田泰弘, 川口博, 吉本雅彦

    2008年05月, 電子情報通信学会技術研究報告,, VLD2008-12, pp.31-36, 日本語

    研究論文(国際会議プロシーディングス)

  • サブ 100mW H.264 AVC MP@L4.1 HDTV 解像度対応整数画素精度動き検出プロセッサコア

    水野 孝祐, 宮越 純一, 村地 勇一郎, 濱本 真生, 飯沼 隆弘, 石原 朋和, 印 芳, 李 将充, 上農 哲也, 川口 博, 吉本 雅彦

    2008年05月, 電子情報通信学会技術研究報告, VLD2008-12, pp.25-30, 日本語

    研究論文(国際会議プロシーディングス)

  • A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition

    MURACHI Yuichiro, FUKUYAMA Yuki, YAMAMOTO Ryo, MIYAKOSHI Junichi, KAWAGUCHI Hiroshi, ISHIHARA Hajime, MIYAMA Masayuki, MATSUDA Yoshio, YOSHIMOTO Masahiko

    2008年04月, IEICE Trans. Electron, 0, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Yuichiro Murachi, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto

    We describe a sub 100-mW H.264 MP@L4.1 integerpel motion estimation processor core for low power video encoder. It supports macro block adaptive frame field (MBAFF) encoding and bidirectional prediction for a resolution of 1920 x 1080 pixels at 30fps. The proposed processor features a novel hierarchical algorithm, reconfigurable ring-connected systolic array architecture and segmentation-free, rectangle-access search window buffer. The hierarchical algorithm consists of a fine search and a coarse search. A complementary recursive cross search is newly introduced in the coarse search. The fine search is adaptively carried out, based on an image analysis result obtained by the coarse search. The proposed systolic array architecture minimizes the amount of transferred data, and lowers computation cycles for the coarse and fine searches. In addition, we propose a novel search window buffer SRAM that has instantaneous accessibility to a rectangular area with arbitrary location. The processor core has been designed with a 90 nm CMOS design rule. Core size is 2.5 x 2.5 mm(2). One core supports one-reference-frame and dissipates 48 mW at 1 V. Two core configuration consumes 96 mW for two-reference-frame search.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2008年04月, IEICE TRANSACTIONS ON ELECTRONICS, E91C (4), 465 - 478, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

    We propose a low-power non-precharge-type two-port SRAM for video processing that exploits statistical similarity in images. To minimize the charge/discharge power on a read bitline, the proposed memory cell (MC) has ten transistors (10T), comprised of the conventional 6T MC, a readout inverter and a transmission gate for a read port. In addition, to incorporate three wordlines, we propose a shared wordline structure, with which the vertical cell size of the 10T MC is fitted to the same size as the conventional 8T MC. Since the readout inverter fully charges/discharges a read bitline, there is no precharge circuit on the read bitline. Thus, power is not consumed by precharging, but is consumed only when a readout datum is changed. This feature is suitable to video processing since image data have spatial correlation and similar data are read out in consecutive cycles. As well as the power reduction, the prechargeless structure shortens a cycle time by 38% compared with the conventional SRAM, because it does not require a precharge period. This, in turn, demonstrates that the proposed SRAM operates at a lower voltage, which achieves further power reduction. Compared to the conventional 8T SRAM, the proposed SRAM reduces a charge/discharge possibility to 19% (81% saving) on the bitlines. As the measurement result, we confirmed that the proposed 64-kb video memory in a 90-nm process achieves an 85% power saving on the read bitline, when considered as an H.264 reconstructed image memory. The area overhead is 14.4%.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2008年04月, IEICE TRANSACTIONS ON ELECTRONICS, E91C (4), 543 - 552, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Kosuke Mizuno, Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper describes an H.264/AVC MP@L4.1 quarter-pel motion estimation processor core for a low power video encoder. It supports macro block adaptive frame field (MBAFF) encoding and bi-directional prediction for a resolution of 1920 × 1080 pixels at 30 fps which haven't been realized by conventional methods yet. The proposed processor consists of four modules for low power consumption: a module for an integer-pel motion estimation, a segmentation-free rectangle-access search window buffer, a module for quarter-pel motion estimation, and a module reducing candidate motion vectors. We propose an adaptive algorithm that reduces a workload and power in quarter-pel motion estimation. The algorithm and architecture for the candidate motion vectors reduction suppress a workload of the following process. The processor core has been designed in a 90 nm CMOS technology. The core size is 6.0 × 6.0 mm2. With this core, two reference frame can be handled, and 160.1 mW is consumed at 1.0 V. © 2008 IEEE.

    2008年, Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, 1179 - 1182, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Yuichiro Murachi, Kosuke Mizuno, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper describes a sub 100-mW H.264/AVC MP@L4.1 integer-pel motion estimation processor core for a low power video encoder. It supports macro block adaptive frame field (MBAFF) encoding and bi-directional prediction for a resolution of 1920 x 1080 pixels at 30 fps which haven't been realized by conventional methods[1][2]. The proposed processor core features a novel hierarchical algorithm, a reconfigurable ring-connected systolic array architecture, and a segmentation-free rectangle-access search window buffer. The processor core has been designed in a 90 nm CMOS technology, and its core size is 2.5 x 2.5 mm2. With one core, one reference frame can be handled, and 48 mW is consumed at 1 V. Two-core configuration dissipates 96 mW for two reference frames. ©2008 IEEE.

    2008年, Proceedings - IEEE International Symposium on Circuits and Systems, 848 - 851, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Quality of a bit (QoB): A new concept in dependable SRAM

    Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto

    We propose a novel dependable SRAM with 7T memory cells, and introduce a new concept, "quality of a bit (QoB)" for it. The proposed SRAM has three modes: a typical mode, high-speed mode, and dependable mode, in which the QoB is scalable. That is, the area, speed, reliability, and/or power of one-bit information can be controlled. In the typical mode, assignment of information is as usual as one memory cell has one bit. On the other hand, in the high-speed or dependable mode, one-bit information is stored in two memory cells, which boosts the speed or increases the reliability. By carrying out Monte Carlo simulation of dynamic cell stability in a 90-nm process technology, we confirmed the advantage of the proposed SRAM.

    IEEE COMPUTER SOC, 2008年, ISQED 2008: PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, pp. 98-102, 98 - 102, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Impact of divided static random access memory considering data aggregation for wireless sensor networks

    Takashi Matsuda, Shintaro Izumi, Takashi Takeuchi, Hidehiro Fujiwara, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

    The most challenging issue of sensor networks is extension of overall network system lifetimes. It is important for the extension of system lifetime to determine the routing considering data aggregation. Data aggregation can reduce network traffic by the elimination of the redundant data. Though data aggregation is effective, sensor node needs a certain amount of RAM to aggregate data. RAM has standby energy, and its power consumption is one of the major factors in sensor node. In this work, we investigate the relationship among RAM capacity, data aggregation and power consumption. Then, we propose to use divided operating SRAM. Proposal method can reduce energy of sensor node even if RAM capacity is large.

    IEEE, 2008年, 2008 7TH ASIA-PACIFIC SYMPOSIUM ON INFORMATION AND TELECOMMUNICATION TECHNOLOGIES, pp. 130-134, 115 - +, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Hop Count Aware broadcast algorithm with Random Assessment Delay Extension for wireless sensor networks

    Shintaro Izumi, Takashi Matsuda, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

    Broadcasting is an elementary operation in wireless multi-hop networks. Flooding is a simple broadcast protocol but it frequently causes serious redundancy, contention and collisions. Probability based methods are promising because they can reduce broadcast messages without additional hardwares and control packets. In this paper, the counter-based scheme which is one of the probability based methods is focused on as a broadcast protocol, and the RAD (Random Assessment Delay) Extension is proposed to improve the original counter-based scheme. The RAD Extension can be implemented without additional hardwares, so that the strength of the counter-based scheme can be preserved. In addition, we propose the additional algorithm called Hop Count Aware RAD Extension to establish shorter path from the source node. Simulation results show that both of the RAD Extension and the Hop Count Aware RAD Extension reduce the number of retransmitting nodes by about 10% compared with the original scheme. Furthermore, the Hop Count Aware RAD Extension can establish almost the same path length as the counter-based scheme.

    IEEE, 2008年, 2008 7TH ASIA-PACIFIC SYMPOSIUM ON INFORMATION AND TELECOMMUNICATION TECHNOLOGIES, pp. 30-35, 207 - +, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A power-efficient SRAM core architecture with segmentation-free and rectangular accessibility for super-parallel video processing

    Yuichiro Murachi, Tetsuya Kamino, Junichi Miyakoshi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper describes a unique SRAM architecture for super-parallel video processing. It features one cycle functional access of a rectangular image data (n x m pixels) with segmentation-free. To achieve this accessibility, a local word-line select scheme and a merged X-decoder method are newly introduced with elimination of extra X-decoder employed in usage of the conventional divided SRAM macro. The proposed SRAM has been adopted to a search window buffer for H.264 motion estimation processor for HDTV resolution video. As a result, a power and area of the search window buffer are reduced by 49 % and by 48 %, respectively. Furthermore, it is shown that the proposed SRAM is more efficient for super-HDTV resolution video which requires more parallelism.

    IEEE, 2008年, 2008 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM, pp. 63-66, 63 - +, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding

    Yuichiro Murachi, Kosuke Mizuno, Junichi Miyakoshi, Masaki Harnarnoto, Takahiro Linurna, Tornokazu Ishibara, Fang Yin, Jangchung Lee, Tetsuya Karnino, Hiroshi Kawaguchi, Masahiko Yoshirnoto

    This paper describes a sub 100-mW H.264/AVC MP@L4.1 integer-pel motion estimation processor core for a low power video encoder. It supports macro block adaptive frame field (MBAFF) encoding and bi-directional prediction for a resolution of 1920 x 1080 pixels at 30 fps which haven't been realized by conventional methods[1][2]. The proposed processor core features a novel hierarchical algorithm, a reconfigurable ring-connected systolic array architecture, and a segmentation-free rectangle-access search window buffer. The processor core has been designed in a 90 nm CMOS technology, and its core size is 2.5 x 2.5 mm(2). With one core, one reference frame can be handled, and 48 mW is consumed at 1 V. Two-core configuration dissipates 96 mW for two reference frames.

    IEEE, 2008年, PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 0, 848 - 851, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Which is the best dual-port SRAM in 45-nm process technology? 8T, 10T single end, and 10T differential

    Hiroki Noguchi, Shunsuke Okumura, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper compares readout powers and operating frequencies among dual-port SRAMs: an 8T SRAM, 10T single-end SRAM, and 10T differential SRAM. The conventional 8T SRAM has the least transistor count, and is the most area efficient. However, the readout power becomes large and the cycle time increases due to peripheral circuits. The 10T single-end SRAM is our proposed SRAM, in which a dedicated inverter and transmission gate are appended as a single-end read port. The readout power of the 10T single-end SRAM is reduced by 75% and the operating frequency is increased by 95%, over the 8T SRAM. On the other hand the 10T differential SRAM can operate fastest, because its small differential voltage of 50 mV achieves the high-speed operation. In terms of the power efficiency, however, the sense amplifier and precharge circuits lead to the power overhead. As a result, the 10T single-end SRAM always consumes lowest readout power compared to the 8T and the 10T differential SRAM.

    IEEE, 2008年, 2008 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS, pp.55-58,, 55 - 58, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding

    Yuichiro Murachi, Kosuke Mizuno, Junichi Miyakoshi, Masaki Harnarnoto, Takahiro Linurna, Tornokazu Ishibara, Fang Yin, Jangchung Lee, Tetsuya Karnino, Hiroshi Kawaguchi, Masahiko Yoshirnoto

    This paper describes a sub 100-mW H.264/AVC MP@L4.1 integer-pel motion estimation processor core for a low power video encoder. It supports macro block adaptive frame field (MBAFF) encoding and bi-directional prediction for a resolution of 1920 x 1080 pixels at 30 fps which haven't been realized by conventional methods[1][2]. The proposed processor core features a novel hierarchical algorithm, a reconfigurable ring-connected systolic array architecture, and a segmentation-free rectangle-access search window buffer. The processor core has been designed in a 90 nm CMOS technology, and its core size is 2.5 x 2.5 mm(2). With one core, one reference frame can be handled, and 48 mW is consumed at 1 V. Two-core configuration dissipates 96 mW for two reference frames.

    IEEE, 2008年, PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 0, 848 - 851, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • 鶴田 嵩, 和泉 慎太郎, 李 赫鍾, 竹内 隆, 川口 博, 吉本 雅彦

    本論文ではコグニティブ無線向け可変帯域ディジタルBPF(Band-Pass Filter)を用いたベースバンドプロセッサを提案する.BPFにDA(Distributed Arithmetic)アルゴリズムを適応することで,内蔵するSRAMのデータを書き換えるだけでBPFの特性(チャネル中心周波数とバンド幅)を変化させることが可能となる.試作したベースバンドプロセッサではバンド幅を40kHzから240kHzまで10kHz単位で変化させることが可能である.CMOS 180nmプロセスで設計し,電源電圧1.8Vで消費電力は13.5mWであった.

    一般社団法人 映像情報メディア学会, 2008年, 映像情報メディア学会技術報告, 32 (0), 137 - 141, 日本語

    研究論文(国際会議プロシーディングス)

  • An Inter-Die Variability Compensation Scheme for 0.42-V 486-kb FD-SOI SRAM using Substrate Control

    Hidehiro Fujiwara, Takashi Takeuchi, Yu Otake, Masahiko Yoshimoto, Hiroshi Kawaguchi

    We propose a novel substrate-bias control scheme for FD-SOI SRAM that suppresses inter-die variability and achieves low-voltage operation. Substrate-bias control circuits automatically detect an inter-die threshold-voltage variation, and then maximize read/write margins of memory cells. We confirmed that a 486-kb SRAM operates at 0.42 V, in which an FS/SF comers can be compensated as much as 0.14 V or more.

    IEEE, 2008年, 2008 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, pp. 93-94, 93 - 94, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Memory Bandwidth Gaussian Mixture Model (GMM) Processor for 20,000-Word Real-Time Speech Recognition FPGA System

    Kazuo Miura, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    We propose a GMM processor for large vocabulary real-time continuous speech recognition. This processor achieves low operating frequency and low memory bandwidth using parallelization and vector look-ahead schemes, which are suitable to FPGA implementation. We designed the proposed processor on a Celoxica RC250 FPGA board, and confirmed that the required frequency and memory bandwidth for real-time operation are reduced by 89.8% and 84.2%, respectively. The 20,000-word real-time GMM computation is made at a frequency of 30.4 MHz and memory bandwidth of 4 7 Mbps, on the prototype.

    IEEE, 2008年, PROCEEDINGS OF THE 2008 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY, 0, 341 - 344, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A Flexible Baseband Processor with Multi-Resolution Spectrum-Sensing Functionality

    Koh Tsuruda, Shintaro Izumi, Hyeokjong Lee, Takashi Takeuchi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    In this paper, we propose a reconfigurable baseband processor for a cognitive radio that has multi-resolution bandpass filters. By applying the distributed arithmetic algorithm to the reconfigurable baseband processor and rewriting SRAM data in it, a channel center frequency and bandwidth are reconfigurable. The filter bandwidth can be changed from 40 kHz to 240 kHz with a 10 kHz resolution on our prototype processor. The power is 13 mW at a supply voltage of 1.8 V in a 0.18-mu m CMOS process.

    IEEE, 2008年, 2008 INTERNATIONAL SYMPOSIUM ON INFORMATION THEORY AND ITS APPLICATIONS, VOLS 1-3, pp. 1423-1428, 1422 - 1427, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Masahiko Yoshimoto, Hiroshi Kawaguchi

    We propose a microphone array network that realizes ubiquitous sound acquisition. Several nodes with 16 microphones are connected to form a novel huge sound acquisition system, which carries out voice activity detection (VAD), sound source localization, and separation. The three operations are distributed among nodes. Using the distributed network, we achieve a low-traffic data-intensive array network. To manage nodes' power consumption, VAD is implemented. Consequently, the system uses little power when speech is not active. For sound localization, a network-connected multiple signal classification (MUSIC) algorithm is used. The sound separation system can improve a signal-noise ratio (SNR) by 7.75 dB using 112 microphones. Network traffic is reduced by 99.11% when using 1024 microphones.

    IEEE, 2008年, 2010 FOURTH INTERNATIONAL CONFERENCE ON SENSOR TECHNOLOGIES AND APPLICATIONS (SENSORCOMM), pp. 157-162, 157 - 162, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • 超並列画像処理応用 任意位置任意サイズ矩形画素の1サイクルアクセスが可能なブロックアクセスメモリアーキテクチャ

    村地 勇一郎, 宮越 純一, 上農 哲也, 川口 博, 吉本 雅彦

    2007年12月, 電子情報通信学会技術研究報告,ICD2007-128, Vol.107,No.382,pp.47-52, 日本語

    研究論文(国際会議プロシーディングス)

  • Takashi Matsuda, Masumi Ichien, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

    One challenging issue of sensor networks is extension of overall network system lifetimes. In periodic data gathering applications, the typical sensor node spends more time in the idle state than active state. Consequently, it is important to decrease power consumption during idle time. In this study, we propose a scheduling scheme based on the history of RTS/CTS exchange during the setup phase. Scheduling the transmission during transfer phase enables each node to turn off its RF circuit during idle time. By tracing ongoing RTS/CTS exchange during the steady phase, each node knows the progress of the data transfer process. Thereby, it can wait to receive packets for data aggregation. Simulation results show a 160-260% longer system lifetime with the proposed scheduling scheme compared to the existing approaches.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2007年12月, IEICE TRANSACTIONS ON COMMUNICATIONS, E90B (12), 3410 - 3418, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper compares areas between a 6T and 8T SRAM cells, in a dual-V-dd scheme and a dynamic voltage scaling (DVS) scheme. In the dual-V-dd scheme, we predict that the area of the 6T cell keep smaller than that of the 8T cell, over feature technology nodes all down to 32 nm. In contrast, in the DVS scheme, the 8T cell will becomes superior to the 6T cell after the 32-nm node, in terms of the area.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2007年12月, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E90A (12), 2695 - 2702, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Kohei Onizuka, Kenichi Inagaki, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai

    An on-chip buck converter which is implemented by stacking chips and suitable for on-chip distributed power supply systems is proposed. The operation of the converter with 3-D chip stacking is experimentally verified for the first time. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70 mA and a voltage conversion ratio of 0.7 with a switching frequency of 200 MHz and a 2 × 2 mm on-chip LC output filter. The active part and the passive LC output filter are implemented on separate chips fabricated in 0.35- μm CMOS and connected with metal bumps. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3% is also discussed. © 2007 IEEE.

    2007年11月, IEEE Journal of Solid-State Circuits, 42 (11), 2404 - 2410, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Improvement of Counter-based Broadcasting by Random Assessment Delay Extension for Wireless Sensor Networks

    IZUMI Shintaro, MATSUDA Takashi, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

    2007年10月, Proc. International Conference on Sensor Technologies and Applications (SENSORCOMM 2007), pp.76-81, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Cross-Layer Design for Low-Power Wireless Sensor Node using Long-Wave Standard Time Code

    OTAKE Yu, ICHIEN Mashumi, TAKEUCHI Takashi, GION Akihiro, MIKAMI Shinji, FUJIWARA Hidehiro, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

    2007年10月, Proc. International Conference on Sensor Technologies and Applications (SENSORCOMM 2007), pp.341-346, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper shows that an 8T SRAM cell is superior to a 6T cell in terms of cell area in a future process. At a 65-nm node and later, the 6T cell comprised of the minimum-channel-length transistors cannot make the minimum area because of threshold-voltage variation. In contrast, the 8T cell can employ the optimized transistors and achieves the minimum area even if it is used as a single-port SRAM. In a 32-nm process, the 8T-cell area is smaller than the 6T cell by 14.6% at a supply voltage of 0.8 V. We also discuss the area and access time comparisons between the 6T-SRAM and 8T-SRAM macros.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2007年10月, IEICE TRANSACTIONS ON ELECTRONICS, E90C (10), 1949 - 1956, 英語

    [査読有り]

    研究論文(学術雑誌)

  • An elastic pipeline architecture for dynamic voltage scaling and its application to low-power portable H.264/AVC decoder with embedded frame buffer SRAM

    SAKATA Yoshinori, KAWAKAMI Kentaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

    2007年09月, EUROPEAN COMPUTING CONFERENCE, pp.00-00, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • DVS環境下での小面積・低電圧動作8T SRAMの設計

    森田 泰弘, 藤原 英弘, 野口 紘希, 井口 友輔, 新居 浩二, 川口 博, 吉本 雅彦

    2007年08月, 電子情報通信学会技術研究報告,ICD2007-95, Vol.107,No.195,pp.139-144, 日本語

    研究論文(国際会議プロシーディングス)

  • 電源電圧と周波数の動的制御によるH.264/AVC デコーダの低消費電力化

    坂田 義典, 川上 健太郎, 川口 博, 吉本 雅彦

    2007年07月, 電子情報通信学会技術研究報告,ICD2007-52, Vol.107,No.163,pp.89-94, 日本語

    研究論文(国際会議プロシーディングス)

  • 長波帯標準電波を用いた低電力センサーノードのための垂直統合設計

    大竹 優, 一圓 真澄, 竹内 隆, 祗園 昭宏, 三上 真司, 藤原 英弘, 川口 博, 太田 能, 吉本 雅彦

    2007年07月, 電子情報通信学会技術研究報告,ICD2007-49, Vol.107,No.163,pp.71-76, 日本語

    研究論文(国際会議プロシーディングス)

  • ワイヤレスセンサーネットワーク応用キャリアセンス機能を持つ433MHz帯、356-uW電圧増幅器

    李 赫鍾, 三上 真司, 竹内 隆, 一圓 真澄, 川口 博, 太田 能, 吉本 雅彦

    2007年07月, 電子情報通信学会技術研究報告,ICD2007-50, Vol.107,No.163,pp.77-82, 日本語

    研究論文(国際会議プロシーディングス)

  • ビット線電力を74%削減する動画像処理応用 10T 非プリチャージ 2-port SRAMの設計

    奥村 俊介, 野口 紘希, 井口 友輔, 藤原 英弘, 森田 泰弘, 新居 浩二, 川口 博, 吉本 雅彦

    2007年07月, 電子情報通信学会技術研究報告,ICD2007-53, Vol.107,No.163,pp.95-100, 日本語

    研究論文(国際会議プロシーディングス)

  • ビット線の電力を削減する実時間動画像処理応用2-port SRAM

    藤原 英弘, 新居 浩二, 野口 紘希, 宮越 純一, 村地 勇一郎, 森田 泰弘, 川口 博, 吉本 雅彦

    2007年04月, 電子情報通信学会技術研究報告,ICD2007-7, Vol.107,No.1,pp.35-40, 日本語

    研究論文(国際会議プロシーディングス)

  • Hajime Ishihara, Masayuki Miyama, Yoshio Matsuda, Yuichiro Murachi, Yuki Fukuyama, Ryo Yamamoto, Junichi Miyakoshi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper describes an optical-flow processor core for real-time video recognition. The processor is based on the Pyramidal Lucas and Kanade algorithm. It has small chip area, a high pixel rate, and high accuracy compared to conventional optical-flow processors. Introduction of search range limitation and the Carman filter to the original algorithm improves the optical-flow accuracy and reduces the processor hardware cost. Furthermore, window interleaving and window overlap methods can reduce the necessary clock frequency of the processor by 70%. The proposed processor can handle a VGA 30-fps image sequence with 332 MHz clock frequency. The core size and power consumption in 90-nm process technology are estimated respectively as 3.50 × 3.00 mm 2 and 600 mW. ©2007 IEEE.

    IEEE Computer Society, 2007年, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, 188 - 191, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Hiroshi Kawaguchi, Danardono Dwi Antono, Takayasu Sakurai

    Closed-form expressions for a crosstalk noise amplitude and worst-case delay in capacitively coupled two-line and three-line systems are derived assuming bus lines and other signal lines in a VLSI. Two modes are studied a case that adjacent lines are driven from the same direction, and the other case that adjacent lines are driven from the opposite direction. Beside, a junction capacitance of a driver MOSFET is considered. The closed-form expressions are useful for circuit designers in an early stage of a VLSI design to give insight to interconnection problems. The expressions are extensively compared and fitted to SPICE simulations. The relative and absolute errors in the crosstalk noise amplitude are within 63.8% and 0.098 E (where E is a supply voltage), respectively. The relative error in the worst-case delay is less than 8.1%. Copyright © 2007 The Institute of Electronics, Information and Communication Engineers.

    Institute of Electronics, Information and Communication, Engineers, IEICE, 2007年, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E90-A (12), 2669 - 2681, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Kohei Onizuka, Makoto Takamiya, Hiroshi Kawaguchi, Takayasu Sakurai

    A design methodology to transmit power using a chip-to-chip wireless interface is proposed. The proposed power transmission system is based on magnetic coupling, and the power transmission of 5mW/mm2 was verified. The transmission efficiency trade-off with the transmitted power is also discussed. ©2007 IEEE.

    2007年, Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT, 143 - 146, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Makoto Takamiya, Tsuyoshi Sekitani, Yoshio Miyamoto, Yoshiaki Noguchi, Hiroshi Kawaguchi, Takao Someya, Takayasu Sakurai

    Design innovations to overcome the shortcomings of a wireless power transmission sheet made with plastic MEMS switches and OFET for printable low-cost electronics are shown. The mixed circuits of MEMS switches and OFETs with two different frequencies reduce the number of coil sheets form 2 to 1. OFET level-shifters, with the current-source loads with enhancement/depletion mixed threshold voltages realized by controlling the back-gate voltage, bridge the operation voltage gap between silicon VLSIs (below 5 V) and OFETs/MEMS (above 40V). ©2007 IEEE.

    2007年, Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT, 168 - 171, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • David Levacq, Muhammad Yazid, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai

    A new low clock swing flip-flop (F/F) is proposed. The existing low clock-swing F/F's consume high power, introduce speed penalty due to contention currents or require large silicon area due to separate well for substrate biasing. By reducing contention currents, our proposal efficiently mitigates those issues. Measurements and simulations are carried out based on a 90 nm CMOS process, demonstrating reductions of active power by 71%, area by 36% and delay by 35% compared to previous proposals. It is shown that the combination of a low-clock swing distribution tree with the new F/F can save up to 60% of the total clock system power. © 2007 IEEE.

    2007年, ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference, 190 - 193, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Makoto Takamiya, Tsuyoshi Sekitani, Yoshio Miyamoto, Yoshiaki Noguchi, Hiroshi Kawaguchi, Takao Someya, Takayasu Sakurai

    Design innovations that solve shortcomings of a wireless power transmission sheet are presented. The sheet is made with plastic MEMS switches and organic FET circuits. By using a level shifter with adaptive biasing in the organic circuit, the sheet can be directly driven using 5V digital input. It delivers power to multiple objects, frees the user from position adjustment, and reduces the number of coil arrays. © 2007 IEEE.

    2007年, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 355 - 609, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Fayez Robert Saliba, Hiroshi Kawaguchi, Takayasu Sakurai

    We report an SRAM with a 90 reduction of active-leakage power achieved by controlling the supply voltage. In our design, the supply voltage of a selected row in the SRAM goes up to 1 V, while that in other memory cells that are not selected is kept at 0.3 V. This suppresses active leakage because of the drain-induced barrier lowering (DIBL) effect. To avoid unexpected flips in the memory cells, the wordline voltage is controlled so that it is always lower than the supply voltage in the proposed SRAM, with a self-alignment timing generator. The additional area overhead of the timing generator is 3.5. Copyright © 2007 The Institute of Electronics, Information and Communication Engineers.

    Institute of Electronics, Information and Communication, Engineers, IEICE, 2007年, IEICE Transactions on Electronics, E90-C (4), 743 - 748, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Power and memory bandwidth reduction of an H.264/AVC HDTV decoder LSI with elastic pipeline architecture

    Kentaro Kawakami, Mitsuhiko Kuroda, Hiroshi Kawaguchi, Masahiko Yoshimoto

    We propose an elastic pipeline that can apply dynamic voltage scaling (DVS) to hardwired logic circuits. The proposed pipeline can also reduce a required local bus bandwidth. In order to demonstrate its feasibility, a hardwired H.264/AVC HDTV decoder is designed as a real-time application. The proposed architecture reduces a power to 56% in a 90-nm process technology, compared to the conventional clock-gating scheme or a local bus bandwidth to 37.2%.

    IEEE, 2007年, PROCEEDINGS OF THE ASP-DAC 2007, pp.292-297, 292 - +, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Makoto Takamiya, Tsuyoshi Sekitani, Yusaku Kato, Hiroshi Kawaguchi, Takao Someya, Takayasu Sakurai

    An integrated system of organic FETs (OFETs) and plastic actuators is proposed, and it is applied to a Braille sheet display. Some circuit technologies are presented to enhance the speed and the lifetime for the Braille sheet display. An OFET SRAM is developed to hide the slow transition of the actuators. Developed five-transistor SRAM cell reduces the number of the bit lines by one-half and reduces the SRAM cell area by 20%. Pipelining the write-operation reduced the SRAM write-time by 69%. Threshold voltage control technology using a back gate increased the static noise margin of SRAM and compensated for the chemical degradation of the OFETs after 15 days. The oscillation frequency tuning range from -82% to +13% in a five-stage ring oscillator is also demonstrated with the threshold voltage control technology. The overdrive techniques for the driver OFETs reduced the transition time of the actuator from 34 s to 2 s. These developed circuit technologies achieved the practical 1.75-s operation to change all 144 Braille dots on Braille sheet display and will be essential for the future large area electronics made with OFETs.

    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2007年01月, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 42 (1), 93 - 100, 英語

    [査読有り]

    研究論文(学術雑誌)

  • An Efficiency Degradation Model of Power Amplifier the Impact against Transmission Power Control

    MIKAMI Shinji, TAKEUCHI Takashi, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

    2007年01月, Proc. IEEE 2007 Radio Wireless Symposium (RWS 2007), pp.447-450, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A 356-�W 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks

    MIKAMI Shinji, ICHIEN Mashumi, TAKEUCHI Takashi, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

    2007年01月, Proc. IEEE 2007 Radio Wireless Symposium (RWS 2007), pp.451-454, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A 10T non-precharge two-port SRAM for 74% power reduction in video processing

    Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

    We propose a low-power non-precharge-type two-port SRAM for video processing. The proposed memory cell (MC) has ten transistors (10T), comprised of the conventional 6T MC, a readout inverter and a transmission gate for a read port. Since the readout inverter fully charges/discharges a read bitline, there is no precharge circuit on the read bitline. Thus, power is not consumed by precharging, but is consumed only when a readout datum is changed. This feature is suitable to video processing since image data have special correlation and similar data are read out in consecutive cycles. As well as the power reduction, the prechargeless structure shortens a cycle time by 38% compared with the conventional SRAM, because it does not require a precharge period. This, in turn, demonstrates that the proposed SRAM operates at a lower voltage, which achieves further power reduction. Compared to the conventional 8T SRAM, the proposed SRAM reduces a charge/discharge possibility to 19% (81% reduction) on the bitlines, and saves 74% of a readout power when considered as an H.264 reconstructed-image memory. The area overhead is 14.4% in a 90-nm process technology.

    IEEE COMPUTER SOC, 2007年, IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS, pp.107-112, 107 - +, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • An area-conscious low-voltage-oriented 8T-SRAM design under DVS environment

    Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper demonstrates that an 8T memory cell can be alternative design to a 6T cell in a future highly-integrated SRAM. in a 45-nm process and later with large threshold-voltage variation. The proposed voltage-control scheme that improves a write margin and read current, and the write-back scheme that stabilizes unselected cells are applied to the 8T SRAM. We verified that the low-voltage operation at 0.42 V in a 90-nm 64-Mb SRAM is possible under dynamic voltage scaling (DVS) environment.

    JAPAN SOCIETY APPLIED PHYSICS, 2007年, 2007 Symposium on VLSI Circuits, Digest of Technical Papers, pp.256-257, 256 - 257, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Multipath routing using Isochronous medium access control with multi wakeup period for wireless sensor networks

    Takashi Matsuda, Takafumi Aonishi, Takashi Takeuchi, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

    The cycled receiver MAC protocols reduce idle listening by periodically putting nodes into sleep state. Conventional cycled receiver protocols, however, have problem such as overhearing and high latency. In this study, we propose Isochronous MAC with multi wakeup period which can reduce the power consumption due to overhearing without delay increased. To exploit this benefit, we combine it with multipath routing. Simulation results show a 12% longer system lifetime and a 87% lower delay of our proposal scheme than that of the conventional scheme.

    IEEE, 2007年, 2007 FOURTH INTERNATIONAL SYMPOSIUM ON WIRELESS COMMUNICATION SYSTEMS, VOLS 1 AND 2, pp.718-721, 796 - 799, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Danardono Dwi Antono, Kenichi Inagaki, Hiroshi Kawaguchi, Takayasu Sakurai

    A simple analytical model based on Delayed Quadratic (DQ) Transfer Function approximation is proposed for estimating waveforms of inductive single-line interconnects in VLSI's. An expression for overshoot voltage is derived by the model within 17% error for the line width less than 10 times the minimum line width and typical input signal. A delay expression is also proposed within 15% for the same condition. The strength of the inductive effect is shown to be expressed by a closed-form expression, A = 2(L(C-T +0.5C))(1/2)/(R-T(C-T +C-J)+RTC+RCT +0.4RC). By using the criteria, a scaling trend of inductive effects in VLSI's is discussed. It is shown that the inductive effect of single-line, minimum-width VLSI interconnect peaks off at 90 nm based on the ITRS predicted parameters.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2006年12月, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E89A (12), 3569 - 3578, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Junichi Miyakoshi, Yuichiro Murachi, Tetsuro Matsuno, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masayuki Miyama, Masahiko Yoshimoto

    We propose a sub-mW H.264 baseline-profile motion estimation processor for portable video applications. It features a VLSI-oriented block partitioning strategy and low-power SIMD/systolic-array datapath architecture, where the datapath can be switched between an SIMD and systolic array depending on processing flow. The processor supports all the seven kinds of block modes, and can handle three reference frames for a CIF (352 x 288) 30-fps to QCIF (176 x 144) 15-fps sequences with a quarter-pixel accuracy. It integrates 3.3 million transistors, and occupies 2.8 x 3.1 mm(2) in a 130-nm CMOS technology. The proposed processor achieves a power of 800 mu W in a QCIF 15-fps sequence with one reference picture.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2006年12月, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E89A (12), 3623 - 3633, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Kentaro Kawakami, Jun Takemura, Mitsuhiko Kuroda, Hiroshi Kawaguchi, Masahiko Yoshimoto

    We propose an elastic pipeline that can apply dynamic voltage scaling (DVS) to hardwired logic circuits. In order to demonstrate its feasibility, a hardwired H.264/AVC HDTV decoder is designed as a real-time application. An entropy decoding process is divided into context-based adaptive binary arithmetic coding (CABAC) and syntax element decoding (SED), which has advantages of smoothing workload for CABAC and keeping efficiency of the elastic pipeline. An operating frequency and supply voltage are dynamically modulated every slot depending on workload of H.264 decoding to minimize power. We optimize the number of slots per frame to enhance power reduction. The proposed decoder achieves a power reduction of 50% in a 90-nm process technology, compared to the conventional clock-gating scheme.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2006年12月, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E89A (12), 3642 - 3651, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Kentaro Kawakami, Junichi Miyakoshi, Shinji Mikami, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto

    We propose a voltage control scheme for 6T SRAM cells that makes a minimum operation voltage down to 0.3 V under DVS environment. A supply voltage to the memory cells and wordline drivers, bitline voltage, and body bias voltage of load pMOSFETs are controlled according to read and write operations, which secures operation margins even at a low operation voltage. A self-aligned timing control with a dummy wordline and its feedback is also introduced to guarantee stable operation in a wide range of the supply voltage. A measurement result of a 64-kb SRAM in a 90-nm process technology shows that a power reduction of 30% can be achieved at 100 MHz. In a 65-nm 64-Mb SRAM, a 74% power saving is expected at 1/6 of the maximum operating frequency. The performance penalty by the proposed scheme is less than 1% and area overhead-is 5.6%.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2006年12月, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E89A (12), 3634 - 3641, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Kohei Onizuka, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai

    A VD D-hopping accelerator for on-chip power supply circuits is proposed and the effectiveness of the accelerator circuit is experimentally verified. The quick dropper with the linear regulator enables nanosecond-order transient time in on-chip distributed power supply systems. The measured transition time is less than 5 ns with a load circuit equivalent to 25-k logic gates in 0.18-mu m CMOS. This is to be compared with the case without the accelerator of the order of mu s and thus the acceleration by two orders of magnitude is achieved. Extensions of the basic approach are also discussed including implementation of the quick dropper for a switching DC-DC converter, the control stability improvement, automatic timing generation, and the parasitic element effects of the power lines.

    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2006年11月, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 41 (11), 2382 - 2389, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Junichi Miyakoshi, Yuichiro Murachi, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto

    For super-parallel video processing, we proposed a power and area-efficient SRAM core architecture with a segmentation-free access, which means accessibility to arbitrary consecutive pixels, and horizontal/vertical access. To achieve these flexible accesses, a spirally-connected local-wordline select signal and multi-selection scheme in word-lines are proposed, so that extra X-decoders in the conventional multi-division SRAM can be eliminated. Consequently, the proposed SRAM reduces a power and area by 57-60% and 60%, respectively, when it is applied to a 128 parallel architecture. The proposed 160-kbit SRAM with 16-read ports (2-read port SRAM with eight-parallel architecture) is implemented to a search window buffer for an H.264 motion estimation processor core which dissipates 800 mu W for QCIF 15-fps in a 130-nm technology.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2006年11月, IEICE TRANSACTIONS ON ELECTRONICS, E89C (11), 1629 - 1636, 英語

    [査読有り]

    研究論文(学術雑誌)

  • An 800-�W H.264 Baseline-Profile Motion Estimation Processor Core

    IINUMA Takahiro, MIYAKOSHI Junichi, MURACHI Yuichiro, MATSUNO Tetsuro, HAMAMOTO Masaki, ISHIHARA Tomokazu, KAWAGUCHI Hiroshi, MIYAMA Masayuki, YOSHIMOTO Masahiko

    2006年11月, 2006 IEEE Asian Solid-State Circuits Conference Proceedings, pp.99-102, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Isochronous MAC using Low Frequency Radio Wave Time Synchronization for Wireless Sensor Networks

    ICHIEN Mashumi, TAKEUCHI Takashi, MIKAMI Shinji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

    2006年10月, Proc. First International Conference on Communications Electronics (ICCE 2006), p.172-177, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Data Transmission Scheduling based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks

    MATSUDA Takashi, ICHIEN Mashumi, MIKAMI Shinji, KAWAGUCHI Hiroshi, OHTA Chikara, YOSHIMOTO Masahiko

    2006年10月, First International Conference on Communications Electronics (ICCE 2006), pp.00-00, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Shinji Mikami, Takafumi Aonishi, Hironori Yoshino, Chikara Ohta, Hiroshi Kawaguchi, Masahiko Yoshimoto

    In most research work for sensor network routings, perfect aggregation has been assumed. Such an assumption might limit the application of the wireless sensor networks. We address the impact of aggregation efficiency on energy consumption in the context of GIT routing. Our questions are how the most efficient aggregation point changes according to aggregation efficiency and the extent to which energy consumption can decrease compared to the original GIT routing and opportunistic routing. To answer these questions, we analyze a two-source model, which yields results that lend insight into the impact of aggregation efficiency. Based on analytical results, we propose an improved GIT "aggregation efficiency-aware GIT," or AGIT. We also consider a suppression scheme for exploratory messages: "hop exploratory." Our simulation results show that the AGIT routing saves the energy consumption of the data transmission compared to the original GIT routing and opportunistic routing.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2006年10月, IEICE TRANSACTIONS ON COMMUNICATIONS, E89B (10), 2741 - 2751, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Hiroshi Kawaguchi, Shingo Iba, Yusaku Kato, Tsuyoshi Sekitani, Takao Someya, Takayasu Sakurai

    This paper describes a sheet-type scanner and its circuits. The three-dimensional-stacked sheets comprise of two organic-transistor sheets and one organic-photodiode sheet, which enable double-wordline and double-bitline structure. The operation was compared with the conventional single-wordline and single-bitline scheme, and confirmed by measurement. The double-wordline and double-bitline structure reduces the line delay and power by a factor of five and seven, respectively. A new dynamic decoder reduces active leakage current, to which the cut-and-paste customization can be applied.

    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2006年10月, IEEE SENSORS JOURNAL, 6 (5), 1209 - 1217, 英語

    [査読有り]

    研究論文(学術雑誌)

  • しきい値電圧ばらつきを克服したDVS環境下における0.3V動作SRAMの開発

    野口紘希, 森田泰弘, 藤原英弘, 川上健太郎, 宮越純一, 三上真司, 新居浩二, 川口 博, 吉本 雅彦

    2006年08月, 電子情報通信学会技術研究報告, ICD2006-106Vol.106No.206pp.155, 日本語

    研究論文(国際会議プロシーディングス)

  • 消費電力を50%削減する動的電圧/周波数制御型H.264

    川上健太郎, 竹村淳, 黒田光彦, 川口 博, 吉本 雅彦

    2006年06月, 電子情報通信学会技術研究報告, ICD-2006-45 Vol.106 No.92 pp.3, 日本語

    研究論文(国際会議プロシーディングス)

  • A Vth-Variation-Tolerant SRAM with 0.3-V Minimum Operation Voltage for Memory-Rich SoC under DVS Environment

    MORITA Yasuhiro, FUJIWARA Hidehiro, NOGUCHI Hiroki, KAWAKAMI Kentaro, MIYAKOSHI Junichi, MIKAMI Shinji, NII Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

    2006年06月, 2006 Symposium on VLSI Circuits Digest of Technical Papers, pp.16-17, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • An Energy-Harvesting Wireless-Interface SoC for Short-Range Data Communication

    MIKAMI Shinji, MATSUNO Tetsuro, MIYAMA Masayuki, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko, ONO Hiroaki

    2006年05月, IEEJ Trans. Electronics Information Systems, Vol.126 No.5 pp.565-570, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Koichi Ishida, Kouichi Kanda, Atit Tamtrakarn, Hiroshi Kawaguchi, Takayasu Sakurai

    The analog T-switch (AT-switch) scheme is introduced to suppress subthreshold-leakage problems in charge-based analog circuits such as switched capacitors and sample-and-hold circuits. A 0.5-V sigma-delta modulator is manufactured in a 0.15-μm FD-SOI process with low VTH of 0.1 V using the concept. The scheme is compared with another leakage-suppression scheme based on super cut-off CMOS (SCCMOS) and the conventional circuit which are also fabricated. The sigma-delta modulator based on AT-switch greatly improves 8.1-dB SNDR through reducing nonlinear leakage effects while the modulator based on SCCMOS improves the dynamic range rather than the SNDR by comparing with the conventional sigma-delta modulator © 2006 IEEE.

    2006年04月, IEEE Journal of Solid-State Circuits, 41 (4), 859 - 866, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • 定期情報収集型センサネットワークのためのRTS/CTS交換に基づくデータ送信スケジューリング

    松田隆志, 一圓真澄, 三上真司, 太田 能, 川口 博, 吉本 雅彦

    2006年04月, 電子情報通信学会技術研究報告, NS2006-7Vol.106No.14pp.25-28, 日本語

    研究論文(国際会議プロシーディングス)

  • 送信電力制御による効率劣化の影響

    三上真司, 竹内隆, 川口 博, 太田 能, 吉本 雅彦

    2006年04月, 電子情報通信学会技術研究報告, NS2006-4Vol.106No.14pp.13-16, 日本語

    研究論文(国際会議プロシーディングス)

  • 製造ばらつきを考慮したセンサネットワークノード消費電力モデルの提案と評価

    竹内隆, 芳野宏徳, 一圓真澄, 松田隆志, 三上真司, 太田 能, 川口 博, 吉本 雅彦

    2006年04月, 電子情報通信学会技術研究報告, NS2006-6Vol.106No.14pp.21-24, 日本語

    研究論文(国際会議プロシーディングス)

  • センサネットワークのための長波帯標準電波時刻同期を用いた周期起動型MACの提案

    一圓真澄, 竹内隆, 三上真司, 川口 博, 太田 能, 吉本 雅彦

    2006年04月, 電子情報通信学会技術研究報告, NS2006-8Vol.106No.14pp.29-32, 日本語

    研究論文(国際会議プロシーディングス)

  • センサネットワークのための集約率を考慮したGIT経路制御の評価

    青西孝文, 芳野宏徳, 三上真司, 太田 能, 川口 博, 吉本 雅彦

    2006年04月, 電子情報通信学会技術研究報告, NS2006-9Vol.106No.14pp.33-36, 日本語

    研究論文(国際会議プロシーディングス)

  • KS Min, HD Choi, HY Choi, H Kawaguchi, T Sakurai

    As a candidate for the clock-gating scheme, Zigzag Super Cut-off CMOs (ZSCCMOS) has proposed to reduce not only the switching power but also the leakage power. Due to its fast wakeup nature, the ZSCCMOs can be best suited to the clock-gating scheme. The wakeup time of the ZSCCMOS is estimated to be 12 times faster than the conventional Super Cut-off CMOs (SCCMOS) in 70-nm process technology. From the measurement of wakeup time in 0.6-mu m technology, it is observed to be eight times faster than the conventional scheme. Layout area, power, and delay overhead of the ZSCCMOS are discussed and analyzed in this paper.

    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2006年04月, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 14 (4), 430 - 435, 英語

    [査読有り]

    研究論文(学術雑誌)

  • An Architecture Study of Scalable Optical-Flow Processor for Real-Time Video Segmentation

    YAMAMOTO Ryo, FUKAYAMA Yuuki, KATAGIRI Tadayoshi, MIYAKOSHI Junichi, KURODA Yuki, MINEGISHI Noriyuki, MIYAMA Masayuki, KAWAGUCHI Hiroshi, IMAMURA Kosuke, HASHIMOTO Hideo, YOSHIMOTO Masahiko

    2006年04月, Proc. IEEE Symposium on Low-Power High-Speed Chips (COOL Chips IX), pp. 225-240, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • DD Antono, K Inagaki, H Kawaguchi, T Sakurai

    This paper discusses propagation delay error, transient response, and power consumption distribution due to inductive effects in optimal buffered on-chip interconnects. Inductive effect is said to be important to consider in deep submicron (DSM) VLSI design. However, study shows that the effect decreases and can be neglected in next technology nodes for such conditions.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2006年03月, IEICE TRANSACTIONS ON ELECTRONICS, E89C (3), 392 - 394, 英語

    [査読有り]

    研究論文(学術雑誌)

  • An Organic FET SRAM for Braille Sheet Display with Back Gate to Increase Static Noise Margin

    TAKAMIYA Makoto, SEKITANI Tsuyoshi, KATO Yusaku, KAWAGUCHI Hiroshi, SOMEYA Takao, SAKURAI Takayasu

    2006年02月, IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 276-277

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Tsuyoshi Sekitani, Makoto Takamiya, Yoshiaki Noguchi, Shintaro Nakano, Yusaku Kato, Kazuki Hizu, Hiroshi Kawaguchi, Takayasu Sakurai, Takao Someya

    We have successfully manufactured a large-area power transmission sheet by using printing technologies. The position of electronic objects on this sheet can be contactlessly sensed by electromagnetic coupling using an organic transistor active matrix. Power is selectively fed to the objects by an electromagnetic field using a plastic MEMS-switching matrix.

    2006年, Technical Digest - International Electron Devices Meeting, IEDM, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Kohei Onizuka, Hiroshi Kawaguchi, Makoto Takamiya, Tadahiro Kuroda, Takayasu Sakurai

    A chip-to-chip inductive wireless power transmission system is proposed and the feasibility is experimentally demonstrated for the first time. The circuit realized 2.5mW power transmission at the output DC voltage of 0.5V using 700×700μm on-chip planar inductors for the transmitter and the receiver. Methods to optimize the circuit design about the maximum transmission power and the simulated optimization results are discussed. © 2006 IEEE.

    2006年, Proceedings of the Custom Integrated Circuits Conference, 575 - 578, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Kohei Onizuka, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai

    An on-chip buck converter which is implemented by stacking chips and which is suitable for on-chip distributed power supply systems is proposed and the operation is experimentally verified for the first time. The manufactured converter achieves the maximum power efficiency of 62% for an output current of 70mA with a switching frequency of 200MHz with a 2×2mm on-chip LC output filter. The active part and the passive LC output filter are implemented on separate chips fabricated in 0.35-μm CMOS and connected with metal bumps. The optimization and improvement of the power efficiency and implementation structure are also discussed. © 2006 IEEE.

    2006年, 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006, 127 - 130, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Hidetoshi Onodera, Makoto Ikeda, Tohru Ishihara, Tsuyoshi Isshiki, Koji Inoue, Kenichi Okada, Seiji Kajihara, Mineo Kaneko, Hiroshi Kawaguchi, Shinji Kimura, Morihiro Kuga, Atsushi Kurokawa, Takashi Sato, Toshiyuki Shibuya, Yoichi Shiraishi, Kazuyoshi Takagi, Atsushi Takahashi, Yoshinori Takeuchi, Nozomu Togawa, Hiroyuki Tomiyama, Yuichi Nakamura, Kiyoharu Hamaguchi, Yukiya Miura, Shin-Ichi Minato, Ryuichi Yamaguchi, Masaaki Yamada, Yasushi Yuminaka, Takayuki Watanabe, Masanori Hashimoto, Masayuki Miyazaki

    Institute of Electronics, Information and Communication, Engineers, IEICE, 2006年, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E89-A (12), 3377, 英語

    [査読有り]

    研究論文(学術雑誌)

  • T. Someya, T. Sekitani, S. Iba, Y. Kato, T. Sakurai, H. Kawaguchi

    It is believed that skin sensitivity will be important for future robots working in our daily life for home-care and entertainment purposes. However, relatively little progress has been made in the field of pressure recognition compared to the areas of sight and voice recognition, mainly because good artificial "electronic skin with a large area and mechanical flexibility is not yet available. The fabrication of a sensitive skin consisting of thousands of pressure sensors would require a flexible switching matrix that cannot be realized with present silicon-based electronics. Organic field-effect transistors can be used complimentary to such conventional electronics because organic circuits are inherently flexible and potentially ultra-low in cost even for large area. In this paper, we describe that integration of organic transistors and rubber pressure sensors provides an ideal solution to realize a practical artificial skin.

    2006年, Molecular Crystals and Liquid Crystals, 444, 13 - 22, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Canh Quang Tran, Hiroshi Kawaguchi, Takayasu Sakurai

    A low-power FPGA design approach is proposed based on a fine-grain V(DD) control scheme called micro-V(DD)-hopping. Four configurable logic blocks (CLBs) are grouped into one block where V(DD) is shared. In the micro-V(DD)-hopping scheme, V(DD) in each block is changed between V(DDH) (high V(DD)) and V(DDL) (low V(DD)) spatially and temporally in order to achieve lower power without performance degraded. A low-power level shifter that has less contention is also proposed for low-swing inter-block signals. The FPGA incorporates the Zigzag power-gating scheme, in which special care has been taken to cope with a sneak leakage-path problem. A test chip was fabricated using a 0.35-μm CMOS technology, together with the conventional fixed-V(DD) FPGA for comparison. Measurement results show that dynamic power in the proposed scheme can be reduced by 86% when a frequency is half of the maximum one. Simulation using a 90-nm CMOS technology shows that leakage power can be reduced by 97%, when the proposed method is used. The area overhead of the proposed FPGA is 2%. Copyright © 2006 The Institute of Electronics, Information and Communication Engineers.

    Institute of Electronics, Information and Communication, Engineers, IEICE, 2006年, IEICE Transactions on Electronics, E89-C (3), 280 - 286, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Isochronous MAC using long-wave standard time code for wireless sensor networks

    Masumi Ichien, Takashi Takeuchi, Shinji Mikami, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

    This paper proposes Isochronous-MAC (I-MAC), which utilizes low-frequency radio waves time synchronization for sensor networks. Using INIAC, based on the Low Power Listening (LPL), all sensor nodes wake and listen channel periodically and synchronously. Since a sender can easily predict wakeup time of an intended receiver, it can shorten the length of preamble to make the receiver prepare for reception of the following data packet. This saves power consumption for the sender to rendezvous with the receiver. In the paper, we use an analytical model to investigate the impact of the data transmission frequency, the number of neighboring nodes, the wakeup period, the clock drift, and the time-synchronization frequency on the power consumption for consideration of the power overhead to perform the time synchronization. Those results demonstrate that I-MAC allows determination of any arbitrary wakeup period without much difficulty, whereas LPL requires a much more careful setting of the wakeup period because its optimum wakeup period is sensitive to the frequency of data transmission as well as to the number of neighboring nodes. Therefore, IMAC has a great potential to reduce the power consumption in most situations compared with LPL, in spite of the overhead to perform time synchronization.

    IEEE, 2006年, 2006 FIRST INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND ELECTRONICS, 172 - +, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • S Iba, Y Kato, T Sekitani, H Kawaguchi, T Sakurai, T Someya

    Inverter circuits have been made by connecting two high-quality pentacene field-effect transistors. A uniform and pinhole-free 900 nm thick polyimide gate-insulating layer was formed on a flexible polyimide film with gold gate electrodes and partially removed by using a CO2 laser drilling machine to make via holes and contact holes. Subsequent evaporation of the gold layer results in good electrical connection with a gold gate layer underneath the gate-insulating layer. By optimization of the settings of the CO2 laser drilling machine, contact resistance can be reduced to as low as 3 Omega for 180 mu m square electrodes. No degradation of the transport properties of the organic transistors was observed after the laser-drilling process. This study demonstrates the feasibility of using the laser drilling process for implementation of organic transistors in integrated circuits on flexible polymer films.

    SPRINGER HEIDELBERG, 2006年01月, ANALYTICAL AND BIOANALYTICAL CHEMISTRY, 384 (2), 374 - 377, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Impact of aggregation efficiency on GIT routing for wireless sensor networks

    Takafumi Aonishi, Takashi Matsuda, Shinji Mikami, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

    In most research work for sensor network routings, perfect aggregation has been assumed. Such an assumption might limit the application of the wireless sensor networks. We address the impact of aggregation efficiency on energy consumption in the context of GIT routing. Our questions are how the most efficient aggregation point changes according to aggregation efficiency and the extent to which energy consumption can decrease compared to the original GIT routing and opportunistic routing. To answer these questions, we analyze a two-source model, which yields results that lend insight into the impact of aggregation efficiency. Based on analytical results, we propose an improved GIP "aggregation efficiency-aware GIT", or AGIT We also consider a suppression scheme for exploratory messages: "hop exploratory," Our simulation results show that the AGIT routing saves the energy consumption of the data transmission compared to the original GIT routing and opportunistic routing.

    IEEE COMPUTER SOC, 2006年, 2006 INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING WORKSHOPS, PROCEEDINGS, pp.00-00, 151 - +, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering

    Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto

    We propose a low-power two-port SRAM suitable for real-time video processing. In order to minimize discharge power on a read bitline, a majority-logic decides if input data are inverted in a write cycle, so that "1"s are in the majority. In video data, since more significant bits of adjacent pixel data are fortunately lopsided to either "0" or "1" with higher probability, the data bits in the pixels are reordered in each digit group to exploit the majority logic. The speed and area overheads are 4% and 11% in a 90-nm process technology, respectively. The proposed SRAM achieves 53% power reduction on the bitlines, and saves 43% of a total power when considered as an H.264 reconstructed-image memory.

    ASSOC COMPUTING MACHINERY, 2006年, ISLPED '06: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, pp.61-66, 61 - 66, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A power-variation model for sensor node and the impact against life time of wireless sensor networks

    Takashi Matsuda, Takashi Takeuchi, Hironori Yoshino, Masumi Ichien, Shinji Mikami, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

    We introduce manufacturing variation into a power model for a wireless sensor network node. Network protocols for the wireless sensor networks such as media access control and routing should be evaluated in terms of life time in a whole system. In fact, there exists power variation node by node due to the manufacturing variation. In the previous researches, however, this effect has not been investigated at all since it has been supposed that all nodes have a same power. In this paper, we develop a power model for a sensor node, in which we consider threshold-voltage variation derived from a manufacturing process. We take both a microprocessor and an RF part into account for the model, and implement it to QualNet in order to evaluate the impact against a life time of a wireless sensor network. The simulation results show that the conventional model has overestimated the life time longer than our model when nodes are randomly deployed. In contrast, if we make an optimum deployment of nodes by exploiting the power variation, the network life time is extended by 12.7% compared to the case of the conventional model.

    IEEE, 2006年, 2006 FIRST INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND ELECTRONICS, pp.106-111, 106 - +, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A power- and area-efficient SRAM core architecturt for super-parallel video processing

    Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto, Tetsuro Matsuno

    super-parallel video processing, we proposed a power- and area-efficient SRAM core architecture with a segmentation-free access, which means accessibility to arbitrary consecutive pixels, and horizontal/vertical access. To achieve these flexible accesses, a spirally-connected local-wordline select signal and multi-selection scheme in wordlines are proposed, so that extra X-decoders in the conventional muld-division SRAM can be eliminated. Consequently, the proposed SRAM reduces an area and power by 69% and 59%, respectively, when it is applied to a 128 parallel architecture. The proposed 160-kbit SRAM with 16-read ports (eight-division and 2-read port SRAM) is implemented to a search window buffer for an H.264 motion estimation processor core which dissipates 800 mu W for QCIF 15-fps in a 130-nm technology.

    IFIP-INT FEDERATION INFORMATION PROCESSING, 2006年, IFIP VLSI-SOC 2006: IFIP WG 10.5 INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION & SYSTEM-ON-CHIP, pp.192-197, 192 - +, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • T Someya, Y Kato, S Iba, Y Noguchi, T Sekitani, H Kawaguchi, T Sakurai

    A large-area, flexible, and lightweight sheet image scanner has been successfully manufactured on a plastic film by integrating high-quality organic transistors and organic photodetectors. The effective sensing area of the integrated device is 5 x 5 cm(2); the resolution, 36 dots per inch (dpi); and the total number of sensor cells, 5184. The pentacene transistors with top contact geometry have a channel length of 18 mu m and mobility of 0.7 cm(2)/Vs. Organic photodetectors composed of copper phthalocyanine and 3,4,9,10-peryiene-tetracarboxylic-diimide distinguish between black and white parts on paper based on the difference in their reflectivity. Since this new area-type image-capturing device does not require any optics or mechanical scanning devices, the present sheet image scanners are mechanically flexible, lightweight, shock resistant, and potentially inexpensive to manufacture; therefore, they are suitable for human-friendly mobile electronics.

    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2005年11月, IEEE TRANSACTIONS ON ELECTRON DEVICES, 52 (11), 2502 - 2511, 英語

    [査読有り]

    研究論文(学術雑誌)

  • センサネットワークのための集約率を考慮したGIT経路制御の評価

    青西孝文, 芳野宏徳, 三上真司, 太田 能, 川口 博, 吉本 雅彦

    2005年10月, 電子情報通信学会技術研究報告;NS2005-108, Vol.105; No.357; pp.37-40, 日本語

    研究論文(国際会議プロシーディングス)

  • ワイヤレスセンサノードのための送信電力制御におけるインピーダンス不整合の影響

    三上真司, 竹内隆, 太田 能, 川口 博, 吉本 雅彦

    2005年09月, 2005年電子情報通信学会ソサイエティ大会;B-5-148, p.148, 日本語

    研究論文(国際会議プロシーディングス)

  • (Invited) Recent Progress of Organic Transistor Integrated Circuits for Large-Area Sensor Applications

    SOMEYA Takao, SAKURAI Takayasu, SEKITANI Tsuyoshi, KAWAGUCHI Hiroshi, IBA Shingo, KATO Yusaku, NOGUCHI Yoshiaki

    2005年09月, Proceedings of International Conference on Solid State Devices and Materials (SSDM), pp. 380-381

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • T Someya, Y Kato, T Sekitani, S Iba, Y Noguchi, Y Murase, H Kawaguchi, T Sakurai

    Skin-like sensitivity, or the capability to recognize tactile information, will be an essential feature of future generations of robots, enabling them to operate in unstructured environments. Recently developed large-area pressure sensors made with organic transistors have been proposed for electronic artificial skin (E-skin) applications. These sensors are bendable down to a 2-mm radius, a size that is sufficiently small for the fabrication of human-sized robot fingers. Natural human skin, however, is far more complex than the transistor-based imitations demonstrated so far. It performs other functions, including thermal sensing. Furthermore, without conformability, the application of E-skin on three-dimensional surfaces is impossible. In this work, we have successfully developed conformable, flexible, large-area networks of thermal and pressure sensors based on an organic semiconductor. A plastic film with organic transistor-based electronic circuits is processed to form a net-shaped structure, which allows the E-skin films to be extended by 25%. The net-shaped pressure sensor matrix was attached to the surface of an egg, and pressure images were successfully obtained in this configuration. Then, a similar network of thermal sensors was developed with organic semiconductors. Next, the possible implementation of both pressure and thermal sensors on the surfaces is presented, and, by means of laminated sensor networks, the distributions of pressure and temperature are simultaneously obtained.

    NATL ACAD SCIENCES, 2005年08月, PROCEEDINGS OF THE NATIONAL ACADEMY OF SCIENCES OF THE UNITED STATES OF AMERICA, 102 (35), 12321 - 12325, 英語

    [査読有り]

    研究論文(学術雑誌)

  • S Iba, T Sekitani, Y Kato, T Someya, H Kawaguchi, M Takamiya, T Sakurai, S Takagi

    We fabricated pentacene field-effect transistors with planar-type double-gate structures, where the top- and bottom-gate electrodes can independently apply voltage biases to channel layers. The threshold voltage of organic transistors is changed systematically in a wide range from -16 to -43 V when the voltage bias of the top-gate electrode is changed from 0 to +60 V. The mobility in the linear regime is almost constant (0.2 cm(2)/V s) at various voltage biases of the top-gate electrode and the on/off ratio is 10(6). (c) 2005 American Institute of Physics.

    AMER INST PHYSICS, 2005年07月, APPLIED PHYSICS LETTERS, 87 (2), 英語

    [査読有り]

    研究論文(学術雑誌)

  • Frequency-Voltage Cooperative CPU Power Control: A Design Rule and Its Application by Feedback Prediction

    TOYAMA Keisuke, MISAKA Satoshi, AISAKA Kazuo, ARITSUKA Toshiyuki, UCHIYAMA Kunio, ISHIBASHI Koichiro, KAWAGUCHI Hiroshi, SAKURAI Takayasu

    2005年06月, Systems and Computers in Japan, vol. 36, no. 6, pp. 39-48

    [査読有り]

    研究論文(学術雑誌)

  • Time Revising Robust Frequency-Voltage Cooperative Power Reduction for Multi-tasking Multimedia Applications

    MISAKA Satoshi, KAWAGUCHI Hiroshi, SAKURAI Takayasu

    2005年04月, IEEE International Symposium on Low-Power and High-Speed Chips (COOL Chips), pp. 165-180

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Hiroshi Kawaguchi, Youngsoo Shin, Takayasu Sakurai

    This paper presents a cooperative dynamic power management method and its implementation. The implementation consists of design of a real-time OS, applications including MPEG-4, and development of a supporting hardware platform with an off-the-shelf processor. We describe several factors that are important in the implementation and discuss its efficiency through experiment. The experimental results with the prototype system shows that 74% power saving is possible in multi-task multimedia environment.

    2005年02月, IEEE Transactions on Multimedia, 7 (1), 67 - 74, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Canh Q. Tran, Hiroshi Kawaguchi, Takayasu Sakurai

    A leakage current reduction scheme based on ZSCCMOS (zigzag super cutoff CMOS) is proposed for a LUT (look-up table ) using input forcing and an overdriven power gates. A fabricated chip demonstrates that the leakage current of the LUT can be reduced by more than 2 orders of magnitude. The wake-up time of the proposed LUT is 10 times as short as that of the LUT using SCCMOS (super cutoff CMOS). The area and delay overheads are 15% and 8%, respectively. © 2005 IEEE.

    2005年, Proceedings - IEEE International Symposium on Circuits and Systems, 4701 - 4704, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • K. Ishida, K. Kanda, A. Tamtrakarn, H. Kawaguchi, T. Sakurai

    A subthreshold-leakage suppressed switched capacitor (SC) circuit based on super cut-off CMOS (SCCMOS) scheme is introduced. This scheme realizes low-voltage SC circuits using low threshold voltage (VTH) transistors which are superior in drivability and are compatible with digital circuits. The SC circuit cannot be operated under 0.5V with high-VTH devices but on the other hand, SC circuits with low-VTH transistors suffer from charge loss even in analog operations. A 0.5-V sigma-delta modulator with the proposed scheme is successfully manufactured and measured by using 0.15-μm FD-SOI process with 0.1-V VTHN transistors. © 2005 IEEE.

    2005年, Proceedings - IEEE International Symposium on Circuits and Systems, 3119 - 3122, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Kyeong-Sik Min, Kouichi Kanda, Hiroshi Kawaguchi, Kenichi Inagaki, Fayez Robert Saliba, Hoon-Dae Choi, Hyun-Young Choi, Daejeong Kim, Dong Myong Kim, Takayasu Sakurai

    A new Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) scheme is proposed to suppress leakage current by two orders of magnitude in the SRAM's for sub-70 nm process technology with sub-1-V V(DD) [10]. This two-order leakage reduction is caused from the cooperation of reverse body-to-source biasing and Drain Induced Barrier Lowering (DIBL) effects. In addition, metal shields are proposed to be inserted between the cell nodes and the bit lines not to allow the cell nodes to be flipped by the external bit-line coupling noise in this paper. A test chip has been fabricated to verify the effectiveness of the RRDSV scheme with the metal shields by using 0.18-μm CMOS process. The retention voltages of SRAM's with the metal shields are measured to be improved by as much as 40-60 mV without losing the stored data compared to the SRAM's without the shields. Copyright © 2005 The Institute of Electronics, Information and Communication Engineers.

    Institute of Electronics, Information and Communication, Engineers, IEICE, 2005年, IEICE Transactions on Electronics, E88-C (4), 760 - 767, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Hiroshi Kawaguchi, Takao Someya, Tsuyoshi Sekitani, Takayasu Sakurai

    The concept of cut-and-paste customization is introduced for the first time in designing integrated circuits based on mechanically flexible organic field-effect transistors, and is applied to electronic artificial skin. The electronic artificial skin comprise of three separate integrated circuits that are a pressure-sensor array, row decoders, and column selectors to read out pressure information over a large area. All of three integrated circuits are scalable in size because the pressure-sensor array is a simple repetition of sensor cells and the row and column decoders adopt wired-NAND circuits, which enables the cut-and-paste customization in size. The physical cut-and-paste procedure is employed by cutting a part of the integrated circuits and pasting it to another integrated circuit with a connecting plastic tape. The integrated circuits are designed with a standard SPICE simulator and layout design tool, and the operation is confirmed by measurement.

    2005年01月, IEEE Journal of Solid-State Circuits, 40 (1), 177 - 185, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Subthreshold-leakage suppressed switched capacitor circuit based on super cut-off CMOS (SCCMOS)

    K Ishida, K Kanda, A Tamtrakarn, H Kawaguchi, T Sakurai

    A subthreshold-leakage suppressed switched capacitor (SC) circuit based on super cut-off CMOS (SCCMOS) scheme is introduced. This scheme realizes low-voltage SC circuits using low threshold voltage (V(TH)) transistors which are superior in drivability and are compatible with digital circuits. The SC circuit cannot be operated under 0.5V with high-V(TH) devices but on the other hand, SC circuits with low-V(TH) transistors suffer from charge loss even in analog operations. A 0.5-V sigma-delta modulator with the proposed scheme is successfully manufactured and measured by using 0.15-mu m FD-SOI process with 0.1-V V(THN) transistors.

    IEEE, 2005年, 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, pp. 3119-3122, 3119 - 3122, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • More than two orders of magnitude leakage current reduction in look-up table for FPGA's

    CQ Tran, H Kawaguchi, T Sakurai

    A leakage current reduction scheme based on ZSCCMOS (Zigzag super cutoff CMOS) is proposed for a LUT (look-up table) using input forcing and an overdriven power gates. A fabricated chip demonstrates that the leakage current of the LUT can be reduced by more than 2 orders of magnitude. The wake-up time of the proposed LUT is 10 times as short as that of the LUT using SCCMOS (super cutoff CMOS). The area and delay overheads am 15% and 8%, respectively.

    IEEE, 2005年, 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, pp. 4701-4704, 4701 - 4704, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Low-power high-speed level shifter design for block-level dynamic voltage scaling environment

    CQ Tran, H Kawaguchi, T Sakurai

    Two novel level shifters that are suitable for block-level dynamic voltage scaling environment (namely, V-DD-hopping) are proposed. In order to achieve reduction in power consumption and delay, the first proposed level shifter which is called Contention Mitigated Level Shifter (CMLS) uses a contention-reduction technique. The simulation results with 65-nm CMOS model show 24% reduction in power and 50% decrease in delay with 4% area increase compared with the conventional level shifter. The second proposed level shifter which is called Bypassing Enabled Level Shifter (BELS) implements a bypass function and it is fabricated using 035pm CMOS technology. The measurement results show that the power and delay of the proposed BELS are reduced by 50% and 65%, respectively with 60% area overhead over the conventional level shifter.

    IEEE, 2005年, 2005 International Conference on Integrated Circuit Design and Technology, pp. 229-232, 229 - 232, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Recent advances in applications of organic integrated circuits for large-area electronics

    T Someya, T Sakurai, T Sekitani, H Kawaguchi, S Iba, Y Kato

    IEEE, 2005年, 2005 International Conference on Integrated Circuit Design and Technology, pp. 57-58, 57 - 58, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Managing leakage in charge-based analog circuits with low-V-TH transistors by analog T-switch (AT-switch) and super cut-off CMOS

    K Ishida, K Kanda, A Tamtrakarn, H Kawaguchi, T Sakurai

    Analog T-switch scheme is introduced to suppress subthreshold-leakage problems in charge-based analog circuits such as switched capacitor and sample and hold circuits. A 0.5-V sigma-delta modulator is manufactured in a 0.15-mu m FD-SOI process with low V-TH of 0.1V using the concept. The scheme is compared with another leakage suppressed scheme based on Super Cut-off CMOS (SCCMOS) and the conventional circuit which are also fabricated. The sigma-delta modulator based on analog T-switch realizes 6-bit resolution through reducing non-linear leakage effects while the conventional circuit and the scheme based on SCCMOS can achieve 4-bit and 5-bit resolution, respectively.

    JAPAN SOCIETY APPLIED PHYSICS, 2005年, 2005 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 122-125, 122 - 125, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Experimental verification of row-by-row variable V-DD scheme reducing 95% active leakage power of SRAM's

    FR Saliba, H Kawaguchi, T Sakurai

    Low-power SRAM has become a critical component in recent VLSI systems. This paper reports an SRAM reducing 95% of active leakage power. The SRAM is successfully implemented and reliably measured for the first time, with self-aligned timing generation to avoid malfunction during V-DD transition. The cycle time overhead is 9%, and the area overhead is 3.5%.

    JAPAN SOCIETY APPLIED PHYSICS, 2005年, 2005 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 162-165, 162 - 165, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Pocket scanner using organic transistors and detectors

    T Someya, T Sakurai, T Sekitani, H Kawaguchi, Y Kato, S Iba

    A pocket scanner has been manufactured by integrating high-quality organic transistors with organic photodetectors. Because the pocket scanner requires no mechanical components, it is mechanically flexible, light to transport, shock-resistant and potentially inexpensive to manufacture.

    IEEE, 2005年, 2005 IEEE LEOS Annual Meeting Conference Proceedings (LEOS), pp. 59-60, 59 - 60, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • 95% Leakage-reduced FPGA using zigzag power-gating, dual-V(TH)/V(DD) and micro-VDD-hopping

    Canh Q. Tran, Hiroshi Kawaguchi, Takayasu Sakurai

    Low-power FPGA architecture is proposed based on fine-grained V(DD) control scheme called micro-V(DD)-hopping. Four Configurable Logic Blocks (CLB) are grouped into one block where V(DD) is shared. In the micro-V(DD)-hopping scheme, V(DD) of each block is varied between the higher V(DD) (V(DDH)) and the lower V(DD) (V(DDL)) spatially and temporally to achieve lower power, while keeping performance undegraded. A level shifter that has less contention is proposed. The FPGA also incorporates Zigzag power-gating scheme, special care has been taken to cope with sneak leakage path problem. The proposed FPGA is fabricated using 035 mu m CMOS technology together with the conventional fixed-V(DD) FPGA. Measurement shows that the dynamic power can be reduced by 86% when the required speed is half of the highest speed. Simulation using 90nm CMOS technology shows that a leakage power reduction of 95% can be achieved, when the proposed method is used. Area overhead of the proposed FPGAs 2%.

    IEEE, 2005年, 2005 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS, pp. 149-152, 149 - 152, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • A flexible, lightweight Braille sheet display with plastic actuators driven by an organic field-effect transistor active matrix

    Y Kato, S Iba, T Sekitani, Y Noguchi, K Hizu, XZ Wang, K Takenoshita, Y Takamatsu, S Nakano, K Fukuda, K Nakamura, T Yamaue, M Doi, K Asaka, H Kawaguchi, M Takamiya, T Sakurai, T Someya

    A flexible, shock-resistant, and lightweight Braille sheet display has been successfully manufactured on a plastic film by integrating a plastic sheet actuator array with a high-quality organic transistor active matrix. This is the first demonstration, to the best of our knowledge, to integrate plastic MEMS (microelectromechanical systems) actuators with organic transistor active matrices, which opens up new versatile possibilities for flexible, large-area electronic applications including tactile displays.

    IEEE, 2005年, IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST, pp. 105-108, 105 - 108, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • 95% Leakage-reduced FPGA using zigzag power-gating, dual-V(TH)/V(DD) and micro-VDD-hopping

    Canh Q. Tran, Hiroshi Kawaguchi, Takayasu Sakurai

    Low-power FPGA architecture is proposed based on fine-grained V(DD) control scheme called micro-V(DD)-hopping. Four Configurable Logic Blocks (CLB) are grouped into one block where V(DD) is shared. In the micro-V(DD)-hopping scheme, V(DD) of each block is varied between the higher V(DD) (V(DDH)) and the lower V(DD) (V(DDL)) spatially and temporally to achieve lower power, while keeping performance undegraded. A level shifter that has less contention is proposed. The FPGA also incorporates Zigzag power-gating scheme, special care has been taken to cope with sneak leakage path problem. The proposed FPGA is fabricated using 035 mu m CMOS technology together with the conventional fixed-V(DD) FPGA. Measurement shows that the dynamic power can be reduced by 86% when the required speed is half of the highest speed. Simulation using 90nm CMOS technology shows that a leakage power reduction of 95% can be achieved, when the proposed method is used. Area overhead of the proposed FPGAs 2%.

    IEEE, 2005年, 2005 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS, vol. E89-C, no. 3, pp. 280-286, 149 - 152, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Managing leakage in charge-based analog circuits with low-V-TH transistors by analog T-switch (AT-switch) and super cut-off CMOS

    K Ishida, K Kanda, A Tamtrakarn, H Kawaguchi, T Sakurai

    Analog T-switch scheme is introduced to suppress subthreshold-leakage problems in charge-based analog circuits such as switched capacitor and sample and hold circuits. A 0.5-V sigma-delta modulator is manufactured in a 0.15-mu m FD-SOI process with low V-TH of 0.1V using the concept. The scheme is compared with another leakage suppressed scheme based on Super Cut-off CMOS (SCCMOS) and the conventional circuit which are also fabricated. The sigma-delta modulator based on analog T-switch realizes 6-bit resolution through reducing non-linear leakage effects while the conventional circuit and the scheme based on SCCMOS can achieve 4-bit and 5-bit resolution, respectively.

    JAPAN SOCIETY APPLIED PHYSICS, 2005年, 2005 Symposium on VLSI Circuits, Digest of Technical Papers, vol.41:no. 4:pp. 859-867, 122 - 125, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Takao Someya, Tsuyoshi Sekitani, Shingo Iba, Yusaku Kato, Hiroshi Kawaguchi, Takayasu Sakurai

    It is now widely accepted that skin sensitivity will be very important for future robots used by humans in daily life for housekeeping and entertainment purposes. Despite this fact, relatively little progress has been made in the field of pressure recognition compared to the areas of sight and voice recognition, mainly because good artificial "electronic skin" with a large area and mechanical flexibility is not yet available. The fabrication of a sensitive skin consisting of thousands of pressure sensors would require a flexible switching matrix that cannot be realized with present silicon-based electronics. Organic field-effect transistors can substitute for such conventional electronics because organic circuits are inherently flexible and potentially ultralow in cost even for a large area. Thus, integration of organic transistors and rubber pressure sensors, both of which can be produced by low-cost processing technology such as large-area printing technology, will provide an ideal solution to realize a practical artificial skin, whose feasibility has been demonstrated in this paper. Pressure images have been taken by flexible active matrix drivers with organic transistors whose mobility reaches as high as 1.4 cm2/V·s. The device is electrically functional even when it is wrapped around a cylindrical bar with a 2-mm radius.

    2004年07月06日, Proceedings of the National Academy of Sciences of the United States of America, 101 (27), 9966 - 9970, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Yusaku Kato, Shingo Iba, Ryohei Teramoto, Tsuyoshi Sekitani, Takao Someya, Hiroshi Kawaguchi, Takayasu Sakurai

    The fabrication of high-quality pentacene field-effect transistors on polyethylenenaphthalate (PEN) films with polyimide gate dielectric layers was investigated. It was observed from atomic force microscopy measurements that the surface roughness of the gate dielectric layer was 0.2 nm, while of the base film was 1 nm. The on/off ratio and mobility of the transistors with pentacene channel layers, which were deposited on 990 nm polyimide gate dielectric layers, were 106 and 0.3 cm2/V s respectively. It was also observed that the mobility of the transistors was enhanced up to 1 cm 2/V s by decreasing the thickness of the polyimide gate dielectric layers to 540 nm.

    2004年05月10日, Applied Physics Letters, 84 (19), 3789 - 3791, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Row-by-row dynamic source-line voltage control (RRDSV) scheme for two orders of magnitude leakage current reduction of sub-1-V-V-DD SRAM's

    KS Min, K Kanda, T Sakurai

    A new Row-by-Row Dynamic Source-line Voltage control (RRDSV) scheme is proposed to reduce the active leakage as well as the stand-by leakage in SRAM. By dynamically controlling the source-line voltage of cells row by row, the cell leakage through inactive cells can be reduced by two orders of magnitude. Moreover, the bit-line leakage through pass transistors can be completely cut off. This leakage reduction is caused from the cooperation of reverse body-to-source biasing and Drain Induced Barrier Lowering (DIBL) effects. A test chip has been fabricated using 0.18-mum triple-well CMOS technology to verify the data retention capability of this RRDSV scheme. The minimum retention voltage in the RRDSV is measured to be reduced by more than 60mV, when shielding metal is inserted to protect the memory cell nodes from bit-line coupling noise. It can reduce the leakage by another 50% in addition to the reduction by two orders of magnitude.

    ASSOC COMPUTING MACHINERY, 2003年, ISLPED'03: PROCEEDINGS OF THE 2003 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, vol. E88-C, no. 4, pp. 760-767, 66 - 71, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Koichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi, Seongsoo Lee, Takayasu Sakurai

    In order to suppress the power consumption in low-voltage processors, a threshold voltage hopping (VTH-hopping) scheme is proposed where the threshold voltage is dynamically controlled through software depending on a workload. V TH-hopping is shown to reduce the power to 18% of the fixed low-threshold voltage circuits in 0.5-V supply voltage regime for multimedia applications. A positive back-gate bias scheme with V TH-hopping is presented for the high-performance and low-voltage processors. In order to verify the effectiveness of V TH-hopping, a small-scale RISC processor with V TH-hopping capability and the positive back-gate bias scheme is fabricated in a 0.6-μm CMOS technology. MPEG4 encoding is simulated based on the measured data. The result shows that 86 % power saving can be achieved by using V TH-hopping compared with the fixed positive back-gate bias scheme.

    2002年03月, IEEE Journal of Solid-State Circuits, 37 (3), 413 - 419, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Kouichi Kanda, Takayuki Miyazaki, Mitt Kyeong Sik, Hiroshi Kawaguchi, Takayasu Sakurai

    A novel SRAM scheme is proposed that can reduce the active leakage power by two orders of magnitude. In low voltage region less than IV, the VTH, VTH, is lowered to less than 0.2V and leakage power of memory cells becomes a dominant issue. By dynamically dropping the supply voltage of un-accessed cells row by row, the cell leakage can be reduced exponentially through the Drain Induced Barrier Lowering (DIBL) effect. Additionally, to lower the leakage from bit-line through transfer gates of memory cells, un-accessed word line is applied negative voltage together with reduced swing write technique. The bASIC advantage is verified by measurement and the effectiveness in future generations is discussed by simulations.

    Institute of Electrical and Electronics Engineers Inc., 2002年, Proceedings of the Annual IEEE International ASIC Conference and Exhibit, 2002-, 381 - 385, 英語

    [査読有り]

    研究論文(国際会議プロシーディングス)

  • Kouichi Kanda, Kouichi Nose, Hiroshi Kawaguchi, Takayasu Sakurai

    In Sub-1-V CMOS designs, especially around 0.5-V CMOS designs, on-state drain current of MOSFETs shows positive temperature dependence, being different from the negative temperature dependence in the conventional voltage designs. Combined with low threshold voltage less than 0.2 V, the possibility of temperature instability increases. This paper describes possible temperature instabilities in the low-voltage regime by using circuit simulation environments incorporating temperature change in time and experiments using MOSFETs and the 32-bit adder circuit in quarter-micrometer CMOS technology with a low threshold voltage of 0.25 V.

    2001年10月, IEEE Journal of Solid-State Circuits, 36 (10), 1559 - 1564, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Hiroshi Kawaguchi, Koichi Nose, Takayasu Sakurai

    A super cut-off CMOS (SCCMOS) scheme is proposed and demonstrated by measurement to achieve high-speed and low stand-by current CMOS VLSIs in sub-1-V supply voltage regime. By overdriving the gate of a cut-off MOSFET, the SCCMOS suppresses leakage current below 1 pA per logic gate in a stand-by mode while high-speed operation in an active mode is possible with low-threshold voltage of 0.1-0.2 V. The SCCMOS pushes the low-voltage operation limit 0.2 V further down compared with conventional schemes while maintaining the same stand-by current level.

    IEEE, 2000年10月, IEEE Journal of Solid-State Circuits, 35 (10), 1498 - 1501, 英語

    [査読有り]

    研究論文(学術雑誌)

  • Hiroshi Kawaguchi, Takayasu Sakurai

    A reduced clock-swingflip-flop (RCSFF) is proposed, which is composed of a reduced swing clock driver and a special flip-flop which embodies the leak current cutoff mechanism. The RCSFF can reduce the clock system power of a VLSI down to one-third compared to the conventional flip-flop. This power improvement is achieved through the reduced clock swing down to 1 V. The area and the delay of the RCSFF can also be reduced by a factor of about 20% compared to the conventional flipflop. The RCSFF can also reduce the RC delay of a long RC interconnect to one-half.

    John Wiley and Sons Inc., 1999年01月01日, High-Performance System Design: Circuits and Logic, 349 - 353, 英語

    [査読有り]

    論文集(書籍)内論文

  • Hiroshi Kawaguchi, Takayasu Sakurai

    A reduced clock-swing flip-flop (RCSFF) is proposed, which is composed of a reduced swing clock driver and a special flip-flop which embodies the leak current cutoff mechanism. The RCSFF can reduce the clock system power of a VLSI down to one-third compared to the conventional flip-flop. This power improvement is achieved through the reduced clock swing down to 1 V. The area and the delay of the RCSFF can also be reduced by a factor of about 20% compared to the conventional flipflop. The RCSFF can also reduce the RC delay of a long RC interconnect to one-half.

    1998年05月, IEEE Journal of Solid-State Circuits, 33 (5), 807 - 811, 英語

    [査読有り]

    研究論文(学術雑誌)

MISC

  • 消化管内への留置を目的とした飲み込み型デバイスの検討

    中村 亮太, 和泉 慎太郎, 川口 博, 吉本 雅彦, 太田 英敏

    Institute of Electrical Engineers of Japan, 2017年10月31日, 「センサ・マイクロマシンと応用システム」シンポジウム論文集 電気学会センサ・マイクロマシン部門 [編], 34, 1 - 5, 日本語

  • 和泉 慎太郎, 川口 博, 吉本 雅彦

    一般社団法人 電気学会, 2016年, 電気学会論文誌. E, センサ・マイクロマシン部門誌, 136 (3), NL3_2 - NL3_2, 日本語

  • 和泉 慎太郎, 川口 博, 吉本 雅彦

    生活習慣の改善や疾病のスクリーニングを目的とした,長期間の生体信号計測可能な生体センサ技術が注目されている.本稿では不揮発性素子を用いたノーマリオフ技術,および高信頼心拍センシング手法を用いた超低消費電力心電・心拍センサSoCについて紹介する.

    公益社団法人 応用物理学会, 2016年, 応用物理, 85 (4), 301 - 305, 日本語

    [査読有り][招待有り]

    記事・総説・解説・論説等(学術雑誌)

  • ウェアラブルデバイスのための圧電ポンプを用いた触覚刺激アクチュエータ

    児玉 泰佑, 和泉 慎太郎, 正木 何奈, 川口 博, 吉本 雅彦, 前中 一介

    Institute of Electrical Engineers of Japan, 2015年10月28日, 「センサ・マイクロマシンと応用システム」シンポジウム論文集 電気学会センサ・マイクロマシン部門 [編], 32, 1 - 5, 日本語

  • マイクロ波ドップラーセンサと距離画像センサを用いた非接触かつ高精度な心拍抽出手法

    松永 大地, 和泉 慎太郎, 奥野 圭祐, 川口 博, 吉本 雅彦

    Institute of Electrical Engineers of Japan, 2015年10月28日, 「センサ・マイクロマシンと応用システム」シンポジウム論文集 電気学会センサ・マイクロマシン部門 [編], 32, 1 - 5, 日本語

  • ウェアラブル生体センサのための心電計測手法(ポスターセッション,学生・若手研究会)

    田中 義人, 河本 優太, 中井 陽三郎, 奥野 圭祐, 和泉 慎太郎, 川口 博, 吉本 雅彦

    一般社団法人電子情報通信学会, 2014年11月24日, 電子情報通信学会技術研究報告. CPSY, コンピュータシステム, 114 (346), 47 - 47, 日本語

  • 不揮発マイコンを用いたノーマリーオフ生体計測SoC(ポスターセッション,学生・若手研究会)

    松永 大地, 中井 陽三郎, 河本 優太, 中川 知己, 奥野 圭祐, 和泉 慎太郎, 川口 博, 吉本 雅彦

    一般社団法人電子情報通信学会, 2014年11月24日, 電子情報通信学会技術研究報告. CPSY, コンピュータシステム, 114 (346), 49 - 49, 日本語

  • 0.38V動作可能なプロセスばらつき耐性を有する65nm 8Mb STT-MRAM読出しセンスアンプ (集積回路)

    梅木 洋平, 柳田 晃司, 吉本 秀輔, 和泉 慎太郎, 吉本 雅彦, 川口 博, 角田 浩司, 杉井 寿博

    本稿では65nmプロセスを用いた単一0.38V電源で動作可能なプロセスばらつき耐性を持つSTT-MRAM(磁気抵抗変化型ランダムアクセスメモリ)向け読出しセンスアンプを提案する.提案センスアンプはnMOSによる負荷回路とpMOSを用いた負性抵抗回路により読出し電流を供給し,全てのプロセスコーナにおいて読出しマージンを持つ.提案回路を用いた8Mb STT-MRAMマクロを試作したところ,0.38Vにおいてサイクルタイム1.9μs(=0.526MHz)の速度を確認した.同電圧・速度における消費電力は1.70μWであった.アクセスエネルギが最小となる条件はVDD=0.44Vでありその際の消費エネルギは1.12pJ/bitであった.提案STT-MRAMは従来型低電圧動作SRAMと比較して,帯域幅の使用率が14%未満である場合において優れている.

    一般社団法人電子情報通信学会, 2014年04月17日, 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 114 (13), 47 - 51, 日本語

  • 磁性変化型メモリの書き込み速度を改善するメモリアーキテクチャ(ポスターセッション,学生・若手研究会)

    森 陽紀, 柳田 晃司, 梅木 洋平, 吉本 秀輔, 和泉 慎太郎, 吉本 雅彦, 川口 博, 角田 浩司, 杉井 寿博

    一般社団法人電子情報通信学会, 2014年01月21日, 電子情報通信学会技術研究報告. ICD, 集積回路, 113 (419), 27 - 27, 日本語

  • 強誘電体メモリの高速回路技術(ポスターセッション,学生・若手研究会)

    中川 知己, 吉本 秀輔, 北原 佑起, 柳田 晃司, 和泉 慎太郎, 川口 博, 吉本 雅彦

    一般社団法人電子情報通信学会, 2014年01月21日, 電子情報通信学会技術研究報告. ICD, 集積回路, 113 (419), 39 - 39, 日本語

  • ウェアラブル生体センサのための心電図解析手法(ポスターセッション,学生・若手研究会)

    中井 陽三郎, 和泉 慎太郎, 中野 将尚, 山下 顕, 藤井 貴英, 川口 博, 吉本 雅彦

    一般社団法人電子情報通信学会, 2014年01月21日, 電子情報通信学会技術研究報告. ICD, 集積回路, 113 (419), 61 - 61, 日本語

  • ノーマリーオフコンピューティング:4. ヘルスケア応用生体情報計測センサにおけるノーマリーオフコンピューティング

    藤森 敬和, 和泉 慎太郎, 川口 博, 志賀 利一, 吉本 雅彦

    本稿ではウェアラブルな貼り付け型生体情報計測センサにおける課題と,生体信号計測のためのノーマリーオフコンピューティング手法について解説する.また,本研究で試作した貼り付け型生体情報計測センサLSIを紹介する.常時計測可能な貼り付け型生体情報計測センサノードを実現するためには,センサのサイズと重量を可能な限り削減する必要がある.貼り付け型センサノードを構成する要素の内,重量に対して最も支配的な要素はバッテリであり,ノーマリーオフコンピューティングによってセンサLSIの消費電力を極限まで削減することを目指している.

    情報処理学会 ; 1960-, 2013年06月15日, 情報処理, 54 (7), 677 - 682, 日本語

  • 川口 博, 吉本 秀輔, 奥村 俊介, 天下 卓郎, 和泉 慎太郎, 吉本 雅彦

    日本信頼性学会, 2013年, 日本信頼性学会誌 信頼性, 35 (8), 432 - 432, 日本語

  • Shimpei Soda, Masahide Nakamura, Shinsuke Matsumoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    2013年01月, 電子情報通信学会技術研究報告, 112 (388), 19 - 24, 英語

  • C-12-3 温度変化を考慮したSRAMのBER導出手法の検討(C-12.集積回路,一般セッション)

    北原 佑起, 鍵山 裕輝, 奥村 俊介, 柳田 晃司, 吉本 秀輔, 中田 洋平, 和泉 慎太郎, 川口 博, 吉本 雅彦

    一般社団法人電子情報通信学会, 2012年03月06日, 電子情報通信学会総合大会講演論文集, 2012 (2), 75 - 75, 日本語

  • マイクアレイネットワークを用いたホームネットワークサービス向けハンズフリー音声インタフェース

    祖田心平, 中村 匡秀, 松本 真佑, 松原 典行, 久賀田 耕史, 和泉 慎太郎, 川口 博, 吉本 雅彦

    2012年03月, 電子情報通信学会技術研究報告, Vol. 111, No. 481, pp.73-78, 日本語

    速報,短報,研究ノート等(学術雑誌)

  • 低電力20相出力発振回路

    奥野 圭祐, 小西 恵大, 李 赫鍾, 和泉 慎太郎, 川口 博, 吉本 雅彦

    本稿ではmulti-phase oscillator(MPOSC)の低消費電力化に適した,位相補間素子(transfer gate phase coupler, TGPC)を提案する.我々が提案するMPOSCは位相補間素子にnMOSを用いており,電荷を消費しないことで低消費電力を実現する.また,提案MPOSCは出力を任意の数にすることができる.180nm,65nmCMOSプロセスで900位相差信号を含む20相の位相を出力するMPOSCの試作を行い,プロセススケーラビリティが得られることを確認した.180nmプロセスで設計した試作チップと従来回路との設計比較を行った結果,Power Delay(PD)積に関して,位相補間にインバータを用いた回路と比較し36.6%,nMOSラッチを用いた回路と比較し38.3%改善された.また65nmプロセスで設計した試作チップを測定した結果,DNLは±1.22°,3σジッタは5.82psとなり,消費電力は出力周波数1.85GHzの場合で284μWとなった.

    一般社団法人電子情報通信学会, 2011年12月08日, 電子情報通信学会技術研究報告. ICD, 集積回路, 111 (352), 149 - 154, 日本語

  • マイクアレイネットワークを用いた宅内サービス実現可能性の検討

    祖田 心平, [マツ]本 真佑, 中村 匡秀, 和泉 慎太郎, 川口 博, 吉本 雅彦

    ユビキタス技術の進化に伴い,家庭内の設備をネットワークに接続したホームネットワークシステム(HNS)の研究開発が進んでいる.住人の位置に応じて適切なサービスを提供する位置アウェアなサービスは,HNSにおける重要課題の一つである.従来,複数のマイクアレイをネットワークで接続し,話者の位置推定等に応用する研究が行われている.本研究では,このマイクアレイネットワークの宅内位置アウェアサービスヘの適用可能性を,3つのサービス例を挙げて検討する.

    一般社団法人電子情報通信学会, 2011年10月14日, 電子情報通信学会技術研究報告. CPSY, コンピュータシステム, 111 (255), 61 - 66, 日本語

    速報,短報,研究ノート等(学術雑誌)

  • Multiple-Bit- Upset Tolerant 8T SRAM Cell Layout with Divided Wordline Structure

    S. Yoshimoto, T. Amashita, D. Kozuwa, T. Takata, M. Yoshimura, Y. Matsunaga, H. Yasuura, H. Kawaguchi, M. Yoshimoto

    2011年03月, Proceedings of Silicon Errors in Logic - System Effects (SELSE), pp. 106 -111, 英語

    [査読有り]

    その他

  • Block-Basis On-Line BIST Architecture for Embedded SRAM Using Wordline and Bitcell Voltage Optimal Control

    Masahiro Yoshikawa, Shunsuke Okumura, Yohei Nakata, Yuki Kagiyama, Hiroshi Kawaguchi, Masahiko Yoshimoto

    A system on a chip (SOC) is becoming smaller and denser. Shrinking transistor size facilitates the integration of functionality on the chip operating at low supply voltage, although this trend lowers the silicon chip reliability. Nevertheless, it is necessary to maintain complete functionality during a long duration, even under changing environments such as temperature fluctuation and/or device wearout: Bias temperature instability must be considered as a time-varying parameter as well. Consequently, techniques that can maintain chip reliability with self-diagnosis and self-repair capabilities are required. In this paper, we propose a dependable SRAM with a built-in self-test that can diagnose and repair itself using wordline and bitcell voltage control. The proposed SRAM comprises memory blocks; each block has independent supply voltages for the wordlines and bitcells. This diagnosis and repair scheme is especially effective for faults that occur in the field. The self-testing capability is available on-line. It is completely transparent to a user, who can use the SRAM with no modification or speed degradation in the memory access protocol. A 1-Mb (64-Kb x 16 blocks) SRAM with the BIST was fabricated with a 65-nm CMOS process and verified. The area overhead is 2.8%.

    IEEE, 2011年, 2011 12TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), pp. 322- 325, 322 - 325, 英語

    [査読有り]

    その他

  • A 58-uW Sensor Node LSI with Synchronous MAC Protocol

    S. Izumi, T. Takeuchi, T. Matsuda, H. Lee, T. Konishi, K. Tsuruda, Y. Sakai, C. Ohta, H. Kawaguchi, M. Yoshimoto

    2010年09月, Proceedings of Asia-aPacific Radio Science Conference (AP-RASC), 英語

    [査読有り]

    その他

  • Scalable Parallel Processing for H.264 Encoding Application to Multi/Many-core Processor

    Y. Takeuchi, Y. Nakata, H. Kawaguchi, M. Yoshimoto

    2010年08月, Proceedings of the International Conference on Intelligent Control and Information Processing (ICICIP), pp. 163-170, 英語

    [査読有り]

    その他

  • Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video

    K. Mizuno, H. Noguchi, G. He, Y. Terachi, T. Kamino, H. Kawaguchi, M. Yoshimoto

    2010年08月, Proceedings of 20th International Conference on Field Programmable Logic and Applications (FPL), pp608-611, 英語

    [査読有り]

    その他

  • 0.5-V Operation Variation-Aware Word-Enhancing Cache Architecture Using 7T/14T hybrid SRAM

    Y. Nakata, S. Okumura, H. Kawaguchi, M. Yoshimoto

    2010年08月, Proceedings of International Symposium on Low Power Electronics and Design (ISLPED), pp. 219-224, 英語

    [査読有り]

    その他

  • Parallel-Processing VLSI Architecture for Mixed Integer Linear Programming

    Hiroki Noguchi, Junichi Tani, Yusuke Shimai, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper describes parallel processor architecture for a mixed integer linear programming (MILP) solver to realize motion planning and hybrid system control in robot applications. It features pipeline architecture with an MILP-specific configuration and two-port SRAM. Based on the architecture, both FPGA and VLSI implementations have been done to solve sample problems including 16 variables. The FPGA implementation can reduce the power consumption to 13 W: an 85.4% reduction compared to a 3.0-GHz processor (Pentium 4; Intel Corp.). The VLSI solver further reduces the power to 6.4 W using 0.18-mu m CMOS technology.

    IEEE, 2010年, 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, pp. 2362-2365, 2362 - 2365, 英語

    [査読有り]

    その他

  • A 34.7-mW Quad-Core MIQP Solver Processor for Robot Control

    Hiroki Noguchi, Junichi Tani, Yusuke Shimai, Masanori Nishino, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto

    We propose a quad-core mixed integer quadric programming (MIQP) solver processor. The MIQP solver is applicable to hybrid control systems including real-time control robotics. Using multi-core architecture, fixed-point calculations, and branch-and-bound method with high-dispersion performance while processing a 50-variable problem, our design achieves 34.7-mW operation at a frequency of 52 MHz in measurement results, although a core 2 duo PC requires 3.16 GHz to solve it as rapidly.

    IEEE, 2010年, IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010, 英語

    [査読有り]

    その他

  • 7T SRAM Enabling Low-Energy Simultaneous Block Copy

    Shunsuke Okumura, Shusuke Yoshimoto, Kosuke Yamaguchi, Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper proposes 7T SRAM which realizes block-level simultaneous copying feature. The proposed SRAM can be used for data transfer between local memories such as checkpoint data storage and transactional memory. The 1-Mb SRAM is comprised of 32-kb blocks, in which 16-kb data can be copied in 33.3 ns at 1.2V. The proposed scheme reduces energy consumption in copying by 92.7% compared to the conventional read-modify-write manner.

    IEEE, 2010年, IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010, Dig. Tech. Papers, 英語

    [査読有り]

    その他

  • FPGA Implementation of Mixed Integer Quadratic Programming Solver for Mobile Robot Control

    Y. Shimai, J. Tani, H. Noguchi, H. Kawaguchi, M. Yoshimoto

    2009年12月, Proceedings of IEEE International Conference on Field-Programmable Technology (FPT), pp. 447-450, 英語

    その他

  • 時刻同期型MACプロトコルを用いる58-μWワンチップセンサノードプロセッサ

    和泉 慎太郎, 竹内 隆, 松田 隆志, 李 赫鍾, 小西 恵大, 鶴田 嵩, 酒井 康晴, 川口 博, 太田 能, 吉本 雅彦

    本研究では,時刻同期型MACプロトコル(I-MAC)を用いる1-chipセンサノードSoCの垂直統合設計を行った.提案するセンサノードはトランシーバ,通信制御用マイクロコントローラ,電源管理モジュールから構成される.CMOS 180nmプロセスでの試作を行い,コアサイズ3mmx3mm,1.38MトランジスタのセンサノードLSIを実現した.また,データ収集型のネットワーク環境において,ノード全体で58.0μWの平均消費電力を達成した.

    一般社団法人電子情報通信学会, 2009年09月24日, 電子情報通信学会技術研究報告. ICD, 集積回路, 109 (214), 141 - 145, 日本語

  • コグニティブ無線向け可変帯域ディジタルバンドパスフィルタの設計

    鶴田 嵩, 和泉 慎太郎, 李 赫鍾, 竹内 隆, 川口 博, 吉本 雅彦

    本論文ではコグニティブ無線向け可変帯域ディジタルBPF(Band-Pass Filter)を用いたベースバンドプロセッサを提案する.BPFにDA(Distributed Arithmetic)アルゴリズムを適応することで,内蔵するSRAMのデータを書き換えるだけでBPFの特性(チャネル中心周波数とバンド幅)を変化させることが可能となる.試作したベースバンドプロセッサではバンド幅を40kHzから240kHzまで10kHz単位で変化させることが可能である.CMOS 180nmプロセスで設計し,電源電圧1.8Vで消費電力は13.5mWであった.

    一般社団法人電子情報通信学会, 2008年10月15日, 電子情報通信学会技術研究報告. ICD, 集積回路, 108 (253), 137 - 141, 日本語

  • Shintaro Izumi, Koh Tsuruda, Takashi Takeuchi, Hyeokjong Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto

    Concomitantly with the progress of wireless communications, cognitive radio has attracted attention as a solution for depleted frequency bands. Cognitive radio is suitable for wireless sensor networks because it reduces collisions and thereby achieves energy-efficient communication. To make cognitive radio practical, we propose a low-power multi-resolution spectrum sensing (MRSS) architecture that has flexibility in sensing frequency bands. The conventional MRSS scheme consumes much power and can be adapted only slightly to process scaling because it comprises analog circuits. In contrast, the proposed architecture carries out signal processing in a digital domain and can detect occupied frequency bands at multiple resolutions and with low power. Our digital MRSS module can be implemented in 180-nm and 65-nm CMOS processes using Verilog-HDL. We confirmed that the processes respectively dissipate 9.97 mW and 3.45 mW.

    IEEE, 2008年, 2010 FOURTH INTERNATIONAL CONFERENCE ON SENSOR TECHNOLOGIES AND APPLICATIONS (SENSORCOMM), pp. 39-44, 39 - 44, 英語

    [査読有り]

    その他

  • A-21-26 ワイヤレスセンサネットワークのためのタイマ制御によるカウンタベースブロードキャスティング方式の改良(A-21.センサネットワーク,一般講演)

    和泉 慎太郎, 松田 隆志, 三上 真司, 川口 博, 太田 能, 吉本 雅彦

    一般社団法人電子情報通信学会, 2007年03月07日, 電子情報通信学会総合大会講演論文集, 2007, 417 - 417, 日本語

  • 有機トランジスタとプラスチックアクチュエータを集積化したフレキシブルな点字ディスプレイ向けの回路技術

    川口 博, 高宮 真, 関谷 毅, 加藤 祐作, 染谷 隆夫, 桜井 貴康

    2006年05月, 電子情報通信学会技術研究報告, ICD2006-22、1-6ページ, 日本語

    [査読有り]

    その他

  • BS-10-5 センサノードの製造バラツキを考慮したネットワーク可用時間改善の一検討(BS-10.移動通信環境統合化ネットワーク技術,シンポジウム)

    芳野 宏徳, 青西 孝文, 一圓 真澄, 松田 隆志, 太田 能, 川口 博, 吉本 雅彦

    一般社団法人電子情報通信学会, 2006年03月08日, 電子情報通信学会総合大会講演論文集, 2006 (2), "S - 72"-"S-73", 日本語

講演・口頭発表等

  • 光電式容積脈波法による脈拍測定の低消費電力化手法

    渡辺 健斗, 和泉 慎太郎, 矢野 祐二, 川口 博, 吉本 雅彦

    ヘルスケア・医療情報通信技術研究会(MICT), 2019年01月, 日本語, 電子情報通信学会, 東京都千代田区明治大学駿河台キャンパス, 国内会議

    口頭発表(一般)

  • ウェアラブルデバイスのための心拍変動モニタリングにおけるサンプリングレート低減手法

    西河 有貴, 和泉 慎太郎, 矢野 祐二, 川口 博, 吉本 雅彦

    第35回「センサ・マイクロマシンと応用システム」シンポジウム, 2018年10月, 日本語, 電気学会 センサ・マイクロマシン部門, 北海道札幌市 札幌市民交流プラザ, 国内会議

    ポスター発表

  • ウェアラブルデバイスのための圧電素子を用いたマルチモーダルな心血管情報の計測

    岡野 孝昭, 和泉 慎太郎, 勝浦 巧, 川口 博, 吉本 雅彦

    第34回「センサ・マイクロマシンと応用システム」シンポジウム,01am2-PS-135,広島,2017年11月1日, 2017年11月, 日本語, 国内会議

    口頭発表(一般)

  • 消化管内への留置を目的とした飲み込み型デバイスの検討

    中村 亮太, 和泉 慎太郎, 川口 博, 太田 英敏, 吉本 雅彦

    第34回「センサ・マイクロマシンと応用システム」シンポジウム,31pm3-PS-46,広島,2017年10月31日, 2017年10月, 日本語, 国内会議

    口頭発表(一般)

  • ノイズフィードバック技術を用いたウェアラブル向け容量結合型心電センサ

    永里 佑樹, 和泉 慎太郎, 川口 博, 吉本 雅彦

    IEICEソサイエティ大会, 2017年9月12-15日,東京, 2017年09月, 日本語, 国内会議

    口頭発表(一般)

  • 選択的ソース線駆動方式を用いた画像処理プロセッサ向け低消費電力28nm FD-SOI 8TデュアルポートSRAM

    森 陽紀, 中川 知己, 北原 佑起, 河本 優太, 高木 健太, 吉本 秀輔, 和泉 慎太郎, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ2017 ポスターセッション, 東京, 2017年5月, 2017年05月, 日本語, 国内会議

    口頭発表(一般)

  • マイクロ波ドップラーセンサを用いた車両走行中の心拍計測手法

    松永 大地, 和泉 慎太郎, 川口 博, 吉本 雅彦

    電子情報通信学会総合大会,B-20-10, 名古屋, 2017年3月22日., 2017年03月, 日本語, 名古屋, 国内会議

    口頭発表(一般)

  • プロセスばらつき耐性を有する低電圧動作STT-MRAM向けカウンターベース読出し回路

    梅木 洋平, 柳田 晃司, 吉本 秀輔, 和泉 慎太郎, 吉本 雅彦, 川口 博, 角田 浩司, 杉井 寿博

    LSIとシステムのワークショップ2016, 2016年05月, 日本語, 国内会議

    ポスター発表

  • 消化管内に留置可能な飲み込み型生体センサー

    和泉 慎太郎, 中村 亮太, 川口 博, 吉本 雅彦

    電子情報通信学会総合大会, 2016年03月, 日本語, 福岡, 国内会議

    口頭発表(一般)

  • ヘルスケアデバイスから見た材料科学への期待

    川口 博

    日本化学会第96春季年会, 2016年03月, 日本語, 京都, 国内会議

    [招待有り]

    口頭発表(招待・特別)

  • Process variation tolerant counter base read circuit for low-voltage operating STT-MRAM

    UMEKI Yohei, YANAGIDA Koji, KUROTSU Hiroaki, KITAHARA Hiroto, MORI Haruki, IZUMI Shintaro, YOSHIMOTO Masahiko, KAWAGUCHI Hiroshi, YOSHIMOTO Shusuke, TSUNODA Koji, SUGII Toshihiro

    DATE EMS Workshop, 2016年03月, 英語, Dresden,Germany, 国際会議

    ポスター発表

  • Analysis of Soft Error Propagation considering Masking Effects on Re-convergent Path

    KIMI Yuta, MATSUKAWA Go, YOSHIDA Shuhei, IZUMI Shintaro, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

    IEEE Asian Test Symposium (ATS), 2015年11月, 英語, 国際会議

    口頭発表(一般)

  • A 298-fJ/writecycle 650-fJ/readcycle 8T Three-Port SRAM in 28-nm FD-SOI Process Technology for Image Processor

    MORI Haruki, NAKAGAWA Tomoki, KITAHARA Yuki, KAWAMOTO Yuta, TAKAGI Kenta, YOSHIMOTO Shusuke, IZUMI Shintaro, Nii Koji, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

    IEEE Custom Integrated Circuits Conference (CICC), 2015年09月, 英語, 国際会議

    口頭発表(一般)

  • 時間デジタル変換器を用いたIOサイズ8bitAD変換器

    奥野圭祐, 小西恵大, 和泉慎太郎, 吉本雅彦, 川口博

    LSIとシステムのワークショップ2015 ポスターセッション, 2015年05月, 日本語, 小倉, 国内会議

    ポスター発表

  • ウェアラブル心電図計測SoC

    田中義人, 中井陽三郎, 河本優太, 中川知己, 奥野圭祐, 和泉慎太郎, 川口博, 木村啓明, 丸元共治, 渕上貴昭, 藤森敬和, 吉本雅彦

    LSIとシステムのワークショップ2015, 2015年05月, 日本語, 小倉, 国内会議

    ポスター発表

  • 6T4C型低消費電力不揮発メモリ

    北原弘登, 中川知己, 和泉慎太郎, 柳田晃司, 北原佑起, 吉本秀輔, 梅木洋平, 森陽紀, 川口博, 木村啓明, 丸元共治, 渕上貴昭, 藤森敬和, 吉本雅彦

    LSIとシステムのワークショップ2015, 2015年05月, 日本語, 小倉, 国内会議

    ポスター発表

  • 温度補償回路を用いた高速セットリングADPLL

    奥野 圭祐, 正木 何奈, 和泉 慎太郎, 川口 博, 吉本 雅彦

    第37回アナログRF研究会, 2014年12月, 日本語, 国内会議

    口頭発表(一般)

  • 低消費電力貼り付け型センサのためのテンプレートマッチングを用いたロバスト心拍抽出手法の開発

    中井 陽三郎, 和泉 慎太郎, 中野 将尚, 山下 顕, 藤井 貴英, 川口 博, 吉本 雅彦

    第31回「センサ・マイクロマシンと応用システム」シンポジウム, 2014年10月, 日本語, 国内会議

    口頭発表(一般)

  • 動作環境変動に応じて動的に動作マージンを拡大する自律制御キャッシュ

    木美 雄太, 中田 洋平, 奥村 俊介, 鄭 晋旭, 澤田 卓也, 利川 托, 永田 真, 中野 博文, 藪内 誠, 藤原 英弘, 新居 浩二, 河合 浩行, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ2014 ポスターセッション, 2014年05月, 日本語, 小倉, 国内会議

    ポスター発表

  • 磁性変化型メモリの書き込み高速化メモリアーキテクチャ

    森 陽紀, 柳田 晃司, 梅木 洋平, 吉本秀輔, 和泉 慎太郎, 川口 博, 吉本 雅彦, 角田 浩司, 杉井 寿博

    LSIとシステムのワークショップ2014 ポスターセッション, 2014年05月, 日本語, 電子情報通信学会集積回路研究専門委員会, 小倉, 国内会議

    ポスター発表

  • 温度補償回路を用いた高速セットリングADPLL

    正木 何奈, 奥野 圭祐, 和泉 慎太郎, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ2014 ポスターセッション, 2014年05月, 日本語, 電子情報通信学会集積回路研究専門委員会, 小倉, 国内会議

    ポスター発表

  • 一括コピー・比較が可能なSRAMを用いた低遅延デュアルコアロックステップアーキテクチャ

    吉田 周平, 松川 豪, 中田 洋平, 木美 雄太, 勝 康夫, 下澤 晶史, 於保 茂, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ2014 ポスターセッション, 2014年05月, 日本語, 電子情報通信学会集積回路研究専門委員会, 小倉, 国内会議

    ポスター発表

  • 38μAウェアラブル生体情報計測プロセッサ

    中井 陽三郎, 和泉 慎太郎, 山下 顕, 中野 将尚, 藤井 貴英, 小西 恵大, 川口 博, 木村 啓明, 丸元 共治, 渕上 貴昭, 藤森 敬和, 中嶋 宏, 志賀 利一, 吉本 雅彦

    LSIとシステムのワークショップ2014 ポスターセッション, 2014年05月, 日本語, 国内会議

    ポスター発表

  • ロバストな瞬時心拍抽出機能を有する低消費電力ウェアラブルヘルスケアシステム

    和泉 慎太郎, 中野 将尚, 山下 顕, 川口 博, 吉本 雅彦

    第14回計測自動制御学会システムインテグレーション部門講演会SI2013, 2013年12月, 日本語, 神戸市, 国内会議

    [招待有り]

    口頭発表(招待・特別)

  • 読出しビット線振幅制限機構及び読み出し加速回路を備えた8T SRAM

    梅木 洋平, 吉本 秀輔, 和泉 慎太郎, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ2013, 2013年05月, 日本語, 北九州市, 国内会議

    ポスター発表

  • 車載ECUのSRAMへの故障注入による自動車制御システムの挙動評価

    藤川 飛鳥, 竹内 勇介, 中田 洋平, 伊藤 康宏, 勝 康夫, 於保 茂, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ2013, 2013年05月, 日本語, 北九州市, 国内会議

    ポスター発表

  • 核反応シミュレータを用いたソフトエラー率導出ツール及び耐マルチビットエラー6T SRAM

    吉本 秀輔, 和泉 慎太郎, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ2013, 2013年05月, 日本語, 北九州市, 国内会議

    ポスター発表

  • ラウドコンピュータを用いたディペンダブルプロセッサの大規模故障注入評価

    松川 豪, 中田 洋平, 伊藤 康宏, 竹内 勇介, 勝 康夫, 於保 茂, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ2013, 2013年05月, 日本語, 北九州市, 国内会議

    ポスター発表

  • ゼロデータを利用したSTT-RAMキャッシュの低エネルギー化設計

    木美 雄太, 鄭 晋旭, 中田 洋平, 吉本 雅彦, 川口 博

    LSIとシステムのワークショップ2013, 2013年05月, 日本語, 北九州市, 国内会議

    ポスター発表

  • HDTV解像度対応 実時間HOG特徴量抽出と複数物体検出を実現する43mWデュアルコアプロセッサ

    高木 健太, 水野 孝祐, 和泉 慎太郎, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ2013, 2013年05月, 日本語, 北九州市, 国内会議

    ポスター発表

  • 65nm 700-μm2 61-dB 低ジッター2次ΔΣT-D変換器

    奥野 圭祐, 小西 恵大, 和泉 慎太郎, 吉本 雅彦, 川口 博

    LSIとシステムのワークショップ2013, 2013年05月, 日本語, 北九州市, 国内会議

    ポスター発表

  • ウェアラブルヘルスケアシステムのための 短時間自己相関を用いた瞬時心拍検出手法

    中野将尚, 小西恵大, 和泉慎太郎, 川口博, 吉本 雅彦

    電気学会センサ・マイクロマシン部門大会, 2012年10月, 日本語, 北九州, 国内会議

    シンポジウム・ワークショップパネル(公募)

  • 低電圧動作マージン拡大機能を有する連想度可変キャッシュ

    鄭晋旭, 中田洋平, 奥村俊介, 川口博, 吉本 雅彦

    LSIとシステムのワークショップ 2012, 2012年05月, 日本語, 北九州, 国内会議

    ポスター発表

  • プロセスばらつきを考慮したNoCアーキテクチャ

    中田洋平, 川口博, 吉本 雅彦

    LSIとシステムのワークショップ 2012, 2012年05月, 日本語, 北九州, 国内会議

    ポスター発表

  • 6万語彙実時間連続音声認識のための40nm, 144mW音声認識専用プロセッサの開発

    何光霽, 菅原隆伸, 藤永剛史, 宮本優貴, 野口紘希, 和泉慎太郎, 川口博, 吉本 雅彦

    LSIとシステムのワークショップ 2012, 2012年05月, 日本語, 北九州, 国内会議

    ポスター発表

  • 40nm 640μm2 7.2bit プロセススケーラブル・オペアンプレス時間演算型AD変換器

    小西恵大, 奥野圭祐, 和泉慎太郎, 吉本雅彦, 川口 博

    LSIとシステムのワークショップ 2012, 2012年05月, 日本語, 北九州, 国内会議

    ポスター発表

  • 0.5V 12.9pJ/accessを実現する低電力ライトバック技術を備えた40nm 8T SRAM

    吉本秀輔, 寺田正治, 奥村俊介, 鈴木利一, 宮野信治, 川口博, 吉本 雅彦

    LSIとシステムのワークショップ 2012, 2012年05月, 中国語, 北九州, 国内会議

    ポスター発表

  • 温度変化を考慮したSRAMのBER導出手法の検討

    北原 佑起, 鍵山 祐輝, 奥村 俊介, 柳田 晃司, 吉本 秀輔, 中田 洋平, 和泉 慎太郎, 川口 博, 吉本 雅彦

    電子情報通信学会総合大会, 2012年03月, 日本語, 電子情報通信学会, 岡山市, 国内会議

    口頭発表(一般)

  • マイクアレイネットワークを用いたホームネットワークサービス向けハンズフリー音声インタフェース

    祖田 心平, 中村 匡秀, まつ本 真佑, 松原 典行, 久賀田 耕史, 和泉 慎太郎_IZUMI_Shintaro, 川口 博, 吉本 雅彦

    電子情報通信学会研究会, 2012年03月, 日本語, 電子情報通信学会集積回路研究専門委員会, 那覇市, 国内会議

    口頭発表(一般)

  • ディペンダブルSRAMのためのオンライン故障診断技術の開発

    藤川 飛鳥, 吉川 将弘, 奥村 俊介, 中田 洋平, 鍵山 祐輝, 川口 博, 吉本 雅彦

    電子情報通信学会総合大会, 2012年03月, 日本語, 電子情報通信学会, 岡山市, 国内会議

    口頭発表(一般)

  • 0.6V動作可能なハーフセレクト耐性を向上させる差動書込み技術を用いた40-nm 8T SRAM

    梅木 洋平, 寺田 正治, 吉本 秀輔, 川口 博, 吉本 雅彦

    電子情報通信学会総合大会, 2012年03月, 日本語, 電子情報通信学会, 岡山市, 国内会議

    口頭発表(一般)

  • 低電圧動作におけるマージン拡大機能を有する連想度可変キャッシュ

    鄭 晋旭, 中田 洋平, 奥村 俊介, 川口 博, 吉本 雅彦

    電子情報通信学会研究会, 2012年01月, 日本語, 電子情報通信学会集積回路研究専門委員会, 東京, 国内会議

    口頭発表(一般)

  • 実時間ロボット制御のための75変数MIQP問題ソルバープロセッサ

    西野 允雅, 野口 紘希, 嶋井 優介, 和泉 慎太郎, 川口 博, 吉本 雅彦

    電子情報通信学会研究会, 2012年01月, 日本語, 電子情報通信学会集積回路研究専門委員会, 東京, 国内会議

    口頭発表(一般)

  • 低電力20相出力発振回路

    奥野 圭祐, 小西 恵大, 李 赫鍾, 和泉 慎太郎_IZUMI_Shintaro, 川口 博, 吉本 雅彦

    電子情報通信学会研究会, 2011年12月, 日本語, 電子情報通信学会集積回路研究専門委員会, 大阪, 国内会議

    口頭発表(一般)

  • マルチビットアップセット耐性及びシングルビットアップセット耐性を備えた8T SRAM セルレイアウト

    梅木 洋平, 吉本 秀輔, 天下 卓郎, 川口 博, 吉本 雅彦

    電子情報通信学会研究会, 2011年12月, 日本語, 電子情報通信学会集積回路研究専門委員会, 大阪, 国内会議

    口頭発表(一般)

  • チップ間ばらつき及びチップ内ばらつきを抑制する基板バイアス制御回路を備えた0.42-V 576-Kb 0.15-um FD-SOI 7T/14T SRAM

    吉本 秀輔, 山口 幸介, 奥村 俊介, 吉本 雅彦, 川口 博

    電子情報通信学会研究会 (2011), 2011年12月, 日本語, 国内会議

    ポスター発表

  • 6万語彙実時間連続音声認識のための40nm,144mW音声認識専用プロセッサの開発

    菅原 隆伸, 何 光霽, 藤永 剛史, 宮本 優貴, 野口 紘希, 和泉 慎太郎_IZUMI_Shintaro, 川口 博, 吉本 雅彦

    デザインガイア2011, 2011年11月, 日本語, 電子情報通信学会集積回路研究専門委員会, 宮崎市, 国内会議

    口頭発表(一般)

  • 故障注入技術を用いたディペンダブルSRAMを搭載するプロセッサの信頼性評価・検証

    竹内 勇介, 中田 洋平, 伊藤 康宏, 勝 康夫, 於保 茂, 奥村 俊介, 川口 博, 吉本 雅彦

    コンピュータシステム研究会, 2011年10月, 日本語, 電子情報通信学会, 神戸市, 国内会議

    口頭発表(一般)

  • マイクアレイネットワークを用いた宅内サービス実現可能性の検討

    祖田 心平, 中村 匡秀, まつ本 真佑, 松原 典行, 久賀田 耕史, 和泉 慎太郎_IZUMI_Shintaro, 川口 博, 吉本 雅彦

    コンピュータシステム研究会, 2011年10月, 日本語, 電子情報通信学会, 神戸市, 国内会議

    口頭発表(一般)

  • 低電力20相出力発振回路

    奥野 圭祐, 小西 恵大, 和泉 慎太郎_IZUMI_Shintaro, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ 2011, 2011年05月, 日本語, 電子情報通信学会集積回路研究専門委員会, 北九州市, 国内会議

    ポスター発表

  • 次世代知能ロボット制御のための混合整数2次計画問題(MIQP)ソルバーコアプロセッサ

    西野 允雅, 野口 紘希, 谷 純一, 嶋井 優介, 和泉 慎太郎, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ 2011, 2011年05月, 日本語, 電子情報通信学会集積回路研究専門委員会, 北九州市, 国内会議

    ポスター発表

  • マルチビットアップセット耐性を備えた8T SRAMセルレイアウト

    天下 卓郎, 吉本 秀輔, 小津和 大昌, 高田 大河, 吉村 正義, 松永 裕介, 安浦 寛人, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ 2011, 2011年05月, 日本語, 電子情報通信学会集積回路研究専門委員会, 北九州市, 国内会議

    ポスター発表

  • ブロックデータ一括コピー機能を有する7T SRAM

    鍵山 祐輝, 奥村 俊介, 吉本 秀輔, 中田 洋平, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ 2011, 2011年05月, 日本語, 電子情報通信学会集積回路研究専門委員会, 北九州市, 国内会議

    ポスター発表

  • フルHDTV実時間動画像認識のための低消費電力SIFT特徴量抽出プロセッサ

    寺地 陽祐, 水野 孝祐, 何 光霽, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ 2011, 2011年05月, 日本語, 電子情報通信学会集積回路研究専門委員会, 北九州市, 国内会議

    ポスター発表

  • ビットエラー耐性及びソフトエラー耐性を備えたFD-SOI 7T/14T SRAM

    吉本 秀輔, 天下 卓郎, 奥村 俊介, 山口 幸介, 吉本 雅彦, 川口 博

    LSIとシステムのワークショップ 2011, 2011年05月, 日本語, 北九州市, 国内会議

    ポスター発表

  • システムレベル故障注入技術によるディペンダブルメモリを搭載したプロセッサの評価・検証

    竹内 勇介, 中田 洋平, 伊藤 康宏, 勝 康夫, 於保 茂, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ 2011, 2011年05月, 日本語, 電子情報通信学会集積回路研究専門委員会, 北九州市, 国内会議

    ポスター発表

  • しきい値ばらつき耐性を有する0.45V動作9T/18TデュアルポートSRAM

    柳田 晃司, 野口 紘希, 奥村 俊介, 高木 智也, 久賀田 耕史, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ 2011, 2011年05月, 日本語, 電子情報通信学会集積回路研究専門委員会, 北九州市, 国内会議

    ポスター発表

  • 7T/14T SRAMの細粒度制御による低電圧動作キャッシュアーキテクチャ

    鄭 晋旭, 中田 洋平, 奥村 俊介, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ 2011, 2011年05月, 日本語, 電子情報通信学会集積回路研究専門委員会, 北九州市, 国内会議

    ポスター発表

  • しきい値ばらつき耐性を有する0.45V動作9T/18TデュアルポートSRAM

    柳田 晃司, 野口 紘希, 奥村 俊介, 高木 智也, 久賀田 耕史, 川口 博, 吉本 雅彦

    電子情報通信学会研究会, 2011年04月, 日本語, 電子情報通信学会集積回路研究専門委員会, 神戸市, 国内会議

    ポスター発表

  • プロセスばらつきを考慮したNoCアーキテクチャの検討

    中田 洋平, 竹内 幸大, 川口 博, 吉本 雅彦

    情報処理学会研究報告 計算機アーキテクチャ(ARC), 2010年10月, 日本語, 国内会議

    その他

  • 分散処理を用いた超低消費電力 ネットワーク型マイクロホンアレーの研究

    祖田 心平, 久賀田 耕史, 高木 智也, 和泉 慎太郎, 野口 紘希, 吉本 雅彦, 川口 博

    日本音響学会2010年秋季研究発表会, 2010年09月, 日本語, 関西大学, 国内会議

    ポスター発表

  • マルチコアプロセッサにおけるH.264/AVC符号化処理の並列度とメモリアクセスに関する高効率実装

    中田 洋平, 竹内 幸大, 川口 博, 吉本 雅彦

    DAシンポジウム2010, 2010年09月, 日本語, 豊橋市, 国内会議

    ポスター発表

  • 高精度音源定位および音源分離機能を有する低消費電力ユビキタス・センサネットの開発

    高木 智也, 川口 博, 吉本 雅彦

    STARCフォーラム/シンポジウム2009, 2010年08月, 日本語, 国内会議

    ポスター発表

  • ネットワーク分散処理を用いた超低消費電力音声信号処理プロセッサ

    久賀田 耕史, 野口 紘希, 高木 智也, 祖田 心平, 吉本 雅彦, 川口 博

    STARC フォーラム/シンポジウム2010, 2010年08月, 日本語, 横浜市, 国内会議

    ポスター発表

  • 分散処理型ユビキ タスセンサネットワークのための超低消費電力音声処理プロセッサ

    高木 智也, 野口 紘希, 久賀田 耕史, 吉本 雅彦, 川口 博

    LSIとシステムのワークショップ 2010, 2010年05月, 日本語, 北九州市, 国内会議

    ポスター発表

  • 知能ロボットのためのマルチコアMIQPソルバープロセッサのFPGA実装

    嶋井 優介, 谷 純一, 野口 紘輝, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ 2010, 2010年05月, 日本語, 北九州, 国内会議

    ポスター発表

  • 大語彙連続音声認識のための並列Viterbiプロセッサアーキテクチャ

    藤永 剛史, 三浦 和夫, 野口 紘輝, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ 2010, 2010年05月, 日本語, 北九州, 国内会議

    ポスター発表

  • ワイヤレスセンサネットワークのためのΔ-Σ変調とデジタルアシストを用いたイメージ信号除去に関する研究

    小西 恵大, 李 赫鍾, 和泉 慎太郎, 竹内 隆, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ 2010, 2010年05月, 日本語, 北九州市, 国内会議

    ポスター発表

  • 7T/14T SRAMを内部メモリに用いたマルチコアプロセッサアーキテクチャ

    中田 洋平, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ 2010, 2010年05月, 日本語, 北九州市, 国内会議

    ポスター発表

  • "時刻同期型MACプロトコルを用いる6.4μWシングルチップセンサーノードLSI,

    和泉 慎太郎, 李 赫鍾, 小西 恵大, 岡 顕久, 松田 隆志, 竹内 隆, 太田 能, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ 2010, 2010年05月, 日本語, 北九州市, 国内会議

    ポスター発表

  • 時刻同期型MACプロトコルを用いる58-uWワンチップセンサノードプロセッサ

    和泉 慎太郎, 竹内 隆, 松田 隆志, 李 赫鍾, 小西 恵大, 鶴田 嵩, 酒井 康晴, 川口 博, 太田 能, 吉本 雅彦

    電子情報通信学会技術研究報告, 2009年10月, 日本語, 電子情報通信学会, 国内会議

    ポスター発表

  • 高精度音源定位および音源分離機能を有する低消費電力ユビキタス・センサネットの開発

    高木 智也, 川口 博

    STARCフォーラム/シンポジウム2009 学生ポスターセッション, 2009年08月, 日本語, 株式会社 半導体理工学研究センター(STARC), 新横浜国際ホテル, 国内会議

    ポスター発表

  • 7T/14T SRAMを内部メモリに用いたマルチコアプロセッサアーキテクチャの検討

    中田 洋平, 川口 博, 吉本 雅彦

    DAシンポジウム2009, 2009年08月, 日本語, 情報処理学会 システムLSI設計技術研究会, 石川, 国内会議

    ポスター発表

  • 全整数計画問題のソルバーのFPGA実装

    谷 純一, 野口 紘希, 嶋井 優介, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ2009 ポスターセッション, 2009年05月, 日本語, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, 国内会議

    ポスター発表

  • 時間同期型MACプロトコルの垂直統合設計によるセンサノードVLSIの低消費電力化

    和泉 慎太郎, 松田 隆志, 竹内 隆, 川口 博, 太田 能, 吉本 雅彦

    LSIとシステムのワークショップ2009 ポスターセッション, 2009年05月, 日本語, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, 国内会議

    ポスター発表

  • 高信頼性モードを有する7T/14TディペンダブルSRAM,

    奥村 俊介, 藤原 英弘, 井口 友輔, 野口 紘希, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ2009 ポスターセッション, 2009年05月, 日本語, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, 国内会議

    ポスター発表

  • リアルタイム20,000語彙連続音声認識のためのGMMプロセッサのFPGA実装

    三浦 和夫, 野口 紘希, 藤永 剛史, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ2009 ポスターセッション, 2009年05月, 日本語, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, 国内会議

    ポスター発表

  • マイクロホンアレイ・センサネットワークによるインテリジェント・ユビキタス音声処理システムと,その低消費電力LSIの提案,

    高木 智也, 野口 紘希, 吉本 雅彦, 川口 博

    LSIとシステムのワークショップ2009 ポスターセッション, 2009年05月, 日本語, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, 国内会議

    ポスター発表

  • チップ間ばらつき補正機能を有する基板バイアス制御を用いた0.42V動作486-kb FD-SOI SRAM,

    山口 幸介, 藤原 英弘, 竹内 隆, 大竹 優, 吉本 雅彦, 川口 博

    LSIとシステムのワークショップ2009 ポスターセッション, 2009年05月, 日本語, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, 国内会議

    ポスター発表

  • カラム線制御回路を用いた0.56V動作128-kb10T小面積SRAM,

    吉本 秀輔, 井口 友輔, 奥村 俊介, 藤原 英弘, 野口 紘希, 新居 浩二, 川口 博, 吉本 雅彦

    LSIとシステムのワークショップ2009 ポスターセッション, 2009年05月, 日本語, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, 国内会議

    ポスター発表

  • 低電圧・低消費電力SRAM

    川口 博

    IEEE Solid-State Circuits Society Kansai Chapter Technical Seminar, 2008年12月, 日本語, 国内会議

    口頭発表(招待・特別)

  • 発話推定を用いたインテリジェント認識システムの低消費 電力化技術

    野口 紘希, 川口 博

    半導体理工学研究センター(STARC)フォーラム/シンポジウム学生ポ スターセッション, 2008年07月, 日本語, パシフィコ横浜, 国内会議

    ポスター発表

  • 発話推定を用いたインテリジェント認識システムの低消費電力化技術

    野口紘希, 川口 博

    STARCフォーラム/シンポジウム2008 学生ポスターセッション, 2008年07月, 日本語, 半導体理工学研究センター, 横浜, 国内会議

    ポスター発表

  • 動的電源電圧/周波数制御によるフレームバッファSRAM内蔵型H.264 AVCデコーダの低消費電力化

    坂田 義典, 中田 洋平, 川上 健太郎, 川口 博, 吉本 雅彦

    第11回システムLSIワークショップ ポスタセッション, 2007年11月, 日本語, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, 国内会議

    ポスター発表

  • 長波帯標準電波を用いた低電力センサノードのための垂直統合設計

    大竹 優, 一圓 真澄, 竹内 隆, 祗園 昭宏, 三上 真司, 藤原 英弘, 川口 博, 太田 能, 吉本 雅彦

    第11回システムLSIワークショップ ポスタセッション, 2007年11月, 日本語, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, 国内会議

    ポスター発表

  • 超並列画像処理プロセッサ応用任意位置任意サイズ矩形データの1サイクルアクセスが可能なメモリアーキテクチャ

    上農 哲也, 宮越 純一, 村地 勇一郎, 川口 博, 吉本 雅彦

    第11回システムLSIワークショップ ポスタセッション, 2007年11月, 日本語, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, 国内会議

    ポスター発表

  • サブ100mW H.264 MP@L4.1 HDTV解像度対応 整数画素精度動き検出プロセッサコア

    水野 孝祐, 宮越 純一, 村地 勇一郎, 濱本 真生, 飯沼 隆弘, 石原 朋和, 川口 博, 吉本 雅彦

    第11回システムLSIワークショップ ポスタセッション, 2007年11月, 日本語, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, 国内会議

    ポスター発表

  • VGA 30fps実時間動画像認識応用オプティカルフロープロセッサコア

    村地 勇一郎, 福山 祐貴, 山本 亮, 宮越 純一, 川口 博, 石原 一, 深山 正幸, 松田 吉雄, 吉本 雅彦

    第11回システムLSIワークショップ ポスタセッション, 2007年11月, 日本語, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, 国内会議

    ポスター発表

  • H.264 MP@L4.1エンコーダLSIのためのHDTV解像度対応適応的階層探索動き検出アルゴリズム

    印 芳, 村地 勇一郎, 濱本 真生, 飯沼 隆弘, 石原 朋和, 李 将充, 川口 博, 吉本 雅彦

    第11回システムLSIワークショップ ポスタセッション, 2007年11月, 日本語, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, 国内会議

    ポスター発表

  • DVS環境下での小面積・低電圧動作8T SRAMの設計-32nm世代以降で8Tセルが小面積・低電圧動作を同時に実現

    森田 泰弘, 藤原 英弘, 野口 紘希, 井口 友輔, 新居 浩二, 川口 博, 吉本 雅彦

    第11回システムLSIワークショップ ポスタセッション, 2007年11月, 日本語, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州市, 国内会議

    ポスター発表

  • ビット線電力を削減する;動画像処理応用 10T 非プリチャージ 2-port SRAM

    井口 友輔, 野口 紘希, 奥村 俊介, 藤原 英弘, 森田 泰弘, 新居 浩二, 川口 博, 吉本 雅彦

    VDEC LSIデザイナーフォーラム2007(若手の会)ポスターセッション, 2007年09月, 日本語, 東京大学大規模集積システム設計教育研究センター, 北海道, 国内会議

    ポスター発表

  • ワイヤレスセンサネットワークのためのタイマ制御によるカウンターベースブロードキャスティング方式の改良

    和泉 慎太郎, 松田 隆志, 三上 真司, 川口 博, 太田 能, 吉本 雅彦

    2007年電子情報通信学会総合大会, 2007年03月, 日本語, 電子情報通信学会, 名古屋, 国内会議

    口頭発表(一般)

  • ビット線電力を8割削減する動画像処理応用 10T非プリチャージ2-port SRAM

    井口 友輔, 野口 紘希, 藤原 英弘, 森田 泰弘, 新居 浩二, 川口 博, 吉本 雅彦

    2007年電子情報通信学会総合大会, 2007年03月, 日本語, 電子情報通信学会, 名古屋, 国内会議

    口頭発表(一般)

  • Design Solutions for a Multi-Object Wireless Power Transmission Sheet Based on Plastic Switches

    高宮 真, 関谷 毅, 宮本 善生, 野口 儀晃, 川口 博, 桜井 貴康, 染谷 隆夫

    IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2007年02月, 英語, IEEE, San Francisco, USA, 国際会議

    口頭発表(一般)

  • A Large-area Flexible Wireless Power Transmission Sheet Using Printed Plastic MEMS Switches and Organic Field-effect Transistors

    関谷 毅, 高宮 真, 野口 儀晃, S. NAKANO, 加藤 祐作, K. HIZU, 川口 博, 桜井 貴康, 染谷 隆夫

    IEEE International Electron Devices Meeting Digest of Technical Papers (IEDM), 2006年12月, 英語, IEEE, San Francisco, USA, 国際会議

    口頭発表(一般)

  • (Invited) Flexible Braille Sheet Display with Organic FETs and Plastic Actuators

    高宮 真, 関谷 毅, 加藤 祐作, 川口 博, 染谷 隆夫, 桜井 貴康

    International Display Workshops (IDW), 2006年12月, 英語, 大津市, 国際会議

    [招待有り]

    口頭発表(招待・特別)

  • 超並列画像処理のための、任意位置・水平垂直連続複数画素を同時アクセスできるメモリアーキテクチャ

    石原 朋和, 宮越 純一, 村地 勇一郎, 川口 博, 吉本 雅彦

    第10回システムLSIワークショップ ポスタセッション, 2006年11月, 日本語, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, 国内会議

    ポスター発表

  • 消費電力を50%削減する動的電圧/周波数スケーリング型H.264 Main Profile@Level 4ビデオデコーダLSI

    川上 健太郎, 黒田 光彦, 坂田 義典, 川口 博, 吉本 雅彦

    第10回システムLSIワークショップ ポスタセッション, 2006年11月, 日本語, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, 国内会議

    ポスター発表

  • 実時間動画像認識応用スケーラブルオプティカルフロープロセッサ

    福山祐貴, 山本亮, 宮越純一, 片桐忠義, 峯岸孝行, 川口 博, 深山正幸, 今村幸祐, 橋本秀雄, 吉本 雅彦

    第10回システムLSIワークショップ ポスタセッション, 2006年11月, 日本語, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, 国内会議

    ポスター発表

  • ワイヤレスセンサーネットワーク応用キャリアセンス機能を持つ433MHz帯、356-uW電圧増幅器

    大竹 優, 三上 真司, 竹内 隆, 一圓 真澄, 川口 博, 太田 能, 吉本 雅彦

    第10回システムLSIワークショップ ポスタセッション, 2006年11月, 日本語, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, 国内会議

    ポスター発表

  • ワイヤレスセンサーネットワークにおける送信電力制御による送信効率劣化が消費電力モデルに与えるネガティブインパクト

    三上 真司, 竹内 隆, 大竹 優, 川口 博, 太田 能, 吉本 雅彦

    第10回システムLSIワークショップ ポスタセッション, 2006年11月, 日本語, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, 国内会議

    ポスター発表

  • ビット線電力を53%削減できる実時間動画像処理応用2ポートSRAM

    藤原英弘, 新居浩二, 宮越純一, 村地勇一郎, 森田泰弘, 川口 博, 吉本 雅彦

    第10回システムLSIワークショップ ポスタセッション, 2006年11月, 日本語, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, 国内会議

    ポスター発表

  • しきい値電圧ばらつきを克服したDVS環境下における0.3V動作SRAMの開発

    野口紘希, 森田泰弘, 藤原英弘, 新居浩二, 川口 博, 吉本 雅彦

    第10回システムLSIワークショップ ポスタセッション, 2006年11月, 日本語, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, 国内会議

    ポスター発表

  • Stacked-Chip Implementation of On-Chip Buck Converter for Power-Aware Distributed Power Supply Systems

    ONIZUKA Kohei, 川口 博, 高宮 真, 桜井 貴康

    IEEE Asian Solid-State Circuits Conference Proceedings of Technical Papers (A-SSCC), 2006年11月, 英語, IEEE, Hangzhou, China, 国際会議

    口頭発表(一般)

  • 800-μW H.264 Baseline-Profile対応動き検出プロセッサIP

    飯沼 隆弘, 宮越 純一, 村地 勇一郎, 松野 哲郎, 濱本 真生, 石原 朋和, 川口 博, 深山 正幸, 吉本 雅彦

    第10回システムLSIワークショップ ポスタセッション, 2006年11月, 日本語, 電子情報通信学会集積回路研究専門委員会(ICD), 北九州, 国内会議

    ポスター発表

  • Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications

    ONIZUKA Kohei, 川口 博, 高宮 真, T. KURODA, 桜井 貴康

    Proceedings of IEEE Custom Integrated Circuits Conference (CICC), 2006年09月, 英語, IEEE, San Jose, USA, 国際会議

    口頭発表(一般)

  • (Invited) Low Power and Flexible Braille Sheet Display with Organic FET's and Plastic Actuators

    高宮 真, 関谷 毅, 加藤 祐作, 川口 博, 染谷 隆夫, 桜井 貴康

    Proceedings of IEEE International Conference on IC Design and Technology (ICICDT), 2006年05月, 英語, Italy, 国際会議

    口頭発表(一般)

  • 動的電圧制御環境下における0.3-V 動作64-kb SRAM

    森田 泰弘, 藤原 英弘, 野口 紘希, 川上 健太郎, 宮越 純一, 三上 真司, 新居 浩二, 川口 博, 吉本 雅彦

    2006年電子情報通信学会総合大会;AS-2-2, 2006年03月, 日本語, 電子情報通信学会, 東京都, 国内会議

    口頭発表(一般)

  • 動的電圧制御環境下における0.3-V 動作64-kb SRAM

    森田 泰弘, 藤原 英弘, 野口 紘希, 川上 健太郎, 宮越 純一, 三上 真司, 新居 浩二, 川口 博, 吉本 雅彦

    電子情報通信学会総合大会, 2006年03月, 日本語, 東京, 国内会議

    口頭発表(一般)

  • センサノードの製造バラツキを考慮したネットワーク可用時間改善の一検討

    芳野 宏徳, 青西 孝文, 一圓 真澄, 松田 隆志, 太田 能, 川口 博, 吉本 雅彦

    2006年電子情報通信学会総合大会;BS-10-5, 2006年03月, 日本語, 電子情報通信学会, 東京都, 国内会議

    口頭発表(一般)

  • センサノードの製造バラツキを考慮したネットワーク可用時間改善の一検討

    芳野 宏徳, 青西 孝文, 一圓 真澄, 松田 隆志, 太田 能, 川口 博, 吉本 雅彦

    電子情報通信学会総合大会, 2006年03月, 日本語, 東京, 国内会議

    口頭発表(一般)

  • センサネットワークのための集約率を考慮したGIT経路制御の評価

    青西 孝文, 芳野 宏徳, 三上 真司, 太田 能, 川口 博, 吉本 雅彦

    電子情報通信学会技術研究報告, 2005年10月, 日本語, 新潟, 国内会議

    口頭発表(一般)

  • ワイヤレスセンサノードのための送信電力制御におけるインピーダンス不整合の影響

    三上 真司, 竹内 隆, 太田 能, 川口 博, 吉本 雅彦

    電子情報通信学会ソサイエティ大会, 2005年09月, 日本語, 北海道大学, 国内会議

    口頭発表(一般)

  • 二重ワード線と二重ビット線を用いた3次元積層シート型スキャナ

    川口 博, 伊庭 信吾, 加藤 祐作, 関谷 毅, 染谷 隆夫, 桜井 貴康

    電子情報通信学会技術研究報告, 2005年05月, 日本語, 神戸, 国内会議

    口頭発表(一般)

所属学協会

  • ACM

  • IEEE

共同研究・競争的資金等の研究課題

産業財産権

  • 低電圧動作キャッシュメモリ

    吉本 雅彦, 川口 博, 中田 洋平, 奥村 俊介, 鄭 晋旭

    特願2012-267445, 2012年12月06日, 大学長, 特許6024897, 2016年10月21日

    特許権

  • 半導体メモリおよびプログラム(韓国)

    吉本 雅彦, 川口 博, 藤原 英弘, 奥村 俊介

    10-2010-7016180, 2009年01月07日, TLO, 10-1569540, 2015年11月10日

    特許権

  • メモリセルアレイを用いたIDチップ

    吉本 雅彦, 川口 博, 奥村 俊介

    特願2010-219910, 2010年09月29日, 大学長, 特許5499365, 2014年03月20日

    特許権

  • データ一括比較処理回路、データ一括比較処理方法およびデータ一括比較プログラム

    吉本 雅彦, 川口 博, 奥村 俊介

    特願2010-219902, 2010年09月29日, 大学長, 特許5488920, 2014年03月07日

    特許権

  • キャッシュメモリとそのモード切替方法

    吉本 雅彦, 川口 博, 中田 洋平

    特願2009-189603, 2009年08月18日, 大学長, 特許5397843, 2013年11月01日

    特許権

  • 共有キャッシュメモリとそのキャッシュ間のデータ転送方法

    吉本 雅彦, 川口 博, 藤原 英弘, 奥村 俊介

    特願2009-082997, 2009年03月30日, 大学長, 特許5311309, 2013年07月12日

    特許権

  • 半導体メモリのハーフセレクト防止セル配置

    吉本 雅彦, 川口 博, 藤原 英弘, 奥村 俊介

    特願2009-000012, 2009年01月04日, 大学長, 特許5298373, 2013年06月28日

    特許権

  • 画像処理用メモリ

    吉本 雅彦, 川口 博, 宮越 純一, 村地勇一郎

    特願2007-298743, 2007年11月18日, 大学長, 特許5261694, 2013年05月10日

    特許権

  • 半導体メモリのメモリセル間のデータコピー方法

    吉本 雅彦, 川口 博, 藤原 英弘, 奥村 俊介

    特願2009-082996, 2009年03月30日, 大学長, 特許5256534, 2013年05月02日

    特許権

  • 半導体メモリおよびプログラム

    吉本 雅彦, 川口 博, 藤原 英弘, 奥村 俊介

    特願2009-548936, 2009年01月07日, TLO, 特許5196449, 2013年02月15日

    特許権

  • 不良メモリセルの予知診断アーキテクチャーと予知診断方法

    吉本 雅彦, 川口 博, 藤原 英弘, 奥村 俊介

    特願2009-082998, 2009年03月30日, 大学長, 特許5187852, 2013年02月01日

    特許権

  • 半導体記憶装置

    吉本 雅彦, 川口 博, 藤原 英弘, 森田 泰弘

    特願2006-061644, 2006年03月07日, TLO, 特許5119489, 2012年11月02日

    特許権

  • 半導体メモリおよびプログラム SEMICONDUCTOR MEMORY AND PROGRAM

    吉本 雅彦, 川口 博, 藤原 英弘, 奥村 俊介

    US12,809,684, 2009年01月07日, TLO, 8,238,140, 2012年08月07日

    特許権

  • 画像処理装置

    吉本 雅彦, 川口 博, 宮越 純一, 村地 勇一郎, 濱本 真生, 飯沼 隆弘, 石原 朋和

    特願2007-298142, 2007年11月16日, 大学長, 特許5020029, 2012年06月22日

    特許権

  • センサネットワークにおける無線トランシーバー用電圧増幅器

    吉本 雅彦, 太田 能, 川口 博, 三上 真司

    特願2007-035223, 2007年02月15日, 大学長, 特許5019362, 2012年06月22日

    特許権

  • センサネットワークシステム及びメディアアクセス制御方法

    吉本 雅彦, 太田 能, 川口 博, 一圓 真澄

    特願2006-279761, 2006年10月13日, 大学長, 特許4919204, 2012年02月10日

    特許権

  • データ送信スケジューリング方法およびそれを用いたセンサネットワークシステム

    吉本 雅彦, 川口 博, 太田 能, 三上 真司

    特願2006-279760, 2006年10月13日, 大学長, 特許4863069, 2011年11月18日

    特許権