Directory of Researchers
| KUROKI Nobutaka |  |
| Graduate School of Engineering / Department of Electrical and Electronic Engineering | |
| Associate Professor | |
| Electro-Communication Engineering |
Researcher Profile and Settings
Affiliation
＜Faculty / Graduate School / Others＞
Graduate School of Engineering / Department of Electrical and Electronic Engineering＜Related Faculty / Graduate School / Others＞
Faculty of Engineering / Department of Electrical and Electronic Engineering, Center for Mathematical and Data Sciences
Teaching
- Faculty of Engineering / Department of Electrical and Electronic Engineering, 2022, Electric Circuit Theory IA
- Faculty of Engineering / Department of Electrical and Electronic Engineering, 2022, Electric Circuit Theory Practice A
- Faculty of Engineering / Department of Electrical and Electronic Engineering, 2022, Electric Circuit Theory I
- Faculty of Engineering / Department of Electrical and Electronic Engineering, 2022, Electric Circuit Theory Practice
- Faculty of Engineering / Department of Electrical and Electronic Engineering, 2022, Electric Circuit Theory Practice
- Faculty of Engineering / Department of Electrical and Electronic Engineering, 2022, Electric Circuit Theory IB
- Faculty of Engineering / Department of Electrical and Electronic Engineering, 2022, Electric Circuit Theory Practice B
- Faculty of Engineering / Department of Electrical and Electronic Engineering, 2022, Electrical and Electronics Engineering Laboratory I and Safety Guidance A
- Faculty of Engineering / Department of Electrical and Electronic Engineering, 2022, Electrical and Electronics Engineering Laboratory I and Safety Guidance
- Faculty of Engineering / Department of Electrical and Electronic Engineering, 2022, Electrical and Electronics Engineering Laboratory I and Safety Guidance B
- Graduate School of Engineering / Department of Electrical and Electronic Engineering, 2022, Special Lecture ⅠＡ
- Graduate School of Engineering / Department of Electrical and Electronic Engineering, 2022, Advanced Electrical and Electronics Seminar
- Graduate School of Engineering / Department of Electrical and Electronic Engineering, 2022, Special Lecture ⅠＢ
- Graduate School of Engineering / Department of Electrical and Electronic Engineering, 2022, Integrated Circuit Design
- Graduate School of Engineering / Department of Electrical and Electronic Engineering, 2022, Advanced Course on Image Processing
Research Activities
Research Interests
Research Areas
Committee Memberships
Awards
Aug. 2019 第32回 回路とシステムワークショップ, 奨励賞, 極低電圧エネルギーハーベスティングに向けたスイッチトキャパシタ型昇圧コンバータ
May 2018 第31回 回路とシステムワークショップ, 奨励賞, 最大効率点追従制御を用いたスイッチトキャパシタ型降圧コンバータの高効率化
Sep. 2017 東京大学VDEC, 平成29年度VDECデザイナーズフォーラム, 優秀賞, 超低消費電力32-kHzリアルタイムクロック生成回路
Japan society
Sep. 2017 IEEE SSCS Japan Chapter, IEEE SSCS Japan Chapter VDEC Design Award, 超低消費電力32-kHzリアルタイムクロック生成回路
Japan society
May 2017 IEEE SSCS Japan Chapter, IEEE SSCS Japan Chapter Academic Research Award, リアルタイムクロックに向けた電流比較型超低電力フルオンチップRC発振器
Japan society
Aug. 2016 平成28年度 VDECデザイ ナーズフォーラム, 優秀賞, 1マイクロ秒以内の高速起動を特徴とする高精度32-MHz弛張発振器
Japan society
Jun. 2016 14th IEEE International NEWCAS Conference, Best Student Paper Award, A fully integrated, 1-us start-up time, 32-MHz relaxation oscillator for low-power intermittent systems
International society
May 2016 電子情報通信学会集積回路研究専門委員会, IEEE SSCS Japan Chapter Academic Research Award, 間欠動作型VLSIシステムに向けた高速起動可能な32-MHzフルオンチップ弛張発振器
Japan society
Published Papers
In the world today, we can always shoot digital videos with smartphones and share them with family or friends after editing them. It is necessary to check whether these videos have been tampered with to use them as forensic evidence in criminal investigations. This paper proposes a method for detecting tampered regions in a video where a specific subject is removed from a scene. In the proposed method, we use LSTM for the time domain analysis and UNet for the space domain analysis. The detection accuracy achieved 0.98 in terms of F-measure, even though tampered the region was deformed or moved in the video. The experimental results show superior performance in the detection of tampered regions in digital videos.
WILEY, Aug. 2020, ELECTRONICS AND COMMUNICATIONS IN JAPAN, English[Refereed]
Scientific journal
- Improvement of Luminance Isotropy for Convolutional Neural Networks-Based Image Super-Resolution
Convolutional neural network (CNN)-based image super-resolutions are widely used as a high-quality image-enhancement technique. However, in general, they show little to no luminance isotropy. Thus, we propose two methods, "Luminance Inversion Training (LIT)" and "Luminance Inversion Averaging (LIA)," to improve the luminance isotropy of CNN-based image super-resolutions. Experimental results of 2× image magnification show that the average peak signal-to-noise ratio (PSNR) using Luminance Inversion Averaging is about 0.15-0.20dB higher than that for the conventional super-resolution.
Institute of Electronics, Information and Communication Engineers(IEICE), 01 Jul. 2020, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 103 (7), 955 - 958, English[Refereed]
This paper proposes an ultra-low power active diode (ADIO) using a hysteresis common gate comparator for low-voltage and low-power energy harvesting systems. The proposed ADIO consists of a MOS switch and hysteresis common gate comparator, which eliminates unwanted ripple and noise voltages. The hysteresis comparator controls the MOS switch to turn ON or OFF, depending on the input and output voltages. The hysteresis voltages of the comparator can be controlled by the current flowing in the comparator. The measurement results demonstrated that the hysteresis comparator had -26 and 25 mV hysteresis voltages and the ADIO using the hysteresis comparator eliminated unwanted ripple voltage. The maximum current consumption of our ADIO was 11.8 nA.
Institute of Electronics, Information and Communication Engineers(IEICE), 10 Jun. 2020, IEICE Electronics Express, 17 (11), 20200103 - 20200103, English[Refereed]
Scientific journal
- IEEE, Jun. 2020, 2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)
International conference proceedings
- IEEE, Jun. 2020, 2020 18th IEEE International New Circuits and Systems Conference (NEWCAS), English
[Refereed]
International conference proceedings
- Feb. 2020, 2020 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2020), EnglishRotation invariant-digits recognition with single convolutional neural networks
[Refereed]
International conference proceedings
- Feb. 2020, 2020 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2020), EnglishCNN-based Segmentationand Recognition of Traffic Signs with Parameter Regions
[Refereed]
International conference proceedings
This paper proposes an image super-resolution using convolutional neural networks (CNNS) with multiple paths.
After SRCNN was proposed by C. Dong et al., CNN-based super resolutions are getting larger and deeper. They do not work quickly without accelerators such as GPU any more. For practical use, however, we need to design CNNs with less internal parameters and low computational costs for convolution operation.
The proposed CNN architecture consists of multiple paths with different depth. While a shallow path generates low frequency components, a deep path generates high frequency ones. Finally, they are synthesized at the last layer. This architecture can reduce the number of parameters relative to its performance.
Experimental results have shown that the average processing time for the proposed CNN was only 25% of the conventional MCH while keeping high image qualities.
The Institute of Electrical Engineers of Japan, 2020, IEEJ Transactions on Electronics, Information and Systems, 140 (6), 638 - 650, Japanese[Refereed]
© 2019 IEEE. This paper proposes an extremely-low-voltage CMOS driver circuit for multi-stage switched-capacitor (SC) voltage boost converter (VBC). The SC VBC using a conventional driver could not generate sufficient boosted clock signals when the input voltage becomes low. This is because the output voltages of the driver degrade significantly as the input voltage decreases. To mitigate the problem, we develop the low-voltage CMOS driver circuit to improve the low-voltage operation of the SC VBC. The proposed driver consists of a ring oscillator, non-overlap clock generator, and main driver (MD) circuits. Simulated results demonstrated that the proposed driver can generate sufficient amplitude of the clock signals and the SC VBC using the proposed driver generates a 600-mV output from a 100-mV input when the voltage conversion ratio of the VBC is set to 6. The peak efficiency was 48.9% at 120-nA load current. The driver circuit can operate at 79-mV input voltage.
Nov. 2019, 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019, 530 - 533[Refereed]
International conference proceedings
- Oct. 2019, The 22nd Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2019), EnglishAn error diagnosis technique using ZDD to extract error location sets
[Refereed]
International conference proceedings
- Oct. 2019, The 22nd Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2019), EnglishIncremental approaches for locating design errors: averaging epi-groups and generating additional input patterns
[Refereed]
International conference proceedings
- Oct. 2019, The 22nd Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2019), EnglishA global placement method for RECON spare cells in ECO-friendly design style
[Refereed]
International conference proceedings
- Oct. 2019, The 22nd Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2019), EnglishA 4ch CNN hardware architecture for image super-resolution
[Refereed]
International conference proceedings
© 2018 IEEE. This paper proposes an ultra-low power active diode using a hysteresis common gate comparator for low-voltage and low-power energy harvesting systems. The proposed active diode consists of a MOS switch and hysteresis common gate comparator, which eliminates unwanted ripple and noise voltages. The hysteresis comparator controls the MOS switch to turn ON or OFF, depending on the input and output voltages. The hysteresis voltages of the comparator can be controlled by the current flowing in the comparator. Simulation results demonstrated that the hysteresis comparator has a -27 and 25 mV hysteresis voltages and the active diode using the hysteresis comparator eliminates unwanted ripple voltage.
The Institute of Electrical and Electronics Engineers, 19 Feb. 2019, IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, 2018-October, 196 - 200, English[Refereed]
International conference proceedings
© 2018 IEEE. This paper presents an ultra-low-power switched-capacitor (SC) voltage buck converter (VBC) with step-down-ratio and clock-frequency controllers for ultra-low-power IoT devices. The proposed VBC consists of an n/8 SC VBC, step-down ratio controller, clock (CLK) generator, load current monitor, local VDD generator, and output voltage monitor. The step-down-ratio controller monitors an input voltage and then changes the step-down ratio n/8 of the SC VBC according to the input voltage (n=5,6,7,8). This enables the SC VBC wide input voltage operation. The CLK generator with the load current monitor changes an operating clock frequency in accordance with the load current to achieve highly efficient power conversion. Simulation results demonstrated that our proposed VBC converted 1.4-2.4 V input to 1.33-1.57 V output. The power dissipation at the steady state was 14.6 nW.
The Institute of Electrical and Electronics Engineers, 17 Jan. 2019, 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018, 209 - 212, English[Refereed]
International conference proceedings
- 電気学会, Nov. 2018, 電気学会論文誌C（電子・情報・システム部門誌）, 138 (11), 1417 - 1424, Japanese
[Refereed]
Scientific journal
© 2018 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc. In this paper, we propose a fully integrated and area-efficient resistor-less relaxation oscillator (ROSC) for ultra-low power real-time clock (RTC) applications. The proposed ROSC is based on a conventional current-mode ROSC and is modified to be an area-efficient circuit configuration without using resistors. The proposed ROSC consists of a temperature-compensated bias current generator (BCG), proportional to absolute temperature (PTAT) voltage source, current-mode ROSC, shunt regulator, and output logic circuit. The BCG, PTAT voltage source, and shunt regulator are used to compensate for the temperature characteristics of the ROSC. The area of our proposed ROSC was extremely small, 0.022 mm2. Simulated results demonstrated that our proposed ROSC generates a 32.5 kHz clock frequency and achieves ultra-low power dissipation of 271 nW. The temperature and voltage dependence of the oscillation frequency were 138 ppm/°C and 13.9 ppm/mV, respectively. Monte Carlo statistical simulations showed that the mean, standard deviation, and coefficient of variation are 32.3, 0.6 kHz, and 1.9%, respectively. © 2018 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.
Institute of Electrical Engineers of Japan, Nov. 2018, IEEJ Transactions on Electrical and Electronic Engineering, 13 (11), 1633 - 1641, English[Refereed]
Scientific journal
© 2018 The Japan Society of Applied Physics. In this paper, we present a wide-load-range switched-capacitor DC-DC buck converter with an adaptive bias comparator for ultra-low-power power management integrated circuit. The proposed converter is based on a conventional one and modified to operate in a wide load range by developing a load current monitor used in an adaptive bias comparator. Measurement results demonstrated that our proposed converter generates a 1.0V output voltage from a 3.0V input voltage at a load of up to 100 μA, which is 20 times higher than that of the conventional one. The power conversion efficiency was higher than 60% in the load range from 0.8 to 100 μA.
The Japan Society of Applied Physics, Apr. 2018, Japanese Journal of Applied Physics, 57 (4), English[Refereed]
International conference proceedings
© 2018 IEEE. An analytical study of a multi-stage switched-capacitor (SC) voltage boost converter (VBC) for ultra-low voltage energy harvesting is presented. Because the output impedance of the VBC plays an important role in the VBC's performance, we developed an analytical model to achieve a highly efficient VBC. In our proposed method, we focus on currents flowing into input and output terminals of each stage and model the VBCs using switching frequency f, charge transfer capacitance Cf, and load capacitance CL. A comparison between simulated and calculated results showed that our model can estimate the output impedance of the VBC accurately. Our model is useful to compare the relative merits of different types of multi-stage SC VBCs.
The Institute of Electrical and Electronics Engineers, Apr. 2018, Proceedings - IEEE International Symposium on Circuits and Systems, 2018-May, 1 - 5, English[Refereed]
International conference proceedings
This paper presents a fully integrated 32-MHz relaxation oscillator (ROSC) capable of sub-1-mu s start-up time operation for low-power intermittent VLSI systems. The proposed ROSC employs current mode architecture that is different from conventional voltage mode architecture. This enables compact and fast switching speed to be achieved. By designing transistor sizes equally between one in a bias circuit and another in a voltage to current converter, the effect of process variation can be minimized. A prototype chip in a 0.18-mu m CMOS demonstrated that the ROSC generates a stable clock frequency of 32.6 MHz within 1-mu s start-up time. Measured line regulation and temperature coefficient were +/- 0.69% and +/- 0.38%, respectively.
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Mar. 2018, IEICE TRANSACTIONS ON ELECTRONICS, E101C (3), 161 - 169, English[Refereed]
Scientific journal
© 2018 The Institute of Electronics, Information and Communication Engineers. This paper presents a fully integrated 32-MHz relaxation oscillator (ROSC) capable of sub-1-μs start-up time operation for lowpower intermittent VLSI systems. The proposed ROSC employs current mode architecture that is different from conventional voltage mode architecture. This enables compact and fast switching speed to be achieved. By designing transistor sizes equally between one in a bias circuit and another in a voltage to current converter, the effect of process variation can be minimized. A prototype chip in a 0.18-μm CMOS demonstrated that the ROSC generates a stable clock frequency of 32.6 MHz within 1-μs start-up time. Measured line regulation and temperature coefficient were ±0.69% and ±0.38%, respectively.
The Institute of Electronics, Information and Communication Engineers, Mar. 2018, IEICE Transactions on Electronics, E101C (3), 161 - 169, English[Refereed]
Scientific journal
- SASIMI Workshop, Mar. 2018, Proceedings of the 21st workshop on synthesis and system integration of mixed information technologies, 81 - 86, EnglishAn error diagnosis technique based on unsatisfiable cores to extract error locations sets
[Refereed]
Scientific journal
© 2017 IEEE. This paper proposes an ultra-low-power supercapacitor voltage monitoring system (VMS) for low-voltage energy harvesting. The proposed VMS consists of a voltage divider, control logic circuit, multiplexer (MUX), sample-and-hold circuit, nano-ampere current reference (IREF), and 4-bit successive approximation register analog to digital converter (SAR ADC). The proposed VMS monitors the supercapacitor voltage and converts it into digital codes. We employ power gating technique and a nano-ampere current reference circuit to achieve ultra-low power operation. Simulation results showed that our proposed VMS achieved the DNL/INL of 0.15/0.21LSB. Its ENOB was 3.83bit at 100 Hz and the average power dissipation was 58.0 nW.
The Institute of Electrical and Electronics Engineers, 14 Feb. 2018, ICECS 2017 - 24th IEEE International Conference on Electronics, Circuits and Systems, 2018-January, 498 - 501, English[Refereed]
International conference proceedings
© 2017 IEEE. This paper proposes a fully integrated voltage boost converter (VBC) for low-voltage energy harvesting. The proposed VBC consists of three stage charge pumps (CPs) with a low-leakage driver, ring oscillator, and 4-phase clock generator. The output voltage is four times higher than an input voltage Fin. The low-leakage driver generates control signals to operate CPs with low leakage current. The amplitude of the control signals is 2VIN and does not depend on the load current. The proposed VBC achieves a wide load current, high output voltage, and high efficiency, even with a low-voltage input of the harvester. Simulation results demonstrated that the proposed VBC converted 0.1-V input to 0.362-V output and 0.6-V input to 2.38-V output, when the load current is zero. The peak efficiency was 70.3% at a 0.6-V input and 1-mA load current.
The Institute of Electrical and Electronics Engineers, 14 Feb. 2018, ICECS 2017 - 24th IEEE International Conference on Electronics, Circuits and Systems, 2018-January, 502 - 505, English[Refereed]
International conference proceedings
- Analytical Study of Multi-stage Switched-Capacitor Voltage Boost Converter for Ultra-low Voltage Energy Harvesting
An analytical study of a multi-stage switched-capacitor (SC) voltage boost converter (VBC) for ultra-low voltage energy harvesting is presented. Because the output impedance of the VBC plays an important role in the VBC's performance, we developed an analytical model to achieve a highly efficient VBC. In our proposed method, we focus on currents flowing into input and output terminals of each stage and model the VBCs using switching frequency f, charge transfer capacitance C-F, and load capacitance C-L. A comparison between simulated and calculated results showed that our model can estimate the output impedance of the VBC accurately. Our model is useful to compare the relative merits of different types of multi-stage SC VBCs.
IEEE, 2018, 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), English[Refereed]
International conference proceedings
© 2018 The Institute of Electrical Engineers of Japan. This paper proposes an image super-resolution technique with convolutional neural networks using horizontal and vertical filters. In the proposed method, calculation costs become small because square filters at a hidden layer are replaced with horizontal and vertical bar filters. Experimental results have shown that the average processing time for the proposed architecture was only a half of the conventional one while keeping high image qualities.
電気学会, 2018, IEEJ Transactions on Electronics, Information and Systems, 138 (7), 957 - 963, Japanese[Refereed]
Scientific journal
© 2017 IEEE. In this paper, we propose a fully integrated and area-efficient resistor-less relaxation oscillator (ROSC) for ultra-low power real-time clock (RTC) applications. The proposed ROSC is based on a conventional ROSC and modified to be area-efficient circuit configuration, without using resistors. The proposed ROSC consists of a bias current source, proportional to absolute temperature (PTAT) voltage source, current mode ROSC, shunt regulator, and output logic circuit. The PTAT voltage source and shut regulator are used to compensate for the temperature characteristics of the ROSC. By implementing our proposed ROSC in a 65-nm CMOS process, the area was 0.022 mm2. Simulated results demonstrated that our proposed ROSC generates 32.5-kHz clock frequency and achieves ultra-low power dissipation of 271 nW. The temperature and voltage dependences of the oscillation frequency were 138ppm/°C and 13.9ppm/mV, respectively. Monte Carlo statistical simulations showed that the mean, standard deviation, and the coefficient of variation are 32.3 kHz, 0.6 kHz, and 1.9%, respectively.
The Institute of Electrical and Electronics Engineers, 25 Sep. 2017, Proceedings - IEEE International Symposium on Circuits and Systems, 477 - 480, English[Refereed]
International conference proceedings
- The Japan Society of Applied Physics, Sep. 2017, Extended abstract of the 2017 international conference on solid state devices and materials, 511 - 512, EnglishA wide load range switched capacitor DC-DC converter with adaptive bias comparator for ultra-low-power power management integrated circuit
[Refereed]
Scientific journal
We present a low-power and low-energy level shifter (LS) circuit that can convert extremely low-voltage input into high-voltage output. The proposed LS consists of a pre-amplifier (pre-AMP) and an output latch. The pre-AMP employs a logic error correction circuit, which generates an operating current for the pre-AMP only when the logic levels of the input and output do not correspond. The pre-AMP generates complementary amplified signals, and the latch converts them into full-swing outputs. Measurement results demonstrated that the proposed LS fabricated in 0.18-mu m CMOS technology was able to convert an extremely low-voltage input of 80 mV into a high-voltage output of 1.8 V. The energy of the proposed LS was 0.35 pJ, when the low supply voltage, high supply voltage, and input pulse frequency were 0.4 V, 1.8 V, and 10 kHz, respectively. The static power dissipation without input was 0.12 nW.
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, Aug. 2017, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 64 (8), 2026 - 2035, English[Refereed]
Scientific journal
In this paper, we present a 151 nA quiescent and 6.8mA maximum-output-current low-dropout (LDO) linear regulator for micropower battery management. The LDO regulator employs self-biasing and multiple-stacked cascode techniques to achieve efficient, accurate, and high-voltage-input-tolerant operation. Measurement results demonstrated that the proposed LDO regulator operates with an ultralow quiescent current of 151 nA. The maximum output currents with a 4.16 V output were 1.0 and 6.8mA when the input voltages were 4.25 and 5.0 V, respectively. (C) 2017 The Japan Society of Applied Physics
IOP PUBLISHING LTD, Apr. 2017, JAPANESE JOURNAL OF APPLIED PHYSICS, 56 (4), 04CF11, English[Refereed]
Scientific journal
- Mar. 2017, Proceedings of the 2017 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2017), 1PM2 - 3-3, EnglishSegmentation and colorization of grayscale image using convolutional neural network
[Refereed]
International conference proceedings
- Mar. 2017, Proceedings of the 2017 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2017), 1AM2 - 1-4, EnglishRestoring defocus images with Wiener filter and convolutional neural network
[Refereed]
International conference proceedings
- Mar. 2017, Proceedings of the 2017 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2017), 3AM2 - 3-5, EnglishA study on point cloud registration with SIFT features
[Refereed]
International conference proceedings
© 2017 The Institute of Electronics, Information and Communication Engineers. This paper proposes image super-resolution techniques with multi-channel convolutional neural networks. In the proposed method, output pixels are classified into K × K groups depending on their coordinates. Those groups are generated from separate channels of a convolutional neural network (CNN). Finally, they are synthesized into a K × K magnified image. This architecture can enlarge images directly without bicubic interpolation. Experimental results of 2×2, 3×3, and 4×4 magnifications have shown that the average PSNR for the proposed method is about 0.2 dB higher than that for the conventional SRCNN.
Feb. 2017, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E100A (2), 572 - 580, English[Refereed]
Scientific journal
This paper proposes image super-resolution techniques with multi-channel convolutional neural networks. In the proposed method, output pixels are classified into K x K groups depending on their coordinates. Those groups are generated from separate channels of a convolutional neural network (CNN). Finally, they are synthesized into a K x K magnified image. This architecture can enlarge images directly without bicubic interpolation. Experimental results of 2x2, 3x3, and 4x4 magnifications have shown that the average PS NR for the proposed method is about 0.2 dB higher than that for the conventional SRCNN.
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Feb. 2017, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E100A (2), 572 - 580, English[Refereed]
Scientific journal
Today we can take many pictures with smart phones or digital cameras, and can edit them easily by ourselves. These pictures are very useful not only for hobby, but for investigation. It is very important to check whether they are doctored or not. This paper proposes an automatic detection method of doctored JPEG images based on two different analyisis: the block noise analysis and the Double-JPEG analysis. Former can find unnatural boundaries of 8×8 DCT blocks while latter can find double saved images by other editing software. Finally SVM classifies images into doctored and undoctored groups based on the above analysis. Experimental results have shown that the detection accuracy of our method achieves 0.90 in terms of F-measure while J. He's method achieves 0.82.
Institute of Electrical Engineers of Japan, 2017, IEEJ Transactions on Electronics, Information and Systems, 137 (5), 742 - 749, Japanese[Refereed]
Scientific journal
- Sub-1-mu s Start-up Time, 32-MHz Relaxation Oscillator for Low-Power Intermittent VLSI Systems
We propose a sub-1-mu s start-up time, fully integrated 32-MHz relaxation oscillator (ROSC) for intermittent VLSI systems. Our proposed ROSC employs current mode architecture that is different from conventional voltage mode architecture. This enables compact and fast switching speed to be achieved. The measurement results demonstrated that the ROSC achieved sub-1-mu s start-up time and generated stable output frequency of 32.6 MHz. Measured line regulation, temperature coefficient, and variation coefficient in 10 samples were +/- 0.69, +/- 0.38, and 0.62%, respectively.
IEEE, 2017, 2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 35 - 36, English[Refereed]
International conference proceedings
In this paper, we present an impedance matching technique in magnetic-coupling-resonance wireless power transfer system for small implantable medical devices. By developing an equivalent circuit model of the WPT system, we show that impedance matching can be realized. Electromagnetic field simulations demonstrated that our proposed technique has capability of achieving maximum input power and available efficiency without using impedance matching circuits.
IEEE, 2017, 2017 IEEE WIRELESS POWER TRANSFER CONFERENCE (WPTC 2017), 1 - 4, English[Refereed]
International conference proceedings
Copyright © 2016 The Institute of Electronics, Information and Communication Engineers. This paper presents a fully integrated voltage boost converter consisting of a charge pump (CP) and maximum power point tracking (MPPT) controller for ultra-low power energy harvesting. The converter is based on a conventional CP circuit and can deliver a wide range of load current by using nMOS and pMOS driver circuits for highly efficient charge transfer operation. The MPPT controller we propose dissipates nano-watt power to extract maximum power regardless of the harvester's power generation conditions and load current. The measurement results demonstrated that the circuit converted a 0.49-V input to a 1.46-V output with 73% power conversion efficiency when the output power was 348 μW. The circuit can operate at an extremely low input voltage of 0.21V.
Dec. 2016, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E99A (12), 2491 - 2499, English[Refereed]
International conference proceedings
This paper presents a fully integrated voltage boost converter consisting of a charge pump (CP) and maximum power point tracking (MPPT) controller for ultra-low power energy harvesting. The converter is based on a conventional CP circuit and can deliver a wide range of load current by using nMOS and pMOS driver circuits for highly efficient charge transfer operation. The MPPT controller we propose dissipates nano-watt power to extract maximum power regardless of the harvester's power generation conditions and load current. The measurement results demonstrated that the circuit converted a 0.49-V input to a 1.46-V output with 73% power conversion efficiency when the output power was 348 mu W. The circuit can operate at an extremely low input voltage of 0.21V.
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Dec. 2016, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E99A (12), 2491 - 2499, English[Refereed]
Scientific journal
- Oct. 2016, Proceedings of the 20th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2016), 205 - 210, EnglishOn component ratio of RECON spare cells for ECO-friendly design style
[Refereed]
International conference proceedings
This paper proposes a fully-integrated high-conversion-ratio dual-output voltage boost converter (VBC) with maximum power point tracking (MPPT) circuits for low-voltage energy harvesting. The VBC consists of two voltage generators that generate V-OUT1 and V-OUT2. V-OUT1 and V-OUT2 are three and nine times higher than the harvester's output V-IN, respectively. V-OUT1 is used as a supply voltage for on-chip application circuits while V-OUT2 is used as the charging voltage for a Li-ion secondary battery. The VBC achieves a high voltage conversion ratio (max. x 9) and a high power conversion efficiency. The MPPT circuits control the operating frequencies of the CPs to extract maximum power at each output. The measurement results demonstrated that the circuit converted a 0.59 V input to a 1.41 V output with 75.8% efficiency when the output powers of V-OUT1 and V-OUT2 were 396 and 0 mu W, respectively, and a 0.62 V input to a 4.54 V output with 49.1% efficiency when the output powers were 0 and 114 mu W, respectively.
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, Oct. 2016, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 51 (10), 2398 - 2407, English[Refereed]
Scientific journal
- Oct. 2016, Proceedings of the 20th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2016), 317 - 322, EnglishAn error diagnosis technique based on averaged EPI values to extract error locations sets
[Refereed]
International conference proceedings
- Oct. 2016, Proceedings of the 20th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2016), 268 - 273, EnglishA hardware architecture to perform K-means clustering for learning-based super-resolution combining self-learning and prior-learning dictionaries
[Refereed]
International conference proceedings
- Sep. 2016, Extended abstract of the 2016 International Conference on Solid State Devices and Materials (SSDM 2016), 463 - 464, EnglishA self-biased low-dropout linear regulator for ultra-low power battery management
[Refereed]
Research society
- Sep. 2016, 第15回情報科学技術フォーラム（FIT2016）講演論文集, RI - 005, Japanese4出力の畳み込みニューラルネットワークを用いた超解像
[Refereed]
Symposium
- May 2016, 第29回 回路とシステムワークショップ論文集, 301 - 306, Japanese極低入力電圧を昇圧するチャージポンプ回路の設計
[Refereed]
Symposium
- May 2016, 電子情報通信学会論文誌, J99-D (5), 588 - 593, Japanese4並列の畳み込みニューラルネットワークを用いた超解像
[Refereed]
Scientific journal
- Apr. 2016, Journal of Signal Processing, 20 (4), 217 - 220, EnglishLocally weighted averaging for denoising of medical tomographic images
[Refereed]
Scientific journal
- Research institute of signal processing japan, Mar. 2016, RISP international workshop on nonlinear circuits, 570 - 573, EnglishThree dimensional NL-Means method for denoising continuous shooting photography
[Refereed]
International conference proceedings
- Research institute of signal processing japan, Mar. 2016, RISP international workshop on nonlinear circuits, 566 - 569, EnglishNoise reduction for medical tomographic images based on locally weighted averaging
[Refereed]
International conference proceedings
- Research institute of signal processing japan, Mar. 2016, RISP international workshop on nonlinear circuits, 423 - 426, EnglishCrack extraction from noisy images with fractal dimension analysis
[Refereed]
International conference proceedings
- Research institute of signal processing japan, Mar. 2016, RISP international workshop on nonlinear circuits, 419 - 422, EnglishAnomalous behavior detection in videos based on deformable part models
[Refereed]
International conference proceedings
- The japan society of applied physics, Mar. 2016, Japanese journal of applied phisycs, 55 (4s), 04EF09 - 1-04EF09-5, EnglishA fully on-chip 3-terminal switched-capacitor DC-DC converter for low-voltage CMOS LSIs
[Refereed]
Scientific journal
- Image Super-Resolution with Multi-Channel Convolutional Neural Networks
This paper proposes image super-resolution techniques with multi-channel convolutional neural networks (CNN). In the proposed method, output pixels are classified into four groups depending on their positions. Those groups are generated from separate channels of the CNN. Finally, they are synthesized into a 2x2 magnified image. This architecture can enlarge images directly without bicubic interpolation. Experimental results have shown that the average PSNR for the proposed method achieves 36.88 dB, which is 0.39 dB higher than that for the conventional SRCNN.
IEEE, 2016, 2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 1 - 4, English[Refereed]
International conference proceedings
- A Fully Integrated, 1-mu s Start-up Time, 32-MHz Relaxation Oscillator for Low-Power Intermittent Systems
This paper proposes a fully integrated 32-MHz relaxation oscillator (ROSC) capable of fast start-up time operation for low-power intermittent VLSI systems. The proposed ROSC employs current mode architecture that is different from conventional voltage mode architecture. This enables compact and fast switching speed to be achieved. By designing transistor sizes equally between one in a bias circuit and another in a voltage to current converter, the effect of process variation can be minimized. A prototype chip in a 0.18-mu m CMOS demonstrated that the ROSC generates a stable clock frequency of 32.6 MHz within 1-mu s start-up time. Measured line regulation and temperature coefficient were +/-0.69% and +/-0.38%, respectively.
IEEE, 2016, 2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 1 - 4, English[Refereed]
International conference proceedings
- A 1.66-nW/kHz, 32.7-kHz, 99.5ppm/degrees C Fully Integrated Current-Mode RC Oscillator for Real-Time Clock Applications with PVT Stability
A compact and low-power current-mode RC oscillator (RCO) with process, voltage, and temperature (PVT) stability has been developed. The circuit employs a current-mode RCO architecture without using a conventional comparator based voltage-mode architecture. The current-mode architecture enables a compact RCO and faster switching speed to be achieved. By designing transistor sizes equally between one in a bias circuit and another in a voltage to current converter, the effect of process variation can be minimized. A prototype chip in a 0.18-mu m CMOS process demonstrated that the RCO generates a stable clock frequency of 32.7 kHz with a small area of 0.19 mm 2 and low-power dissipation of 54.2 nW at 0.85-V power supply, which achieves a figure of merit (FoM) of 1.66 nW/kHz. The measured temperature coefficient and line regulation were 99.5ppm/degrees C and 8.9ppm/mV, respectively.
IEEE, 2016, ESSCIRC CONFERENCE 2016, 149 - 152, English[Refereed]
International conference proceedings
- Highly-Efficient Power Transmitter Coil Design for Small Wireless Sensor Nodes
We present a power transmitter coil design for millimeter-size small wireless sensor nodes to improve coupling coefficient. We also develop a wireless power transfer (WPT) system using resonant coupling to achieve higher power transfer efficiency. Simulation results demonstrated that the power transfer efficiency was 60% at z-gap = 10 mm. Compared with conventional system, coupling coefficient was improved about 2.5 times higher and the power transfer efficiency was improved by 3% when z-gap = 10 mm.
IEEE, 2016, 2016 INTERNATIONAL SYMPOSIUM ON ANTENNAS AND PROPAGATION (ISAP), 512 - 513, English[Refereed]
International conference proceedings
- Analytical Study of Rectifier Circuit for Wireless Power Transfer Systems
In this paper, we develop an analytical model of a rectifier circuit that is used in wireless power transfer (WPT) systems, considering the switching timing, ON/OFF resistance, and load characteristics of the rectifier. The model enables us to estimate the performance of the rectifier and optimum load resistance that maximizes the output power and the power efficiency. The model can be extended into Y parameter, which is useful when we consider to develop multi-stage rectifier circuit. By comparing the derived model with the circuit simulation, we confirmed that the performance of the rectifier can be estimated with high accuracy.
IEEE, 2016, 2016 INTERNATIONAL SYMPOSIUM ON ANTENNAS AND PROPAGATION (ISAP), 338 - 339, English[Refereed]
International conference proceedings
- A 0.38-mu W Stand-by Power, 50-nA-to-1-mA Load Current Range DC-DC Converter with Self-Biased Linear Regulator for Ultra-Low Power Battery Management
This paper proposes a DC-DC converter for ultra low power battery management. The proposed circuit consists of a switched capacitor converter (SCC) and self-biased linear regulator (SBLR). The SBLR monitors an output load current and controls the switching frequency of the SCC to achieve both ultra-low stand-by power and wide load current capability. Measurement results demonstrated that the converter successfully converts a 4.2-V input into a 0.98-V output. The stand-by power was extremely low, 0.38 mu W. The load current range where the power conversion efficiency was higher than 50% was from 2 mu A to 1 mA. The efficiency was 54% when the input voltage and output power were 4.0 V and 0.97 mW, respectively.
IEEE, 2016, 2016 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 225 - 228, English[Refereed]
International conference proceedings
This paper proposes a fully integrated 32-MHz relaxation oscillator (ROSC) capable of fast start-up time operation for low-power intermittent VLSI systems. The proposed ROSC employs current mode architecture that is different from conventional voltage mode architecture. This enables compact and fast switching speed to be achieved. By designing transistor sizes equally between one in a bias circuit and another in a voltage to current converter, the effect of process variation can be minimized. A prototype chip in a 0.18-mu m CMOS demonstrated that the ROSC generates a stable clock frequency of 32.6 MHz within 1-mu s start-up time. Measured line regulation and temperature coefficient were +/-0.69% and +/-0.38%, respectively.
IEEE, 2016, 2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 101-C (3), 161 - 169, English[Refereed]
International conference proceedings
In this paper, we propose a low-power circuit-shared static flip-flop ((CSFF)-F-2) for extremely low power digital VLSIs. The (CSFF)-F-2 consists of five static NORs and two inverters (INVs). The (CSFF)-F-2 utilizes a positive edge of a buffered clock signal, which is generated from a root clock, to take data into a master latch and a negative edge of the root clock to hold the data in a slave latch. The total number of transistors is only 24, which is the same as the conventional transmission-gate flip flop (TGFF) used in the most standard cell libraries. SPICE simulations in 0.18-mu m standard CMOS process demonstrated that our proposed (CSFF)-F-2 achieved clock-to-Q delay of 18.3 ns, setup time of 10.0 ns, hold time of 5.5 ns, and power dissipation of 9.7nW at 1-MHz clock frequency and 0.5-V power supply. The physical design area increased by 16% and power dissipation was reduced by 13% compared with those of conventional TGFF. Measurement results demonstrated that our proposed (CSFF)-F-2 can operate at 0.352V with extremely low energy of 5.93 fJ.
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Dec. 2015, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E98A (12), 2600 - 2606, English[Refereed]
Scientific journal
Copyright © 2015 The Institute of Electronics, Information and Communication Engineers. In this paper, we propose a low-power circuit-shared static flip-flop (CS2FF) for extremely low power digital VLSIs. The CS2FF consists of five static NORs and two inverters (INVs). The CS2FF utilizes a positive edge of a buffered clock signal, which is generated from a root clock, to take data into a master latch and a negative edge of the root clock to hold the data in a slave latch. The total number of transistors is only 24, which is the same as the conventional transmission-gate flip flop (TGFF) used in the most standard cell libraries. SPICE simulations in 0.18-μm standard CMOS process demonstrated that our proposed CS2FF achieved clock-to-Q delay of 18.3 ns, setup time of 10.0 ns, hold time of 5.5 ns, and power dissipation of 9.7nW at 1-MHz clock frequency and 0.5-V power supply. The physical design area increased by 16% and power dissipation was reduced by 13% compared with those of conventional TGFF. Measurement results demonstrated that our proposed CS2FF can operate at 0.352V with extremely low energy of 5.93 fJ.
The institute of electronics, information and communication engineers (IEEE), Dec. 2015, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E98A (12), 2600 - 2606, English[Refereed]
Scientific journal
- The japan society of applied physics, Sep. 2015, Extended abstract of the 2015 international conference on solid state devices and materials, 154 - 155, EnglishA wireless power transfer system for small-sized sensor applications
[Refereed]
International conference proceedings
- The japan society of applied physics, Sep. 2015, Extended abstract of the 2015 international conference on solid state devices and materials, 158 - 159, EnglishA fully on-chip 3-terminal switched-capacitor DC-DC converter with startup/fail-safe circuit
[Refereed]
International conference proceedings
- 電子情報通信学会, Aug. 2015, 第28回 回路とシステムワークショップ, 94 - 99, Japanese適応バイアス技術を用いた超低電力・高速オペアンプの高性能化
[Refereed]
Symposium
- 電子情報通信学会, Aug. 2015, 第28回 回路とシステムワークショップ, 258 - 263, Japanese小型センサデバイスに向けた無線給電システムの設計
[Refereed]
Symposium
- 電子情報通信学会, Aug. 2015, 第28回 回路とシステムワークショップ, 264 - 269, Japanese高耐圧CMOSプロセスによる超低電力・適応バイアス型シリーズレギュレータ
[Refereed]
Symposium
- 電子情報通信学会, Aug. 2015, 第28回 回路とシステムワークショップ, 70 - 75, Japanese高速起動を特徴とするフルオンチップ32 MHz弛張発振回路
[Refereed]
Symposium
- 電子情報通信学会, Aug. 2015, 第28回 回路とシステムワークショップ, 270 - 275, Japaneseスイッチトキャパシタ回路を用いたオンチップ電源回路の高効率化
[Refereed]
Symposium
- 電子情報通信学会, Aug. 2015, 第28回 回路とシステムワークショップ, 88 - 93, Japaneseサブスレッショルド領域動作に適したスタンダードセルのサイジング手法
[Refereed]
Symposium
© 2015 IEEE. In this paper, we propose a low-power level shifter (LS) capable of converting extremely low-input voltage into highoutput voltage. The proposed LS consists of a pre-amplifier with a logic error correction circuit and an output latch stage. The pre-amplifier generates complementary amplified signals, and the latch stage converts them into full-swing output signals. Simulated results demonstrated that the proposed LS in a 0.18-μm CMOS process can convert a 0.19-V input into 1.8-V output correctly. The energy and the delay time of the proposed LS were 0.24 pJ and 21.4 ns when the low supply voltage, high supply voltage, and the input pulse frequency, were 0.4, 1.8 V, and 100 kHz, respectively.
27 Jul. 2015, Proceedings - IEEE International Symposium on Circuits and Systems, 2015-July, 2948 - 2951[Refereed]
International conference proceedings
This paper proposes an ultra-low power fully on-chip CMOS relaxation oscillator (ROSC) for a real-time clock application. The proposed ROSC employs a compensation circuit of a comparator's non-idealities caused by offset voltage and delay time. The ROSC can generate a stable, and 32-kHz oscillation clock frequency without increasing power dissipation by using a low reference voltage and employing a novel compensation architecture for comparators. Measurement results in a 0.18-mu m CMOS process demonstrated that the circuit can generate a stable clock frequency of 32.55 kHz with low power dissipation of 472nW at 1.8-V power supply. Measured line regulation and temperature coefficient were 1.1%/V and 120 ppm/degrees C, respectively.
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, May 2015, IEICE TRANSACTIONS ON ELECTRONICS, E98C (5), 446 - 453, English[Refereed]
Scientific journal
Copyright © 2015 The Institute of Electronics, Information and Communication Engineers. This paper proposes an ultra-low power fully on-chip CMOS relaxation oscillator (ROSC) for a real-time clock application. The proposed ROSC employs a compensation circuit of a comparator's non-idealities caused by offset voltage and delay time. The ROSC can generate a stable, and 32-kHz oscillation clock frequency without increasing power dissipation by using a low reference voltage and employing a novel compensation architecture for comparators. Measurement results in a 0.18-μm CMOS process demonstrated that the circuit can generate a stable clock frequency of 32.55 kHz with low power dissipation of 472 nW at 1.8-V power supply. Measured line regulation and temperature coefficient were 1.1%/V and 120 ppm/°C, respectively.
The institute of electronics, information and communication engineers (IEEE), 01 May 2015, IEICE Transactions on Electronics, E98C (5), 446 - 453, English[Refereed]
Scientific journal
© 2015 The Japan Society of Applied Physics. In this paper, we present a rail-to-rail folded-cascode amplifier (AMP) with adaptive biasing circuits (ABCs). The circuit uses a nano ampere current reference circuit to achieve ultralow-power and ABCs to achieve high-speed operation. The ABCs are based on conventional circuits and modified to be suitable for rail-to-rail operation. The measurement results demonstrated that the AMP with the proposed ABCs can operate with an ultralowpower of 384 nA when the input voltage was 0.9V and achieve high speeds of 0.162V/μs at the rise time and 0.233V/μs at the fall time when the input pulse frequency and the amplitude were 10 kHz and 1.5 Vpp, respectively.
The Japan Society of Applied Physics (JSAP), Apr. 2015, Japanese Journal of Applied Physics, 54 (4), 1 - 7, English[Refereed]
International conference proceedings
© 2015 IEEE. We propose a fully integrated 3-terminal voltage converter with a maximum power point tracking (MPPT) circuit for ultra-low voltage energy harvesting. The MPPT circuit dissipates nano-watt power to extract maximum output power. The measurement results demonstrated that the circuit converted a 0.49-V input to a 1.46-V output with 73.6% power conversion efficiency when the output power was 348 μW. The circuit can operate at an extremely low input voltage of 0.21 V.
The Institute of Electrical and Electronics Engineers (IEEE), 11 Mar. 2015, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, 30 - 31, English[Refereed]
International conference proceedings
- Research Institute of Signal Processing Japan (RISP), Mar. 2015, Proceedings of 2015 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2015), 218 - 221, EnglishObject Detection with Deformable Part Models and Deep Convolutional Neural Networks
[Refereed]
International conference proceedings
- Research Institute of Signal Processing Japan (RISP), Mar. 2015, Proceedings of 2015 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2015), 421 - 424, EnglishBayer Demosaicing with Example-Based Super-Resolution
[Refereed]
International conference proceedings
- Research Institute of Signal Processing Japan (RISP), Mar. 2015, Proceedings of 2015 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2015), 353 - 356, EnglishArchitecture of a JPEG Noise Reduction Method with Total Variation
[Refereed]
International conference proceedings
- Mar. 2015, Proceedings of the 19th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2015), 319 - 324, EnglishAn ECO-friendly design style based on reconfigurable cells
[Refereed]
International conference proceedings
© IEICE 2015. In this paper, we present an ultra-low voltage Advanced Encryption Standard (AES) SubBytes transformation (S-BOX) circuit. The S-BOX is widely used as a basic cryptographic primitive for the secure transaction in wireless sensor networks. We employ an asynchronous circuit design technique for low-voltage operations to achieve ultra-low power dissipation. In the proposed approach, we apply a quasi-delay-insensitive (QDI) design methodology to the asynchronous S-BOX circuit to reduce the spurious transitions in combinational logics and to increase robustness against PVT variations. Measurement results in 0.18-µm CMOS process demonstrated that our asynchronous S-BOX circuit consumes only 0.99-pJ at 330-mV, which is 12% less energy than that of synchronous one. QDI asynchronous circuits in the datapath are an effective solution in the near-threshold and sub-threshold regimes.
The Institute of Electronics, Information and Communication Engineers (IEICE), 30 Jan. 2015, IEICE Electronics Express, 12 (4), 1 - 10, English[Refereed]
Scientific journal
- A 0.19-V Minimum Input Low Energy Level Shifter for Extremely Low-Voltage VLSIs
In this paper, we propose a low-power level shifter (LS) capable of converting extremely low-input voltage into high-output voltage. The proposed LS consists of a pre-amplifier with a logic error correction circuit and an output latch stage. The pre-amplifier generates complementary amplified signals, and the latch stage converts them into full-swing output signals. Simulated results demonstrated that the proposed LS in a 0.18-mu m CMOS process can convert a 0.19-V input into 1.8-V output correctly. The energy and the delay time of the proposed LS were 0.24 pJ and 21.4 ns when the low supply voltage, high supply voltage, and the input pulse frequency, were 0.4, 1.8 V, and 100 kHz, respectively.
IEEE, 2015, 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2948 - 2951, English[Refereed]
International conference proceedings
- A Fully-Integrated, High-Conversion-Ratio and Dual-Output Voltage Boost Converter with MPPT for Low-Voltage Energy Harvesting
This paper proposes a fully-integrated high-conversion-ratio dual-output voltage boost converter (VBC) with maximum power point tracking (MPPT) circuits for low-voltage energy harvesting. The VBC consists of two voltage generators that generate V-OUT1 and V-OUT2. V-OUT1 and V-OUT2 are three and nine times higher than the harvester's output V-IN, respectively. V-OUT1 is used as a supply voltage for on-chip application circuits while V-OUT2 is used as the charging voltage for a Li-ion battery. The VBC achieves a high voltage conversion ratio (max. x 9) and a high power conversion efficiency with a small number of charge pumps (CPs). The MPPT circuits control the operating frequencies of the CPs to extract maximum power at each output. The measurement results demonstrated that the circuit converted a 0.59-V input to a 1.41-V output with 75.8% efficiency when the output powers of V-OUT1 and V-OUT2 were 396 and 0 mu W, respectively, and a 0.62-V input to a 4.54-V output with 49.1% efficiency when the output powers were 0 and 114 mu W, respectively.
IEEE, 2015, 2015 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 297 - 300, English[Refereed]
International conference proceedings
- 情報処理学会, Sep. 2014, 情報処理学会 第13回情報科学技術フォーラム（FIT2014）, 173 - 174, Japanese学習型超解像による4倍拡大映像出力ハードウェアの実現と辞書探索回路の規模削減
Symposium
- The Japan Society of Applied Physics (JSAP), Sep. 2014, Extended abstract of the 2014 International Conference on Solid State Devices and Materials (SSDM 2014), 964 - 965, EnglishA Nano-Watt Power Rail-to-Rail CMOS Amplifier with Adaptive Biasing for Ultra-Low Power Analog LSIs
[Refereed]
Research society
- 電子情報通信学会, Aug. 2014, 第27 回 回路とシステムワークショップ, 25 - 30, Japanese電力変換効率の負荷電流依存性を考慮したオンチップチャージポンプの高効率化
[Refereed]
Symposium
- 電子情報通信学会, Aug. 2014, 電子情報通信学会 集積回路研究会, 99 - 104, Japanese時間計測アプリケーシ ョンに向けた超低電力弛張発振回路
Symposium
- 電子情報通信学会, Aug. 2014, 第27 回 回路とシステムワークショップ, 31 - 35, Japanese高耐圧CMOSトランジスタによる低電力バンドギャップリファレンス回路
[Refereed]
Symposium
- 電子情報通信学会, Aug. 2014, 第27 回 回路とシステムワークショップ, 300 - 305, JapanesePWM制御方式を用いた時間分解能型ADコンバータの低電力化
[Refereed]
Symposium
A fully on-chip CMOS relaxation oscillator (ROSC) with a PVT variation compensation circuit is proposed in this paper. The circuit is based on a conventional ROSC and has a distinctive feature in the compensation circuit that compensates for comparator's non-idealities caused by not only offset voltage, but also delay time. Measurement results demonstrated that the circuit can generate a stable clock frequency of 6.66 kHz. The current dissipation was 320 nA at 1.0-V power supply. The measured line regulation and temperature coefficient were 0.98%/V and 56 ppm/ °C, respectively. Copyright © 2014 The Institute of Electronics, Information and Communication Engineers.
The Institute of Electronics, Information and Communication Engineers (IEICE), Jun. 2014, IEICE Transactions on Electronics, E97-C (6), 512 - 518, English[Refereed]
Scientific journal
A fully on-chip CMOS relaxation oscillator (ROSC) with a PVT variation compensation circuit is proposed in this paper. The circuit is based on a conventional ROSC and has a distinctive feature in the compensation circuit that compensates for comparator's non-idealities caused by not only offset voltage, but also delay time. Measurement results demonstrated that the circuit can generate a stable clock frequency of 6.66 kHz. The current dissipation was 320 nA at 1.0-V power supply. The measured line regulation and temperature coefficient were 0.98%/V and 56 ppm/degrees C, respectively.
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jun. 2014, IEICE TRANSACTIONS ON ELECTRONICS, E97C (6), 512 - 518, English[Refereed]
Scientific journal
- RISP, Mar. 2014, 2014 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2014), 41 - 44, EnglishScene Segmentation for TV Programs Based on a Bag-of-VisualWords Model
[Refereed]
International conference proceedings
- RISP, Mar. 2014, 2014 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2014), 501 - 504, EnglishEstimation of Visual Importance Map for Image Quality Assessment
[Refereed]
International conference proceedings
- RISP, Mar. 2014, 2014 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2014), 361 - 364, EnglishA Scene Matching Method for TV Programs Based on Audio Features
[Refereed]
International conference proceedings
- RISP, Mar. 2014, 2014 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2014), 301 - 304, EnglishArchitecture of Digital Zooming Function with Example-Based Hierarchical Super-Resolution
[Refereed]
International conference proceedings
- A 24-Transistor Static Flip-Flop Consisting of NORs and Inverters for Low-Power Digital VLSIs
In this paper, we propose a low-power circuit-shared static flip-flop (CS2 FF) for extremely low power digital VLSIs. The CS2 FF consists of five static NORs and two inverters (INVs). The CS2 FF utilizes a positive edge of a buffered clock signal, which is generated from a root clock, to take data into a master latch and a negative edge of the root clock to hold the data in a slave latch. The total number of transistors is only 24, which is the same as the conventional tri-state buffer based flip flop (TBFF) used in the most standard cell libraries. SPICE simulations in 0.18-mu m standard CMOS process demonstrated that our proposed (CSFF)-F-2 achieved clock-to-Q delay of 17.4 ns, setup time of 5.91 ns, hold time of 1.17 ns, and power dissipation of 15.4 nW at 1-MHz clock frequency and 0.5-V power supply. The physical design area increased by 21% and power dissipation was reduced by 26% compared with those of conventional TBFF. Our proposed CS2 FF can operate at 0.347 V with extremely low power of 6.61 nW, 33% less than that of TBFF.
IEEE, 2014, 2014 IEEE 12TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 137 - 140, English[Refereed]
International conference proceedings
- A 0.21-V Minimum Input, 73.6% Maximum Efficiency, Fully Integrated Voltage Boost Converter with MPPT for Low-Voltage Energy Harvesters
This paper proposes a fully integrated voltage boost converter with a maximum power point tracking (MPPT) circuit for ultra-low power energy harvesting. The converter is based on a conventional charge pump circuit and can deliver a wide range of load current by using nMOS and pMOS driver circuits for highly efficient switching operation. The MPPT circuit we propose dissipates nano-watt power to extract maximum power regardless of the harvester's power generation conditions and load current. The measurement results demonstrated that the circuit converted a 0.49-V input to a 1.46-V output with 73.6% power conversion efficiency when the output power was 348 mu W. The circuit can operate at an extremely low input of 0.21 V.
IEEE, 2014, PROCEEDINGS OF THE 40TH EUROPEAN SOLID-STATE CIRCUIT CONFERENCE (ESSCIRC 2014), 255 - 258, English[Refereed]
International conference proceedings
- Oct. 2013, 18th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2013), 253 - 258, EnglishTechnology remapping based on multiple solutions for post-mask functional ECO
[Refereed]
International conference proceedings
- Oct. 2013, 18th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2013), 170 - 175, EnglishA technique for accelerating adaptive super resolution technique based on local features of images using GPU
[Refereed]
International conference proceedings
- Oct. 2013, 18th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2013), 28 - 33, EnglishAn error diagnosis technique using QBF solver to fix LUT functions
[Refereed]
International conference proceedings
- Oct. 2013, 18th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2013), 360 - 365, EnglishA memory-saving technique for 4K super-resolution circuit with binary tree dictionary
[Refereed]
International conference proceedings
- Oct. 2013, 18th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2013), 118 - 122, EnglishA compact and energy-efficient Muller C-element for low-voltage asynchronous CMOS digital circuits
[Refereed]
International conference proceedings
- RISP, Mar. 2013, Proceedings of 2013 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2013), 373 - 376, EnglishHighlight Generation Technique for Baseball Games Based on Information Entropies
[Refereed]
International conference proceedings
- 電子情報通信学会, Feb. 2013, 電子情報通信学会論文誌, J96-D (2), 357 - 361, Japanese学習型超解像のための二分木辞書
[Refereed]
Scientific journal
This paper presents bandgap reference (BGR) and sub-BGR circuits for nanowatt LSIs. The circuits consist of a nano-ampere current reference circuit, a bipolar transistor, and proportional-to-absolute-temperature (PTAT) voltage generators. The proposed circuits avoid the use of resistors and contain only MOSFETs and one bipolar transistor. Because the sub-BGR circuit divides the output voltage of the bipolar transistor without resistors, it can operate at a sub-1-V supply. The experimental results obtained in the 0.18-μm CMOS process demonstrated that the BGR circuit could generate a reference voltage of 1.09 V and the sub-BGR circuit could generate one of 0.548 V. The power dissipations of the BGR and sub-BGR circuits corresponded to 100 and 52.5 nW. © 1966-2012 IEEE.
IEEE, 2013, IEEE Journal of Solid-State Circuits, 48 (6), 1530 - 1538, English[Refereed]
Scientific journal
This paper proposes an ultra-low power fully on-chip CMOS relaxation oscillator (ROSC) for a real-time clock application. The circuit has a distinctive feature in compensation architecture of a comparator's non-idealities caused by offset voltage and delay time. The ROSC can generate a stable and higher oscillation clock frequency without increasing power by using a low reference voltage and employing a novel compensation architecture for comparators. Measurement results in a 0.18-μm CMOS process demonstrated that the circuit can generate a stable clock frequency of 32.55 kHz. The power dissipation was 472 nW. Measured line regulation and temperature coefficient were 1.1%/V and 120ppm/°C, respectively. © 2013 IEEE.
2013, European Solid-State Circuits Conference, 315 - 318, English[Refereed]
International conference proceedings
- JSAP, Sep. 2012, Extended abstract of the 2012 International Conference on Solid State Devices and Materials, 154 - 155, EnglishA dynamic comparator using dynamic currents of CMOS logic gates for low-power and high-efficient offset calibration
[Refereed]
International conference proceedings
This paper presents a level shifter circuit capable of handling extremely low-voltage inputs. The circuit has a distinctive current generation scheme using a logic error correction circuit that works by detecting the input and output logic levels. The proposed level shifter circuit can convert low-voltage digital input signals into high-voltage digital output signals. The circuit achieves low-power operation because it dissipates operating current only when the input signal changes. Measurement results demonstrated that the circuit can convert a 0.23-V input signal into a 3-V output signal. The power dissipation was 58 nW for a 0.4-V 10-kHz input pulse.
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, Jul. 2012, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 47 (7), 1776 - 1783, English[Refereed]
Scientific journal
- Mar. 2012, The 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012), pp. 192-196, EnglishSaving power consumption in final stage adder of multiplier by using difference in arrival times with input signals
[Refereed]
International conference proceedings
- Mar. 2012, The 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012), pp. 534-538, EnglishReduction of glitches for low-power multipliers using 4-2 compressors based on hybrid-CMOS logic style
[Refereed]
International conference proceedings
- Mar. 2012, The 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012), pp. 199-204, EnglishReconfigurable cells for post-mask ECO
[Refereed]
International conference proceedings
- Mar. 2012, The 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012), pp. 492-496, EnglishHardware architecture for real-time operation of learning-based super-resolution using binary search tree
[Refereed]
International conference proceedings
- Mar. 2012, The 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012), pp. 28-32, EnglishA technique for accelerating SVM-based image recognition using GPU
[Refereed]
International conference proceedings
- Mar. 2012, The 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012), pp. 544-548, EnglishAn error diagnosis technique based on SAT solver
[Refereed]
International conference proceedings
- Mar. 2012, The 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012), pp. 555-559, EnglishA delay control technique for low-voltage subthreshold CMOS digital circuits
[Refereed]
International conference proceedings
- Feb. 2012, 神戸大学大学院工学研究科紀要, 第3号, pp. 32-39, Japaneseカラー画像に対応した画質評価手法VSNRC
[Refereed]
Scientific journal
This paper presents an ultra-low power CMOS amplifier (AMP) using a simple and novel adaptive biasing current circuit (ABCC). The circuit uses a nano-ampere current source to achieve nano-watt power dissipation and the adaptive biasing technique to achieve high speed operation. The ABCC monitors the input voltages and supplies adaptive biasing current to the AMP. Because the adaptive biasing current is generated only when the AMP does not maintain its virtual short characteristic in the feedback configuration, the circuit operates with nano-watt power dissipation. Measurement results demonstrated that the circuit can operate with ultra-low power of 325 nA and high speed of 0.0506 V/μs at the rise time and 0.0579 V/μs at the fall time, when the input pulse frequency and the amplitude were 1 kHz and 0.8 Vpp. © 2012 IEEE.
IEEE, 2012, European Solid-State Circuits Conference, 69 - 72, English[Refereed]
International conference proceedings
- A Low-Power Single-Slope Analog-to-Digital Converter with Digital PVT Calibration
A low-power single-slope analog-to-digital converter (SS ADC) is presented that uses an ultra-low-power reference current to achieve nano-watt power dissipation and a digital calibration function to compensate for the effect of process, voltage and temperature (PVT) variations. It converts two analog reference voltages into digital reference codes before it converts the input voltage into an input digital code. The SS ADC is tolerant to PVT variations due to the processing of the input digital code and two reference codes in the digital domain. A prototype was fabricated in the 180 nm CMOS process. Measurements demonstrated that it achieved a signal-to-noise- and-distortion ratio of 40.8 dB and an effective number of bits of 6.49 at a sampling rate of 800 S/s. It dissipated 174 nW in analog power and 36.5 nW in digital power, corresponding to the figure of merit for the 293 pJ/conversion-step.
IEEE, 2012, 2012 19TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 613 - 616, English[Refereed]
International conference proceedings
- A 6.66-kHz, 940-nW, 56ppm/degrees C, Fully On-chip PVT Variation Tolerant CMOS Relaxation Oscillator
A fully on-chip CMOS relaxation oscillator (ROSC) with a PVT variation compensation circuit is proposed in this paper. The circuit is based on a conventional ROSC and has a distinctive feature in the compensation circuit that compensates for comparator's non-idealities caused by offset voltage and delay time. We also developed a bias circuit consisting of positive and negative temperature coefficient resistors to obtain the temperature compensated clock frequency. Measurement results demonstrated that the circuit can generate a stable clock frequency of 6.66 kHz. The power dissipation was 940 nW. The measured line regulation and temperature coefficient were 0.98%/V and 56ppm/degrees C, respectively.
IEEE, 2012, 2012 19TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 97 - 100, English[Refereed]
International conference proceedings
- Sep. 2011, 2011 International Conference on Solid State Devices and Materials (SSDM 2011), pp. 176-177, EnglishCurrent compensation circuit for precise nano-ampere current reference
[Refereed]
International conference proceedings
We propose a subthreshold Static Random Access Memory (SRAM) circuit architecture with improved write ability. Even though the circuits can achieve ultra-low power dissipation in subthreshold digital circuits, the performance is significantly degraded with threshold voltage variations due to the fabrication process and temperature. Because the write operation of SRAM is prone to failure due to the unbalance of threshold voltages between the nMOSFET and pMOSFET, stable operation cannot be ensured. To achieve robust write operation of SRAM, we developed a compensation technique by using an adaptive voltage scaling technique that uses an on-chip threshold voltage monitoring circuit. The monitoring circuit detects the threshold voltage of a MOSFET with the on-chip circuit configuration. By using the monitoring voltage as a supply voltage for SRAM cells, write operation can be compensated without degrading cell stability. Monte Carlo simulations demonstrated that the proposed SRAM architecture exhibits a smaller write operation failure rate and write time variation than a conventional 6T SRAM.
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jun. 2011, IEICE TRANSACTIONS ON ELECTRONICS, E94C (6), 1042 - 1048, English[Refereed]
Scientific journal
In this paper, we propose a level shifter circuit capable of handling a wide input voltage range. The circuit is based on a conventional two-stage comparator, and has a distinctive feature in that it operates a current amplification scheme for ultra low-power operation. The proposed circuit can convert low-voltage input digital signals into high-voltage output digital signals. The circuit achieves low power dissipation because it dissipates operating current only when the input signals change. Measurement results demonstrated that the circuit can convert low voltage input signals of 0.4V into 3V output signals. The power dissipation was 0.15 mu W at 0.4-V and 10-kHz input pulse.
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jun. 2011, IEICE ELECTRONICS EXPRESS, 8 (12), 890 - 896, English[Refereed]
Scientific journal
- Apr. 2011, 電子情報通信学会論文誌, vol. J94-D, no. 4, pp. 742-745, Japaneseクロス形状フラクタルを用いた画像の高解像度化
[Refereed]
Scientific journal
We have developed a low-power current reference circuit with little temperature dependence for micro-power LSIs in a 0.35-mu m standard complementary metal-oxide-semiconductor (CMOS) process. The proposed circuit consists of a bias-voltage subcircuit, a current-source subcircuit, and an offset-voltage generation (OVG) subcircuit. The OVG subcircuit consists of a subthreshold MOS resistor ladder. It is used to generate a small offset voltage that is independent of temperature and compensates for the temperature dependence of the reference current. Experimental results demonstrated that the proposed circuit generated a 95-nA reference current and that the total power dissipation was 598 nW. The temperature coefficient of the reference current can be kept within 523 ppm/degrees C at temperatures from -20 to 100 degrees C. (C) 2011 The Japan Society of Applied Physics
IOP PUBLISHING LTD, Apr. 2011, JAPANESE JOURNAL OF APPLIED PHYSICS, 50 (4), English[Refereed]
Scientific journal
A low-power current reference circuit was developed in a 0.35-μm standard CMOS process. The proposed circuit utilizes an offset-voltage generation subcircuit consisting of subthreshold MOS resistor ladder and generates temperature compensated reference current. Experimental results demonstrated that the proposed circuit generated a 95-nA reference current, and that the total power dissipation was 586 nW. The temperature coefficient of the reference current can be kept small within 523ppm/°C in a temperature range from -20 to 100°C. ©2011 IEEE.
2011, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 113 - 114[Refereed]
International conference proceedings
A delay-compensation circuit for low-power subthreshold digital circuits is proposed. Delay in digital circuits operating in the subthreshold region of MOSFETs changes exponentially with process and temperature variations. Threshold-voltage monitoring and supply-voltage scaling techniques are adopted to mitigate such variations. The variation in the delay can be significantly reduced by monitoring the threshold voltage of a MOSFET in each LSI chip and exploiting the voltage as the supply voltage for subthreshold digital circuits. The supply voltage generated by the threshold voltage monitoring circuit can be regarded as the minimum supply voltage to meet the delay constraint. Monte Carlo SPICE simulations demonstrated that a delay-time variation can be improved from having a log-normal to having a normal distribution. A prototype in a 0.35-mu m standard CMOS process showed that the exponential delay variation with temperature of the ring-oscillator frequency in the range from 0.321 to 212 kHz can remain by using compensation in the range from 5.26 to 19.2 kHz.
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jan. 2011, IEICE TRANSACTIONS ON ELECTRONICS, E94C (1), 80 - 88, English[Refereed]
Scientific journal
In this paper, we propose a level shifter circuit capable with a wide input voltage range. The circuit is based on a conventional two-stage comparator, and has a distinctive feature in current generation scheme by monitoring input and output logic levels. The proposed circuit can convert low voltage input digital signals into high voltage output digital signals. The circuit achieves low power operation because it dissipates operating current only when the input signals change. A SPICE demonstrated that the circuit can convert low voltage signals of 0.4 V into 3 V. The power dissipation was 6 nW at 0.4-V and 1-kHz input pulse. The circuit is useful for an ultra-low voltage digital circuit system co-existing with high voltage digital circuit systems. © 2011 IEEE.
2011, 2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011, pp. 201-204, 201 - 204, English[Refereed]
International conference proceedings
- High Current Efficiency Sense Amplifier Using Body-Bias Control for Ultra-Low-Voltage SRAM
We propose a current latch sense amplifier with a current-reuse technique (CLSA-w/CR). The CLSA-w/CR is capable of high-speed pre-charging with little increase in power dissipation. The CLSA-w/CR controls body bias voltages of pre-charge transistors in a conventional CLSA. Even though a forward body bias control over MOSFETs can achieve highspeed operation of the circuit, it induces large substrate leakage current and increases the power dissipation of the circuit. The CLSA-w/CR we propose, however, can achieve high-speed pre-charging without increasing power dissipation. We evaluated the performance of the CLSA-w/CR using SPICE with a set of 0.35/.L m standard CMOS parameters. The pre-charge time decreased by 86.9% and the power dissipation increased by only 8.6% compared to that of a conventional CLSA. The CLSA-w/CR showed high-speed pre-charging with small power overhead.
IEEE, 2011, 2011 IEEE 54TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), Wp2Track2_1-1, English[Refereed]
International conference proceedings
A level shifter circuit capable of extremely low-voltage inputs is presented in this paper. The circuit has a distinctive feature in current generation scheme with logic error correction circuit by detecting input and output logic levels. The proposed circuit can convert low-voltage input digital signals into high-voltage output digital signals. The circuit achieves low-power operation because it dissipates operating current only when the input signals change. Measurement results demonstrated that the circuit can convert low-voltage input signals of 0.4 V into 3 V output signals. The power dissipation was 58 nW at 0.4-V and 10-kHz input pulse. © 2011 IEEE.
2011, European Solid-State Circuits Conference, pp. 199-202, 199 - 202, English[Refereed]
International conference proceedings
- A 105-nW CMOS Thermal Sensor for Power-aware Applications
We propose an ultra-low power thermal sensor consisting of a nano-ampere CMOS current source circuit and a single bipolar transistor. Since the stability of current source circuits is the most important issue for our thermal sensor, we developed a circuit with an improved process and temperature stability. Our simulations and the measurements we conducted on the proposed thermal sensor demonstrated that it can be robustly operated in a wide temperature range. The power dissipation of the circuit was 105 nW for a 3-V power supply. The accuracy was within +/- 1 degrees C in a wide temperature range of -20 to 120 degrees C.
IEEE, 2011, 2011 IEEE SENSORS, pp. 1265-1268, 1265 - 1268, English[Refereed]
International conference proceedings
An ultra-low power comparator circuit using adaptive bias current generator (ABCG) is proposed. The circuit consists of an input differential pair, an ABCG, and a latch circuit. The ABCG generates an adaptive bias current, and the latch circuit determines the output logic and controls the operation of the ABCG for ultra-low power dissipation. The ABCG and the latch operate only when the input voltage levels and the logic of the latch do not correspond with each other. Measurements demonstrated that the circuit can achieve highspeed and low-power dissipation due to such operation. The standby current was 18.9 nA with a 10-nA bias current. The power dissipation was 88.5 nW at a 1-kHz input frequency and 3-V supply voltage. © 2011 IEEE.
2011, 2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011, pp. 237-240, 237 - 240, English[Refereed]
International conference proceedings
- Dec. 2010, 映像情報メディア学会誌, vol.64, no.12, pp.1940-1943, Japanese情報エントロピーに基づく野球中継番組のダイジェスト自動生成
[Refereed]
Scientific journal
In this paper, we propose an error diagnosis technique based on clustering LUT elements to shorten the processing time. By grouping some elements as a cluster, our technique reduces the number of elements to be considered, which is effective to shorten the processing time for screening error location sets. First, the proposed technique partitions the circuit into FFR (fanout-free region) called cluster, which is a subcircuit composed of LUT elements without fanout. After screening the set of clusters including error locations, this technique screens error location sets composed of elements in the remaining set of clusters, where corrections should be made. Experimental results with benchmark circuits have shown that our technique shortens the processing time to 1/170 in the best case, and rectifies circuits including 6 errors which cannot be rectified by the conventional technique. Copyright © 2010 The Institute of Electronics, Information and Communication Engineers.
Dec. 2010, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E93-A (12), 2490 - 2496, Japanese[Refereed]
Scientific journal
We propose the use of a super-resolution (SR) technique for thermographies. This system captures several thermal images for a reconstruction-based SR. However, it does not require the subpixel registration required by conventional SRs. In this system, a pair of a low-resolution thermal image and a high-resolution visible image is captured synchronously. While the thermal images are used as source data for SR, the visible images are used for pixel registrations. Because the resolution of the visible images from CCD sensors is over 4 times higher than that of the thermal images, a simple pixel registration on the former is equivalent to a precise subpixel registration on the latter. Thus, we can reconstruct a high quality thermogram without the need for a complex subpixel registration technique. Experimental results demonstrate that a pair of a thermographic camera with only 8 x 8 pixels and a visible CCD camera with 320 x 240 pixels generates a thermogram with 32 x 32 pixels. This fact means that a pair of a low cost thermographic camera and a standard CCD camera provides high-quality thermography. ©2010 IEEE.
2010, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, 1895 - 1898[Refereed]
International conference proceedings
In this paper, we propose a subthreshold Static Random Access Memory (SRAM) circuit architecture with improved write ability. In subthreshold digital circuits, though the circuits can achieve ultra-low power dissipation, the performance is significantly degraded with threshold voltage variations due to the fabrication process and temperature. In particular, because the write operation of SRAM is prone to fail due to the unbalance of threshold voltages between the nMOSFET and pMOSFET, stable operation cannot be ensured. To achieve robust write operation of SRAM, we developed a compensation technique by using an adaptive voltage scaling technique that uses an onchip threshold voltage monitoring circuit. The monitoring circuit detects the threshold voltage of a MOSFET with the on-chip circuit configuration. By using the monitoring voltage as a supply voltage for SRAM cells, write operation can be compensated. Monte Carlo simulations demonstrated that the proposed SRAM architecture exhibits a less write operation failure rate and smaller write time variation than a conventional 6T SRAM. © 2010 IEEE.
2010, Midwest Symposium on Circuits and Systems, 133 - 136[Refereed]
International conference proceedings
In this paper, we propose a low-power current reference circuit with little temperature dependence for micro-power electronics applications. The current reference circuit consists of a bias-voltage subcircuit, a current-source subcircuit, and an offset-voltage generation subcircuit. The offset-voltage generation subcircuit is used to compensate for temperature dependence of the reference current. A SPICE simulation demonstrated that the circuit generates a 93-nA current, and the total power dissipation is 811 nW. The temperature coefficient of the reference current can be kept small, i.e., within 288ppm/°C, in a temperature range of -20 to 100°C. © 2010 IEEE.
2010, Midwest Symposium on Circuits and Systems, 668 - 671[Refereed]
International conference proceedings
This paper proposes CMOS bandgap reference (BGR) and sub-BGR circuits without resistors for nanowatt power LSIs. The BGR circuit consists of a nano-ampere current reference, a bipolar transistor, and a proportional to absolute temperature (PTAT) voltage generator. The PTAT voltage generator consists of source-coupled differential pairs and generates a positive temperature dependent voltage. The PTAT voltage generator compensates for negative temperature dependence of a base-emitter voltage in a PNP bipolar transistor. The circuit generates a bandgap voltage of silicon. The sub-BGR circuit uses a voltage divider to generate low-voltage sub-bandgap reference. Experimental results demonstrated that the BGR and sub-BGR circuits can generate a 1.18-V and 553-mV reference voltages, respectively. The power dissipation of the BGR and sub-BGR circuits were 108-nW and 110-nW, respectively. ©2010 IEEE.
2010, 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, 77 - 80[Refereed]
International conference proceedings
We have developed a nano-ampere CMOS current reference circuit that is tolerant to threshold voltage variations. This paper describes the circuit and its temperature dependence control technique for ultra-low power LSIs. Because the generated current increases with temperature, we propose a temperature dependence control architecture for a reference current by using the different temperature characteristics of "electron" and "hole" mobilities. Experiment results demonstrated that the circuit can generate a temperature compensated reference current of 9.95 nA and that the temperature dependence of the output reference current can be controlled by using the different temperature dependences of electron and hole mobilities. The temperature dependence controllability was 8.57 pA/°C·bit and its total current dissipation was 68.1 nA. ©2010 IEEE.
2010, ESSCIRC 2010 - 36th European Solid State Circuits Conference, 114 - 117[Refereed]
International conference proceedings
This paper presents an error diagnosis technique for incremental synthesis, called EXLLS (Extended X-algorithm for LUT-based circuit model based on Location sets to rectify Subcircuits), which rectifies five or more functional errors in the whole circuit based on location sets to rectify subcircuits. Conventional error diagnosis technique, called EXLIT, tries to rectify five or more functional errors based on incremental rectification for subcircuits. However, the solution depends on the selection and the order of modifications on subcircuits, which increases the number of locations to be changed. To overcome this problem, we propose EXLLS based on location sets to rectify subcircuits, which obtains two or more solutions by separating i) extraction of location sets to be rectified, and ii) rectification for the whole circuit based on the location sets. Thereby EXL LS can rectify five or more errors with fewer locations to change. Experimental results have shown that EXLLS reduces increase in the number of locations to be rectified with conventional technique by 90.1%. Copyright © 2009 The Institute of Electronics, Information and Communication Engineers.
Dec. 2009, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E92-A (12), 3136 - 3142, English[Refereed]
Scientific journal
Subthreshold LSIs can achieve ultra-low power. However, threshold voltage variations with temperature and fabrication process have significant impact on the circuit performance. In subthreshold digital circuits, delay time changes exponentially with threshold-voltage variations. To solve this problem, we propose a delay-compensation technique for subthreshold digital circuits. On-chip threshold-voltage monitoring and supply-voltage scaling are adopted to mitigate threshold-voltage variations. As examples of subthreshold digital circuits, we have evaluated the delay time in a ring oscillator and an 8-bit ripple carry adder. With the proposed techinque, the delay time can be improved from log-normal to normal distribution.
The Institute of Image Information and Television Engineers, 2009, ITE Technical Report, 33, 165 - 170, JapaneseThis paper describes a switching-voltage detector and compensation circuits for an ultra-low-voltage CMOS inverter. The switching voltage of an inverter is an important design parameters for a digital circuit, and is determined by the difference in threshold voltages between MOSFETs. However, switching voltage varies significantly with fabrication process conditions and temperature. To address this problem, we have developed a threshold voltage difference detector circuit. We have also proposed a possible compensation technique for the inverter. Monte Carlo simulations demonstrated that the threshold voltage detector circuit can monitor the threshold voltage difference between pMOSFET and nMOSFET, and that the proposed inverter can achieve 80% reduction in switching-voltage variation compared to a conventional CMOS inverter. © 2009 IEEE.
2009, Midwest Symposium on Circuits and Systems, 483 - 486[Refereed]
International conference proceedings
In this paper, we propose delay-compensation techniques for subthreshold digital circuits. Delay in digital circuits that are operated in the subthreshold region of a MOSFET changes exponentially with variations in threshold voltage. To mitigate such variations, threshold-voltage monitoring and supply-voltage scaling techniques are adopted. By monitoring the threshold voltage of each LSI chip and exploiting the voltage to supply voltage to subthreshold digital circuits, variations in delay time can be suppressed significantly. Monte Carlo SPICE simulation demonstrates that delay-time distribution can be improved from log-normal to normal. The coefficient of variation for the proposed technique is 31%. © 2009 IEEE.
2009, Midwest Symposium on Circuits and Systems, 503 - 506[Refereed]
International conference proceedings
We developed a technique to detect duplicated scenes, such as commercial messages, TV program theme songs, and repeated scenes from MPEG streams. Conventional matching techniques require numerous calculations to estimate similarity between scenes. In our technique, similarity is estimated with compressed code sizes without decoding pictures. We divided scenes into shots by detecting cut points, which probably correspond to large segments of generated code in MPEG streams. Pictures in these shots are not decoded, but only shot lengths are used for scene matching. If a series of shot lengths for scene A is the same as that for scene B, we can infer that both scenes are identical. This technique, called shot length matching (SLM), requires no image processing and works very fast. We applied SLM to 80 min. MPEG streams stored on an hard disk drive to detect and delete duplicated scenes, and we obtained 99.5 % precision and a processing time of 0.157 s.
Nov. 2006, Kyokai Joho Imeji Zasshi/Journal of the Institute of Image Information and Television Engineers, 60 (11), 1823 - 1828, Japanese[Refereed]
Scientific journal
- Nov. 2006, 映像情報メディア学会誌, vol.60, no.11, pp.1823-1828, Japanese生成符号量に着目したMPEGストリーム中における重複シーンの検出
[Refereed]
Scientific journal
A triple density Error Diffusion for medical monochrome LCDs is proposed to improve their gray-scale precisions. In addition, a measurement technique of image qualities based on E-MSE (Eye model-based Mean Square Error) is proposed. Several conventional techniques for medical LCDs, such as Sub-Pixel Modulation and Error Diffusion, are evaluated based on E-MSE and the validity of the proposed technique is ensured objectively.
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jun. 2006, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E89A (6), 1866 - 1868, English[Refereed]
Scientific journal
We propose estimation technique of user preferences for TV programs based on channel operations. The user preferences are available for automatic recommendation of TV programs. For practical use, automatically learning the preferences of a user from a channel selection history is important. However, obtaining such information is difficult because most users change channels frequently and do not watch programs from beginning to end. For automatic learning under such situations, an appropriate hypothesis describing the relationship between viewing time and preference degree for a program is needed. We propose three hypotheses and compared their utility in our program recommendation system. Experimental results showed that the preference for a TV program is not proportional to the viewing time, but becomes either 1 (like) or 0 (dislike) about 30 minutes after channel selection.
Mar. 2006, Kyokai Joho Imeji Zasshi/Journal of the Institute of Image Information and Television Engineers, 60 (3), 454 - 457, Japanese[Refereed]
Scientific journal
- Mar. 2006, 映像情報メディア学会誌, Vol. 60,No. 3, pp.454-457, Japaneseテレビ視聴者の選局行動に基づく番組嗜好度の推定
[Refereed]
Scientific journal
- 2005, 電子情報通信学会論文誌, J88-A(2),142-151, Japanese社内環境における頭部追跡を目的とした赤外線マルチカメラシステムの開発
[Refereed]
- 2004, 11th International Display Workshops(IDW2004), 1643-1645, EnglishTriple density error diffusion for medical monochrome LCDs and evaluation of its performance
[Refereed]
Scientific journal
- 2004, 12th Workshop on synthesis and system Integration of Mixed Information Technologies(SASIMI2004), 345-350, EnglishExtraction of subcircuits for incremental synthesis based on error diagbosis
[Refereed]
Scientific journal
- 2004, 12th Workshop on synthesis and system Integration of Mixed Information Technologies(SASIMI2004), 339-344, EnglishError diagnosis techniquie based on boolean resubstitution
[Refereed]
Scientific journal
- Reduction of FFT circuit area for OFDM demodulator based on skipping-point representation
In order to reduce FFT circuit area in OFDM demodulator for terrestrial digital broadcasting system in Japan, we propose an approach to reduce bit width for operations without performance degradation of the demodulator. The most important point is employing 11-bit skipping-point representation for internal operation in FFT instead of 14-bit fixed-point representation. The assignment of bit-fields that minimizes BER (Bit Error Rate) has been chosen for the 11-bit skipping-point representation: 10 bit for significand, and I bit for radix-16 exponent. By reducing the bit width for internal operation from 14 to 11, we can reduce the circuit area by 17.6 % with the complex multipliers, and by 21.4 % with the RAM's used in FFT. In total, the area of the whole FFT circuit has been reduced by 18 %. This result shows the effectiveness of the proposed method.
IEEE, 2004, PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 430-431, 430 - 431, English[Refereed]
International conference proceedings
- Lossless coding of color quantized images based on pseudo distance
As pixels in quantized images such as GIF formatted images with 256 colors are usually represented by index numbers in a color Palette, it is impossible to get high efficient compression by using conventional predictive coding to such images. In this paper, a novel predictive coding approach is proposed for images with quantized colors. In this approach, the prediction error is not a index number difference between an original color and its predicted color, but a value called as "pseudo distance" which is related to the Euclidian distance between these two colors in the 3-D color space. As the pseudo distance is small when the predicted color is perceptually close to the original color, the distribution of the pseudo distance is peaklike resulting in low entropy. Preliminary computer simulation results show that the proposed approach outperforms the index based linear prediction.
IEEE, 2004, 2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, CONFERENCE PROCEEDINGS, 1,245-247, 245 - 247, English[Refereed]
International conference proceedings
- Improvement of image quality by optical image processing suitable for pixel shape of display
An optical image processing to improve image quality on flat panel displays is proposed. In this method, grid lines between adjacent pixels are hidden by scattering their luminescence areas. It can restrain jaggies and moires on images. The validity of the proposed technique is evaluated with eye model-based SNR objectively.
IEEE, 2004, 2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, CONFERENCE PROCEEDINGS, 1,305-308, 305 - 308, English[Refereed]
International conference proceedings
- An LUT-based error diagnosis technique improved in multiplicity of rectifiable errors
In an LSI design process, Engineering Change Orders (ECO's) are often given due to logic design errors, changes of specification, and timing issue. This paper presents an improved technique called EXLIT to rectify multiple logic design errors using LUT-based circuit model, which is needed to rectify errors with compound cells often used in standard-cell design. In contrast to the conventional technique: EXLTV applicable only to four errors at the maximum, EXLIT rectifies ten errors by employing iterative diagnosis procedure for subcircuits extracted based on the correctness of primary output functions. By handling the sulicircuits, EXLIT reduces both the number of LUT's and the number of errors to be considered at once. Experimental results demonstrate that most of circuits including eight to ten design errors can be rectified within shorter processing time.
IEEE, 2004, 2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, CONFERENCE PROCEEDINGS, 1,525-528, 525 - 528, English[Refereed]
International conference proceedings
- An approach for integration of demodulators for digital broadcasting
We propose a method to reduce the circuit size with demodulators for BS digital broadcasting and for terrestrial broadcasting by integrating them. Specifically, we propose an approach for integrating an FIR filter in a BS demodulator, and a carrier filter in a demodulator for terrestrial broadcasting. Experimental results have shown that the proposed approach reduces 17 % of the circuit size compared with the sum of each filter.
IEEE, 2004, PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 416-417, 416 - 417, English[Refereed]
International conference proceedings
- Adaptive arithmetic coding for image prediction errors
This paper presents adaptive arithmetic coding of prediction errors in lossless image compression. Generally, a probability distribution of the errors forms Laplacian distribution with zero mean, but the variance sigma of the distribution may take different value at each local area in the image. The proposed encoder estimates the variance sigma at every pixel to update the probability table. First, at a target pixel, the variance sigma that maximizes the posterior probabilities of neighboring errors is calculated. Next, the error at the target pixel is encoded by arithmetic coding based on probability distribution with the variance a. Since this method calculates the probabilities from fewer neighboring errors, they respond to the rapid changes of image characteristic in narrow area. In this paper, the proposed method is compared with Lempel-Ziv, Huffman, static/adaptive arithmetic coding and JPEG arithmetic coding, and then compression ratios are discussed. On an average, it generates 5% smaller size of compressed data than the adaptive arithmetic method by JPEG.
IEEE, 2004, 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 3, PROCEEDINGS, 111,961-964, 961 - 964, English[Refereed]
International conference proceedings
- 2003, 情報処理学会論文誌, 44(5),1216-1224, Japanese信号線誤りに対応したLUT 論理診断手法
[Refereed]
Scientific journal
Layered blind deconvolution using interband prediction is proposed as a solution to the image recovery problem. With conventional layered blind deconvolution, it was difficult to recover high-band components after subband segmentation. With the proposed algorithm, high-band components are generated from low-band components using interband prediction, and synthesized results are used as initial images for subsequent layers, thus improving the quality of recovered images. The efficiency of interband prediction is proved through comparison in recovery performance between the proposed and conventional method.
Scripta Technica Inc, Mar. 2000, Systems and Computers in Japan, 31 (3), 77 - 83, English[Refereed]
Scientific journal
- HAAR WAVELET TRANSFORM WITH INTERBAND PREDICTION AND ITS APPLICATION TO IMAGE-CODING
Although the discrete cosine transform (DCT) and wavelet transform have been used as effective techniques for reducing the redundancy of image waveforms, they have the problems of high complexity and causing block distortion. Tn this paper, a Haar wavelet transform with interband prediction is proposed that permits high-speed processing and which is suitable for coding as a subband decomposition technique since it generates little block distortion in the decoded images. The interband prediction method of this proposed transform method uses the derivative of the low-band waveform to predict the high-band waveform each time a band is split into two subbands. This results in a transform process that gives a prediction residual signal with lower entropy. During the inverse transform, the prediction coefficients obtained from the forward transform are used to predict the high-frequency waveforms and then, by adding the prediction residual, the original high frequency waveforms are reconstructed. Because the high-frequency waveforms are generated that smoothly interpolate the up-sampled, low-frequency waveforms, any block effects from this prediction technique are difficult to see in the decoded image. A detailed analysis of the proposed interband prediction process is performed by interpreting the proposed transform as a subband decomposition process that is based on the use of a symmetric short-kernel filter (SSKF) filter bank; then experiments are conducted that demonstrate its performance as a subband decomposition for coding of real image data and the possibility of progressive build-up of the decoded images. Results show that this transform method is effective for coding image data.
SCRIPTA TECHNICA PUBL, Apr. 1995, ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE, 78 (4), 103 - 114, EnglishScientific journal
- LOSSLESS IMAGE COMPRESSION BY 2-DIMENSIONAL LINEAR PREDICTION WITH VARIABLE-COEFFICIENTS
A lossless image compression method based on two-dimensional (2D) linear prediction with variable coefficients is proposed. This method employs a space varying autoregressive (AR) model. To achieve a higher compression ratio, the method introduces new ideas in three points: the level conversion, the fast recursive parameter estimation, and the switching method for coding table. The level conversion prevents an AR model from predicting gray-level which does not exist in an image. The fast recursive parameter estimation algorithm proposed here calculates varying coefficients of linear prediction at each pixel in shorter time than conventional one. For encoding, the mean square error between the predicted value and the true one is calculated in the local area. This value is used to switch the coding table at each pixel to adapt it to the local statistical characteristics of an image. By applying the proposed method to "Girl" and "Couple" of IEEE monochromatic standard images, the compression ratios of 100:46 and 100:44 have been achieved, respectively. These results are superior to the best results (100:61 and 100:57) obtained by the approach under JPEG recommendations.
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jul. 1992, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E75A (7), 882 - 889, English[Refereed]
Scientific journal
MISC
- 2021, IEICE Electronics Express (Web), 18 (6)A 35-mV supply ring oscillator consisting of stacked body bias inverters for extremely low-voltage LSIs
- [電子情報通信学会], 17 May 2018, 回路とシステムワークショップ論文集 Workshop on Circuits and Systems, 31, 74 - 79, JapaneseDesign of Hysteresis Comparator for Active Diode
- 電子情報通信学会, 30 Jan. 2017, 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 116 (446), 81 - 86, JapaneseA fully on-chip, ultra-low power RC oscillator with current mode architecture for real time clock applications
- 映像情報メディア学会, Aug. 2016, 映像情報メディア学会技術報告 = ITE technical report, 40 (24), 3 - 8, JapaneseA fast-start up and fully-integrated 32-MHz clock generator for intermittent VLSI systems
- 電子情報通信学会, 01 Aug. 2016, 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 116 (173), 3 - 8, JapaneseA fast-start up and fully-integrated 32-MHz clock generator for intermittent VLSI systems
- Forum on Information Technology, 24 Aug. 2015, 情報科学技術フォーラム講演論文集, 14 (3), 177 - 178, JapaneseH-022 Anomalous Behavior Detection in Videos based on Deformable Part Models
- Forum on Information Technology, 24 Aug. 2015, 情報科学技術フォーラム講演論文集, 14 (3), 245 - 246, JapaneseI-022 Three Dimensional NL-Means method for denoising of continuous shooting photography
- Forum on Information Technology, 24 Aug. 2015, 情報科学技術フォーラム講演論文集, 14 (3), 179 - 180, JapaneseH-023 Applying Supervised Pre-Training to Network in Network for Precise Image Recognition
- Forum on Information Technology, 24 Aug. 2015, 情報科学技術フォーラム講演論文集, 14 (3), 243 - 244, JapaneseI-021 Noise Reduction for Medical Tomographic Images based on Locally Weighted Averaging
- Forum on Information Technology, 24 Aug. 2015, 情報科学技術フォーラム講演論文集, 14 (1), 253 - 254, JapaneseC-010 A Hardware Architecture to Perform K-means Clustering for Learning-Based Super-Resolution Combining Self-Learning and Prior-Learning Dictionaries
- Function approximation of visual importance for image quality assessment
This paper studies the function approximation of visual importance map that can be used for general purposes in image quality assessment. Conventional techniques that estimate the visual importance by eye tracking have many problems such as a loss of time, an enormous effort of a preliminary experiment, and an expensive equipment. Therefore, by analyzing the correlation between SSIM in local areas and subjective evaluation of the image, we estimate the human's gazing area and create the visual importance map. Experimental results have shown the high correlation between subjective evaluation and weighted SSIM based on the visual importance map. The proposed technique can be used widely even if the ROI is unknown.
The Institute of Electronics, Information and Communication Engineers, 13 Dec. 2013, 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 113 (350), 11 - 14, Japanese - Forum on Information Technology, 20 Aug. 2013, 情報科学技術フォーラム講演論文集, 12 (3), 317 - 318, JapaneseI-033 Learning of Geometric Patterns in Example-Based Super-Resolution
- Forum on Information Technology, 20 Aug. 2013, 情報科学技術フォーラム講演論文集, 12 (3), 319 - 320, JapaneseI-034 Architecture of Electric Zooming with Super Resolution and Error Feedback
- Forum on Information Technology, 20 Aug. 2013, 情報科学技術フォーラム講演論文集, 12 (3), 123 - 124, JapaneseH-015 An Architecture of HOG Based Classifier and Its Application to Pedestrian Detection
- The Institute of Electronics, Information and Communication Engineers, 05 Mar. 2013, Proceedings of the IEICE General Conference, 2013 (2), 132 - 132, JapaneseC-12-61 ARELAXATION OSCILLATOR FOR REAL TIME CLOCK WITH LOW REFERENCE VOLTAGE
- The Institute of Electronics, Information and Communication Engineers, 05 Mar. 2013, Proceedings of the IEICE General Conference, 2013 (2), 119 - 119, JapaneseC-12-48 Ultra-Low Power and High Speed Rail-to-Rail Operational Amplifier with Adaptive Biasing Technique
- A Study of JPEG Codec with Super-Resolution
This paper proposes a new JPEG codec in which super-resolution technique.AC coefficients are predicted from DC coefficients by a
The Institute of Electronics, Information and Communication Engineers, 06 Dec. 2012, IEICE technical report. Image engineering, 112 (335), 27 - 30, Japanese - Relationship between subjective qualities and SSIM of color imager
This paper studies a SSIM based-quality assessment for color images. Though SSIM metrics is similar to human subjective evaluation for gray-scale images, it can not evaluate images including degradations in color difference signals because it evaluates only a luminance signal. We incorporate new evaluation terms for the color difference signals into the conventional formula. The weights for them are determined in our experiment subjectively. Experimental results showed that the correlation coefficient between SSIM and subjective evaluation was improved.
The Institute of Electronics, Information and Communication Engineers, 05 Oct. 2012, 電子情報通信学会技術研究報告. IMQ, イメージ・メディア・クオリティ : IEICE technical report, 112 (234), 7 - 10, Japanese - Forum on Information Technology, 04 Sep. 2012, 情報科学技術フォーラム講演論文集, 11 (3), 123 - 124, JapaneseH-004 Layout Recognition of Score Ticker on Broadcasted Baseball Games
- Forum on Information Technology, 04 Sep. 2012, 情報科学技術フォーラム講演論文集, 11 (3), 243 - 244, JapaneseI-005 Similar Scene Detection in Broadcasted Videos using Bag-of-Visual Words
- Forum on Information Technology, 04 Sep. 2012, 情報科学技術フォーラム講演論文集, 11 (3), 261 - 262, JapaneseI-011 Architecture of Electronic Zooming with Hierarchical Super Resolution
- Forum on Information Technology, 04 Sep. 2012, 情報科学技術フォーラム講演論文集, 11 (3), 181 - 182, JapaneseH-029 Layout Recognition of Objects and Labels Based on Combination Optimization Algorithm
- Forum on Information Technology, 04 Sep. 2012, 情報科学技術フォーラム講演論文集, 11 (1), 173 - 174, JapaneseB-004 A Technique for GPU-Based Acceleration of Learning-Based Super-Resolution Using Wavelet Transform
- Forum on Information Technology, 04 Sep. 2012, 情報科学技術フォーラム講演論文集, 11 (1), 175 - 176, JapaneseB-005 A Technique for GPU-Based Acceleration of Classifier with Weighted Majority Voting for Multimodal Input
- The Institute of Electronics, Information and Communication Engineers, 28 Aug. 2012, Proceedings of the Society Conference of IEICE, 2012 (2), 97 - 97, JapaneseC-12-24 A PVT Variation Tolerant Single Slope AD Converter
- The Institute of Electronics, Information and Communication Engineers, 28 Aug. 2012, Proceedings of the Society Conference of IEICE, 2012 (2), 96 - 96, JapaneseC-12-23 A High Resolution Offset Calibration Technique for Ultra-Low-Voltage Dynamic Comparator
- The Institute of Electronics, Information and Communication Engineers, 28 Aug. 2012, Proceedings of the Society Conference of IEICE, 2012 (2), 91 - 91, JapaneseC-12-18 A CMOS Operational Amplifier with Adaptive Biasing for Ultra Low-power LSIs
- The Institute of Electronics, Information and Communication Engineers, 28 Aug. 2012, Proceedings of the Society Conference of IEICE, 2012 (2), 90 - 90, JapaneseC-12-17 A Relaxation Oscillator with Variation Compensation Techniques for Comparator
- A Study of Quality Assessment for Color Images
This paper studies a VSNR based-quality assessment for color images. Though VSNR metrics is similar to human subjective evaluation for gray-scale images, it can not evaluate images including degradations in color difference signals because it evaluates only a luminance signal. We incorporate new evaluation terms for the color difference signals into the conventional formula. The weights for them are determined in our experiment subjectively. Experimental results showed that the proposed assessment has high correlation to the human subjective evaluation.
The Institute of Electronics, Information and Communication Engineers, 22 Mar. 2012, Technical report of IEICE. PRMU, 111 (499), 193 - 198, Japanese - The Institute of Electronics, Information and Communication Engineers, 06 Mar. 2012, Proceedings of the IEICE General Conference, 2012 (2), 125 - 125, JapaneseC-12-53 Switched-Capacitor DC-DC Converter with Adaptive Bias Current Generating Comparator
- The Institute of Electronics, Information and Communication Engineers, 06 Mar. 2012, Proceedings of the IEICE General Conference, 2012 (2), 121 - 121, JapaneseC-12-49 A Study on Offset Calibration Technique for Ultra-Low-Voltage Dynamic Comparator
- The Institute of Electronics, Information and Communication Engineers, 06 Mar. 2012, Proceedings of the IEICE General Conference, 2012 (2), 124 - 124, JapaneseC-12-52 A Low Voltage Nano-Ampere Current Reference Circuit
- The Institute of Electronics, Information and Communication Engineers, 06 Mar. 2012, Proceedings of the IEICE General Conference, 2012 (2), 126 - 126, JapaneseC-12-54 Boost Converter with Quasi-Continuous-Mode Digital Control
- The Institute of Electronics, Information and Communication Engineers, 06 Mar. 2012, Proceedings of the IEICE General Conference, 2012 (2), 114 - 114, JapaneseC-12-42 High Speed Technique of Ultra-Low Power Operational Amplifier
- The Institute of Electronics, Information and Communication Engineers, 06 Mar. 2012, Proceedings of the IEICE General Conference, 2012, 19 - 19, JapaneseA-1-19 Load Characteristics Improvement of Charge Pump Circuits for Light Energy Harvesting
- The Institute of Electronics, Information and Communication Engineers, 06 Mar. 2012, Proceedings of the IEICE General Conference, 2012, 20 - 20, JapaneseA-1-20 Improvement of Efficiency by Reduction in Reverse Current of Differential-Drive CMOS Rectifier
- The Institute of Electronics, Information and Communication Engineers, 06 Mar. 2012, Proceedings of the IEICE General Conference, 2012, 45 - 45, JapaneseA-1-45 Analysis of Reduction in Capacitive DAC for High Resolution SAR ADC
- Smart Dictionary for Learning-Based Super-Resolution
In this paper, a novel dictionary construction technique for example based super-resolution is proposed. Conventional technique needs enormous number of images to make a dictionary describing pairs of low frequency components and high frequency components. As a result, the dictionary size increases and the search speed decreases. On the other hand, our goal is to maximize the ratio between PSNR and dictionary size. We use only a image to make a very small dictionary with a binary tree structure. Experimental results have shown that the proposed dictionary of only 536 patches can improve PSNR about 1 dB.
The Institute of Electronics, Information and Communication Engineers, 11 Nov. 2011, IEICE technical report. Image engineering, 111 (284), 35 - 40, Japanese - Forum on Information Technology, 07 Sep. 2011, 情報科学技術フォーラム講演論文集, 10 (3), 337 - 338, JapaneseI-025 Search and generation technique for high-frequency patches in learning-based super-resolution
- Forum on Information Technology, 07 Sep. 2011, 情報科学技術フォーラム講演論文集, 10 (3), 123 - 124, JapaneseH-010 Classifier with Weighted Majority Voting for Multimodal Input
Books etc
Presentations
- 電子情報通信学会 ICD/CAS研究会 学生・若手研究会, Dec. 2019, Japaneseリアルタイムクロックに向けた超低消費電力32 kHz水晶発振回路
Oral presentation
- 電子情報通信学会 ICD/CAS研究会 学生・若手研究会, Dec. 2019, Japanese低電圧エネルギーハーベスティングシステムに向けた超低消費電力電圧モニタ回路
Oral presentation
- 電子情報通信学会 ICD/CAS研究会 学生・若手研究会, Dec. 2019, Japaneseワイヤレス給電システムの位置自由度を改善するパワーマネジメント回路に関する研究
Oral presentation
- 令和元年電気関係学会関西連合大会, Dec. 2019, Japanese畳み込みニューラルネットワークを用いたアスファルトのひび割れ検出と画像の自動スケール判断
Oral presentation
- 第18回情報科学技術フォーラム, Sep. 2019, JapaneseVGGとU-Netを組み合わせたニューラルネットワークによるグレースケール画像の自動着色
Oral presentation
- 第18回情報科学技術フォーラム, Sep. 2019, JapaneseCNNを用いた近赤外線画像のセグメンテーションとカラリゼーション
Oral presentation
- 第18回情報科学技術フォーラム, Sep. 2019, JapaneseSkip-ConnectionとSeparable畳み込みを用いたCNNによる画像の単眼深度推定
Oral presentation
- 第18回情報科学技術フォーラム, Sep. 2019, Japanese分岐構造のCNNによる高速な多クラス分類システムに関する研究
Oral presentation
- 第18回情報科学技術フォーラム, Sep. 2019, JapaneseCNNのハードウェア実装における全結合層のリソース削減手法に関する一検討
Oral presentation
- 第32回 回路とシステムワークショップ, Aug. 2019, Japanese極低電圧エネルギーハーベスティングに向けたスイッチトキャパシタ型昇圧コンバータ
Oral presentation
- LSIとシステムのワークショップ2019, May 2019, Japanese超低消費電力で動作するアクティブダイオードの設計
Poster presentation
- 第17回情報科学技術フォーラム, Sep. 2018, Japanese, 電子情報通信学会，情報処理学会, Domestic conference論理再合成における遅延時間抑制に有効なRECONスペアセルの概略配置手法
Oral presentation
- 第17回情報科学技術フォーラム, Sep. 2018, Japanese, 電子情報通信学会，情報処理学会, Domestic conference誤り追跡入力の追加生成に基づく論理診断処理の効率化
Oral presentation
- 第17回情報科学技術フォーラム, Sep. 2018, Japanese, 電子情報通信学会，情報処理学会, Domestic conferenceセグメンテーションを組み合わせたDCGANによる画像の自動生成
Oral presentation
- 第17回情報科学技術フォーラム, Sep. 2018, Japanese, 電子情報通信学会，情報処理学会, Domestic conferenceCNNハードウェアにおけるDRAMアクセス量削減手法
Oral presentation
- 第17回情報科学技術フォーラム, Sep. 2018, Japanese, 電子情報通信学会，情報処理学会, Domestic conference4CH出力CNNを用いた超解像処理のハードウェア化
Oral presentation
- LSIとシステムのワークショップ2018, May 2018, Japanese, 電子情報通信学会集積回路研究専門委員会, Domestic conference低電圧・微弱環境エネルギー利用に向けたパワーマネジメントシステム
Poster presentation
- 第31回 回路とシステムワークショップ, May 2018, Japanese, 電子情報通信学会, Domestic conference最大効率点追従制御を用いたスイッチトキャパシタ型降圧コンバータの高効率化
Oral presentation
- 第31回 回路とシステムワークショップ, May 2018, Japanese, 電子情報通信学会, Domestic conference過電流制御技術を用いた自己バイアス型シリーズレギュレータ
Oral presentation
- 第31回 回路とシステムワークショップ, May 2018, Japanese, 電子情報通信学会, Domestic conferenceアクティブダイオードに向けたヒステリシスコンパレータの設計
Oral presentation
- IEEE EDS Kansai Chapter, The 17th Kansai Colloquium Electron Devices Workshop, Jan. 2018, Japanese, The Institute of Electrical and Electronics Engineers, Domestic conferenceA self-biased low-dropout linear regulator for ultra-low power battery management
[Invited]
Invited oral presentation
- 電子情報通信学会 集積回路研究専門委員会 学生・若手研究会, Dec. 2017, Japanese, 電子情報通信学会集積回路研究専門委員会, Domestic conference時間計測アプリケーションに向けた抵抗レスで面積利用効率の高い超低電力フルオンチップ弛張発振回路
Oral presentation
- 平成29年度VDECデザイナーズフォーラム, Sep. 2017, Japanese, 東京大学大規模集積システム設計教育研究センター, Domestic conference超低消費電力32-kHzリアルタイムクロック生成回路
Oral presentation
- 第16回情報科学技術フォーラム, Sep. 2017, Japanese, 電子情報通信学会，情報処理学会, Domestic conference畳み込みニューラルネットワークを用いた赤外線画像のカラー化
Oral presentation
- 第16回情報科学技術フォーラム, Sep. 2017, Japanese, 電子情報通信学会，情報処理学会, Domestic conference畳み込みニューラルネットワークを用いた改ざんJPEG画像の検出
Oral presentation
- 第16回情報科学技術フォーラム, Sep. 2017, Japanese, 電子情報通信学会，情報処理学会, Domestic conference畳み込みニューラルネットワークと生成型学習法を用いたコンクリートのひび割れ抽出
Oral presentation
- LSIとシステムのワークショップ2017, May 2017, Japanese, 電子情報通信学会集積回路研究専門委員会, Domestic conference極低入力電圧エネルギーハーベスティングに向けた昇圧コンバータの設計
Poster presentation
- LSIとシステムのワークショップ2017, May 2017, Japanese, 電子情報通信学会集積回路研究専門委員会, Domestic conferenceリアルタイムクロックに向けた電流比較型超低電力フルオンチップRC発振器
Poster presentation
- 電子情報通信学会 集積回路研究専門委員会 集積回路研究会, Jan. 2017, Japanese, 電子情報通信学会集積回路研究専門委員会, みやじま杜の宿, Domestic conference時間計測アプリケーションに向けた超低電力フルオンチップ電流比較型RC発振器
Oral presentation
- 電子情報通信学会 集積回路研究専門委員会 集積回路研究会 学生・若手研究会, Dec. 2016, Japanese, 電子情報通信学会集積回路研究専門委員会, 東京工業大学, Domestic conference適応バイアス技術を用いた低電流・高速スイッチトキャパシタ型増幅回路
Poster presentation
- 電子情報通信学会 集積回路研究専門委員会 集積回路研究会 学生・若手研究会, Dec. 2016, Japanese, 電子情報通信学会集積回路研究専門委員会, 東京工業大学, Domestic conference超低電力・環境発電デバイスに向けた最大発電量予測システム
Poster presentation
- 第15回情報科学技術フォーラム（FIT2016）, Sep. 2016, Japanese, Domestic conference畳み込みニューラルネットワークを用いたモノクロ画像のカラリゼーション
Oral presentation
- 電子情報通信学会 リコンフィギャラブルシステム研究会, Sep. 2016, Japanese, Domestic conference近似を導入した簡略化アルゴリズムに基づくRNN回路のリソース削減と高効率化
Oral presentation
- 第15回情報科学技術フォーラム（FIT2016）, Sep. 2016, Japanese, Domestic conferenceぶれ画像復元のためのPSF推定に関する研究
Oral presentation
- 第15回情報科学技術フォーラム（FIT2016）, Sep. 2016, Japanese, Domestic conferenceハードウェア化に適した近似関数の導入によるRNN回路のリソース削減と低消費電力化
Oral presentation
- 第15回情報科学技術フォーラム（FIT2016）, Sep. 2016, Japanese, Domestic conferenceSIFT特徴点を用いたPoint Cloudの位置合わせ手法に関する研究
Oral presentation
- 電子情報通信学会 集積回路研究専門委員会 集積回路研究会, Aug. 2016, Japanese, 電子情報通信学会集積回路研究専門委員会, 中央電気倶楽部, Domestic conference高速起動を特徴とした間欠動作型VLSIシステム用32-MHzオンチップクロック源回路
Oral presentation
- 平成28年度VDECデザイナーズフォーラム, Aug. 2016, Japanese, 東京大学大規模集積システム設計教育研究センター, 東京大学大規模集積システム設計教育研究センター, Domestic conference1マイクロ秒以内の高速起動を特徴とする高精度32-MHz弛張発振器
Oral presentation
- LSIとシステムのワークショップ2016, May 2016, Japanese, 電子情報通信学会集積回路研究専門委員会, 東京大学, Domestic conference間欠動作型VLSIシステムに向けた高速起動可能な32-MHzフルオンチップ弛張発振器
Poster presentation
- 第14回情報科学技術フォーラム, Sep. 2015, Japanese, 情報処理学会, 愛媛, Domestic conference連写画像におけるノイズ除去のための三次元NL-Means法
Oral presentation
- 第14回情報科学技術フォーラム, Sep. 2015, Japanese, 情報処理学会, 愛媛, Domestic conference自己学習型超解像に適用するK-meansクラスタリング処理のハードウェアによる実現
Oral presentation
- 第14回情報科学技術フォーラム, Sep. 2015, Japanese, 情報処理学会, 愛媛, Domestic conference事前教師あり学習を適用したNetwork in Networkによる画像認識の高精度化
Oral presentation
- 第14回情報科学技術フォーラム, Sep. 2015, Japanese, 情報処理学会, 愛媛, Domestic conference局所的加重平均を用いた医用断層画像のノイズ除去手法
Oral presentation
- 第14回情報科学技術フォーラム, Sep. 2015, Japanese, 情報処理学会, 愛媛, Domestic conferenceDeformable Part Modelsによる映像中の異常行動検出
Oral presentation
- 平成27年度 VDECデザイナーズフォーラム, Aug. 2015, Japanese, 東京大学大規模集積システム設計教育研究センター, 石川, Domestic conference幅広い電圧レベル変換を実現する低消費電力レベルシフタ
Oral presentation
- 平成27年度 VDECデザイナーズフォーラム, Aug. 2015, Japanese, 東京大学大規模集積システム設計教育研究センター, 石川, Domestic conference低電圧入力で動作するマイクロ環境発電のための高効率3端子昇圧コンバータ
Oral presentation
- 第41回アナログRF研究会, Jul. 2015, Japanese, 電子情報通信学会, 屋久島, Domestic conference振動エネルギーを用いた環境発電のための超低電力・適応バイアス型シリーズレギュレータ
Poster presentation
- LSIとシステムのワークショップ2015, May 2015, Japanese, 電子情報通信学会, 北九州, Domestic conference低電圧エネルギー・ハーベスティングに向けた高効率3端子昇圧コンバータ
Poster presentation
- 電子情報通信学会 集積回路研究専門委員会 アナログRF研究会, Jul. 2014, Japanese, 電子情報通信学会, 屋久島町, Domestic conference逐次比較AD コンバータに向けたコンパレータのオフセット補正アーキテクチャ
Poster presentation
- 電子情報通信学会技術研究報告, Dec. 2013, Japanese, 電子情報通信学会, 浜松市, Domestic conference画質評価のための注視重要度の関数近似
Oral presentation
- 第12回情報科学技術フォーラム（FIT2013）, Sep. 2013, Japanese, 情報処理学会, 鳥取市, Domestic conference超解像と誤差帰還を用いた電子ズームの構成方法
Oral presentation
- 第12回情報科学技術フォーラム（FIT2013）, Sep. 2013, Japanese, 情報処理学会, 鳥取市, Domestic conference事例参照型超解像における幾何学模様の学習
Oral presentation
- 第12回情報科学技術フォーラム（FIT2013）, Sep. 2013, Japanese, 情報処理学会, 鳥取市, Domestic conferenceHOGを用いた識別器の構成方法と歩行者検出への応用
Oral presentation
- 第26回 回路とシステムワークショップ, Aug. 2013, Japanese, 電子情報通信学会, 淡路市, Domestic conference低電圧エネルギー・ハーベスティングに向けた0.27-V入力，効率75%，オンチップ・チャージポンプ回路
Oral presentation
- LSIとシステムのワークショップ2013, May 2013, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conference適応バイアス電流生成技術を用いた超低電力・高速Rail-to-Railオペアンプ
Poster presentation
- LSIとシステムのワークショップ2013, May 2013, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市, Domestic conferenceばらつき補正技術を用いたシングルスロープADコンバータ
Poster presentation
- 電子情報通信学会 総合大会, Mar. 2013, Japanese, 電子情報通信学会, 岐阜, Domestic conference適応バイアス技術を用いた超低電力・高速Rail-to-Railオペアンプ
Oral presentation
- 電子情報通信学会 総合大会, Mar. 2013, Japanese, 電子情報通信学会, 岐阜, Domestic conference低参照電圧を用いた実時間計測用弛張発振回路
Oral presentation
- 情報処理学会オーディオビジュアル複合情報処理研究会, Nov. 2012, Japanese, 情報処理学会, 福井市, Domestic conference超解像を用いたJPEGコーデックに関する一検討
Oral presentation
- 電子情報通信学会イメージ・メディア・クオリティ研究会, Oct. 2012, Japanese, 電子情報通信学会, 京都市, Domestic conferenceカラー画像の主観的品質とSSIMの関係について
Oral presentation
- 電子情報通信学会・情報処理学会 第11回情報科学技術フォーラム(FIT2012), Sep. 2012, Japanese, 電子情報通信学会・情報処理学会, 東京都, Domestic conference野球中継映像におけるスコアテロップのレイアウト認識
Oral presentation
- 電子情報通信学会 ソサイエティ大会, Sep. 2012, Japanese, 電子情報通信学会, 富山, Domestic conference適応バイアス技術を用いた超低電力CMOSオペアンプの評価
Oral presentation
- 電子情報通信学会 ソサイエティ大会, Sep. 2012, Japanese, 電子情報通信学会, 富山, Domestic conference超低電圧ダイナミックコンパレータのためのオフセット電圧補正回路の高精度化
Oral presentation
- 電子情報通信学会・情報処理学会 第11回情報科学技術フォーラム(FIT2012), Sep. 2012, Japanese, 電子情報通信学会, 東京都, Domestic conference組合せ最適化アルゴリズムに基づくオブジェクトとラベルのレイアウト認識
Oral presentation
- 電子情報通信学会・情報処理学会 第11回情報科学技術フォーラム(FIT2012), Sep. 2012, Japanese, 電子情報通信学会・情報処理学会, 東京都, Domestic conference階層的超解像による電子ズームの構成方法
Oral presentation
- 電子情報通信学会・情報処理学会 第11回情報科学技術フォーラム(FIT2012), Sep. 2012, Japanese, 電子情報通信学会・情報処理学会, 東京都, Domestic conferenceマルチモーダル入力に対応した重み付き多数決による識別器のGPU による高速化
Oral presentation
- 電子情報通信学会 ソサイエティ大会, Sep. 2012, Japanese, 電子情報通信学会, 富山, Domestic conferenceコンパレータのバラツキ補正技術を用いた弛張発振回路の評価
Oral presentation
- 電子情報通信学会・情報処理学会 第11回情報科学技術フォーラム(FIT2012), Sep. 2012, Japanese, 電子情報通信学会・情報処理学会, 東京都, Domestic conferenceウェーブレット変換に基づく学習型超解像のGPU による高速化手法
Oral presentation
- 電子情報通信学会 ソサイエティ大会, Sep. 2012, Japanese, 電子情報通信学会, 富山, Domestic conferencePVTバラツキ耐性を持つシングルスロープADコンバータ
Oral presentation
- 電子情報通信学会・情報処理学会 第11回情報科学技術フォーラム(FIT2012), Sep. 2012, Japanese, 電子情報通信学会, 東京都, Domestic conferenceBag-of-Visual Words 表現を用いた放送映像中の類似シーン検出
Oral presentation
- 情報処理学会 DA シンポジウム2012, Aug. 2012, Japanese, 情報処理学会, 下呂市, Domestic conference二分木辞書を用いた学習型超解像のストリーム処理型アーキテクチャ
Oral presentation
- 情報処理学会 DA シンポジウム2012, Aug. 2012, Japanese, 情報処理学会, 下呂市, Domestic conference充足可能性判定に基づく誤り追跡入力生成と機能特定を用いた論理診断手法
Oral presentation
- 情報処理学会 DA シンポジウム2012, Aug. 2012, Japanese, 情報処理学会, 下呂市, Domestic conferenceメタル配線により再構成可能なセルと論理再合成への応用
Oral presentation
- 電子情報通信学会 総合大会, Mar. 2012, Japanese, 電子情報通信学会, 岡山市, Domestic conference適応バイアス型コンパレータを用いたSC型DC-DC コンバータ
Oral presentation
- 電子情報通信学会 総合大会, Mar. 2012, Japanese, 電子情報通信学会, 岡山市, Domestic conference低電圧カレントミラー回路を用いた高精度ナノアンペア電流源
Oral presentation
- 電子情報通信学会 総合大会, Mar. 2012, Japanese, 電子情報通信学会, 岡山市, Domestic conference超低電力オペアンプの高速化技術
Oral presentation
- 電子情報通信学会 総合大会, Mar. 2012, Japanese, 電子情報通信学会, 岡山市, Domestic conference超低電圧ダイナミックコンパレータ回路のオフセットキャリブレーション手法の検討
Oral presentation
- 電子情報通信学会 総合大会, Mar. 2012, Japanese, 電子情報通信学会, 岡山市, Domestic conference準連続モードで動作するデジタル制御昇圧回路
Oral presentation
- 電子情報通信学会 総合大会, Mar. 2012, Japanese, 電子情報通信学会, 岡山市, Domestic conference高分解能SAR ADCに向けた容量DACの面積削減の検討
Oral presentation
- 電子情報通信学会 総合大会, Mar. 2012, Japanese, 電子情報通信学会, 岡山市, Domestic conference光エネルギー・ハーベスティングに向けたチャージポンプ回路の負荷電流特性改善
Oral presentation
- 電子情報通信学会 総合大会, Mar. 2012, Japanese, 電子情報通信学会, 岡山市, Domestic conference逆流電流削減による差動型整流回路の変換効率改善
Oral presentation
- 電子情報通信学会 パターン認識・メディア理解研究会, Mar. 2012, Japanese, 電子情報通信学会, 神戸市, Domestic conferenceカラー画像の品質評価に関する検討
Oral presentation
- STARCシンポジウムFY2011, Feb. 2012, Japanese, STARC, 横浜市, Domestic conference適応バイアス電流生成技術を用いたナノワットパワー・オペアンプの高速化
Poster presentation
- 電子情報通信学会 画像工学研究会, Nov. 2011, Japanese, 電子情報通信学会, 飯塚市, Domestic conference学習型超解像のための高能率な辞書
Oral presentation
- 電子情報通信学会 ソサイエティ大会, Sep. 2011, Japanese, 電子情報通信学会, 札幌市, Domestic conference超低電力CMOS温度センサの評価
Oral presentation
- 電子情報通信学会・情報処理学会 第10回情報科学技術フォーラム(FIT2011), Sep. 2011, Japanese, 電子情報通信学会・情報処理学会, 函館市, Domestic conference学習型超解像における高周波パッチの探索および生成手法
Oral presentation
- 電子情報通信学会・情報処理学会 第10回情報科学技術フォーラム(FIT2011), Sep. 2011, Japanese, 電子情報通信学会・情報処理学会, 函館市, Domestic conferenceマルチモーダル入力に対応した重み付き多数決による識別器
Oral presentation
- 電子情報通信学会 ソサイエティ大会, Sep. 2011, Japanese, 電子情報通信学会, 札幌市, Domestic conferenceコンパレータのバラツキ補正回路を用いた弛張発振回路
Oral presentation
- 情報処理学会 DAシンポジウム2011, Aug. 2011, Japanese, 情報処理学会, 下呂市, Domestic conference修正可能な外部出力数に着目した部分修正に基づく論理診断手法
Oral presentation
- 情報処理学会 DAシンポジウム2011, Aug. 2011, Japanese, 情報処理学会, 下呂市, Domestic conferenceビット構成の異なる加算器を組み合わせた木構造部分積加算回路による乗算器のグリッチ削減
Oral presentation
- 情報処理学会 DAシンポジウム2011, Aug. 2011, Japanese, 情報処理学会, 下呂市, Domestic conferenceSVMに基づく画像認識処理のGPUを用いた高速化手法
Oral presentation
- 電子情報通信学会 集積回路研究会, Jul. 2011, Japanese, 電子情報通信学会, 広島市, Domestic conference超低電圧ディジタル回路に向けた入出力論理補正レベルシフタ回路
Oral presentation
- 電子情報通信学会 集積回路研究会, Jul. 2011, Japanese, 電子情報通信学会, 広島市, Domestic conference基板バイアス制御を用いた超低電圧センスアンプ回路の高速化
Oral presentation
- 電子情報通信学会 第24回 シリコンアナログRF研究会, Mar. 2011, Japanese, 電子情報通信学会, 東京, Domestic conference微小オフセット電圧による温度特性を改善した基準電流源回路
Oral presentation
- 電子情報通信学会総合大会, Mar. 2011, Japanese, 電子情報通信学会, 東京, Domestic conference熱電変換素子を用いた電力変換インターフェース回路
Oral presentation
- 電子情報通信学会総合大会, Mar. 2011, Japanese, 電子情報通信学会, 東京, Domestic conference超低電力CMOSスマート温度センサ回路
Oral presentation
- 電子情報通信学会総合大会, Mar. 2011, Japanese, 電子情報通信学会, 東京, Domestic conference超低電圧SRAM用センスアンプ回路のプリチャージ動作の高速化
Oral presentation
- 電子情報通信学会総合大会, Mar. 2011, Japanese, 電子情報通信学会, 東京, Domestic conference極低消費電力バンドギャップリファレンス回路の高精度化
Oral presentation
- 電子情報通信学会総合大会, Mar. 2011, Japanese, 電子情報通信学会, 東京, Domestic conferenceナノアンペア電流源回路の電流バラツキ補正
Oral presentation
- 電子情報通信学会総合大会, Mar. 2011, Japanese, 電子情報通信学会, 東京, Domestic conferenceサブスレッショルド・ディジタルLSIに向けた遅延制御回路技術
Oral presentation
- 電子情報通信学会総合大会, Mar. 2011, Japanese, 電子情報通信学会, 東京, Domestic conferenceサブスレッショルドLSIに適したオンチップ電源回路の検討
Oral presentation
- The 16th Asia and South Pacific Design Automation Conference, Jan. 2011, English, IEEE, 横浜市, International conferenceA 95-nA, 523ppm/C, 0.6-uW CMOS Current Reference Circuit with Subthreshold MOS Resistor Ladder
Oral presentation
- IEEE Asian Solid-State Circuits Conference 2011, Nov. 2010, English, IEEE, 北京(中国), International conferenceA CMOS Bandgap and Sub-Bandgap Voltage Reference Circuits for Nanowatt Power LSIs
Oral presentation
- Synthesis And System Integration of Mixed Information technologies 2010 (SASIMI2010), Oct. 2010, English, SASIMI Organizing Committee, Taipei,TW., International conferenceAn incremental synthesis technique for ECO based on iterative procedure for error diagnosis and spare cell assignment
Oral presentation
- Synthesis And System Integration of Mixed Information technologies 2010 (SASIMI2010), Oct. 2010, English, SASIMI Organizing Committee, Taipei,TW., International conferenceAn incremental synthesis technique based on error diagnosis and technology remapping for clusters
Oral presentation
- DA シンポジウム2010, Sep. 2010, Japanese, 情報処理学会, 豊橋市, Domestic conference入力信号間に生じる遅延を考慮した桁上げ吸収回路の低消費電力化
Oral presentation
- 電子情報通信学会 ソサイエティ大会, Sep. 2010, Japanese, 電子情報通信学会, さかい, Domestic conference書き込み安定性を向上させたサブスレッショルドSRAM
Oral presentation
- 第9回情報科学技術フォーラム (FIT2010), Sep. 2010, Japanese, 電子情報通信学会, 福岡市, Domestic conference局所ヒストグラムの時間変動に着目したディゾルブ検出手法
Oral presentation
- DA シンポジウム2010, Sep. 2010, Japanese, 情報処理学会, 豊橋市, Domestic conferenceクラスタ単位のセル割当てを用いた論理再合成手法
Oral presentation
- 第9回情報科学技術フォーラム (FIT2010), Sep. 2010, Japanese, 電子情報通信学会, 福岡市, Domestic conferenceウェーブレット係数の主成分分析を用いた学習型超解像
Oral presentation
- 電子情報通信学会 ソサイエティ大会, Sep. 2010, Japanese, 電子情報通信学会, 堺市, Domestic conferenceTFFを用いた相補構成スイッチトキャパシタ型DC-DC コンバータ
Oral presentation
- 2010 International Conference on Solid State Devices and Materials, Sep. 2010, English, JSAP, 東京, International conferenceTemperature Compensated Nano-Ampere CMOS Current Reference Circuit Using Small Offset Voltage
Oral presentation
- The 36th European Solid-State Circuits Conference, Sep. 2010, English, IEEE, セビリア(スペイン), International conferenceA nano-ampere current reference circuit and its temperature dependence control by using temperature characteristics of carrier mobilities
Oral presentation
- STARCフォーラム/シンポジウム2010, Aug. 2010, Japanese, 半導体理工学研究センター, 横浜市, Domestic conference適応バイアス技術を用いた超低電力コンパレータのチップ測定
Poster presentation
- 2010 IEEE International 53rd Midwest Symposium on Circuits and Systems, Aug. 2010, English, IEEE, シアトル(米国), International conferenceWrite-Assisted Subthreshold SRAM by Using On-Chip Threshold Voltage Monitoring Circuit
Oral presentation
- 2010 IEEE International 53rd Midwest Symposium on Circuits and Systems, Aug. 2010, English, IEEE, シアトル(米国), International conferenceNano-Ampere CMOS Current Reference with Little Temperature Dependence Using Small Offset Voltage
Oral presentation
- 電子情報通信学会 集積回路研究会, Jul. 2010, Japanese, 電子情報通信学会, 大阪市, Domestic conference低電圧ディジタルLSIのためのレベルコンバータ回路
Oral presentation
- LSIとシステムのワークショップ2010, May 2010, Japanese, 電子情報通信学会, 北九州市, Domestic conference超低電力で動作するオンチップ参照クロック源
Poster presentation
- LSIとシステムのワークショップ2010, May 2010, Japanese, 電子情報通信学会, 北九州市, Domestic conferenceサブスレッショルド・ディジタル回路のためのオンチップ遅延バラツキ補正回路の評価
Poster presentation
- LSIとシステムのワークショップ2010, May 2010, Japanese, 電子情報通信学会, 北九州市, Domestic conferenceサブスレッショルドLSIにむけた低電圧レギュレータ回路
Poster presentation
- IEEE International Symposium on Circuits and Systems (ISCAS 2010), May 2010, English, IEEE, Paris,FR., International conferenceSuper-Resolution Technique for Thermography with Dual-Camera System
Oral presentation
- 第38回知能システムシンポジウム, Mar. 2010, Japanese, 計測自動制御学会, 神戸市, Domestic conference汎用監視支援システムの構築-動き特徴量の抽出-
Oral presentation
- 第38回知能システムシンポジウム, Mar. 2010, Japanese, 計測自動制御学会, 神戸市, Domestic conference汎用監視支援システムの構築-HOG特徴量と動き特徴量を用いた識別-
Oral presentation
- 電子情報通信学会総合大会, Mar. 2010, Japanese, 電子情報通信学会(IEICE), 仙台, Domestic conference適応バイアス技術を用いた極低消費電流コンパレータ
Oral presentation
- 電子情報通信学会総合大会, Mar. 2010, Japanese, 電子情報通信学会(IEICE), 仙台, Domestic conference低電圧サブスレッショルドLSIに向けたリニア・レギュレータ回路
Oral presentation
- 電子情報通信学会総合大会, Mar. 2010, Japanese, 電子情報通信学会(IEICE), 仙台, Domestic conferenceデューティ制御回路を用いたスイッチトキャパシタ型DC-DCコンバータ
Oral presentation
- 電子情報通信学会総合大会, Mar. 2010, Japanese, 電子情報通信学会(IEICE), 仙台, Domestic conferenceサブスレッショルドCMOSディジタル回路の遅延バラツキ補正アーキテクチャの評価
Oral presentation
- 電子情報通信学会総合大会, Mar. 2010, Japanese, 電子情報通信学会(IEICE), 仙台, Domestic conferenceSource-Coupled Logic回路を用いたサブスレッショルドSRAMセルの検討
Oral presentation
- 電子情報通信学会総合大会, Mar. 2010, Japanese, 電子情報通信学会(IEICE), 仙台, Domestic conferencePVTバラツキ耐性を有する基準クロック発振回路
Oral presentation
- 映像情報メディア学会メディア工学研究会, Dec. 2009, Japanese, ITE, 松本市, Domestic conference野球中継番組におけるテロップ情報を用いたダイジェスト映像自動生成
Oral presentation
- 情報処理学会研究報告, Dec. 2009, Japanese, IPSJ, 高知市, Domestic conference回路構造を考慮した修正箇所候補抽出に基づく論理診断手法
Oral presentation
- 情報処理学会研究報告, Dec. 2009, Japanese, IPSJ, 高知市, Domestic conferenceハイブリッド型CMOS論理構成の4-2加算器による乗算器のグリッチ削減
Oral presentation
- Workshop on Information; Nano and Photonics Technology 2009, Dec. 2009, English, 神戸大学, 連携創造本部先端研究推進部門, Kobe, Japan, International conferenceAn on-chip delay compensation for nano-power subthreshold CMOS digital LSIs
Poster presentation
- 電子情報通信学会第24回信号処理シンポジウム, Nov. 2009, Japanese, IEICE, 鹿児島市, Domestic conferenceクロス形状フラクタルを用いた画像の高解像度化
Oral presentation
- 電子情報通信学会 集積回路研究会, Oct. 2009, Japanese, 電子情報通信学会(IEICE), 東京, Domestic conference極低電力サブスレッショルド・ディジタル回路のオンチップ遅延バラツキ補正技術
Oral presentation
- The 35th European Solid-State Circuits Conference, Sep. 2009, English, 米国電気電子学会(IEEE), Athens, Greece, International conferenceVariation Tolerant Subthreshold Adder Design for Ultra-low Power LSIs
Poster presentation
- 情報処理学会DAシンポジウム2009, Aug. 2009, Japanese, IPSJ, 加賀市, Domestic conference素子のクラスタリングを用いた論理診断手法
Oral presentation
- 情報処理学会DAシンポジウム2009, Aug. 2009, Japanese, IPSJ, 加賀市, Domestic conference信号線欠落に対応した論理診断における変更箇所数削減
Oral presentation
- 52nd. IEEE International Midwest Symposium on Circuits and Systems, Aug. 2009, English, 米国電気電子学会(IEEE), Cancun, Mexico, International conferenceSwitching-voltage detection and compensation circuits for ultra-low-voltage CMOS inverters
Oral presentation
- 52nd. IEEE International Midwest Symposium on Circuits and Systems, Aug. 2009, English, 米国電気電子学会(IEEE), Cancun, Mexico, International conferenceDelay-compensation techniques for ultra-low-power subthreshold CMOS digital LSIs
Oral presentation
- 東京大学VDECデザイナーズフォーラム2009, Jun. 2009, Japanese, 東京大学VDEC, 東京, Domestic conference逆流電流遮断による同期整流型DC-DCコンバータの電力変換効率改善
Poster presentation
- 東京大学VDECデザイナーズフォーラム2009, Jun. 2009, Japanese, 東京大学VDEC, 東京, Domestic conferencePVTバラツキ特性を改善したサブスレッショルド電流源
Poster presentation
- 電子情報通信学会 LSIとシステムのワークショップ2009, May 2009, Japanese, 電子情報通信学会(IEICE), 北九州, Domestic conferenceサブスレッショルド・ディジタル回路における遅延時間制御の一設計手法
Poster presentation
- 電子情報通信学会 LSIとシステムのワークショップ2009, May 2009, Japanese, 電子情報通信学会(IEICE), 北九州, Domestic conferenceインダクタの逆流電流検出回路を用いた高効率同期整流型DC-DCコンバータ
Poster presentation
- 電子情報通信学会 LSIとシステムのワークショップ2009, May 2009, Japanese, 電子情報通信学会(IEICE), 北九州, Domestic conferenceMOSFETのキャリア移動度温度特性を利用した基準電流源回路
Poster presentation
- 電子情報通信学会総合大会, Mar. 2009, Japanese, IEICE, 松山, Domestic conference電源電圧制御によるサブスレッショルド・ディジタル回路のプロセスバラツキ補正技術
Oral presentation
- 電子情報通信学会総合大会, Mar. 2009, Japanese, IEICE, 松山, Domestic conference軽負荷動作時の逆流電流損失を改善した同期整流型DC-DCコンバータ
Oral presentation
- 電子情報通信学会総合大会, Mar. 2009, Japanese, IEICE, 松山, Domestic conferenceサブスレッショルドCMOS LSIに向けたスイッチトキャパシタ型DC-DCコンバータ
Oral presentation
- 電子情報通信学会総合大会, Mar. 2009, Japanese, IEICE, 松山, Domestic conferenceMOSFETのしきい値電圧差を利用した参照電圧源回路
Oral presentation
- 電子情報通信学会総合大会, Mar. 2009, Japanese, IEICE, 松山, Domestic conferenceMOSFETのキャリア移動度温度特性を利用した基準電流源回路
Oral presentation
- 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009), Mar. 2009, English, 沖縄, International conferenceAn error diagnosis technique based on location sets to rectify subcircuits
Poster presentation
- Workshop on Information, Nano, and Photonics Technology, Nov. 2008, English, 神戸大学産学連携推進本部, 神戸, International conferenceAn On-Chip Threshold Voltage Difference Monitor Circuit for Nano-Power Sub-threshold Digital LSIs
Poster presentation
- 第7回情報科学技術フォーラム, Sep. 2008, Japanese, 神奈川県藤沢市, Domestic conference野球中継番組におけるダイジェスト映像自動生成
Oral presentation
- 第7回情報科学技術フォーラム, Sep. 2008, Japanese, 神奈川県藤沢市, Domestic conference赤外線サーモグラフィのための超解像手法
Oral presentation
- 第7回情報科学技術フォーラム, Sep. 2008, Japanese, 神奈川県藤沢市, Domestic conferenceTotal Variationに基づく画像雑音除去の高速化手法
Oral presentation
- 情報処理学会DA シンポジウム2008, Aug. 2008, Japanese, 静岡県浜松市, Domestic conference部分回路の修正箇所情報を利用した論理診断手法
Oral presentation
- 13th International OFDM-Workshop 2008, Aug. 2008, English, Hamburg, Germany, International conferenceFading Compensation for OFDM Mobile Reception Using Guard Interval
Oral presentation
- 14th Workshop on Synthesis And System Integration of Mixed Information technologies, Oct. 2007, English, IEEE Sapporo Section, 札幌市, International conferenceAn LUT-Based Error Diagnosis Technique Extended for Multiple Missing Line Errors Based on Iterative Diagnosis Procedure
Oral presentation
- 14th Workshop on Synthesis And System Integration of Mixed Information technologies, Oct. 2007, English, IEEE Sapporo Section, 札幌市, International conferenceAn Error Diagnosis Technique Based on Specifications with Don't Cares
Oral presentation
- 第6回情報科学技術フォーラム, Sep. 2007, Japanese, 情報処理学会, 豊田市, Domestic conferenceルームミラー装着式車内カメラの自動キャリブレーションと運転者の頭部位置推定
Oral presentation
- 第6回情報科学技術フォーラム, Sep. 2007, Japanese, 情報処理学会, 豊田市, Domestic conferenceクローズドキャプションを用いた野球映像インデキシング
Oral presentation
- 第6回情報科学技術フォーラム, Sep. 2007, Japanese, 情報処理学会, 豊田市, Domestic conferenceクローズドキャプションを用いたニュース番組におけるトピック分割手法
Oral presentation
- 情報処理学会 DA シンポジウム2007, Aug. 2007, Japanese, 情報処理学会, 浜松市, Domestic conference補正乗算器の動的割当てによるVSBイコライザの消費電力削減
Oral presentation
- 情報処理学会 DA シンポジウム2007, Aug. 2007, Japanese, 情報処理学会, 浜松市, Domestic conference部分回路の修正解に含まれるドントケアを考慮した論理診断手法
Oral presentation
- 電子情報通信学会技術研究報告, Aug. 2007, Japanese, 電子情報通信学会, 高知市, Domestic conference演算量を抑えたOFDM 移動受信のためのICI 除去
Oral presentation
- 情報処理学会 DA シンポジウム2007, Aug. 2007, Japanese, 情報処理学会, 浜松市, Domestic conferenceタイミングを考慮した論理再合成手法
Oral presentation
- FIT2006, Sep. 2006, Japanese, 福岡大学, Domestic conference赤外線ポインタと画像処理によるプレゼンテーション支援システム
Oral presentation
- FIT2006, Sep. 2006, Japanese, 福岡大学, Domestic conference視覚特性を考慮した誤差拡散法によるディスプレイの高階調化
Oral presentation
- FIT2006, Sep. 2006, Japanese, 福岡大学, Domestic conference医療用液晶ディスプレイのための3 倍密度誤差拡散法とその拡散係数の改善
Oral presentation
- 電子情報通信学会ITS研究会, Sep. 2005, Japanese, 機械振興会館, Domestic conference近赤外線パルス照明とステレオカメラを用いた運転手の頭部追跡手法
Oral presentation
- DAシンポジウム2005, Aug. 2005, Japanese, 情報処理学会 システムLSI設計技術研究会, 遠鉄ホテルエンパイア, Domestic conference複数の信号線欠落誤りに対応した論理診断手法
Oral presentation
- DAシンポジウム2005, Aug. 2005, Japanese, 情報処理学会 システムLSI設計技術研究会, 遠鉄ホテルエンパイア, Domestic conferenceOFDM復調用FFTの消費電力削減
Oral presentation
- システム制御情報学会第3回サイバネティック・フレキシブルオートメーションシンポジウム, 2003, Japanese, システム制御情報学会, 千里ライフサイエンスセンター, Domestic conference色相情報を用いた高速な頭部領域検出手法について
Oral presentation
- 第2回情報科学技術フォーラム, 2003, Japanese, 情報処理学会, 札幌学院大学, Domestic conference医用画像DICOMの可逆圧縮に関する検討
Oral presentation
- 第2回情報科学技術フォーラム, 2003, Japanese, 情報処理学会, 札幌学院大学, Domestic conferenceマルチカメラ映像からの球追跡のための一手法
Oral presentation
- 映像情報メディア学年年次大会, 2003, Japanese, 映像情報メディア学会, 未記入, Domestic conferenceディスプレイの画素形状に応じた光学的画像処理による映像品質の改善
Oral presentation
- 映像情報メディア学年年次大会, 2003, Japanese, 映像情報メディア学会, 未記入, Domestic conferenceディジタルディスプレイのための疑似階調表現手法とその客観評価
Oral presentation
- 映像情報メディア学年年次大会, 2003, Japanese, 映像情報メディア学会, 未記入, Domestic conferenceサブフィールド法における発光パターンの解析と評価
Oral presentation
Association Memberships
Research Projects
- 学術研究助成基金助成金／基盤研究(C), Apr. 2018 - Mar. 2021
Competitive research funding
- 学術研究助成基金助成金／基盤研究(C), Apr. 2015 - Mar. 2018
Competitive research funding
- 学術研究助成基金助成金／基盤研究(C), Apr. 2015 - Mar. 2018, Principal investigator
Competitive research funding
- 科学研究費補助金／基盤研究(C), Apr. 2012 - Mar. 2015
Competitive research funding
- 科学研究費補助金／基盤研究(C), Apr. 2012 - Mar. 2015, Principal investigator
Competitive research funding
- 科学研究費補助金／基盤研究(C), 2009
Competitive research funding
- 2007, Principal investigatorルームミラー透過式赤外カメラを用いた安全運転支援のための車内撮像システム
Competitive research funding
- 科学研究費補助金／基盤研究(C), 2006
Competitive research funding