Directory of Researchers

NAGATA Makoto
"Graduate School of Science, Technology and Innovation / Department of Science, Technology and Innovation"
Professor
Electro-Communication Engineering
Last Updated :2020/08/05

Researcher Profile and Settings

Affiliation

  • <Faculty / Graduate School / Others>

    "Graduate School of Science, Technology and Innovation / Department of Science, Technology and Innovation"
  • <Related Faculty / Graduate School / Others>

    Faculty of Engineering / Department of Computer Science and Systems Engineering, Graduate School of Engineering / Department of Chemical Science and Engineering, Graduate School of Engineering / Department of Computer Science and Systems Engineering, Graduate School of System Informatics / Department of Information Science

Teaching

Research Activities

Research Interests

  • Hardware Security
  • Advanced Electronics Packaging
  • Electromagnetic Compatibility
  • Integrated Circuit Design

Research Areas

  • Informatics / Computer systems
  • Manufacturing technology (mechanical, electrical/electronic, chemical engineering) / Electronic devices and equipment

Awards

  • May 2011 (社)電子情報通信学会集積回路研究専門委員会, 優秀若手講演賞, アナログ基本回路の基板雑音感度に関する考察

    TAKAYA Satoshi, BANDO Yoji, HASEGAWA Takashi, OHKAWA Toru, SOUDA Masaaki, TAKARAMOTO Toshiharu, YAMADA Toshio, KUMASHIRO Shigetaka, MOGAMI Tohru, NAGATA Makoto

  • May 2009 エレクトロニクス実装学会, 平成21年技術賞, デジタルLSI電源ノイズのオンチップ観測とシミュレーション技術

    NAGATA Makoto, IWATA Atsushi

  • Jun. 2005 中国地域産学官コラボレーションセンター, 大学発ベンチャー功労賞, アナログ/RF回路混載LSIの設計開発と設計者人材育成~株式会社エイアールテック設立~

    IWATA Atsushi, MORIE Takashi, NAGATA Makoto

  • May 2005 LSI IPデザイン・アワード運営委員会, 第7回LSI IPデザイン・アワード IP賞, ミックストシグナルLSIのためのオンチップマルチチャネル信号モニタ

    NOGUCHI Koichiro, NAGATA Makoto

Published Papers

  • ICチップパッケージングにおけるノイズ抑制磁性材料の導入と評価

    青井舞, 渡邊航, 小松美早紀, 地家幸祐, 田中聡, 三浦典之, 永田真, 宮澤安範, 山口正洋

    Mar. 2020, 2020年電子情報通信学会総合大会, 272, Japanese

  • マイクロウェーブ展会場における不要電波の評価

    宮澤安範, 田中聡, 山口正洋, 椙本祥史, 渡邊航, 永田真, 沖米田恭之

    Mar. 2020, 2020年電子情報通信学会総合大会, 266, Japanese

  • パワー半導体インバータ回路における放射ノイズの広帯域評価

    小松美早紀, 渡邊航, 青井舞, 田中聡, 三浦典之, 永田真

    Mar. 2020, 2020年電子情報通信学会総合大会, 257, Japanese

  • 暗号回路における基板電流検出型レーザー故障注入攻撃対策の軽量設計法

    山下憂記, 松田航平, 永田真, 三浦典之

    Mar. 2020, 電子情報通信学会技術報告, 119 (444), 283 - 284, Japanese

  • ICチップレベル電源雑音シミュレーョンによる暗号モジュールのサイドチャネ漏洩評価

    安田一樹, 門田和樹, 月岡暉裕, 三浦典之, 永田真, カシーク スリニバサン, シャン ワン, ラン リン, イン シュン リー, ノーマン チャン

    Mar. 2020, 電子情報通信学会技術報告, 119 (444), 279 - 282, Japanese

  • 誘導インパルス型の瞬時自己破壊回路を利用した検知後対処に基づく物理攻撃対策

    多田捷, 松田航平, 永田真, 﨑山一男, 三浦典之

    Mar. 2020, 電子情報通信学会技術報告, 119 (444), 275 - 277, Japanese

  • An IC-level countermeasure against laser fault injection attack by information leakage sensing based on laser-induced opto-electric bulk current density

    Kohei Matsuda, Sho Tada, Makoto Nagata, Yuichi Komano, Yang Li, Takeshi Sugawara, Mitsugu Iwamoto, Kazuo Ohta, Kazuo Sakiyama, Noriyuki Miura

    Feb. 2020, Japanese Journal of Applied Physics (JJAP), 59, 1 - 12, English

    [Refereed]

  • A C-P-S Simulation Technique of Power-Noise Side Channel Leakage in Cryptographic Integrated Circuits

    Makoto Nagata, Akihiro Tsukioka, Norman Chang, Karthik Srinivasan

    Jan. 2020, in Proc. 25th DesignCon 2020, English

    [Refereed]

  • Deployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security

    Makoto Nagata

    Dec. 2019, in Proceedings of the 9th International Conference on Security, Privacy, and Applied Cryptography Engineering (SPACE 2019), 1 - 5, English

    [Refereed][Invited]

  • GHz帯に対応するノイズ抑制シートを用いたインバータ機器からの不要電波の抑制

    近藤幸一, 栗本正樹, 大平祐介, 田中聡, 永田真, 沖米田恭之, 山口正洋

    Nov. 2019, MWE2019 Microwave Workshop Digest, 377 - 380, Japanese

  • 電力用インバータ機器からの不要放射によるモバイル通信への干渉評価

    永田真, 渡邊航, 三浦典之, 宮澤安範, 田中聡, 山口正洋

    Nov. 2019, MWE2019 Microwave Workshop Digest, 373 - 376, Japanese

  • 半導体チップの異種パッケージングにおける電源ノイズ特性の評価

    地家幸佑, 渡邊航, 三浦典之, 永田真

    Nov. 2019, エレクトロニクス実装学会/超高速・高周波エレクトロニクス実装研究会, 令和元年度第3回公開研究会論文集, 19 (3), 13 - 18, Japanese

  • 楕円曲線ディジタル署名(ECDSA)ハードウェアモジュールの動作性能評価

    高橋佑弥, 門田和樹, 佐藤俊寛, 沖殿貴朗, 三木拓司, 三浦典之, 永田真

    Nov. 2019, 電子情報通信学会技術報告, 119 (284), 37 - 40, Japanese

  • 半導体チップのハードウェアトロージャンに対する物理レベルの取り組み(I)

    川村信一, 今福健太郎, 坂根広史, 堀洋平, 永田真, 林優一, 松本勉

    Nov. 2019, 電子情報通信学会技術報告, 119 (260), 47 - 52, Japanese

  • 暗号モジュールにおける電源ノイズとサイドチャネル漏洩の対策(?)

    門田和樹, 月岡暉裕, 中川大地, 安田一樹, 三浦典之, 永田真, カシーク スリニバサン, シャン ワン, ラン リン, イン シュン リー, ノーマン チャン

    Nov. 2019, 電子情報通信学会技術報告, 119 (261), 25 - 28, Japanese

  • ペアリング暗号ハードウェアの相関電磁波解析に関する検討

    門脇悠真, 上野嶺, ヴィッレ ウリマウル, 藤本大介, 林優一, 永田真, 池田誠, 松本勉, 本間尚文

    Nov. 2019, 電子情報通信学会技術報告, 119 (260), 13 - 18, Japanese

  • A Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices

    Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi

    Nov. 2019, in Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC 2019), 25 - 28, English

    [Refereed]

  • Masahiro Yamaguchi, Akihiro Takahashi, Yasunori Miyazawa, Koh Watanabe, Kosuke Jike, Satoshi Tanaka, Noriyuki Miura, Makoto Nagata

    NiCuZn spinel ferrite particles were sintered into 50 μm-thick plate and mounted in between IC die and its interposer to explore their suitability as electromagnetic noise suppressor up to 10 GHz. A 50 μm thick Y-Type hexaferrite plate with density of 5.2 g/cm3 exhibits the figure-of-merit, Ploss/Pin, as high as 0.27 at 7 GHz. The test ferrite plate was embedded in between IC chip and interposer using a newly developed pre-assembly technique. This was enough to suppress on-chip conduction noise and corresponding near field emission by 4-17 dB in wireless communication channels.

    Oct. 2019, Proceedings of the The 12th International Workshop on the Electromagnetic Compatibility of Integrated Circuits(EMC Compo 2019), 231 - 233, English

    [Refereed]

    International conference proceedings

  • ICチップパッケージング内における磁性膜による不要電波抑制技術及び無線通信品質の向上

    渡邊航, 地家幸祐, 田中聡, 三浦典之, 永田真, 高橋昭博, 宮澤安範, 山口正洋

    Oct. 2019, 電子情報通信学会技術報告, 119 (241), 175 - 178, Japanese

  • Development of Backside Buried Metal Layer Technology for 3D-Ics

    Naoya Watanabe, Yuuki Araga, Haruo Shimamoto, Katsuya Kikuchi, Makoto Nagata

    Oct. 2019, in Proceedings of The 52th International Symposium on Microelectronics (IMAPS 2019), 1 - 6, English

    [Refereed]

  • Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital Ics

    Takuji Miki, Makoto Nagata, Akihiro Tsukioka, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi

    Oct. 2019, IEEE 2019 International 3D Systems Integration Conference (3DIC 2019), 1 - 4, English

    [Refereed]

  • Development of novel Cu electroplating for electronic interconnects in advanced packaging

    Tomoaki Mahiko, Makoto Nagata

    Oct. 2019, in Proceedings of the 29th Asian Session of Advanced Metallization Conference 2019 (ADMETAplus 2019), P-5 (poster presentation), 47 - 48, English

    [Refereed]

  • In-Place Power Noise and Signal Waveform Measurements on LVDS Channels in Fan-Out Multiple IC Chip Packaging

    Hiroki Sonoda, Makoto Nagata, Daisuke Tanaka, Yoshihide Murakami, Kyoshi Mihara, Kazuo Makida, Katsuya Kikuchi

    Oct. 2019, in Proceedings of the 12th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo 2019), 1 - 3, English

    [Refereed]

  • Magnetic Composite Sheets in IC Chip Packaging for Suppression of Undesired Noise Emission to Wireless Communication Channels

    Koh Watanabe, Kosuke Jike, Satoshi Tanaka, Noriyuki Miura, Makoto Nagata, Akihiro Takahashi, Yasunori Miyazawa, Masahiro Yamaguchi

    Oct. 2019, in Proceedings of the 12th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo 2019), 1 - 3, English

    [Refereed]

  • Sintered Ferrite Thin Plate Noise Suppressor Mounted on IC Chip Interposer

    Masahiro Yamaguchi, Akihiro Takahashi, Yasunori Miyazawa, Koh Watanabe, Kosuke Jike, Satoshi Tanaka, Noriyuki Miura, Makoto Nagata

    Oct. 2019, in Proceedings of the 12th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo 2019), 1 - 3, English

    [Refereed][Invited]

  • On-Chip Protection of Cryptographic ICs Against Physical Side Channel Attacks

    Makoto Nagata

    Oct. 2019, in Proceedings of the 13th IEEE International Conference on ASIC (ASICON 2019), 1 - 4, English

    [Refereed][Invited]

  • Evaluation of Undesired Radio Waves below -170 dBm/Hz from Semiconductor Switching Devices for Impact on Wireless Communication

    Koh Watanabe, Yoshifumi Sugimoto, Satoshi Tanaka, Noriyuki Miura, Makoto Nagata, Yasunori Miyazawa, Masahiro Yamaguchi

    Sep. 2019, IEEE Letters on Electromagnetic Compatibility Practice and Applications, 72 - 76, English

    [Refereed]

  • 3次元集積回路の電源品質改善のための裏面埋設配線の形成プロセス

    渡辺直也, 荒賀佑樹, 島本晴夫, 永田真, 菊地克弥

    Sep. 2019, エレクトロニクス実装学会第29回マイクロエレクトロニクスシンポジウム(MES), 259 - 262, Japanese

  • ディジタルIC チップにおける不要ノイズ低減対策のオンチップ及びオンボード評価

    地家幸祐, 渡邊航, 三浦典之, 永田真

    Sep. 2019, 2019年電子情報通信学会ソサイエティ大会, 234 - 234, Japanese

  • IC チップレベル消費電流シミュレーションによる 暗号モジュールのサイドチャネル漏洩評価

    安田 一樹, 門田和樹, 月岡暉裕, 三浦典之, 永田真

    Sep. 2019, 2019年電子情報通信学会ソサイエティ大会, 138 - 138, Japanese

  • レーザーフォールト注入攻撃への対策が施されたAES暗号チップの脆弱性評価

    羽田野 凌太, 李 陽, 多田 捷, 松田 航平, 三浦 典之, 菅原 健, 崎山 一男

    Sep. 2019, 2019年電子情報通信学会ソサイエティ大会, 47 - 47, Japanese

  • Evaluation of Near-Field Undesired Radio Waves from Semiconductor Switching Circuits

    Makoto Nagata, Koh Watanabe, Yoshifumi Sugimoto, Noriyuki Miura, Satoshi Tanaka, Yasunori Miyazawa, Masahiro Yamaguchi

    Sep. 2019, in Proceedings of the 2019 International Symposium on Electromagnetic Compatibility (EMC Europe 2019), 866 - 869, English

    [Refereed]

  • An Information Leakage Sensor Based on Measurement of Laser-Induced Opto-Electric Bulk Current Density

    Kohei Matsuda, Sho Tada, Makoto Nagata, Yang Li, Takeshi Sugawara, Mitsugu Iwamoto, Kazuo Ohta, Kazuo Sakiyama, Noriyuki Miura

    Sep. 2019, in Extended Abstracts of International Conference on Solid State Devices and Materials (SSDM), 501 - 502, English

    [Refereed]

  • 磁性体を利用したディジタルICチップノイズ対策手法の評価

    地家幸佑, 渡邊航, 田中聡, 三浦典之, 永田真, 高橋昭博, 宮澤安範, 山口正洋

    Aug. 2019, 電子情報通信学会技術報告, 119 (162), 79 - 83, Japanese

  • センサデバイスの非理想特性を利用した固有性抽出法

    Thibaut Constant, 永田真, 三浦典之

    Jul. 2019, 電子情報通信学会技術報告, 119 (143), 389 - 390, Japanese

  • 乗法的オフセットに基づく高効率AESハードウェアアーキテクチャの設計

    上野嶺, 森岡澄夫, 三浦典之, 松田航平, 永田真, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, 本間尚文

    Jul. 2019, 電子情報通信学会技術報告, 119 (143), 375 - 382, Japanese

  • ICチップレベル消費電流シミュレーションによる暗号モジュールのサイドチャネル漏洩評価

    安田一樹, 門田和樹, 月岡暉裕, 三浦典之, 永田真

    Jul. 2019, 電子情報通信学会技術報告, 119 (143), 139 - 143, Japanese

  • A 0.72pJ/bit 400μm2 Physical Random Number Generator Utilizing SAR Technique for Secure Implementation on Sensor Nodes,

    Takuji Miki, Noriyuki Miura, Makoto Nagata

    Jul. 2019, IEICE Transactions on Electronics, E102-C (7), 530 - 537, English

    [Refereed]

  • Impacts of Undesired Radio Waves on Mobile Communications Nearby Inverter Power Devices

    Koh Watanabe, Yoshifumi Sugimoto, Noriyuki Miura, Makoto Nagata, Satoshi Tanaka, Yasunori Miyazawa, Masahiro Yamaguchi

    Jul. 2019, in Proceedings of the 2019 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI 2019), English

    [Refereed]

  • Compact Simulation of Chip-to-Chip Active Noise Coupling on A System PCB Board

    Hiroshi Suenaga, Akihiro Tsukioka, Kosuke Jike, Makoto Nagata

    Jul. 2019, in Proceedings of the 2019 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI 2019), English

    [Refereed]

  • A Fast Side-channel Leakage Simulation Technique Based on IC Chip Power Noise Modeling

    Akihiro Tsukioka, Makoto Nagata, Karthik Srinivasan, Shan Wan, Lang Lin, Ying-Shiun Li, Norman Chang

    Jul. 2019, in Proceedings of the 2019 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI 2019), English

    [Refereed]

  • Analysis of Disturbance Propagation in Silicon Substrate on SOI-BCD Process,

    Ko Oyama, Yasuyuki Ishikawa, Shuji Agatsuma, Makoto Nagata

    Jun. 2019, Proceedings of the IEICE EMC Sapporo 2019/IEEE APEMC 2019, English

    [Refereed]

  • Chip to Chip Noise Interference Simulation Via Package and Board,

    Hiroshi Suenaga, Akihiro Tsukioka, Makoto Nagata

    Jun. 2019, Proceedings of the IEICE EMC Sapporo 2019/IEEE APEMC 2019, English

    [Refereed]

  • Immunity Simulation of ESD Protection Devices in High Voltage BiCD Technology

    Akihiro Tsukioka, Makoto Nagata, Noriyuki Miura, Kenji Niinomi, Rieko Akimoto, Takao Egami, Karthik Srinivasan, Ying-Shiun Li, Norman Chang

    Jun. 2019, Proceedings of the IEICE EMC Sapporo 2019/IEEE APEMC 2019, English

    [Refereed]

  • Interference of Undesired Radio Waves Near Inverter Power Devices on Mobile Communications

    Koh Watanabe, Yoshifumi Sugimoto, Noriyuki Miura, Makoto Nagata, Satoshi Tanaka, Yasunori Miyazawa, Masahiro Yamaguchi

    Jun. 2019, Proceedings of the IEICE EMC Sapporo 2019/IEEE APEMC 2019, English

    [Refereed]

  • Suppression of Unnecessary Radio Wave Radiated from Power Electronics Equipment Using Noise Suppression Sheet

    Masaki Kurimoto, Koichi Kondo, Yusuke Ohdaira, Yasunori Miyazawa, Satoshi Tanaka, Makoto Nagata, Yasuyuki Okiyoneda, Masahiro Yamaguchi, Shigeyoshi Yoshida

    Jun. 2019, Proceedings of the IEICE EMC Sapporo 2019/IEEE APEMC 2019, English

    [Refereed]

  • Magnetic Powder Composite Noise Suppressor for Flip Chip Mounted High Speed IC Chip

    Masahiro Yamaguchi, Mitsuharu Sato, Akihiko Takahashi, Yasunori Miyazawa, Satoshi Tanaka, Kosuke Jike, Koh Watanabe, Noriyuki Miura, Makoto Nagata

    Jun. 2019, Proceedings of the IEICE EMC Sapporo 2019/IEEE APEMC 2019, English

    [Refereed]

  • Collision-Based EM Analysis on ECDSA Hardware and a Countermeasure

    Kosuke Koiwa, Rei Ueno, Daisuke Fujimoto, Yuichi Hayashi, Makoto Nagata, Makoto Ikeda, Tsutomu Matsumoto, Naofumi Homma

    Jun. 2019, Proceedings of the IEICE EMC Sapporo 2019/IEEE APEMC 2019, English

    [Refereed]

  • A Full System Simulation Technique of Power-noise Side Channel Leakage in Cryptographic Integrated Circuits

    Akihiro Tsukioka, Makoto Nagata, Karthik Srinivasan, Shan Wan, Lang Lin, Ying-Shiun Li, Norman Chang

    Jun. 2019, ACM/IEEE Design Automation Conference (DAC 2019), English

    [Refereed]

  • Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology

    Jean-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, Kazuo Sakiyama, Noriyuki Miura, Makoto Nagata, Sylvain Guilley

    May 2019, DSD 2018, 5 - 5, English

    [Invited]

  • Side-channel leakage from sensor-based countermeasures against fault injection attack

    Takeshi Sugawara, Natsu Shoji, Kazuo Sakiyama, Kohei Matsuda, Noriyuki Miura, Makoto Nagata

    May 2019, Elsevier Microelectronics Journal,, 90, 63 - 71, English

    [Refereed]

  • On-Chip Physical Attack Protection Circuits for Hardware Security

    Makoto Nagata, Takuji Miki, Noriyuki Miura

    Apr. 2019, Proceedins of the IEEE Custom Integrated Circuits Conference (CICC 2019),, 1 - 6, English

    [Refereed][Invited]

  • 無線カオス発振型チップ・パッケージ・ボード相互作用PUFの統合回路設計手法とその評価

    TAKAHASHI Masanori, NAGATA Makoto, MIURA Noriyuki

    Mar. 2019, 電子情報通信学会技術報告, 118 (458), 223 - 224, Japanese

    Symposium

  • 楕円曲線デジタル署名アルゴリズムのASICチップ実装と評価

    SATOH Sousuke, YOSHIDA Hiroki, MONTA Kazuki, OKIDONO Takaaki, MIKI Takuji, MIURA Noriyuki, NAGATA Makoto

    Mar. 2019, 電子情報通信学会技術報告, 118 (458), 267 - 269, Japanese

    Symposium

  • センサーMCUのAD変換器を悪用したアナログ情報漏洩・改竄攻撃

    MIZUTA Kento, MIKI Takuji, MIURA Noriyuki, NAGATA Makoto

    Mar. 2019, 2019年電子情報通信学会総合大会, Japanese

    Symposium

  • オンチップ電源回路によるサイドチャネル漏洩抑制効果の解析

    MIKI Takuji, MIURA Noriyuki, NAGATA Makoto

    Mar. 2019, 2019年電子情報通信学会総合大会, Japanese

    Symposium

  • オンチップLC発振器の電磁ノイズ注入同期現象の測定とその応用

    Cheng Yue, WATANABE Koh, MIURA Noriyuki, NAGATA Makoto

    Mar. 2019, 電子情報通信学会技術報告, 118 (507), 93 - 95, Japanese

    Symposium

  • インバータ電源装置近傍における不要電波と移動通信への干渉評価

    SUGIMOTO Yasufumi, WATANABE Koh, MIURA Noriyuki, NAGATA Makoto, MIYAZAWA Yasunori, TANAKA Satoshi, YAMAGUCHI Masahiro

    Mar. 2019, 2019年電子情報通信学会総合大会, Japanese

    Symposium

  • インバータ電源装置における不要電波の高感度測定と無線通信への干渉の評価

    SUGIMOTO Yasufumi, WATANABE Koh, MIURA Noriyuki, NAGATA Makoto, MIYAZAWA Yasunori, TANAKA Satoshi, YAMAGUCHI Masahiro

    Mar. 2019, 電子情報通信学会技術報告, 118 (507), 23 - 25, Japanese

    Symposium

  • PRINCEファミリ暗号プロセッサの超軽量実装

    MATSUDA Kohei, NAGATA Makoto, MIURA Noriyuki

    Mar. 2019, 電子情報通信学会技術報告, 118 (458), 261 - 265, Japanese

    Symposium

  • A Thick Cu Layer Buried in Si Interposer Backside for Global Power Routing,

    ARAGA Yuuki, NAGATA Makoto, IKEDA Hiroaki, MIKI Takuji, MIURA Noriyuki, WATANABE Naoya, SHIMAMOTO Haruo, KIKUCHI Katsuya

    Mar. 2019, IEEE Transactions on Components, Packaging and Manufacturing Technology, 9 (3), 502 - 510, English

    [Refereed]

    Scientific journal

  • A Random Interrupt Dithering SAR Technique for Secure ADC Against Reference-Charge Side-Channel Attack,

    MIKI Takuji, MIURA Noriyuki, SONODA Hiroki, MIZUTA Kento, NAGATA Makoto

    Feb. 2019, IEEE Transactions on Circuits and Systems II: Express Briefs,, English

    [Refereed]

    Scientific journal

  • 低遅延暗号における中間ラウンドからのサイドチャネル漏えいとそのRSMに基づく効率的な対策

    Ville Yli-Mayry, UENO Rei, HONMA Naofumi, AOKI Takafumi, MIURA Noriyuki, MATSUDA Kohei, NAGATA Makoto, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger

    Jan. 2019, 2019年暗号と情報セキュリティシンポジウム(SCIS2019), Japanese

    Symposium

  • ミリ波レーダの環境擾乱応答評価システムの軽量実装と精度解析

    MACHIDA Tatsuya, MATSUDA Kohei, MIURA Noriyuki, NASHIMOTO Shoei, SUZUKI Daisuke, NAGATA Makoto

    Jan. 2019, 2019年暗号と情報セキュリティシンポジウム(SCIS2019), Japanese

    Symposium

  • デジタルICチップの電源ノイズ特性におけるパッケージング実装形態依存性の解析

    TSUKIOKA Akihiro, JIKE Kosuke, WATANABE Koh, MIURA Noriyuki, NAGATA Makoto

    Dec. 2018, 電子情報通信学会技術報告, 37 - 42, Japanese

    Symposium

  • Electromagnetic Radiation by IC Chip and Evaluation of Mobile Communication Interference

    SUGIMOTO Yoshifumi, WATANABE Koh, NAGATA Makoto, MIURA Noriyuki, MIYAZAWA Yasunori, TANAKA Satoshi, YAMAGUCHI Masahiro

    Nov. 2018, IEICE Techinical Report EMCJ2018, 31 - 33, English

    Symposium

  • 暗号モジュールにおける電源ノイズとサイドチャネル漏洩の対策(Ⅰ)

    MONTA Kazuki, SATOH Sousuke, TSUKIOKA Akihiro, OKIDONO Takaaki, MIKI Takuji, MIURA Noriyuki, NAGATA Makoto

    Oct. 2018, 電子情報通信学会学術報告, 7 - 11, Japanese

    Symposium

  • 無線結合とカオス発振を利用したチップ・パッケージ・ボード相互作用PUFの実験と評価

    TAKAHASHI Masanori, MATSUDA Kohei, NAGATA Makoto, MIURA Noriyuki

    Sep. 2018, 電子情報通信学会ソサイエティ大会, 183, Japanese

    Symposium

  • ノイズ抑制シートによるインバータ機器の不要電波抑制効果

    KURIMOTO Masaki, KONDO Koichi, OHIRA Yusuke, MIYAZAWA Yasunori, TANAKA Satoshi, YOSHIDA Eikichi, NAGATA Makoto, OKIYONEDA Yasuyuki, YAMAGUCHI Masahiro

    Sep. 2018, 電子情報通信学会ソサイエティ大会, 225, Japanese

    Symposium

  • SOI-BCDプロセスにおける支持基板伝播ノイズ解析技術の検討

    OYAMA Ko, KONDO Yosuke, IKOMA Daisaku, ISHIKAWA Yasuyuki, MURATA Akitaka, AGATSUMA Shuji, NAGATA Makoto

    Sep. 2018, 電気学会電子回路研究会, Japanese

    Symposium

  • ICチップによる電磁輻射のパッケージング依存性

    WATANABE Koh, SUGIMOTO Yoshifumi, JIKE Kosuke, MIURA Noriyuki, NAGATA Makoto, MIYAZAWA Yasunori, TANAKA Satoshi, YAMAGUCHI Masahiro

    Sep. 2018, 電子情報通信学会ソサイエティ大会, 220, Japanese

    Symposium

  • ICチップによる電磁輻射と移動通信干渉の評価

    SUGIMOTO Yoshifumi, WATANABE Koh, MIURA Noriyuki, NAGATA Makoto, MIYAZAWA Yasunori, TANAKA Satoshi, YAMAGUCHI Masahiro

    Sep. 2018, 電子情報通信学会ソサイエティ大会, 221, Japanese

    Symposium

  • A 286 F2/Cell Distributed Bulk-Current Sensor and Secure Flush Code Eraser Against Laser Fault Injection Attack on Cryptographic Processor,

    MATSUDA Kohei, FUJII Tatsuya, SHOJI Natsu, SUGAWARA Takeshi, SAKIYAMA Kazuo, HAYASHI Yu-ichi, NAGATA Makoto, MIURA Noriyuki

    Sep. 2018, IEEE Journal of Solid-State Circuits, 53 (11), 3174 - 3182, English

    [Refereed]

    Scientific journal

  • レーザー故障注入攻撃対策を備えた暗号ICの設計手法

    MATSUDA Kohei, FUJII Tatsuya, SHOJI Natsu, SUGAWARA Takeshi, SAKIYAMA Kazuo, HAYASHI Yu-ichi, NAGATA Makoto, MIURA Noriyuki

    Aug. 2018, DAシンポジウム2018論文集, 220 - 225, Japanese

    Symposium

  • デジタルICチップにおける電源ノイズの評価及び解析

    JIKE Kosuke, TSUKIOKA Akihiro, SAWADA Ryohei, WATANABE Koh, MIURA Noriyuki, NAGATA Makoto

    Aug. 2018, 電子情報通信学会学術報告, 77 - 82, Japanese

    Symposium

  • Suppression of Unnecessary Radio Wave Radiated from Inverter Equipment using Noise Suppression Sheet,

    KONDO Koichi, KURIMOTO Masaki, OHDAIRA Yusuke, MIYAZAWA Yasunori, TANAKA Satoshi, NAGATA Makoto, OKIYONEDA Yasuyuki, YAMAGUCHI Masahiro

    Aug. 2018, 2018 IEEE Symposium on Electromagetic Compatibility, Signal and Power Integrity (EMC+SIPI 2018), 1, English

    [Refereed]

    International conference proceedings

  • Measurement and Magnetic Countermeasure Methodology to Deal with Inverter Noise,

    YAMAGUCHI Masahiro, MIYAZAWA Yasunori, Jinyang Ma, SATO Mitsuharu, TAKAHASHI Akihiro, TANAKA Satoshi, NAGATA Makoto, Ranajit Sai

    Aug. 2018, Proceedings of the 2018 International Symposium on Electromagnetic Compatibility (EMC Europe 2018), 608 - 612, English

    [Refereed]

    International conference proceedings

  • Interaction of RF DPI with ESD protection Devices in EMS Testing of IC Chips,

    TSUKIOKA Akihiro, NAGATA Makoto, FUJIMOTO Daisuke, MIURA Noriyuki, AKIMOTO Rieko, EGAMI Takao, NIINOMI Kenji, YUHARA Takeshi, HAYASHI Sachio, Karthik Srinivasan, Ying-Shiun Li, Norman Chang

    Aug. 2018, International Symposium on Electromagnetic Compatibility (EMC Europe 2018), 445 - 450, English

    [Refereed]

    International conference proceedings

  • Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology,

    Jean-Luc Danger, YASHIRO Risa, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, SAKIYAMA Kazuo, MIURA Noriyuki, NAGATA Makoto, Sylvain Guilley

    Aug. 2018, Proceedings of the 21th Euromicro Conference on Digital System Design (DSD 2018), 508 - 515, English

    [Refereed]

    International conference proceedings

  • Chip-Package-Board Interactive PUF Utilizing Coupled Chaos Oscillators with Inductor,

    MIURA Noriyuki, TAKAHASHI Masanori, NAGATOMO Kazuki, NAGATA Makoto

    Jul. 2018, IEEE Journal of Solid-State Circuits, 53 (10), 2889 - 2897, English

    [Refereed]

    Scientific journal

  • A Study on Substrate Noise Coupling among TSVs in 3D Chip Stack

    ARAGA Yuuki, NAGATA Makoto, Joeri De Vos, Geert Van der Plas, Eric Beyne

    Jul. 2018, IEICE Electronics Express, 15 (13), 1 - 8, English

    [Refereed]

    Scientific journal

  • A Demonstration of a HT-Detection Method Based on Impedance Measurements of the Wiring Around ICs,

    FUJIMOTO Daisuke, NIN Shota, HAYASHI Yu-ichi, MIURA Noriyuki, NAGATA Makoto, MATSUMOTO Tsutomu

    Jul. 2018, IEEE Transactions on Circuits and Systems II: Express Briefs, 65 (10), 1320 - 1324, English

    [Refereed]

    Scientific journal

  • Extended CPS Simulation for EMC Compliance of Automotive IC Chip Developments,

    TSUKIOKA Akihiro, NAGATA Makoto, EGAMI Takao, AKIMOTO Rieko, NIINOMI Kenji, YUHRA Takeshi, HAYASHI Sachio, Karthik Srinivasan, Ying-Shiun Li, Norman Chang

    Jun. 2018, ACM/IEEE Design Automation Conference (DAC 2018), English

    [Refereed]

    International conference proceedings

  • HT-Detection Method Based on Impedance Measurements of ICs,

    NIN Shota, FUJIMOTO Daisuke, HAYASHI Yuichi, MIURA Noriyuki, NAGATA Makoto, MATSUMOTO Tsutomu

    May 2018, Proceedings of 2018 IEEE International Symposium on Electromagnetic Compatibility and IEEE Asia-Pacific Symposium on Electromagnetic Compatibility (EMC/APEMC), 11, English

    [Refereed]

    International conference proceedings

  • EM Security Analysis of Compact ECDSA Hardware,

    KOIWA Kosuke, FUJIMOTO Daisuke, HAYASHI Yuichi, NAGATA Makoto, IKEDA Makoto, MATSUMOTO Tsutomu, HONMA Naofumi

    May 2018, Proceedings of 2018 IEEE International Symposium on Electromagnetic Compatibility and IEEE Asia-Pacific Symposium on Electromagnetic Compatibility (EMC/APEMC), 12, English

    [Refereed]

    International conference proceedings

  • 基板電流センサと電源瞬断回路を利用した小面積レーザーフォールト注入攻撃対策

    MATSUDA Kohei, FUJII Tatsuya, SHOJI Natsu, SUGAWARA Takeshi, SAKIYAMA Kazuo, HAYASHI Yu-ichi, NAGATA Makoto, MIURA Noriyuki

    Apr. 2018, 電子情報通信学会学術報告, 41 - 44, Japanese

    Symposium

  • Physical-Cyber境界におけるアナログ計測セキュリティ技術

    MIKI Takuji, MIZUTA Kento, MIURA Noriyuki, NAGATA Makoto

    Apr. 2018, 電子情報通信学会学術報告, 45 - 48, Japanese

    Symposium

  • (招待論文)不要電波の広帯域化に対応した電波環境計測技術と改善技術

    YAMAGUCHI Masahiro, TANAKA Satoshi, YOSHIDA Eikichi, ISHIYAMA Kazushi, NAGATA Makoto, KONDO KOICHI, OKIYONEDA Yasuyuki, SATOH Mitsuharu, MIYAZAWA Yasunori, HATAKEYAMA Kensuke

    Mar. 2018, 電子情報通信学会論文誌B分冊, J101–B (3), 204–211, Japanese

    [Refereed]

    Scientific journal

  • 逐次比較型AD変換器に対するサイドチャネル攻撃とその対策

    MIKI Takuji, MIURA Noriyuki, NAGATA Makoto

    Mar. 2018, 電子情報通信学会総合大会, S - 22, Japanese

    Symposium

  • 楕円曲線署名の小規模実装に対する耐タンパー性評価

    KOIWA Kosuke, FUJIMOTO Daisuke, HAYASHI Yuichi, NAGATA Makoto, IKEDA Makoto, MATSUMOTO Tsutomu, HOMMA Naofumi

    Mar. 2018, 電子情報通信学会総合大会, S - 21, Japanese

    Symposium

  • Supply-Chain Security Enhancement by Chaotic Wireless Chip-Package-Board Interactive PUF,

    TAKAHASHI Masanori, NAGATA Makoto, MIURA Noriyuki

    Mar. 2018, 2018 IEEE 68th Electronic Components and Technology Conference(ECTC 2018), 521 - 526, English

    [Refereed]

    International conference proceedings

  • 3kW級WPT用GaNインバータ電源装置による不要電波の無線通信品質への影響評価

    MIYAZAWA Yasunori, TANAKA Satoshi, YAMAGUCHI Masahiro, SUGIMOTO Yasufumi, WATANABE Koh, NAGATA Makoto, OKIYONEDA Yasuyuki, MOCHIZUKI Masashi, WATANABE Hiroshi, YAMAMOTO Kitao

    Mar. 2018, 電子情報通信学会総合大会, 287, Japanese

    Symposium

  • Measurement and Analysis of Power Noise Characteristics for EMI Awareness of Power Delivery Networks in 3-D Through-Silicon Via Integration,

    ARAGA Yuuki, NAGATA Makoto, MIURA Noriyuki, IKEDA Hiroaki, KIKUCHI Katsuya

    Feb. 2018, Measurement and Analysis of Power Noise Characteristics for EMI Awareness of Power Delivery Networks in 3-D Through-Silicon Via Integration,, 8 (2), 277 - 285, English

    [Refereed]

    Scientific journal

  • A 286F²/Cell Distributed Bulk-Current Sensor and Secure Flush Code Eraser Against Laser Fault Injection Attack

    MATSUDA Kohei, FUJII Tatsuya, SHOJI Natsu, SUGAWARA Takeshi, SAKIYAMA Kazuo, HAYASHI Yuichi, NAGATA Makoto, MIURA Noriyuki

    Feb. 2018, Dig. Tech. Papers, 2018 IEEE International Solid-State Circuits Conference (ISSCC), 352 - 353, English

    [Refereed]

    International conference proceedings

  • 電荷再配分型SAR-ADCの変換基準電圧入力を悪用した情報改竄攻撃

    MIZUTA Kento, MIKI Takuji, MIURA Noriyuki, NAGATA Makoto

    Jan. 2018, 2018年暗号と情報セキュリティシンポジウム(SCIS2018), 1D1 - 4, Japanese

    Symposium

  • ミリ波レーダの環境擾乱応答の評価システムの構築

    MACHIDA Tatsuya, MATSUDA Kohei, MIURA Noriyuki, NAGATA Makoto, NASHIMOTO Shoei, SUZUKI Daisuke

    Jan. 2018, 2018年暗号と情報セキュリティシンポジウム(SCIS2018), 2D3 - 4, Japanese

    Symposium

  • フォルト検出センサを悪用した非侵襲プロービング攻撃

    SUGAWARA Takeshi, SHOJI Natsu, SAKIYAMA Kazuo, MATSUDA Kohei, MIURA Noriyuki, NAGATA Makoto

    Jan. 2018, 2018年暗号と情報セキュリティシンポジウム(SCIS2018), 3D3 - 6, Japanese

    Symposium

  • ハードウェアトロ―ジャン検出に向けたIC周辺配線のインピーダンス計測手法

    FUJIMOTO Daisuke, NIN Shota, HAYASHI Yuichi, MIURA Noriyuki, NAGATA Makoto, MATSUMOTO Tsutomu

    Jan. 2018, 2018年暗号と情報セキュリティシンポジウム(SCIS2018), 3D2 - 2, Japanese

    Symposium

  • FMCWレーダにおけるチャープ信号のランダム化

    SUZUKI Daisuke, NASHIMOTO Shoei, NAGATSUKA Tomoyuki, MACHIDA Tatsuya, MIURA Noriyuki, NAGATA Makoto

    Jan. 2018, 2018年暗号と情報セキュリティシンポジウム(SCIS2018), 2D3 - 5, Japanese

    Symposium

  • カオス発振を利用したチップ・パッケージ・ボードインタラクティブPUF

    TAKAHASHI Masanori, MATSUDA Kohei, NAGATA Makoto, MIURA Noriyuki

    Dec. 2017, 電子情報通信学会技術報告, 1 - 2, Japanese

    Symposium

  • 車載ICチップにおけるEMS特性の高精度モデリングおよびシミュレーション手法

    TSUKIOKA Akihiro, NAGATA Makoto, TANIGUCHI Kohki, FUJIMOTO Daisuke, AKIMOTO Rieko, EGAMI Takao, NIINOMI Kenji, YUHARA Takeshi, HAYASHI Sachio, Rob Mathews, Karthik Srinivasan, Ying-Shiun Li, Norman Chang

    Nov. 2017, 電子情報通信学会技術報告, 27 - 32, Chinese

    Symposium

  • Laser fault injection attack countermeasure by abnormal substrate potential bounce monitoring

    MATSUDA Kohei, MIURA Noriyuki, NAGATA Makoto

    Nov. 2017, The 16th International Conference on Computers, Communications, and Systems (ICCCS 2017), 34 - 35, English

    Symposium

  • Chaos, Deterministic Non-Periodic Flow, for Chip-Package-Board Interactive PUF

    MIURA Noriyuki, TAKAHASHI Masanori, NAGATOMO Kazuki, NAGATA Makoto

    Nov. 2017, Proc. 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC 2017), 25 - 28, English

    [Refereed]

    International conference proceedings

  • ディジタル回路における不要電波:移動通信に影響する高次高調波の評価

    SUGIMOTO Yasufumi, WATANABE Koh, MIURA Noriyuki, NAGATA Makoto, MIYAZAWA Yasunori, TANAKA Satoshi, YAMAGUCHI Masahiro

    Oct. 2017, 電子情報通信学会技術報告, 95 - 98, Japanese

    Symposium

  • ディジタル回路の高次高調波ノイズによる移動通信への影響の評価

    SUGIMOTO Yasufumi, WATANABE Koh, MIURA Noriyuki, NAGATA Makoto, MIYAZAWA Yasunori, TANAKA Satoshi, YAMAGUCHI Masahiro

    Sep. 2017, 電子情報通信学会ソサイエティ大会, 207, Japanese

    Symposium

  • インバータ機器から放射される不要電波強度の電界強度換算

    MIYAZAWA Yasunori, TANAKA Satoshi, SUGIMOTO Yasufumi, WATANABE Koh, NAGATA Makoto, YAMAGUCHI Masahiro

    Sep. 2017, 電子情報通信学会ソサイエティ大会, 246, Japanese

    Symposium

  • Simulation Techniques for EMC Compliant Design of Automotive IC Chips and Modules

    OYAMA Ko, KONDO Yosuke, IKOMA Daisaku, ISHIKAWA Yasuyuki, MURATA Akitaka, AGATSUMA Shuji, NAGATA Makoto

    Sep. 2017, Proceedings of the 2017 International Symposium on Electromagnetic Compatibility (EMC Europe 2017), 1 - 5, English

    [Refereed]

    International conference proceedings

  • Exploiting Bitflip Detector for Non-Invasive Probing and its Application to Ineffective Fault Analysis

    SUGAWARA Takeshi, SHOJI Natsu, SAKIYAMA Kazuo, MATSUDA Kohei, MIURA Noriyuki, NAGATA Makoto

    Sep. 2017, Proceedings of the IEEE 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC 2017), 49 - 56, English

    [Refereed]

    International conference proceedings

  • Effect of Field Area on Disturbance Propagation through Silicon Substrates in SOI-BCD Process

    TSUKIOKA Akihiro, NAGATA Makoto, TANIGUCHI Kohki, FUJIMOTO Daisuke, AKIMOTO Rieko, EGAMI Takao, NIINOMI Kenji, YUHARA Takeshi, HAYASHI Sachio, Rob Mathews, Karthik Srinivasan, Ying-Shiun Li, Norman Chang

    Sep. 2017, Proceedings of the 2017 International Symposium on Electromagnetic Compatibility (EMC Europe 2017), 1 - 5, English

    [Refereed]

    International conference proceedings

  • ICチップのEMC性能改善に向けた電源ノイズシミュレーション手法

    TSUKIOKA Akihiro, NAKASHIMA Hiroki, MIURA Noriyuki, NAGATA Makoto

    Aug. 2017, 電気学会電子回路研究会, 1 - 5, Japanese

    Symposium

  • Enhancing Reactive Countermeasure against EM Attacks with Low Overhead

    ISHIHATA Daisuke, HOMMA, HAYASHI Yuichi, MIURA Noriyuki, FUJIMOTO Daisuke, NAGATA Makoto, AOKI Takafumi

    Aug. 2017, Proceedings of the 2017 IEEE International Symposium on Electromagnetic Compatibility, Signal and Power Integrity, 399 - 404, English

    [Refereed]

    International conference proceedings

  • Analysis of Unnecessary Radio Wave Near the Inverter Equipment at the Carrier Frequency-Range of Mobile Terminal

    MIYAZAWA Yasunori, TANAKA Satoshi, NISHIZAWA Masahiro, Jingyan Ma, YAMAGUCHI Masahiro, KONDO Koichi, NAGATA Makoto, OKIYONEDA Yasuyuki

    Aug. 2017, Proceedings of the 2017 IEEE International Symposium on Electromagnetic Compatibility, Signal and Power Integrity, Poster, 283 - 287, English

    [Refereed]

    International conference proceedings

  • Susceptibility Evaluation of CAN Transceiver Circuits with In-Place Waveform Capturing under RF DPI

    TANIGUCHI Kohki, NAGATA Makoto, TSUKIOKA Akihiro, FUJIMOTO Daisuke, MIURA Noriyuki, EGAMI Takao, AKIMOTO Rieko, NIINOMI Kenji, KOMATSU Terumitsu, FUKUBA Yoshinori, TOMISHIMA Atsushi Tomishima

    Jul. 2017, in Proceedings of the 11th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo 2017), 59 - 63, English

    [Refereed]

    International conference proceedings

  • Analysis of Patterned Magnetic Thin-film Noise Suppressor for RF IC Chip

    YAMAGUCHI Masahiro, ENDO Yasushi, Peng Fan, Jingyan Ma, TANAKA Satoshi, MIYAZAWA Yasunori, NAGATA Makoto

    Jul. 2017, in Proceedings of the 11th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo 2017), 45 - 49, English

    [Refereed]

    International conference proceedings

  • Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata

    In this paper, a 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter (VTC) in 28 nm CMOS is presented. A two-step transition inverter raises the Voltage-to-Time (VT) conversion gain to 100 ps/V which is >10x higher than a conventional current-starved inverter. The number of required inverter stages is reduced to 4 from 64, resulting in 1/8 conversion latency and thus 13.2 dB THD suppression at a 500 MHz full Nyquist frequency. A feedback control of the bias voltage in the two-step transition inverter suppresses PVT variations in the VT conversion gain. A test-chip measurement successfully demonstrates -52.5 dB THD at 500 MHz input frequency without sampling-and-hold circuits. Effective VT conversion range over +/-64 ps time difference is measured with 1.2 Vpp differential input while keeping high linearity of less than +/-0.53 LSB INL/DNL, which results in 1 ps/LSB conversion linearity. The proposed VTC occupies 84 um(2) silicon area and consumes 0.18 mW at 1 GS/s.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jun. 2017, IEICE TRANSACTIONS ON ELECTRONICS, E100C (6), 560 - 567, English

    [Refereed]

    Scientific journal

  • A 2.5ns-Latency 0.39pJ/b 289µm²/Gb/s Ultra-Light-Weight PRINCE Cryptographic Processor

    MIURA Noriyuki, MATSUDA Kohei, NAGATA Makoto, Shivam Bhasin, Ville Yli-Mayry, HOMMA Naofumi Homma, Yves Mathieu, Tarik Graba, Jean-Luc Danger

    Jun. 2017, 2017 Symposium on VLSI Circuits, Dig. of Tech. Papers, 20.2, 266 - 267, English

    [Refereed]

    International conference proceedings

  • (招待講演)ナノドット型恒久メモリーの研究

    WATANABE Tsuyoshi, MIURA Noriyuki, RYU Shika, IMAI Shigeki, NAGATA Makoto

    Apr. 2017, 電子情報通信学会技術報告 ICD2017, 17 - 22, Japanese

    Symposium

  • Superior decoupling capacitor for three-dimensional LSI with ultrawide communication bus,

    ARAGA Yuuki, NAGATA Makoto, MIURA Noriyuki, IKEDA Hiroaki, KIKUCHI Katsuya

    Apr. 2017, Japanese Journal of Applied Physics, Vol. 56, No. 4S, 56 (4S), 04CC05 - 1-04EE06-6, English

    [Refereed]

    Scientific journal

  • 複合磁性ペーストを用いたノイズ抑制体の実装方法

    TAKAHASHI Akihiro, YAMAGUCHI Masahiro, NAGATA Makoto, Ranajit Sai, SATOH Mitsuharu

    Mar. 2017, 電子情報通信学会総合大会, Japanese

    Symposium

  • 近接電磁波解析攻撃センサの高感度化手法の提案とその評価

    TANAKA Renta, MIURA Noriyuki, NAGATA Makoto

    Mar. 2017, 電子情報通信学会総合大会, Japanese

    Symposium

  • 基板電流検知回路を用いたレーザーフォールト注入攻撃対策のオーバヘッド推定

    MATSUDA Kohei, MIURA Noriyuki, NAGATA Makoto, HAYASHI Yuichi, FUJII Tatsuya, SAKIYAMA Kazuo

    Mar. 2017, 電子情報通信学会総合大会, Japanese

    Symposium

  • 暗号モジュール搭載VLSIチップの電源ノイズシミュレーション

    YAMAMOTO Naoya, TSUKIOKA Akihiro, KORENAGA Rie, MIURA Noriyuki, NAGATA Makoto

    Mar. 2017, 電子情報通信学会総合大会, Japanese

    Symposium

  • ディジタル回路における不要電波:高次高調波の評価

    KONISHI Shuto, SUGIMOTO Yoshifumi, MIURA Noriyuki, NAGATA Makoto, MIYAZAWA Yasunori, TANAKA Satoshi, YAMAGUCHI Masahiro

    Mar. 2017, 電子情報通信学会総合大会, Japanese

    Symposium

  • VLSIシステムのノイズ問題克服に向けた研究の取組み―エレクトロニクスソサイエティ賞の受賞によせて―,"

    NAGATA Makoto

    電子情報通信学会, Feb. 2017, 電子情報通信学会論文誌C分冊, J100-C (2), 1 - 13, Japanese

    [Refereed]

    Scientific journal

  • Protecting cryptographic integrated circuits with side-channel information,"

    NAGATA Makoto, FUJIMOTO Daisuke, MIURA Noriyuki, HOMMA Naofumi, HAYASHI Yuichi, SAKIYAMA Kazuo

    IEICE, Feb. 2017, IEICE Electronics Express(ELEX), 14 (2), 1 - 13, English

    [Refereed]

    Scientific journal

  • A Permanent Digital Archive System Based on 4F(2) X-Point Multi-Layer Metal Nano-Dot Structure

    Noriyuki Miura, Shijia Liu, Tsuyoshi Watanabe, Shigeki Imai, Makoto Nagata

    IEEE, 2017, 2017 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 270 - 270, English

    [Refereed]

    International conference proceedings

  • 近接電磁波解析攻撃に対する高感度プローブセンサの設計と検出性能の解析

    TANAKA Renta, MIURA Noriyuki, NAGATA Makoto

    Jan. 2017, 2017年暗号と情報セキュリティシンポジウム(SCIS2017), Japanese

    Symposium

  • ミリ波レーダの環境擾乱応答の評価及び解析

    MACHIDA Tatsuya, MIURA Noriyuki, NAGATA Makoto, SUGAWARA TAKESHI, NASHIMOTO Shoei, SUZUKI Daisuke

    Jan. 2017, 2017年暗号と情報セキュリティシンポジウム(SCIS2017), Japanese

    Symposium

  • ミリ波レーダのチャープ信号のランダム化

    SUGAWARA Takeshi, NASHIMOTO Shoei, SUZUKI Daisuke, MACHIDA Tatsuya, MIURA Noriyuki, NAGATA Makoto

    Jan. 2017, 2017年暗号と情報セキュリティシンポジウム(SCIS2017), Japanese

    Symposium

  • インバータ機器の近傍における携帯電話帯域の不要電波の測定

    MIYAZAWA Yasunori, TANAKA Satoshi, MA Jingyan, YAMGUCHI Masahiro, NAGATA Makoto, KONDO Koichi, OKIYONEDA Yasuyuki, NISHZAWA Msahiro

    Jan. 2017, 電子情報通信学会技術報告, Japanese

    Symposium

  • An FPGA-Compatible PLL-Based Sensor against Fault Injection Attack

    Wei He, Jakub Breier, Shivam Bhasin, Noriyuki Miura, Makoto Nagata

    Laser based Fault Injection (LFI) and Electromagnetic Fault Injection (EMFI) are powerful techniques commonly for fault injection against security critical circuits. Since LFI/EMFI creates faults by incurring high energy disturbances, they can be detected in advance by sensing the disturbance using a embedded detector. In this paper, a PLL based sensor system for detecting laser fault injection is presented. Experiments show a high detection rate, with significant power security margin, whilst maintaining low hardware cost, on multiple FPGA platforms.

    IEEE, 2017, 2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 39 - 40, English

    [Refereed]

    International conference proceedings

  • Cu-Sn based joint material having IMC forming control capabilities

    Hiroaki Ikeda, Shigenobu Sekine, Ryuji Kimura, Koichi Shimokawa, Keiji Okada, Hiroaki Shindo, Tatsuya Ooi, Rei Tamaki, Makoto Nagata

    This paper describes development of joint materials using only base metals (Cu and Sn) for power semiconductor assembly. The optimum composition at this moment is Cu8wt% Sn92wt% (8Cu92Sn hereafter) particles: pure Cu (100Cu hereafter) particles = 20: 80 (wt% ratio), which indicates good stability under Thermal Cycling Test (TCT, -55 degrees C similar to+200 degrees C, 20cycles). The composition indicated to be effective to eliminate voids and chip cracks. As an initial choice of joint material using TLPS (Transient Liquid Phase Sintering), we considered SAC305 might have good role as TLPS trigger. But, actual TCT results indicated that existence of Ag must have negative effect to eliminate voids from the joint region. Tentative behavior model using 8Cu92Sn and 100Cu joint material is proposed. Optimized composition indicated shear force 40MPa at 300 degrees C. Re-melting point of the composition is 409 degrees C after TLPS when there is additional Cu supply from substrate and terminal of mounted die.

    IEEE, 2017, 2017 INTERNATIONAL CONFERENCE ON ELECTRONICS PACKAGING (ICEP), TC4-2, 171 - 176, English

    [Refereed]

    International conference proceedings

  • On-chip substrate-bounce monitoring for laser-fault countermeasure

    MATSUDA Kohei, MIURA Noriyuki, NAGATA Makoto, HAYASHI Yuichi, FUJII Tatsuya, SAKIYAMA Kazuo

    IEEE, Dec. 2016, 2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), 1 - 6, English

    [Refereed]

    International conference proceedings

  • TSVを用いた三次元実装LSIの電源配線におけるEMI特性

    ARAGA Yuuki, NAGATA Makoto, MIURA Noriyuki, IKEDA Hiroaki, KIKUCHI Katsuya

    Nov. 2016, 電子情報通信学会技術報告, Japanese

    Symposium

  • Hardware Security of Semiconductor IC Chips

    NAGATA Makoto

    Oct. 2016, Proc. IEEE Intl. SoC Design Conference (ISOCC 2016), English

    Symposium

  • 基板電位変動モニタリングによるレーザーフォールト注入攻撃対策

    MATSUDA Kohei, MIURA Noriyuki, NAGATA Makoto, HAYASHI Yuichi, FUJII Tatsuya, SAKIYAMA Kazuo

    Sep. 2016, 電子情報通信学会ソサイエティ大会, Japanese

    Symposium

  • パターン化した磁性薄膜による集積化デジタルノイズ抑制体

    YAMAGUCHI Masahiro, ENDO Yasushi, Pen Fan, MA Jingyan, TANAKA Satoshi, NAGATA Makoto

    Sep. 2016, 日本磁気学会学術講演会, Japanese

    Symposium

  • インバータ機器の不要電磁波と無線通信

    YAMAGUCHI Masahiro, TANAKA Satoshi, MA Jingyan, MIYAZAWA Yasunori, NAGATA Makoto, KONDO Koichi, OKIYONEDA Yasuyuki, NISHIZAWA Masahiro

    Sep. 2016, 電子情報通信学会ソサイエティ大会, Japanese

    Symposium

  • インバータ機器から発射される携帯電話帯域の不要電波の測定

    MIYAZAWA Yasunori, TANAKA Satoshi, MA Jingyan, YAMAGUCHI Masahiro, NAGATA Makoto, KONDO Koichi, OKIYONEDA Yasuyuki, NISHIZAWA Masahiro

    Sep. 2016, 電子情報通信学会ソサイエティ大会, Japanese

    Symposium

  • Superiority of In-Stack Decoupling Capacitor for 3D-LSI with Wide I/O Data Bus

    ARAGA Yuuki, NAGATA Makoto, MIURA Noriyuki, IKEDA Hiroaki, KIKUCHI Katsuya

    Sep. 2016, Extended Abstracts of the 2016 International Conference on Solid State Devices and Materials (SSDM 2016), 469 - 470, English

    [Refereed]

    International conference proceedings

  • IoT時代に対応する電子回路教育の舵取りとは?

    NAGATA Makoto

    Sep. 2016, 電気学会電子・情報・システム部門大会, Japanese

    Symposium

  • ICチップにおける電源ノイズのオンチップ測定及びオンボード測定

    SAWADA Ryohei, MIURA Noriyuki, NAGATA Makoto

    Sep. 2016, 電子情報通信学会ソサイエティ大会, Japanese

    Symposium

  • FPGA実装した暗号コアからの情報漏洩量と放射電磁ノイズ量の相関評価

    YOSHIDA Hiroki, MIURA Noriyuki, NAGATA Makoto

    Sep. 2016, 電子情報通信学会ソサイエティ大会, Japanese

    Symposium

  • Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata

    In this paper, a 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter (VTC) in 28 nm CMOS is presented. A two-step transition inverter raises the Voltage-to-Time (VT) conversion gain to 100 ps/V which is >10x higher than a conventional current-starved inverter. The number of required inverter stages is reduced to 4 from 64, resulting in 1/8 conversion latency and thus 13.2 dB THD suppression at a 500 MHz full Nyquist frequency. A feedback control of the bias voltage in the two-step transition inverter suppresses PVT variations in the VT conversion gain. A test-chip measurement successfully demonstrates -52.5 dB THD at 500 MHz input frequency without sampling-and-hold circuits. Effective VT conversion range over +/-64 ps time difference is measured with 1.2 Vpp differential input while keeping high linearity of less than +/-0.53 LSB INL/DNL, which results in 1 ps/LSB conversion linearity. The proposed VTC occupies 84 um(2) silicon area and consumes 0.18 mW at 1 GS/s.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jun. 2017, IEICE TRANSACTIONS ON ELECTRONICS, E100C (6), 560 - 567, English

    [Refereed]

    Scientific journal

  • Ring Oscillator Under Laser: Potential of PLL Based Countermeasure Against Laser Fault Injection

    Wei He, Jakub Breier, Shivam Bhasin, MIURA Noriyuki, NAGATA Makoto

    IEEE, Aug. 2016, Proc. IEEE 2016 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC 2016), 102 - 113, English

    [Refereed]

    International conference proceedings

  • On-chip Magnetic Thin-Film Noise Suppressor to Countermeasure Digital Noise from Switching Power Electronic Equipment (invited)

    YAMAGUCHI Masahiro, TANAKA Satoshi, MA Jingyan, MIYAZAWA Yasunori, NAGATA Makoto, KONDO Koichi, OKIYONEDA Yasuyuki, NISHIZAWA Masahiro

    Aug. 2016, International Conference of Asian Union of Magnetics Societies (ICAUMS 2016), English

    Symposium

  • Noriyuki Miura, Zakaria Najm, Wei He, Shivam Bhasin, Xuan Thuy Ngo, Makoto Nagata, Jean-Luc Danger

    \Electromagnetic injection (EMI) is a powerful and precise technique for fault injection in modern ICs. This intentional fault can be utilized to steal secret information hidden inside of ICs. Unlike laser fault injection, tedious package decapsulation is not needed for EMI, which reduces an attacker's cost and thus causes a serious information security threat. In this paper, a PLL-based sensor circuit is proposed to detect EMI reactively on chip. A fully automatic design flow is devised to integrate the proposed sensor together with a cryptographic processor. A high fault detection coverage and a small hardware overhead are demonstrated experimentally on an FPGA platform.

    ASSOC COMPUTING MACHINERY, 2016, 2016 ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 1 - 6, English

    [Refereed]

    International conference proceedings

  • Patterned Magnetic Thin-film Digital Noise Suppressor for Future Telecommunication Systems RF IC

    YAMAGUCHI Masahiro, ENDO Yasushi, Pen Fan, TANAKA Satoshi, NAGATA Makoto

    IEEE, Jun. 2016, IEEE International Conference on Microwave Magnetics (ICMM2016), English

    Symposium

  • Die Attach Material for Power Semiconductor Having Nano-Level Sn-Cu Diffusion Control

    IKEDA Hiroaki, SEKINE Shigenobu, KIMURA Ryuji, SHIMOKAWA Koichi, OKADA Keiji, SHINDO Hiroaki, OOI Tatsuya, TAMAKI Rei, NAGATA Makoto

    IEEE, Jun. 2016, Proc. 2016 IEEE 66th Electronic Components and Technology Conference (ECTC 2016), 426 - 431, English

    [Refereed]

    International conference proceedings

  • Physical Authentication Using Side-Channel Information

    Kazuo Sakiyama, Momoka Kasuya, Takanori Machida, Arisa Matsubara, Yunfeng Kuai, Yu-ichi Hayashi, Takaaki Mizuki, Noriyuki Miura, Makoto Nagata

    Authentication based on cryptographic protocols is a key technology for recent security systems. This paper proposes a new authentication method that utilizes the side channel that already exists in many authentication systems. Side-channel analysis has been studied intensively from the attacker viewpoint and is best known for key-recovery attacks against cryptographic implementations using physical information. In this paper, reversing the traditional thought, we propose to use the key-dependent side-channel information constructively to enhance, or as an alternate to, existing cryptographic protocols. Using Advanced Encryption Standard (AES)-based authentication as an example, we demonstrate, based on experiments using an Field Programmable Gate Array (FPGA), that the side-channel information leaked from cryptographic devices is sufficiently unique for authentication.

    IEEE, 2016, 2016 4TH INTERNATIONAL CONFERENCE ON INFORMATION AND COMMUNICATION TECHNOLOGY (ICOICT), English

    [Refereed]

    International conference proceedings

  • 三次元積層IC における電源供給特性のインスタック診断手法

    MIURA Ranto, ARAGA Yuuki, IKEDA Hiroaki, MIURA Noriyuki, KIKUCHI Katsuya, NAGATA Makoto

    Mar. 2016, 電子情報通信学会技術報告, ICD2015-102, 33 - 36, Japanese

    Symposium

  • ICチップにおけるオンチップノイズと電磁ノイズの観測と評価

    KOUSAKA Jyunpei, KONISHI Shuto, NAGATA Makoto, TANAKA Satoshi, YAMAGUCHI Masahiro

    Mar. 2016, 電気学会電磁環境研究会, EMC-16-014, 25 - 30, Japanese

    Symposium

  • Daisuke Fujimoto, Shivam Bhasin, Makoto Nagata, Jean-Luc Danger

    2016, IACR Cryptology ePrint Archive, 2016, 522

  • 並列化RNSアーキテクチャによる高速ペアリング実装に関する検討

    FUJIMOTO Daisuke, TERUYA Tadanori, SAKIYAMA Kazuo, HOMMA Naofumi, IKEDA Makoto, NAGATA Makoto, MATSUMOTO Tsutomu

    Jan. 2016, 電子情報通信学会・2016年暗号と情報セキュリティシンポジウム, 2C4-3, 1 - 8, Japanese

    Symposium

  • 電磁波解析攻撃に対する反応型対策の高性能化とその評価

    ISHIHATA Daisuke, HOMMA Naofumi, HAYASHI Yuichi, MIURA Noriyuki, FUJIMOTO Daisuke, NAGATA Makoto, AOKI Takafumi

    Jan. 2016, 電子情報通信学会・2016年暗号と情報セキュリティシンポジウム, 2F2-1, 1 - 6, Japanese

    Symposium

  • 印刷によるTSV形成技術の開発

    IKEDA Hiroaki, SEKINE Shigenobu, KIMURA Ryuji, SHIMOKAWA Koichi, OKADA Keiji, SHINDO Hiroaki, Ooi Tatsuya, TAMAKI Rei, NAGATA Makoto

    Jan. 2016, 電子情報通信学会技術報告, SDM-2015-119, 49 - 54, Japanese

    Symposium

  • レーザーフォールト注入時のIC基板電位変動のオンチップ測定

    MATSUDA Kohei, MIURA Noriyuki, NAGATA Makoto, HAYASHI Yuichi, FUJII Tatsuya, YAGASAKI Reina, SAKIYAMA Kazuo

    Jan. 2016, 電子情報通信学会・2016年暗号と情報セキュリティシンポジウム, 2F1-4, 1 - 4, Japanese

    Symposium

  • Fine Pitch Micro-Bump forming by Printing

    Hiroaki Ikeda, Shigenobu Sekine, Ryuji Kimura, Koichi Shimokawa, Keiji Okada, Hiroaki Shindo, Tatsuya Ooi, Rei Tamaki, Makoto Nagata

    We have examined printing technology which is adaptable to 3DIC bump-forming for (both front-side bump and back-side bump. The materials for bumping require several features for TSV process circumstances and 3DIC stacking followed by reflow. We chose Nano-Function material for the purpose which was initially developed for power semiconductor attachment. The result shows good possibility. 20 mu m bump pitch capability was confirmed.

    IEEE, 2016, 2016 International Conference on Electronics Packaging (ICEP), 260 - 264, English

    [Refereed]

    International conference proceedings

  • EMI Performance of Power Delivery Networks in 3D TSV Integration

    Yuuki Araga, Makoto Nagata, Noriyuki Miura, Hiroaki Ikeda, Katsuya Kikuchi

    A three-dimensionally stacked, large-scale integration (3D-LSI) chip naturally provides densely capacitive and low-impedance characteristics in vertically and horizontally distributed power delivery networks (PDNs). This paper reports the supremacy of a stacked and packaged 3D LSI chip in terms of EMI performance. In-stack power noise monitoring evaluates local shunts by decoupling capacitors within a chip stack for dynamic power currents. On-board near-field magnetic probing confirms global decoupling of a packaged stack from a system power source. These measurements were performed on a real 3D-LSI demonstrator and also a conventional 2D chip for comparison. The 3D-LSI demonstrator includes a Si interposer with explicit as well as implicit capacitors between a stack of active memory and logic tiers fully connected with through-silicon vias (TSVs).

    IEEE, 2016, PROCEEDINGS OF THE 2016 INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY - EMC EUROPE, 428 - 433, English

    [Refereed]

    International conference proceedings

  • 半導体モジュールにおける電源供給特性のチューニング手法

    NAGATA Makoto, TANIGUCHI Kohki, MIURA Noriyuki

    Dec. 2015, 電気学会電子回路研究会, ECT-15-110, 77 - 81, Japanese

    Symposium

  • 適応調律型電源共振抑制フィルタのEMS評価

    TANIGUCHI Kohki, MIURA Noriyuki, NAGATA Makoto

    Dec. 2015, 電子情報通信学会技術報告, ICD2015-57, 29 - 32, Japanese

    Symposium

  • Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks

    HOMMA Naofumi, HAYASHI Yuichi, AOKI Takafumi, MIURA Noriyuki, FUJIMOTO Daisuke, NAGATA Makoto

    Dec. 2015, IACR Journal of Cryptology, 1 - 19, English

    [Refereed]

    Scientific journal

  • In-Place Signal and Power Noise Waveform Capturing Within 3-D Chip Stacking

    NAGATA Makoto, TAKAYA Satoshi, IKEDA Hiroaki

    Nov. 2015, IEEE Design and Test, Vol. 32 (No. 6), 87 - 98, English

    [Refereed]

    Scientific journal

  • Analysis of On-Chip Digital Noise Coupling Path for Wireless Communication IC Test Chip

    TANAKA Satoshi, Peng Fan, Jingyan Ma, AOKI Hanae, YAMAGUCHI Masahiro, NAGATA Makoto, MUROGA Sho

    Nov. 2015, Proc. 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo), #8-1(poster), 216 - 221, English

    [Refereed]

    International conference proceedings

  • A 1mm-Pitch 80x80-Channel 322Hz-Frame-Rate Touch Sensor with Two-Step Dual-Mode Capacitance Scan

    Noriyuki Miura, Shiro Dosho, Satoshi Takaya, Daisuke Fujimoto, Takumi Kiriyama, Hiroyuki Tezuka, Takuji Miki, Hiroto Yanagawa, Makoto Nagata

    IEEE, 2014, 2014 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC), 57 (No. 11), 216 - +, English

    [Refereed]

    International conference proceedings

  • 3DIC/TSV Process Developments by Printing Technologies

    IKEDA Hiroaki, SEKINE Shigenobu, KIMURA Ryuji, SHIMOKAWA Koichi, OKADA Keiji, SHINDO Hiroaki, OOI Tatsuya, TAMAKI Rei, NAGATA Makoto

    Nov. 2015, Proc. IEEE CPMT Symposium Japan (ICSJ 2015), 140 - 143, English

    [Refereed]

    Scientific journal

  • An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference

    SAWADA Takuya, YOSHIKAWA Kumpei, TAKATA Hidehiro, NII Koji, NAGATA Makoto

    Oct. 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23 (No. 10), 2347 - 2351, English

    [Refereed]

    Scientific journal

  • 電源電流イコライザの電力オーバーヘッド低減手法の提案と実証

    KORENAGA Rie, FUJIMOTO Daisuke, MIURA Noriyuki, NAGATA Makoto

    Sep. 2015, 電子情報通信学会ソサイエティ大会, C-12-7, 47, Japanese

    Symposium

  • 実装環境に適応する電源共振ノイズ抑制フィルタの提案と評価

    TANIGUCHI Kohki, MIURA Noriyuki, NAGATA Makoto

    Sep. 2015, 電子情報通信学会ソサイエティ大会, C-12-6, 46, Japanese

    Symposium

  • サイドチャネル近傍電磁波解析攻撃センサの提案とセキュリティ耐性評価

    TANAKA Renta, MIURA Noriyuki, FUJIMOTO Daisuke, HAYASHI Yuichi, HOMMA Naofumi, AOKI Takafumi, NAGATA Makoto

    Sep. 2015, 電子情報通信学会ソサイエティ大会, C-12-5, 45, Japanese

    Symposium

  • VLSIシステムのノイズ問題に関する先駆的貢献

    NAGATA Makoto

    Sep. 2015, 電子情報通信学会ソサイエティ大会, C-12-8, 48, Japanese

    Symposium

  • Nano-Function Materials for TSV Technologies

    IKEDA Hiroaki, SEKINE Shigenobu, KIMURA Ryuji, SHIMOKAWA Koichi, OKADA Keiji, SHINDO Hiroaki, OOI Tatsuya, TAMAKI Rei, NAGATA Makoto

    Sep. 2015, Proc. 2015 International 3D Systems Integration Conference (3DIC 2015), TS5.3.1 - TS5.3.6, English

    [Refereed]

    International conference proceedings

  • Proactive and Reactive Protection Circuit Techniques Against EM Leakage and Injection

    MIURA Noriyuki, FUJIMOTO Daisuke, NAGATA Makoto

    Aug. 2015, Proc. Joint IEEE International Symposium on Electromagnetic Compatibility and EMC Europe (EMC 2015), #SS-1-7, 252 - 257, English

    [Refereed]

    International conference proceedings

  • On-Chip and On-Board RF Noise Coupling and Impacts on LTE Wireless Communication Performance

    NAGATA Makoto, MIURA Noriyuki, MUROGA Sho, TANAKA Satoshi, YAMAGUCHI Masahiro

    Aug. 2015, Proc. 2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT 2015), WE1A-3, 7 - 9, English

    Symposium

  • A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation

    ENDO Sho, Yang Li, HOMMA Naofumi, SAKIYAMA Kazuo, OHTA Kazuo, FUJIMOTO Daisuke, NAGATA Makoto, KATASHITA Toshihiro, Jean-Luc Danger, AOKI Takafumi

    Aug. 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23 (No. 8), 1429 - 1438, English

    [Refereed]

    Scientific journal

  • Analysis of Intra-Chip Degital Noise Coupling Path in Fully LTE Compliant RF Receiver Test Chip

    YAMAGUCHI Masahiro, Peng Fan, TANAKA Satoshi, NAGATA Makoto, MUROGA Sho

    Aug. 2015, Proc. Joint IEEE International Symposium on Electromagnetic Compatibility and EMC Europe (EMC 2015), #Track N-4, 1007 - 1011, English

    [Refereed]

    International conference proceedings

  • Adaptive Suppression of Power Delivery Network Resonance with Chip-Package-Board Interaction

    NAGATA Makoto, TANIGUCHI Kohki, MIURA Noriyuki

    Aug. 2015, Proc. ICDV 2015/VJMW2015, 58 - 60, English

    Symposium

  • EM Attack Sensor: Concept, Circuit, and Design-Automation Methodology (Invited)

    MIURA Noriyuki, FUJIMOTO Daisuke, NAGATA Makoto, HOMMA Naofumi, HAYASHI Yuichi, AOKI Takafumi

    Jun. 2015, Proc. ACM Design Automation Conference 2015 (DAC 2015), #69.2, 1 - 6, English

    [Refereed]

    International conference proceedings

  • On-chip Integrated Magnetic Thin-Film Solution to Countermeasure Digital Noise on RF IC

    YAMAGUCHI Masahiro, TANAKA Satoshi, ENDO Yasushi, MUROGA Sho, NAGATA Makoto

    May 2015, Proc. 2015 IEEE Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC 2015), #SS10-5, English

    [Refereed]

    International conference proceedings

  • At-Product-Test Dedicated Adaptive Supply-Resonance Suppression," Proc. 2015 IEEE 33rd VLSI Test Symposium (VTS 2015)

    TANIGUCHI Kohki, MIURA Noriyuki, HAYASHI Taisuke, NAGATA Makoto

    May 2015, Proc. 2015 IEEE 33rd VLSI Test Symposium (VTS 2015), #TE3-1, 127 - 130, English

    [Refereed]

    International conference proceedings

  • Nano-Function Paste for Power Semiconductors

    IKEDA Hiroaki, SEKINE Shigenobu, KIMURA Ryuji, SHIMOKAWA Koichi, OKADA Keiji, SHINDO Hiroaki, OOI Tatsuya, NAGATA Makoto

    Apr. 2015, Proc. 2015 International Conference on Electrnoics Packaging and iMAPS All Asia Conference (ICEP-IAAC 2015), #06A-1, 482 - 485, English

    [Refereed]

    International conference proceedings

  • KOUSAKA Junpei, SHIMAZAKI Shunsuke, MIURA Noriyuki, MUROGA Sho, TANAKA Satoshi, YAMAGUCHI Masahiro, NAGATA Makoto

    Digital circuits in a mobile communication IC Chip become more enormous for LTE class design. This potentially causes the undesigned noise coupling in the receiver circuit and leads to the deterioration of overall system communication quality. In this study, noise reduction techniques have been explored. A prototype chip having a digital noise generator, LTE-class wireless receiver circuit and on-chip voltage waveform monitor, EMI tester, and the system level simulator for measuring communication quality are prepared for this study. We measured and analyzed the effect of three terminal capacitor on the chip and board level noise coupling. As a result, it exhibits a noise reduction effect of 5dB at the system level in the 2GHz band used in LTE. This will improve communication quality.

    The Institute of Electronics, Information and Communication Engineers, 06 Mar. 2015, IEICE technical report. Electromagnetic compatibility, 114 (503), 35 - 40, Japanese

    Symposium

  • 電磁波攻撃センサの設計と実証

    HOMMA Naofumi, HAYASHI Yuichi, MIURA Noriyuki, FUJIMOTO Daisuke, NAGATA Makoto, AOKI Takafumi

    電子情報通信学会, Jan. 2015, 2015年暗号と情報セキュリティシンポジウム講演論文集, 1-6, Japanese

    Symposium

  • A Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurement

    FUJIMOTO Daisuke, NAGATA Makoto, Shivam Bhasin, Jean-Luc Danger

    Jan. 2015, Proceedings of the 20th Asia and South Pacific Design Automation Conference, #8C-3, 749 - 754, English

    [Refereed]

    International conference proceedings

  • A DPA/DEMA/LEMA-Resistant AES Cryptographic Processor with Supply-Current Equalizer and Micro EM Probe Sensor

    FUJIMOTO Daisuke, MIURA Noriyuki, HAYASHI Yuichi, HOMMA Naofumi, AOKI Takafumi, NAGATA Makoto

    Jan. 2015, Proceedings of the 20th Asia and South Pacific Design Automation Conference, #1S-13, 26 - 27, English

    [Refereed]

    International conference proceedings

  • VLSI チップにおける電源雑音の評価とモデリング

    NAGATA Makoto

    電気学会電子回路研究会, Dec. 2014, ECT-14-107, 1-6, Japanese

    [Invited]

    Symposium

  • サイドチャネル情報漏洩対策のための集積回路技術

    MIURA Noriyuki, FUJIMOTO Daisuke, NAGATA Makoto

    電子情報通信学会, Nov. 2014, ICD2014-67, 9 - 14, Japanese

    Symposium

  • Takefumi Yoshikawa, Makoto Nagata

    This paper presents a circuit technique to enhance a timing margin between internal data and clock by enlarging an eye opening of the internal data in a unique current mode transceiver [1]. This technique compensates a systematic timing offset of the internal data, which is caused by unbalanced transmission current. The test-chip exhibits 0.1UI (Unit Interval) improvement of the internal data eye opening without significant power penalty, and achieves stable data communication through 50% longer transmission lines compared to the previous work [1].

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, 2014, IEICE ELECTRONICS EXPRESS, 11 (19), 1 - 7, English

    [Refereed]

    Scientific journal

  • CDM Protection of a 3D TSV Memory IC with a 100 GB/s Wide I/O Data Bus

    Makoto Nagata, Satoshi Takaya, Hiroaki Ikeda, Dimitri Linten, Mirko Scholz, Shih-Hung Chen, Keiichi Hasegawa, Taizo Shintani, Masanori Sawada

    For the first time, CDM stress tests are studied on a 3D TSV stacked IC for memory applications. The stacked dies have each their ESD protection, but no dedicated ESD protection was placed on the TSVs. A CDM protection level of more than 1.5 kV is obtained.

    IEEE COMPUTER SOC, 2014, 2014 36TH ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM (EOS/ESD), #2A-2, 1 - 7, English

    [Refereed]

    International conference proceedings

  • A Study on Power Integrity in a 3D Chip Stack Using Dynamic Power Supply Current Emulation and Power Noise Monitoring

    ARAGA YUUKI, MIURA Ranto, NAGATA Makoto, Cesar Roda Neve, Joeri De Vos, Geert Van der Plas, Eric Beyne

    Sep. 2014, Proceedings of IEEE Electronics System-Integration Technology Conference, #S14P2, English

    [Refereed]

    International conference proceedings

  • 二段階デュアルモード容量スキャン方式を用いた1mm-Pitch 80x80-Channel 322Hz-Frame-Rateタッチセンサの設計

    MIURA Noriyuki, DOSHO Shiro, FUJIMOTO Daisuke, KIRIYAMA Takuya, TEDUKA Hiroyuki, MIKI Takuji, NAGATA Makoto

    電子情報通信学会, Jul. 2014, ICD2014-20, 7 - 12, Japanese

    Symposium

  • MUROGA Sho, FAN Peng, TANAKA Satoshi, KITAMRA Tomomitsu, MATSUI Hiroaki, AZUMA Naoya, SHIMAZAKI Shunsuke, KOSAKA Junpei, NAGATA Makoto, YAMAGUCHI Masahiro

    The integrated simulation was constructed using the full wave 3-dimensional electromagnetic field simulator and the circuit analysis in order to analyze the mechanism of the on-chip conductive and the inductive noise coupling in LTE-class RFIC. From the constructed simulation, the main EM noise coupling on the chip revealed as the conductive and the inductive noise coupling. Furthermore, the noise suppression mechanism using the magnetic thin film was discussed.

    The Institute of Electronics, Information and Communication Engineers, 20 Jun. 2014, IEICE technical report. Electromagnetic compatibility, 114 (93), 55 - 58, Japanese

    Symposium

  • Yuuki Araga, Makoto Nagata, Geert Van der Plas, Paul Marchal, Michael Libois, Antonio La Manna, Wenqi Zhang, Gerald Beyer, Eric Beyne

    Silicon substrates can be strategically isolated or unified among tiers in a through-silicon-via (TSV)-based 3-D integrated circuit (IC) structure, for the suppression of intertier substrate noise coupling or the reduction of grounding impedance of silicon substrates as a whole, respectively. A two-tier 3-D IC demonstrator in a 130-nm CMOS technology was successfully tested and analyzed with respect to intra and intertier substrate noise coupling. Each tier in the stack includes digital noise source circuits (NSs) and substrate noise monitors, and embodies in-place measurements of substrate noise coupling. An equivalent circuit unifies power and substrate networks of the tiers and simulates the frequency-domain response of substrate noise coupling. Measurements and calculation with the equivalent circuit are consistent for frequency dependency of substrate noise coupling in a 3-D IC demonstrator. Intratier propagation is dominant, while intertier coupling is insignificant for low-frequency substrate noise components. Intertier coupling becomes comparable with and finally overwhelms intratier coupling as the frequency of substrate noise components increases. Substrate noise coupling in a multitier chip stack is strongly impacted by the parasitic capacitance of TSVs, while that coupling becomes predictable with the equivalent circuit of the entire stack.

    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, Jun. 2014, IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 4 (6), 1026 - 1037, English

    [Refereed]

    Scientific journal

  • Satoshi Takaya, Hiroaki Ikeda, Makoto Nagata

    A three dimensional (3D) chip stack featuring a 4096-bit wide I/O demonstrator incorporates an in-place waveform capturer on an intermediate interposer within the stack. The capturer includes probing channels on paths of signaling as well as in power delivery and collects analog waveforms for diagnosing circuits within 3D integration. The collection of in-place waveforms on vertical channels with through silicon vias (TSVs) are demonstrated among 128 vertical I/O channels distributed in 8 banks in a 9.9 mm x 9.9 nun die area. The analog waveforms confirm a full 1.2-V swing of signaling at the maximum data transmission bandwidth of 100 GByte/sec with sufficiently small deviations of signal skews and slews among the vertical channels. In addition, it is also experimentally confirmed that the signal swing can be reduced to 0.75 V for error free data transfer at 100 GByte/sec, achieving the energy efficiency of 0.21 pJ/bit.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jun. 2014, IEICE TRANSACTIONS ON ELECTRONICS, E97C (6), 557 - 565, English

    [Refereed]

    Scientific journal

  • CMOS暗号回路におけるシリコン基板からのサイドチャネル漏洩

    FUJIMOTO Daisuke, MIURA Noriyuki, NAGATA Makoto, HAYASHI Yuichi, HOMMA Naofumi, Shivam Bhasin, Jean-Luc Danger

    電子情報通信学会, Jun. 2014, EMCJ2014-10, 1 - 6, Japanese

    Symposium

  • Naoya Azuma, Shunsuke Shimazaki, Noriyuki Miura, Makoto Nagata, Tomomitsu Kitamura, Satoru Takahashi, Motoki Murakami, Kazuaki Hori, Atsushi Nakamura, Kenta Tsukamoto, Mizuki Iwanami, Eiji Hankui, Sho Muroga, Yasushi Endo, Satoshi Tanaka, Masahiro Yamaguchi

    Substrate noise coupling in RF receiver front-end circuitry for LTE wireless communication was examined by full-chip level simulation and on-chip measurements, with a demonstrator built in a 65 nm CMOS technology. A CMOS digital noise emulator injects high-order harmonic noises in a silicon substrate and induces in-band spurious tones in an RF receiver on the same chip through substrate noise interference. A complete simulation flow of full-chip level substrate noise coupling uses a decoupled modeling approach, where substrate noise waveforms drawn with a unified package-chip model of noise source circuits are given to mixed-level simulation of RF chains as noise sensitive circuits. The distribution of substrate noise in a chip and the attenuation with distance are simulated and compared with the measurements. The interference of substrate noise at the 17th harmonics of 124.8 MHz the operating frequency of the CMOS noise emulator creates spurious tones in the communication bandwidth at 2.1 GHz.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jun. 2014, IEICE TRANSACTIONS ON ELECTRONICS, E97C (6), 546 - 556, English

    [Refereed]

    Scientific journal

  • A Local EM-Analysis Attack Resistant Cryptographic Engine with Fully-Digital Oscillator-Based Tamper-Access Sensor

    MIURA Noriyuki, FUJIMOTO Daisuke, TANAKA Daichi, HAYASHI Yuichi, HOMMA Naofumi, AOKI Takafumi, NAGATA Makoto

    Jun. 2014, Digest of Technical Papers, IEEE 2014 Symposium on VLSI Circuits, #16.4, 172 - 173, English

    [Refereed]

    International conference proceedings

  • Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yuichi Hayashi, Naofumi Homma, Takafumi Aoki, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ho Le, Julien Bringer, Pirouz Bazargan-Sabet, Shivam Bhasin, Jean-Luc Danger

    Power supply noise waveforms within cryptographic VLSI circuits in a 65 Jun CMOS technology are captured by using an on-chip voltage waveform monitor (OCM). The waveforms exhibit the correlation of dynamic voltage drops to internal logical activities during Advance Encryption Standard (AES) processing, and causes side-channel information leakage regarding to secret key bytes. Correlation Power Analysis (CPA) is the method of an attack extracting such information leakage from the waveforms. The frequency components of power supply noise contributing the leakage are shown to be localized in an extremely low frequency region. The level of information leakage is strongly associated with the size of increment of dynamic voltage drops against the Hamming distance in the AES processing. The time window of significant importance where the leakage most likely happens is clearly designated within a single clock cycle in the final stage of AES processing. The on-chip power supply noise measurements unveil the facts about side-channel information leakage behind the traditional CPA with on-board sensing of power supply current through a resistor of 1 ohm.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2014, IEICE TRANSACTIONS ON ELECTRONICS, E97C (4), 272 - 279, English

    [Refereed]

    Scientific journal

  • Shunsuke Shimazaki, Shota Taga, Tetsuya Makita, Naoya Azuma, Noriyuki Miura, Makoto Nagata

    A noise emulator is based on the capacitor charging modeling and generates power and substrate noises expected in a CMOS digital integrated circuit. An off-chip near-magnetic-field sensor indirectly characterizes the distribution of clock timing and the adjustability of skews within on-chip digital circuits. An on-chip noise monitor captures power and substrate noise waveforms and evaluates noise frequency components in a wide frequency bandwidth. A 65 nm CMOS prototype demonstrated power and substrate noise generation in a variety of operating scenarios of digital integrated circuits. Power noise generation emulated at 125 MHz exhibits the enhancements of high-order harmonic components after deskewing at a timing resolution of 37.8 ps, as is specifically seen in more than 10 dB enlargement of the substrate noise component at 2.1 GHz. (C) 2014 The Japan Society of Applied Physics

    IOP PUBLISHING LTD, Apr. 2014, JAPANESE JOURNAL OF APPLIED PHYSICS, 53 (4), 04EE06 - 1-04EE06-6, English

    [Refereed]

    Scientific journal

  • A Passive Supply-Resonance Suppression Filter Utilizing Inductance-Enhanced Coupled Bonding-Wire Coils

    Taisuke Hayashi, Noriyuki Miura, Kumpei Yoshikawa, Makoto Nagata

    This paper presents a low-power and compact passive supply-resonance (SR) suppression filter. By using an on-chip waveform monitor, a power-delivery network (PDN) impedance including package, and board PDNs is in-situ analyzed to identify the SR frequency f(SR). A notch filter which consists of coupled bonding-wire coils and an on-chip MOS capacitor bank is auto-tuned for the SR suppression. This passive filtering approach reduces the power loss to 1/5 similar to 1/10 and the static power to effectively zero as compared to an active SR suppression circuit [1]. The coupled bonding-wire coil enhances its self-inductance and hence shrinks the on-chip capacitor size for the layout-area saving. A 0.18 mu m CMOS test chip demonstrates SR suppression by >43% with only <7% of power loss and <0.034mm(2) layout area penalty.

    IEEE, 2014, 2014 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), #DR52, 121 - 124, English

    [Refereed]

    International conference proceedings

  • Kumpei Yoshikawa, Kouji Ichikawa, Makoto Nagata

    An LSI Chip-Package-Board integrated power noise simulation model and its validity is discussed in this paper. A unified power delivery network (PDN) of LSI chip, package, and printed circuit board (PCB) is connected with on-chip power supply current models with capacitor charging expression. The proposed modeling How is demonstrated for the 32-bit microprocessor in a 1.0 V 90 nm CMOS technology. The PDN of the system that includes a chip, bonding wires and a printed circuit board is modeled in an equivalent circuit. The on-chip power supply noise monitoring technique and the magnetic probe method is applied for validating simulation results. Simulations and measurements explore power supply noise generation with the dependency on operating frequencies in the wide range from 10 MHz to 300 MHz, under the operation mode of dynamic frequency scaling, and in the long time operation with various operation codes. It is confirmed that the proposed power supply noise simulation model is helpful for the noise estimation throughout the design phase of the LSI system.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2014, IEICE TRANSACTIONS ON ELECTRONICS, E97C (4), 264 - 271, English

    [Refereed]

    Scientific journal

  • Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper presents a resilient cache memory for dynamic variation tolerance in a 40-nm CMOS. The cache can perform sustained operations under a large-amplitude voltage droop. To realize sustained operation, the resilient cache exploits 7T/14T bit-enhancing SRAM and on-chip voltage/temperature monitoring circuit. 7T/14T bit-enhancing SRAM can reconfigure itself dynamically to a reliable bit-enhancing mode. The on-chip voltage/temperature monitoring circuit can sense a precise supply voltage level of a power rail of the cache. The proposed cache can dynamically change its operation mode using the voltage/temperature monitoring result and can operate reliably under a large-amplitude voltage droop. Experimental result shows that it does not fail with 25% and 30% droop of V-dd and it provides 91 times better failure rate with a 35% droop of V-dd compared with the conventional design.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2014, IEICE TRANSACTIONS ON ELECTRONICS, E97C (4), 332 - 341, English

    [Refereed]

    Scientific journal

  • Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto

    This paper presents a resilient cache memory for dynamic variation tolerance in a 40-nm CMOS. The cache can perform sustained operations under a large-amplitude voltage droop. To realize sustained operation, the resilient cache exploits 7T/14T bit-enhancing SRAM and on-chip voltage/temperature monitoring circuit. 7T/14T bit-enhancing SRAM can reconfigure itself dynamically to a reliable bit-enhancing mode. The on-chip voltage/temperature monitoring circuit can sense a precise supply voltage level of a power rail of the cache. The proposed cache can dynamically change its operation mode using the voltage/temperature monitoring result and can operate reliably under a large-amplitude voltage droop. Experimental result shows that it does not fail with 25% and 30% droop of V-dd and it provides 91 times better failure rate with a 35% droop of V-dd compared with the conventional design.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2014, IEICE TRANSACTIONS ON ELECTRONICS, E97C (4), 332 - 341, English

    [Refereed]

    Scientific journal

  • Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology

    Shivam Bhasin, Jean-Luc Danger, Tarik Graba, Yves Mathieu, FUJIMOTO Daisuke, NAGATA Makoto

    IEEE, Mar. 2014, Engineering Simulations for Cyber Physical Systems (ES4CPS), #3, 13 - 20, English

    [Refereed]

    International conference proceedings

  • A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance with Bit-Enhancing Memory and On-Chip Diagnosis Structures Delivering x91 Failure Rate Improvement

    Y. Nakata, Y. Kimi, S. Okumura, J. Jung, T. Sawada, T. Toshikawa, M. Nagata, H. nakano, M. Yabuuchi, H. Fujiwara, K. Nii, H. Kawai, H. Kawaguchi, YOSHIMOTO Masahiko

    Mar. 2014, IEEE International Symposium on Quality Electronic Design (ISQED), pp.16 - 23, English

    [Refereed]

    International conference proceedings

  • 動作環境の動的変動を考慮した動作マージン拡大機能を有する自律制御キャッシュ

    KIMI Yuta, NAKATA Yohei, OKUMURA Syunsuke, JUNG Jinwook, 沢田 卓也, 利川 托, 永田 真, 中野 博文, 薮内 誠, 藤原 英弘, 新居 浩二, 河合 浩行, KAWAGUCHI Hiroshi, YOSHIMOTO Masahiko

    Jan. 2014, 信学技報, vol. 113 (no. 419), p. 59, Japanese

    Research society

  • A 1mm-Pitch 80x80-Channel 322Hz-Frame-Rate Touch Sensor with Two-Step Dual-Mode Capacitance Scan

    Noriyuki Miura, Shiro Dosho, Satoshi Takaya, Daisuke Fujimoto, Takumi Kiriyama, Hiroyuki Tezuka, Takuji Miki, Hiroto Yanagawa, Makoto Nagata

    IEEE, 2014, 2014 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC), 57, 216 - +, English

    [Refereed]

    International conference proceedings

  • Side-Channel Leakage on Silicon Substrate of CMOS Cryptographic Chip

    Daisuke Fujimoto, Daichi Tanaka, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Shivam Bhasin, Jean-Luc Danger

    Power supply currents of CMOS digital circuits partly flow through a silicon substrate in their returning (ground) paths. The voltage bounce due to the substrate currents is seen wherever p+ substrate taps on a p-type die and regarded as a substrate noise. An on-chip waveform monitor confirms the side-channel leakage on the silicon substrate from an AES cryptographic module in a 65 nm CMOS demonstrator chip for the first time. The silicon substrate is essentially common to every circuit and inevitably carries the leakage to the observation taps located at the front as well as at the bottom surface of a die, even if the power and ground wires of an AES module are intentionally separated from the other building blocks. Substrate leakage channels may break the hiding of a cryptographic module regarding its location on a die. The physical properties including the distance dependency are experimentally explored.

    IEEE, 2014, 2014 IEEE INTERNATIONAL SYMPOSIUM ON HARDWARE-ORIENTED SECURITY AND TRUST (HOST), #3-3, 32 - 37, English

    [Refereed]

    International conference proceedings

  • On-Chip Magnetic Thin-Film Noise Suppressor for IC Chip Level Digital Noise Countermeasure

    Masahiro Yamaguchi, Yasushi Endo, Satoshi Tanaka, Tetsuo Ito, Sho Muroga, Naoya Azuma, Makoto Nagata

    Crossed anisotropy amorphous Co85Zr3Nb12 thin film with total magnetic thickness of 2.0 mu m is deposited on to the passivation of a bare IC chip to accommodate intra IC chip level digital-to-RF noise suppression and telecommunication performance. On-chip magnetic film processes can be done as the last steps of Si CMOS back end processes. Radiated emission from embedded arbitrary noise generator is suppressed by more than 10 dB. In-band spurious tone is attenuated by 10 dB. Minimum input power level to meet the 3GPP criteria is improved by 8 dB. All of these results are achieved on the fully LTE compliant RF receiver chain.

    IEEE, 2014, 2014 INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, TOKYO (EMC'14/TOKYO), 14P1-B4, 354 - 357, English

    [Refereed]

    International conference proceedings

  • In-Stack Monitoring of Signal and Power Nodes in Three Dimensional Integrated Circuits

    Yuuki Araga, Ranto Miura, Nao Ueda, Noriyuki Miura, Makoto Nagata

    An on-chip waveform monitoring technique embodies in-stack evaluation of three-dimensional integrated circuits (3D IC) regarding physical connections using through silicon vias (TSV) and electronic characteristics of signal transmission as well as noise propagation. On-chip generation of reference voltage steps and sampling timings reduces the complexity of analog signal routing in a chip stack and enhances measurement throughputs. The demonstrated 7.6 effective bit resolution with a 5.8 times higher throughput is suitable for in-stack monitoring. Sinusoidal signal transmission in a two-tier 3D IC is on-chip evaluated.

    IEEE, 2014, 2014 INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, TOKYO (EMC'14/TOKYO), 14P2-B1, 362 - 365, English

    [Refereed]

    International conference proceedings

  • Correlation Power Analysis using Bit-Level Biased Activity Plaintexts against AES Cores with Countermeasures

    Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yuichi Hayashi, Naofumi Homma, Takafumi Aoki, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Shivam Bhasin, Jean-Luc Danger

    Advanced encryption standard (AES) cores suffer from information leakage through power supply currents, even with the wave dynamic differential logic (WDDL) known as one of the most tolerable countermeasure design styles against side channel attacks (SCA). The set of plaintexts having bitlevel biased activities are produced with a known secret key and used for diagnosing the vulnerability of AES cores in their development phases. The CPA with biased plaintexts revealed 128-bit secret keys with less than 4,000 traces from the WDDL AES core both by the measurements and simulations of power supply currents. The core was physically structured by using a 65-nm CMOS standard cell library and assembled on a test vehicle of "SPACES explorer" having an on-board 1-ohm resistor for measuring power supply currents. The derived knowledge should be useful in driving the design of AES cores to be much less prone to information leakage through power supply current and electromagnetic measurements.

    IEEE, 2014, 2014 INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, TOKYO (EMC'14/TOKYO), #14P2-A3, 306 - 309, English

    [Refereed]

    International conference proceedings

  • Integrated-Circuit Countermeasures Against Information Leakage Through EM Radiation

    Noriyuki Miura, Daisuke Fujimoto, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata

    EM radiation from a cryptographic processor IC contains side-channel information of secret data hidden inside the chip. This side-channel information leakage is a potential threat critical to our information society. This paper introduces several circuit-level countermeasures integrated with the cryptographic processor core for advanced hardware security.

    IEEE, 2014, 2014 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC), #TH-AM-3-3, 748 - 751, English

    [Refereed]

    International conference proceedings

  • EM Attack Is Non-invasive? - Design Methodology and Validity Verification of EM Attack Sensor

    Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Makoto Nagata, Takafumi Aoki

    This paper presents a standard-cell-based semi-automatic design methodology of a new conceptual countermeasure against electromagnetic (EM) analysis and fault-injection attacks. The countermeasure namely EM attack sensor utilizes LC oscillators which detect variations in the EM field around a cryptographic LSI caused by a micro probe brought near the LSI. A dual-coil sensor architecture with an LUT-programming-based digital calibration can prevent a variety of microprobe-based EM attacks that cannot be thwarted by conventional countermeasures. All components of the sensor core are semiautomatically designed by standard EDA tools with a fully-digital standard cell library and hence minimum design cost. This sensor can be therefore scaled together with the cryptographic LSI to be protected. The sensor prototype is designed based on the proposed methodology together with a 128bit-key composite AES processor in 0.18 mu m CMOS with overheads of only 2respectively. The validity against a variety of EM attack scenarios has been verified successfully.

    SPRINGER-VERLAG BERLIN, 2014, CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2014, 8731 (LNCS 8731), 1 - 16, English

    [Refereed]

    International conference proceedings

  • Makoto Nagata, Daisuke Fujimoto, Noriyuki Miura

    An on-chip monitoring technique has realized in-place diagnosis of power noise problems. On-chip voltage noise monitor (OCM) circuits are overviewed with some examples of integration in silicon chips. The OCM captures power noise waveforms in a silicon chip and provides the opportunities of diagnosis on unfavorable invisible events within a die. In-band interference of radio-frequency (RF) communication channels by power noise coupling in RF systems-on-chip (SoC) integration, and information leakage through power noise side channels from a cryptographic core are demonstrated.

    IEEE COMPUTER SOC, 2014, 2014 IEEE 23RD ASIAN TEST SYMPOSIUM (ATS), #6C-3, 258 - 262, English

    [Refereed]

    International conference proceedings

  • An Intermittent-Driven Supply-Current Equalizer for 11x and 4x Power-Overhead Savings in CPA-Resistant 128bit AES Cryptographic Processor

    Noriyuki Miura, Daisuke Fujimoto, Rie Korenaga, Kohei Matsuda, Makoto Nagata

    A supply-current equalizer disables a Correlation Power Analysis (CPA) attack on an AES cryptographic processor. An intermittent equalizer operation only at processing rounds critical to key disclosure suppresses the equalizer power overhead significantly. For this low-power intermittent operation, a Thru operation mode is proposed with minimum hardware overhead. A level-shift comparator hides its own power consumption in an internal equalized virtual supply to guarantee secure protection of a secret key. Test-chip measurement in 0.18 mu m CMOS successfully demonstrates CPA-attack resiliency. For the key protection against mostly-common last-round CPA, the equalizer power overhead is reduced by 11x which is only 8% of 128bit AES processor power consumption, and by 4x even including the initial/1st-rounds CPA protection capability.

    IEEE, 2014, 2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), #14-5, 225 - 228, English

    [Refereed]

    International conference proceedings

  • Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring

    ARAGA Yuuki, UEDA Nao, TAKAGI Yasumasa, NAGATA Makoto

    IEICE, Dec. 2013, IEICE Transactions on Fundamentals, E96-A (12), 2516 - 2523, English

    [Refereed]

    Scientific journal

  • Noise Analysis using On-Chip waveform Monitor in Bandgap Voltage References

    MURATA Akitaka, AGATSUMA Shuji, IKOMA Daisuke, ICHIKAWA Kouji, TSUDA Takahiro, NAGATA Makoto, YOSHIKAWA Kumpei, ARAGA Yuuki, HARADA Yuji

    IEEE, Dec. 2013, 2013 IEEE 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo), #IM1-3, 226 - 231, English

    [Refereed]

    International conference proceedings

  • Measurements and Simulation of Substrate Noise Coupling in RF ICs with CMOS Digital Noise Emulator

    AZUMA Naoya, SHIMAZAKI Shunsuke, MIURA Noriyuki, NAGATA Makoto, KITAMURA Tomomitsu, TAKAHASHI Satoru, MURAKAMI Motoki, HORI Kazuaki, NAKAMURA Atsushi, TSUKAMOTO Kenta, IWANAMI Mizuki, HANKUI Eiji, MUROGA Sho, ENDO Yasushi, TANAKA Satoshi, YAMAGUCHI Masahiro

    IEEE, Dec. 2013, 2013 IEEE 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo), #SS-4, 42 - 46, English

    [Refereed]

    International conference proceedings

  • Measurement-Based Diagnosis of Wireless Communication Performance in the Presence of In-Band Interferers in RF Ics

    NAGATA Makoto, SHIMAZAKI Shunsuke, AZUMA Naoya, TAKAHASHI Satoru, MURAKAMI Motoki, HORI Kazuaki, TANAKA Satoshi, YAMAGUCHI Masahiro

    IEEE, Dec. 2013, 2013 IEEE 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo), #SS-3, 37 - 41, English

    [Refereed]

    International conference proceedings

  • In-Band Spurious Attenuation in LTE-Class RFIC Chip using a Soft Magnetic Thin Film

    MUROGA Sho, SHIMADA Yutaka, ENDO Yasushi, TANAKA Satoshi, YAMAGUCHI Masahiro, MURAKAMI Motoki, HORI Kazuaki, AZUMA Naoya, NAGATA Makoto, TAKAHASHI Satoru

    IEEE, Dec. 2013, 2013 IEEE 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo), #SS-5, 47 - 52, English

    [Refereed]

    International conference proceedings

  • Immunity Evaluation of Inverter Chains against RF Power on Power Delivery Network

    YOSHIKAWA Kumpei, HARADA Yuji, MIURA Noriyuki, TAKEDA Noriaki, SAITO Yoshiyuki, NAGATA Makoto

    IEEE, Dec. 2013, 2013 IEEE 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo), #IM1-4, 232 - 237, English

    [Refereed]

    International conference proceedings

  • A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation

    FUJIMOTO Daisuke, KATASHITA Toshihiro, SASAKI Akihiko, SATOH Akashi, NAGATA Makoto

    IEICE, Dec. 2013, IEICE Transactions on Fundamentals, E96-A (12), 2533 - 2541, English

    [Refereed]

    Scientific journal

  • Very low-voltage swing while high-bandwidth data transmission through 4096 bit TSVs

    NAGATA Makoto, TAKAYA Satoshi, IKEDA Hiroaki

    IEEE, Oct. 2013, IEEE International 3D Systems Integration Conference (3DIC 2013), #3-1, 3.1.1 - 3.1.4, English

    [Refereed]

    International conference proceedings

  • On-Chip Power Noise Measurements of Cryptographic VLSI Circuits and Interpretation for Side-Channel Analysis

    FUJIMOTO Daisuke, MIURA Noriyuki, NAGATA Makoto, HAYASHI Yuichi, HOMMA Naofumi, HORI Yohei, KATASHITA Toshihiro, SAKIYAMA Kazuo, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Jean-Luc Danger

    IEEE, Sep. 2013, 2013 IEEE International Symposium on Electromagnetic Compatibility in Europe (EMC Europe 2013), 405 - 410, English

    [Refereed]

    International conference proceedings

  • In-System Diagnosis of RF ICs for Tolerance against On-Chip In-Band Interferers

    AZUMA Naoya, MAKITA Tetsuya, UEYAMA Shinichiro, NAGATA Makoto, TAKAHASHI Satoru, MURAKAMI Motoki, HORI Kazuaki, TANAKA Satoshi, YAMAGUCHI Masahiro

    IEEE, Sep. 2013, 2013 IEEE International Test Conference (ITC 2013), #12.3, 12.3.1 - 12.3.9, English

    [Refereed]

    International conference proceedings

  • Emulation of High Frequency Substrate Noise in CMOS Digital Circuits with Effects of Adjusting Clock Skew

    SHIMAZAKI Shunsuke, TAGA Shota, MAKITA Tetsuya, AZUMA Naoya, MIURA Noriyuki, NAGATA Makoto

    IEEE, Sep. 2013, Extended Abstracts of the 2013 International Conference on Solid State Devices and Materials (SSDM 2013), #PS-5-5, 124, English

    [Refereed]

    International conference proceedings

  • In-Band Spurious Attenuation in LTE-Class RFIC Chip using a Soft Magnetic Thin Film

    MUROGA Sho, ENDO Yasushi, ITO Tetsuo, TANAKA Satoshi, MURAKAMI Motoki, HORI Kazuaki, TAKAHASHI Satoru, AZUMA Naoya, MAKITA Tetsuya, IMAI Satoshi, NAGATA Makoto, YAMAGUCHI Masahiro

    IEEE, Aug. 2013, 2013 IEEE International Symposium on Electromagnetic Compatibility (EMC 2013), TH-AM-3-1, 657 - 661, English

    [Refereed]

    International conference proceedings

  • Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation

    TAKAYA Satoshi, BANDO Yoji, OHKAWA Tohru, TAKARAMOTO Toshiharu, YAMADA Toshio, SODA Masaaki, KUMASHIRO Shigetaka, MOGAMI Tohru, NAGATA Makoto

    IEICE, Jun. 2013, IEICE Transactions on Electronics, E96-C (6), 884 - 893, English

    [Refereed]

    Scientific journal

  • Equivalent Circuit Representation of Silicon Substrate Coupling of Passive and Active RF Components

    AZUMA Naoya, NAGATA Makoto

    IEICE, Jun. 2013, IEICE Transactions on Electronics, E96-C (6), 875 - 883, English

    [Refereed]

    Scientific journal

  • Power-Noise Measurements of Small-Scale Inverter Chains

    HARADA Yuji, YOSHIKAWA Kouji, MIURA Noriyuki, NAGATA Makoto, MURATA Akitaka, AGATSUMA Syuji, ICHIKAWA Kouji

    IEEE, May 2013, IEEE 2013 International Meeting for Future of Electron Devices, Kansai (IMFEDK 2013), #PS-03, 102 - 103, English

    [Refereed]

    International conference proceedings

  • Power Current Modeling of Cryptographic VLSI Circuits for Analysis of Side Channel Attacks

    NAGATA Makoto, FUJIMOTO Daisuke, TANAKA Daichi

    IEEE, May 2013, 2013 IEEE Asia-Pacific International Symposium and Exhibition on Electromagnetic Compatibility (APEMC 2013), #103, 1 - 4, English

    [Refereed]

    International conference proceedings

  • False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation

    SAWADA Takuya, TAKATA Hidehiro, NII Koji, NAGATA Makoto

    JSAP, Apr. 2013, Japanese Journal of Applied Physics, Vol. 52 (4), 04CE14 - 1-04CE14-5, English

    [Refereed]

    Scientific journal

  • Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits

    OKUMOTO Takeshi, YOSHIKAWA Kumpei, NAGATA Makoto

    IEICE, Apr. 2013, IEICE Transactions on Electronics, E96-C (4), 538 - 545, English

    [Refereed]

    Scientific journal

  • Measurements of SRAM Sensitivity against AC Power Noise with Effects of Device Variation

    SAWADA Takuya, YOSHIKAWA Kumpei, TAKATA Hidehiro, NII Koji, NAGATA Makoto

    IEEE, Mar. 2013, Proceedings of 2013 IEEE International Conference on Microelectronic Test Structures (ICMTS 2013), (#4.2), 77 - 80, English

    [Refereed]

    International conference proceedings

  • A 100GB/s Wide I/O with 4096b TSVs Through an Active Silicon Interposer with In-Place Waveform Capturing

    TAKAYA Satoshi, NAGATA Makoto, SAKAI Atsushi, KARIYA Takashi, UCHIYAMA Shiro, KOBAYASHI Harufumi, IKEDA Hiroaki

    IEEE, Feb. 2013, Digest of Technical Papers, 2013 IEEE Intl. Solid-State Circuits Conference (ISSCC), (#24.8), 434 - 435, English

    [Refereed]

    International conference proceedings

  • 容量充電モデルを用いたシミュレーションによる相関電力解析の考察

    TANAKA Daichi, FUJIMOTO Daisuke, NAGATA Makoto

    電子情報通信学会, Jan. 2013, 2013年暗号と情報セキュリティシンポジウム, (1E2-2), 1 - 7, Japanese

    Symposium

  • 容量充電モデルを用いたシミュレーションによるサイドチャネル情報漏洩探索手法

    FUJIMOTO Daisuke, TANAKA Daichi, NAGATA Makoto

    電子情報通信学会, Jan. 2013, 2013年暗号と情報セキュリティシンポジウム, (1E1-2), 1 - 6, Japanese

    Symposium

  • Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits

    YOSHIKAWA Kumpei, SASAKI Yuta, ICHIKAWA Kouji, SAITO Yoshiyuki, NAGATA Makoto

    IEICE, Dec. 2012, IEICE Transactions on Fundamentals, E95-A (12), 2284 - 2291, English

    [Refereed]

    Scientific journal

  • Co-simulation of AC Power Noise of CMOS Microprocessor using Capacitor Charging Modeling

    YOSHIKAWA Kumpei, NAGATA Makoto

    IEEE, Dec. 2012, Proceedings of IEEE CPMT Symposium Japan 2012, (#19-2), 293 - 296, English

    [Refereed]

    International conference proceedings

  • デジタルLSIにおけるLSIチップ・パッケージ・ボードを統合した電源雑音協調評価

    YOSHIKAWA Kumpei, SASAKI Yuta, ICHIKAWA Kouji, SAITO Yoshiyuki, NAGATA Makoto

    電子情報通信学会, Nov. 2012, 電子情報通信学会技術報告, VLD2012 (91), 183 - 188, Japanese

    Symposium

  • Monitoring Effective Supply Voltage within Power Rails of Integrated Circuits

    OKUMOTO Takeshi, YOSHIKAWA Kumpei, NAGATA Makoto

    IEEE, Nov. 2012, Proceedings of 2012 IEEE Asian Solid-State Circuits Conference (A-SSCC 2012), (#4-4), 113 - 116, English

    [Refereed]

    International conference proceedings

  • Sensitivity of SRAM Operation against AC Power Supply Voltage Variation

    SAWADA Takuya, TAKATA Hidehiro, NII Koji, NAGATA Makoto

    JSAP, Sep. 2012, Extended Abstracts of the 2012 International Conference on Solid State Devices and Materials (SSDM 2012), (#J-3-1), 1128 - 1129, English

    [Refereed]

    International conference proceedings

  • 三次元積層LSIチップにおける基板ノイズの層間評価

    TAKAGI Yasumasa, ARAGA Yuuki, NAGATA Makoto, Geert Van der Plas, Jaemin Kim, Nikolaos Minas, Pol Marchal, Michael Libois, Antonio La Manna, Wenqi Zhang, Julien Ryckaert, Eric Beyne

    電子情報通信学会, Aug. 2012, 電子情報通信学会技術報告, ICD2012 (40), 49 - 54, Japanese

    Symposium

  • Measurement of Side-Channel Information from Cryptographic Devices on Security Evaluation Platform: Demonstration of SPACES Project

    ENDO Sho, HAYASHI Yuichi, HOMMA Naofumi, AOKI Takafumi, KATASHITA Toshihiro, HORI Yohei, SAKIYAMA Kazuo, NAGATA Makoto, Jean-Luc Danger, Thanh-Ha Le, Pirouz Bazargan Sabet

    SICE, Aug. 2012, Proceedings of SICE Annual Conference 2012, (#TuA11-05), 313 - 316, English

    [Refereed]

    International conference proceedings

  • Co-Evaluation of Power Supply Noise of CMOS Microprocessor using On-Boar Magnetic Probing and On-Chip Waveform Capturing Techniques

    SASAKI Yuta, YOSHIKAWA Kumpei, ICHIKAWA Kouji, NAGATA Makoto

    IEEE, May 2012, Proceedings of IEEE 2012 International Meeting for Future of Electron Devices, Kansai (IMFEDK 2012), (#S-1), 70 - 71, English

    [Refereed]

    International conference proceedings

  • デジタルLSIの電源ノイズに関するオンボードおよびオンチップ測定の統合評価

    YOSHIKAWA Kumpei, SASAKI Yuta, ICHIKAWA Kouji, NAGATA Makoto

    電子情報通信学会, Apr. 2012, 電子情報通信学会技術報告, EMCJ2012 (7), 37 - 42, Japanese

    Symposium

  • Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation

    SAWADA Takuya, TOSHIKAWA Taku, YOSHIKAWA Kumpei, TAKATA Hidehiro, NII Koji, NAGATA Makoto

    IEICE, Apr. 2012, IEICE Transactions on Electronics, E95-C (4), 586 - 593, English

    [Refereed]

    Scientific journal

  • Modeling and Analysis of Substrate Noise Coupling in Analog and RF ICs (Invited)

    NAGATA Makoto

    Feb. 2012, IEICE Transactions on Fundamentals, Vol. E95-A, No. 2, pp. 430-438, English

    [Refereed]

    Scientific journal

  • On-Chip In-Place Measurements of Vth and Signal/Substrate Response of Differential Pair Transistors

    BANDO Yoji, TAKAYA Satoshi, OHKAWA Toru, TAKARAMOTO Toshiharu, YAMADA Toshio, SOUDA Masaaki, KUMASHIRO Shigetaka, MOGAMI Tohru, NAGATA Makoto

    Jan. 2012, IEICE Transactions on Electronics, Vol. E95-C, No. 1, pp. 137-145, English

    [Refereed]

    Scientific journal

  • In-Tier Diagnosis of Power Domains in 3D TSV Ics

    ARAGA Yuuki, NAGATA Makoto, Geert Van der Plas, Jaemin Kim, Nikolaos Minas, Pol Marchal, Youssef Travaly, Michael Libois, Antonio La Manna Wenqi Zhang, Eric Beyne

    Jan. 2012, IEEE International 3D System Integration Conference, #7-2, pp. 7.2.1-7.2.4, English

    [Refereed]

    International conference proceedings

  • Extraction of Lumped RC Elements Representing Substrate Coupling of RF Devices

    AZUMA Naoya, KANDA Yasutaka, NAGATA Makoto

    Dec. 2011, IEEE International Symposium on Radio-Frequency Integration Technology, #FR2B-3, pp. 217-220, English

    [Refereed]

    International conference proceedings

  • Evaluation of Substrate Noise Coupling in RFICs (Invited)

    NAGATA Makoto, LIN Xihua, AZUMA Naoya, YAMAGUCHI Masahiro

    Dec. 2011, IEEE International Symposium on Radio-Frequency Integration Technology, 1), #TH3B-1, pp. 141-144, English

    [Refereed]

    International conference proceedings

  • Measurements and Co-Simulation of On-Chip and On-Board AC Power Noise in Digital Integrated Circuits

    YOSHIKAWA Kumpei, SASAKI Yuta, ICHIKAWA Kouji, SAITO Yoshiyuki, NAGATA Makoto

    Nov. 2011, IEEE 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits, #S3P2, pp. 76-81, English

    [Refereed]

    International conference proceedings

  • Immunity Evaluation of SRAM Core Using DPI with On-Chip Diagnosis Structures

    SAWADA Takuya, TOSHIKAWA Taku, YOSHIKAWA Kumpei, TAKATA Hidehiro, NII Koji, NAGATA Makoto

    Nov. 2011, IEEE 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits, #S2P6, pp. 65-70, English

    [Refereed]

    International conference proceedings

  • Performance of Integrated Magnetic Thin Film Noise Suppressor Applied to CMOS Noise Test Chips

    Masahiro Yamaguchi, Sho Muroga, Yasushi Endo, Wataru Kodate, Kumpei Yoshikawa, Yuta Sasaki, Makoto Nagata

    Performance of soft magnetic CoZrNb film as a thin film noise suppressor and its application to an noise emulator chip fabricated by 90/65nm CMOS technology are discussed. Intra-chip decoupling was studied by the electromagnetic coupling between two miniature coils made on a noise test chip implemented in CMOS 90nm technology. Inter-chip decoupling (radiation) was evaluated by the coupling between parallel line currents implemented in CMOS 65nm technology chip and off-chip planar shielded-loop coil type miniature magnetic probe. The intra-decoupling was as large as 10 dB at 1.8 GHz where ferromagnetic resonance can be maximized. The inter-decoupling was 7.7 dB at 200 MHz where magnetic shielding is effective. It is found that the product of magnetic film thickness and permeability is a good measure to evaluate magnetic shielding effectiveness for IC chip level inter-decoupling.

    IEEE, 2011, 2011 41ST EUROPEAN MICROWAVE CONFERENCE, #03-3, pp. 49-52, 49 - 52, English

    [Refereed]

    International conference proceedings

  • Masaaki Soda, Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata

    A single tone pseudo-noise generator with a harmonic-eliminated waveform is proposed for measuring noise tolerance of analog IPs. In the waveform, the harmonics up to the thirteenth are eliminated by combining seven rectangular waves with 22.5- degree spacing phases. The proposed waveform includes only high region frequency harmonic components, which are easily suppressed by a low-order filter. This characteristic enables simple circuit implementation for a sine wave generator. In the circuit, the harmonic eliminated waveform generator is combined with a current controlled oscillator and a frequency adjustment circuit. The single tone pseudo-noise generator can generate power line noise from 20 MHz to 220 MHz with I MHz steps. The SFDR of 40 dB is obtained at the noise frequency of 100 MHz. The circuit enables the measurement of frequency response characteristics measurements such as PSRR.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jun. 2011, IEICE TRANSACTIONS ON ELECTRONICS, E94C (6), 1024 - 1031, English

    [Refereed]

    Scientific journal

  • A Fast Power Current Analysis Methodology Using Capacitor Charging Model for Side Channel Attack Evaluation

    FUJIMOTO Daisuke, NAGATA Makoto, KATASHITA Toshihiro, SASAKI Akihiko, HORI Yohei, SATOH Akashi

    Jun. 2011, 2011 IEEE Intl. Symp. Hardware-Oriented Security and Trust, #P35, pp. 87-92, English

    [Refereed]

    International conference proceedings

  • Takushi Hashida, Yuuki Araga, Makoto Nagata

    A diagnosis testbench of analog IP cores characterizes their coupling strengths against on-chip environmental disturbances, specifically with regard to substrate voltage variations. The testbench incorporates multi-tone digital noise generators and a precision waveform capture with multiple probing channels. A prototype test bench fabricated in a 90-nm CMOS technology demonstrates the diagnosis of substrate coupling up to 400 MHz with dynamic range of more than 60 dB. The coefficients of noise propagation as well as noise coupling on a silicon substrate are quantitatively derived for analog IP cores processed in a target technology, and further linked with noise awared EDA tooling for the successful adoption of such IP cores in SoC integration.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Jun. 2011, IEICE TRANSACTIONS ON ELECTRONICS, E94C (6), 1016 - 1023, English

    [Refereed]

    Scientific journal

  • An On-Chip Waveform Capturer for Diagnosing Off-Chip Power Delivery (Invited)

    YOSHIKAWA Kumpei, HASHIDA Takushi, NAGATA Makoto

    May 2011, 2011 IEEE Intl. Conf. on Integrated Circuit Design and Technology, #C3, English

    [Refereed]

    International conference proceedings

  • A Diagnosis Testbench of Analog IP Cores Against On-Chip Environmental Disturbances

    Takushi Hashida, Yuuki Araga, Makoto Nagata

    Analog IP cores exhibit a multivariate response to dynamic variations of an operation environment, that are typically represented by power and substrate voltage changes. A testbench provides a silicon area to embed and diagnose custom IP cores with power delivery and substrate networks, where the area is surrounded by on-chip precision waveform capturing and configurable power and substrate noise generation circuits. The coefficients of noise propagation and noise coupling are quantitatively derived for fabless IP cores processed in a target technology, that will be further linked with EDA tooling for the successful adoption of such IP cores in SoC integration.

    IEEE COMPUTER SOC, 2011, 2011 IEEE 29TH VLSI TEST SYMPOSIUM (VTS), 70 - 75, English

    [Refereed]

    International conference proceedings

  • Evaluation of Thin Film Noise Suppressor Applied to Noise Emulator Chip Implemented in 65 nm CMOS Technology

    MUROGA Sho, ENDO Yasushi, KODATE Wataru, SASAKI Yoshiaki, YOSHIKAWA Kumpei, SASAKI Yuta, NAGATA Makoto, YAMAGUDHI Masahiro

    Apr. 2011, IEEE Intl. Magnetics Conference (Intermag 2011), #HH-03, pp. 1-4, English

    [Refereed]

    International conference proceedings

  • Takushi Hashida, Makoto Nagata

    An on-chip waveform capturer exhibits 8.8-bit effective accuracy at a 5-ps timing resolution and 190 mu V voltage, with an effective bandwidth of 700 MHz in a 65-nm CMOS prototype. Voltage by a digital-to-analog converter with selectable slopes and offsets is linearly translated into timing, that is used for strobing a waveform. Programmable timing and voltage generation as well as selective input channels are intended for exhaustive power noise measurements on power delivery networks (PDNs) across rail-to-rail voltage domains in a chip. The measurement procedures are totally governed by an embedded controller. The waveform capturer, in combination with a PDN exciter, realizes in situ derivation of resonance parameters by assembling oscillatory waveforms. A power noise reduction of more than 50% is accomplished through on-chip PDN diagnosis, in which the operation frequencies are selected such that the periodical appearance of PDN resonance is prevented.

    IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, Apr. 2011, IEEE JOURNAL OF SOLID-STATE CIRCUITS, 46 (4), 789 - 796, English

    [Refereed]

    Scientific journal

  • Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata

    A continuous-time waveform monitoring technique for quality on-chip power noise measurements features matched probing performance among a variety of voltage domains of interest in a VLSI circuit, covering digital Vdd, analog Vdd, as well as at Vss, and multiple probing capability at various locations on power planes. A calibration flow eliminates the offset as well as gain errors among probing channels. The consistency of waveforms acquired by the proposed continuous-time monitoring and sampled-time precise digitization techniques is ensured. A 90-nm CMOS on-chip monitor prototype demonstrates dynamic power supply noise measurements with +/- 200 mV at 2.5 V, 1.0 V. and 0.0 V, respectively, with less than 4 mV deviation among 240 probing channels.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Apr. 2011, IEICE TRANSACTIONS ON ELECTRONICS, E94C (4), 495 - 503, English

    [Refereed]

    Scientific journal

  • Accurate Analysis of Substrate Sensitivity of Active Transistors in an Analog Circuit

    Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata

    A substrate network tailored for a variety of transistor geometry including channel sizes, fingering and folding, and shapes and placements of guard bands, extends the capability and accuracy of full-chip noise coupling analysis of mixed technology VLSI integration. Analysis of substrate sensitivity of differential amplifiers in a 90 nm CMOS technology with more than 64 different geometry and operating conditions well agrees with on-chip substrate coupling measurements, with the discrepancy within 3 dB.

    IEEE, 2011, 2011 12TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), #1B.4, pp. 56-61, 56 - 61, English

    [Refereed]

    International conference proceedings

  • Yoji Bando, Makoto Nagata

    Power noise waveforms of a 32-bit microprocessor were on-chip measured in a 90-nm CMOS technology. A dedicated measurement system combines an embedded programming environment and a measurement flow that ensures acquisition of noise waveforms during designated arithmetic operation. Power noise exhibits clear relation with the contents of computation, where the magnitude of power noise reflects the occupancy ratio of computing resources of a microprocessor. The level of correlation is shown to be different among static and dynamic portions of power noise. It is concluded that practical power noise analysis requires the higher-level abstraction of a large-scale integrated digital system.

    IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, Feb. 2011, IEICE ELECTRONICS EXPRESS, 8 (3), 182 - 188, English

    [Refereed]

    Scientific journal

  • On-Chip Sine-Wave Noise Generator for Analog IP Noise Tolerance Measurements

    SOUDA Masaaki, BANDO Yoji, TAKAYA Satoshi, OHKAWA Toru, TAKARAMOTO Toshiharu, YAMADA Toshio, KUMASHIRO Shigetaka, MOGAMI Tohru, NAGATA Makoto

    Nov. 2010, Proceedings of IEEE Asian Solid-State Circuits Conference 2010, #4-6, pp. 125-128, English

    [Refereed]

    International conference proceedings

  • On-Chip Waveform Capture and Diagnosis of Power Delivery in SoC Integration

    HASHIDA Takushi, NAGATA Makoto

    Jun. 2010, Digest of Technical Papers, IEEE 2010 Symposium on VLSI Circuits, #12-2, pp. 121-122, English

    [Refereed]

    International conference proceedings

  • Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails

    HASHIDA Takush, NAGATA Makoto

    Jun. 2010, IEICE Transactions on Electronics, Vol. E93-C, No. 6, pp. 842-848, English

    [Refereed]

    Scientific journal

  • An On-Chip Waveform Capturing Technique Pursuing Minimum Cost of Integration

    ARAGA Yuuki, HASHIDA Takushi, NAGATA Makoto

    Jun. 2010, Proceedings of IEEE 2010 International Symposium on Circuits and Systems, #C3L-M.4, pp. 3557-3560, English

    [Refereed]

    International conference proceedings

  • An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology

    MATSUNO Tetsuro, FUJIMOTO Daisuke, KOSAKA Daisuke, HAMANISHI Naoyuki, TANABE Ken, SHIOCHI Masazumi, NAGATA Makoto

    Jun. 2010, IEICE Transactions on Electronics, Vol. E93-C, No. 6, pp. 820-826, English

    [Refereed]

    Scientific journal

  • Reference Complementary Metal-Oxide-Semiconductor Circuits and Test Structures for Evaluation of Dynamic Noise in Power Delivery Networks

    MATSUNO Tetsuro, KOSAKA Daisuke, NAGATA Makoto

    Apr. 2010, Japanese Journal of Applied Physics, Vol. 49, pp. 04DE01-1-04DE01-5, English

    [Refereed]

    Scientific journal

  • On-Chip In-situ Measurements of Vth and AC Gain of Differential Pair Transistors

    BANDO Yoji, TAKAYA Satoshi, OHKAWA Toru, TAKARAMOTO Toshiharu, YAMADA Toshio, SOUDA Masaaki, KUMASHIRO Shigetaka, NAGATA Makoto

    Mar. 2010, Proc. IEEE Intl. Conference on Micro Test Structures 2010, #10.4, pp. 232-235, English

    [Refereed]

    International conference proceedings

  • Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits

    MATSUNO Tetsuro, KOSAKA Daisuke, NAGATA Makoto

    Feb. 2010, IEICE Transactions on Fundamentals, Vol.E93-A, No.2, pp. 440-447, English

    [Refereed]

    Scientific journal

  • On-Chip Power Noise Measurements of High-Frequency CMOS Digital Circuits

    MATSUNO Tetsuro, NAGATA Makoto

    Nov. 2009, Proc. IEEE Intl. SoC Design Conference 2010, #S9.3, pp. 198-201, English

    [Refereed]

    International conference proceedings

  • Evaluation of Environmental Noise Susceptibility of RF Circuits Using Direct Power Injection

    AZUMA Naoya, USAMI Yu, NAGATA Makoto

    Nov. 2009, Proc. 2009 IEEE Intl. Symp. on Radio-Frequency Integration Technology, #TH-IF-11, pp. 80-83, English

    [Refereed]

    International conference proceedings

  • An On-Chip Continuous Time Power Supply Noise Monitoring Technique

    BANDO Yoji, TAKAYA Satoshi, NAGATA Makoto

    Nov. 2009, Proc. IEEE Asian Solid-State Circuits Conference 2009, #3-4, pp. 97-100, English

    [Refereed]

    International conference proceedings

  • A Reference CMOS Circuit Structure for Evaluation of Dynamic Voltage Variation in Power Delivery Networks

    MATSUNO Tetsuro, KOSAKA Daisuke, NAGATA Makoto

    Sep. 2009, Ext. Abst. 2009 Intl. Conf. on Solid State Devices and Materials, #D-7-1, pp. 1068-1069, English

    [Refereed]

    International conference proceedings

  • A Full Chip Integrated Power and Substrate Noise Analysis Framework for Mixed-Signal SoC Design

    KOSAKA Daisuke, BANDO Yoji, YOKOMIZO Goichi, TSUBOI Kunihiko, LI Ying Shiun, LIN Shen, NAGATA Makoto

    Sep. 2009, Proc. IEEE 2009 Custom Integrated Circuits Conference, #M-08, pp. 219-222, English

    [Refereed]

    International conference proceedings

  • A 6-bit Arbitrary Digital Noise Emulator in 65nm CMOS Technology

    MATSUNO Tetsuro, FUJIMOTO Daisuke, KOSAKA Daisuke, HAMANISHI Naoyuki, TANABE Ken, SHIOCHI Masazumi, NAGATA Makoto

    Sep. 2009, Proc. IEEE 2009 Custom Integrated Circuits Conference, #M-08, pp. 187-190, English

    [Refereed]

    International conference proceedings

  • Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations

    FUKAZAWA Mitsuya, KURIMOTO Masanori, AKIYAMA Rei, TAKATA Hidehiro, NAGATA Makoto

    Apr. 2009, IEICE Transactions on Electronics, Vol.E92-C, No.4, pp. 475-482, English

    [Refereed]

    Scientific journal

  • Chip-to-Chip Half Duplex Data Communication at 135 Mbps Over Power-Supply Rails

    HASHIDA Takushi, BANDO Yoji, NAGATA Makoto

    Nov. 2008, Proc. IEEE Asian Solid-State Circuits Conference 2008, #7-3, pp. 209-212, English

    [Refereed]

    International conference proceedings

  • Current-Mode Transceiver with Nonfeedback Clock Recovery Capability for Mobile Applications

    YOSHIKAWA Takefumi, Ogino Tetsuhiro, NAGATA Makoto

    Sep. 2008, IEICE Transactions on Electronics, Vol.E91-C, No.9, pp. 1453-1462, English

    [Refereed]

    Scientific journal

  • Experimental Evaluation of Digital-Circuit Susceptibility to Voltage Variation in Dynamic Frequency Scaling

    FUKAZAWA Mitsuya, KURIMOTO Masanori, AKIYAMA Rei, TAKATA Hidehiro, NAGATA Makoto

    Jun. 2008, IEEE 2008 Symposium on VLSI Circuits Digest of Technical Papers, #15-3, pp. 150-151, English

    [Refereed]

    International conference proceedings

  • Measurement-Based Analysis of Electromagnetic Immunity in LSI Circuit Operation

    ICHIKAWA Kouji, TAKAHASHI Yuki, SAKURAI Yukihiko, TSUDA Takahiro, IWASE Isao, NAGATA Makoto

    Apr. 2008, IEICE Transactions on Electronics, Vol.E91-C, No.6, pp. 936-944, English

    [Refereed]

    Scientific journal

  • Chip-Level Substrate Coupling Analysis with Reference Structures for Verification

    KOSAKA Daisuke, NAGATA Makoto, MURASAKA Yoshitaka, IWATA Atsushi

    Dec. 2007, IEICE Transactions on Fundamentals, Vol. E90-A, No. 12, pp. 2651-2, English

    [Refereed]

    Scientific journal

  • A Low-Power Current-Mode Tranceiver with Simultaneous Data and Clock Transmission at 625 Mb/s, 3 mW in 1.5 V for Mobile Applications

    OGINO Tetsuhiro, YOSHIKAWA Takefumi, NAGATA Makoto

    Nov. 2007, IEEE Asian Solid-State Circuits Conference 2007 (A-SSCC), #5-5, pp. 160-163, English

    [Refereed]

    International conference proceedings

  • An On-Chip Multi-Channel Waveform Monitor for Diagnosis of Systems-on-Chip Integration

    NOGUCHI Koichiro, NAGATA Makoto

    Oct. 2007, IEEE Transactions on VLSI Systems, Vol. 15, No. 10, pp. 1101-1110, English

    [Refereed]

    Scientific journal

  • Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for Isolation

    KOSAKA Daisuke, NAGATA Makoto, MURASAKA Yoshitaka, IWATA Atsushi

    Sep. 2007, IEEE 2007 Custom Integrated Circuits Conference (CICC), #27-3, pp. 849-852,, English

    [Refereed]

    International conference proceedings

  • On-Chip Measurements Complementary to Design Flow for Integrity in SoCs

    NAGATA Makoto

    Jun. 2007, Proceedings of Design Automation Conference 2007(DAC 2007), #22.4, pp. 400-403, English

    [Refereed]

    International conference proceedings

  • On-Chip Analog Circuit Diagnosis in Systems-on-Chip Integration

    NOGUCHI Koichiro, HASHIDA Takushi, NAGATA Makoto

    Jun. 2007, IEICE Transactions on Electronics, Vol. E90-C, No. 6, pp. 1189-11, English

    [Refereed]

    Scientific journal

  • Experimental Verification of Power Supply Noise Modeling for EMI Analysis through On-Board and On-Chip Noise Measurements

    ICHIKAWA Koji, TAKAHASHI Yuki, NAGATA Makoto

    Jun. 2007, IEICE Transactions on Electronics, Vol. E90-C, No. 6, pp. 1282-12, English

    [Refereed]

    Scientific journal

  • A Mixed Circuit and System Level Simulation Technique of Collision-Resistant RFID Systems

    FUKUMIZU Yohei, GOCHI Naoki, NAGATA Makoto, TAKI Kazuo

    Jun. 2007, IEICE Transactions on Electronics, Vol. E90-C, No. 6, pp. 1299-13, English

    [Refereed]

    Scientific journal

  • On-Die Monitoring of Substrate Coupling for Mixed-Signal Circuit Isolation

    KOSAKA Daisuke, FUJIWARA Masaki, DANJO Takumi, NAGATA Makoto

    Apr. 2007, Japanese Journal of Applied Physics, Vol. 46, No. 4B, pp. 2244-2251, English

    [Refereed]

    Scientific journal

  • Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias

    KOMATSU Yoshihide, ISHIBASHI Koichiro, NAGATA Makoto

    Mar. 2007, IEICE Transactions on Electronics, Vol.E90-C, No.4, pp. 692-698, English

    [Refereed]

    Scientific journal

  • Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations

    MORIMOTO Masao, NAGATA Makoto, TAKI Kazuo

    Mar. 2007, IEICE Transactions on Electronics, Vol.E90-C, No.4, pp. 675-682, English

    [Refereed]

    Scientific journal

  • On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications

    SATO Tomio, INOUE Atsuki, SHIOTA Tetsuyoshi, INOUE Tomoko, KAWABE Yukihito, HASHIMOTO Tetsutarou, IMAMURA Toshifumi, MURASAKA Yoshitaka, NAGATA Makoto, IWATA Atsushi

    Feb. 2007, 2007 IEEE International Solid-State Circuits Conference (ISSCC 2007), Digest of Technical Papers, #16.3, pp. 290-291, English

    [Refereed]

    International conference proceedings

  • Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs

    FUKAZAWA Mitsuya, MATSUNO Tetsuro, UEMURA Toshifumi, AKIYAMA Rei, KAGEMOTO Tetsuya, MAKINO Hiroshi, TAKATA Hidehiro, NAGATA Makoto

    Feb. 2007, 2007 IEEE International Solid-State Circuits Conference (ISSCC 2007), Digest of Technical Papers, #16.2, pp. 288-289, English

    [Refereed]

    International conference proceedings

  • Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits

    KOSAKA Daisuke, NAGATA Makoto, MURASAKA Yoshitaka, IWATA Atsushi

    Feb. 2007, IEICE Transactions on Fundamentals, Vol.E90-A, No.2, pp. 380-387, English

    [Refereed]

    Scientific journal

  • Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation (Invited)

    Ali Afzali-Kusha, NAGATA Makoto, Nishath K. Verghese, David J. Allstot

    Dec. 2006, Proceedings of the IEEE, Vol. 94, No. 12, pp. 2109-2138, English

    [Refereed]

    Scientific journal

  • Measurement-Based Analysis of Delay Variation Induced by Dynamic Power Supply Noise

    FUKAZAWA Mitsuya, NAGATA Makoto

    Nov. 2006, IEICE Transactions on Electronics, Vol.E89-C, No.11, pp. 1559-156, English

    [Refereed]

    Scientific journal

  • Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach

    FUKUMIZU Yohei, NAGATA Makoto, TAKI Kazuo

    Nov. 2006, IEICE Transactions on Electronics, Vol.E89-C, No.11, pp. 1581-159, English

    [Refereed]

    Scientific journal

  • An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs

    SHIMAZAKI Kenji, NAGATA Makoto, FUKAZAWA Mitsuya, MIYAHARA Shingo, HIRATA Masaki, SATO Kazuhiro, TSUJIKAWA Hiroyuki

    Nov. 2006, IEICE Transactions on Electronics, Vol.E89-C, No.11, pp. 1535-154, English

    [Refereed]

    Scientific journal

  • On-Die Monitoring of Substrate Couplig for Mixed-Signal Circuit Isolation

    KOSAKA Daisuke, FUJIWARA Masaki, DANJO Takumi, NAGATA Makoto

    Sep. 2006, Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials (SSDM 2006), C-1-6, pp. 62-63, English

    [Refereed]

    International conference proceedings

  • On-Chip Analog Circuit Diagnosis in Systems-on-Chip Integration

    NOGUCHI Koichiro, HASHIDA Takushi, NAGATA Makoto

    Sep. 2006, IEEE 32th European Solid-State Circuits Conference (ESSCIRC 2006), A3L-E1, pp. 118-121, English

    [Refereed]

    International conference proceedings

  • Evaluation of LSI Power-Supply Noise Caused by Injected RF Power Using LECCS Model

    NAKAYAMA .T, TAKAHASHI Eiji, SAITO.Y, SHIMAZAKI Kenji, NAGATA Makoto, WADA Osami

    Sep. 2006, EMC Europe, PWeB-2, pp. 209-214, English

    [Refereed]

    International conference proceedings

  • Delay Variation Analysis in Consideration of Dynamic Power Supply Noise Waveform

    FUKAZAWA Mitsuya, NAGATA Makoto

    Sep. 2006, IEEE 2006 Custom Integrated Circuits Conference (CICC), #29-5, pp. 865-868, English

    [Refereed]

    International conference proceedings

  • An On-Chip Multi-Channel Rail-to-Rail Signal Monitoring Technique for Sub-100-nm Digital Signal Integrity

    NOGUCHI Koichiro, NAGATA Makoto

    Jun. 2006, IEICE Transactions on Electronics, Vol.E89-C, No.6, pp. 761-768, English

    [Refereed]

    Scientific journal

  • An Integrated Timing and Dynamic Noise Verification Methodology for Nanometer CMOS SoC Designs (Inited)

    SHIMAZAKI Kenji, NAGATA Makoto, SATO Kazuhiro

    May 2006, 2006 International Conference on IC Design & Technology (ICICDT), #C-1, pp. 44-48, English

    [Refereed]

    International conference proceedings

  • Multi-Ported Register File for Reducing the Impact of PVT Variation

    IKEDA Yuuichirou, SUMITA Masaya, NAGATA Makoto

    Mar. 2006, IEICE Transactions on Electronics, Vol. E89-C;No. 3;pp. 356-363, English

    [Refereed]

    Scientific journal

  • Communication Scheme for a Highly Collision-Resistive RFID System

    FUKUMIZU Yohei, OHNO Shuji, NAGATA Makoto, TAKI Kazuo

    Feb. 2006, IEICE Transactions on Fundamentals, Vol. E89-A;No. 2;pp. 408-415, English

    [Refereed]

    Scientific journal

  • Equivalent Circuit Modeling of Guard Ring Structures for Evaluation of Substrate Crosstalk Isolation

    KOSAKA Daisuke, NAGATA Makoto

    Jan. 2006, Proceedings of Asia and South Pacific Design Automation Conference 2006, pp. 677-682, English

    [Refereed]

    International conference proceedings

  • A Built-in Power Supply Noise Probe for Digital LSIs

    FUKAZAWA Mitsuya, NOGUCHI Koichiro, NAGATA Makoto, TAKI Kazuo

    Jan. 2006, Proceedings of Asia and South Pacific Design Automation Conference 2006, pp. 106-107, English

    [Refereed]

    International conference proceedings

  • Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition

    MORIMOTO Masao, TANAKA Yoshinori, NAGATA Makoto, TAKI Kazuo

    Dec. 2005, IEICE Transactions on Fundamentals, Vol. E88-A;No. 12;pp. 3324-333, English

    [Refereed]

    Scientific journal

  • Measurements of Digital Signal Delay Variation Due to Dynamic Power Supply Noise

    FUKAZAWA Mitsuya, NAGATA Makoto

    Nov. 2005, 2005 IEEE Asian Solid-State Circuits Conference Proceedings of Technical Papers, pp. 165-168, English

    [Refereed]

    International conference proceedings

  • High-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition

    MORIMOTO Masao, NAGATA Makoto, TAKI Kazuo

    Oct. 2005, IEICE Transactions on Electronics, Vol. E88-C;No. 10;pp. 2001-200, English

    [Refereed]

    Scientific journal

  • Substrate-Noise and Random-Fluctuations Reduction with Self-Adjusted Forward Body Bias

    KOMATSU Yoshihide, ISHIBASHI Koichiro, YAMAMOTO Masaharu, TSUKADA Toshiro, SHIMAZAKI Kenji, FUKAZAWA Mitsuya, NAGATA Makoto

    Sep. 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, pp. 35-38, English

    [Refereed]

    International conference proceedings

  • An On-Chip Multi-Channel Waveform Monitor for Mixed Signal VLSI Diagnostics

    NOGUCHI Koichiro, NAGATA Makoto

    Sep. 2005, Proceedings of the 31th European Solid-State Circuits Conference, pp. 295-298, English

    [Refereed]

    International conference proceedings

  • An Integrated Timing and Dynamic Supply Noise Verification for Nano-meter CMOS SoC Designs

    SHIMAZAKI Kenji, FUKAZAWA Mitsuya, NAGATA Makoto, MIYAHARA Shingo, HIRATA Masaaki, SATO Kazuhiro, TSUJIKAWA Hiroyuki

    Sep. 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, pp. 31-34, English

    [Refereed]

    International conference proceedings

  • Isolation Strategy against Substrate Coupling in CMOS Mixed-Signal/RF Circuits

    KOSAKA Daisuke, NAGATA Makoto, HIRAOKA Yukio, IMANISHI Ikuo, MAEDA Masakatsu, MURASAKA Yoshitaka, IWATA Atsushi

    Jun. 2005, 2005 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 276-279, English

    [Refereed]

    International conference proceedings

  • Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits

    SHIMAZAKI Kenji, NAGATA Makoto, OKUMOTO Takeshi, HIRANO Shozo, TSUJIKAWA Hiroyuki

    Apr. 2005, IEICE Transactions on Electronics, Vol. E88-C;pp. 589-596, English

    [Refereed]

    Scientific journal

  • A Built-in Technique for Probing Power Supply and Ground Noise Distribution Within Large-Scale Digital Integrated Circuits

    NAGATA Makoto, OKUMOTO Takeshi, TAKI Kazuo

    Apr. 2005, IEEE Journal of Solid-State Circuits, Vol. 40;pp. 813-819, English

    [Refereed]

    Scientific journal

  • On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits

    NOGUCHI Koichiro, NAGATA Makoto

    Mar. 2005, Proceedings of the Design Automation and Test in Europe 2005, Volume1-2C1, 146-151, English

    [Refereed]

    International conference proceedings

  • Substrate Integrity beyond 1 GHz

    NAGATA Makoto, FUKAZAWA Mitsuya, HAMANISHI Naoyuki, SHIOCHI masazumi, IIDA Tetsuya, WATANABE Junichiro, MURASAKA Yoshitaka, IWATA Atsushi

    Feb. 2005, 2005 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 266-267, English

    [Refereed]

    Scientific journal

  • Full-chip Vectorless Dynamic Power Integrity Analysis and Verification Against 100uV/100ps-Resolution Measurement

    LIN Shen, NAGATA Makoto, SHIMASAKI Kenji, SATOH Kazuhiro, SUMITA Masaya, TSUJIKAWA Hiroyuki, YANG T Andrew

    Oct. 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 509-512, English

    [Refereed]

    International conference proceedings

  • Design of RFID Front-end Circuitry Enabling CDMA-based Collision Resistance

    FUKUMIZU Yohei, OHNO Shuji, NAGATA Makoto, TAKI Kazuo

    Sep. 2004, Extended Abstructs of the 2004 International Conference on solid-state Devices and Materials 2004, 400-401, English

    [Refereed]

    Scientific journal

  • A Design of Transponder IC for Highly Collision Resistive RFID Systems

    FUKUMIZU Yohei, OHNO Shuji, NAGATA Makoto, TAKI Kazuo

    Aug. 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, 438-439, English

    [Refereed]

    International conference proceedings

  • A Built-in Technique for Probing Power-Supply Noise Distribution within Large-Scale Digital Integrated Circuits

    OKUMOTO Takeshi, NAGATA Makoto, TAKI Kazuo

    Jun. 2004, 2004 Symposium on VLSI Circuits Digest of Technical Papers, 98-101, English

    [Refereed]

    Scientific journal

  • Dynamic Power-Supply and Well Noise Measurement and Analysis for High Frequency Body-Biased Cirsuits

    SHIMAZAKI Kenji, NAGATA Makoto, OKUMOTO Takeshi, HIRANO Shouzou, TSUJIKAWA Hiroyuki

    2004, 2004 Symposium on VLSI Circuits Digest of Technical Papers, 94-97, English

    [Refereed]

    Scientific journal

  • A Substrate Noise Analysis Methodology for Large-Scale Mixed-Signal Ics

    CHU Kung Wen, VERGHESE Nishath, CHO Heayn-Jun, SHIMAZAKI Kenji, TSUJIKAWA Hiroyuki, HIRANO Shouzou, DOUSHOH Shirou, NAGATA Makoto, IWATA Atsushi, OHMOTO Takafumi

    2003, Proceedings of IEEE 2003 Custom Integrated Circuits Conference, 369-372, English

    [Refereed]

    International conference proceedings

  • A Multinanodot Floating-Gate MOSFET Circuit for Spiking Neuron Models.

    MORIE Takashi, MATSUURA Tomohiro, NAGATA Makoto, IWATA Atsushi

    2003, IEEE Transactions on Nanotechnology, 2(3),158-164, English

    [Refereed]

    Scientific journal

  • A Highly Collision Resistive RFID System

    FUKUMIZU Yohei, OHNO Shuji, NAGATA Makoto, TAKI Kazuo

    2003, Proceedings of 5th Asia-Pacific Symposium on Information and Telecommunication Technologies, 223-228, English

    [Refereed]

    International conference proceedings

  • High Throughput/Gate AES Hardware Architectures Based on Datapath Compression

    Rei Ueno, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Naofumi Homma

    Apr. 2020, 69 (4), 534 - 548, English

    [Refereed]

  • Tomoaki Mahiko, Taro Yoshikawa, Makoto Nagata

    IOP Publishing, Jan. 2020, Japanese Journal of Applied Physics, 59 (SLLD04), 1 - 7, English

    [Refereed]

    Scientific journal

MISC

  • Deployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security

    Makoto Nagata

    Mar. 2020, The Innovation Platform, 340 - 341, English

  • 電子産業を支える集積回路:若手人材の育成に向けた取組み

    永田 真

    Jan. 2020, 電子情報通信学会エレクトロニクスソサイエティ・ニュースレター, 176, 23, Japanese

  • Hardware Security and Safety

    Makoto Nagata

    Nov. 2019, Sci TechEurope Quarterly, 33, 38 - 39, English

  • レーザーフォールト攻撃対策である電源遮断回路実装時のサイドチャネル耐性評価

    郡 義弘, 藤本大介, 林 優一, 三浦典之, 永田 真, 崎山一男

    Mar. 2018

    Summary national conference

  • インピーダンス計測に基づくICの周辺に実装されたHT検出手法の検討

    任 翔太, 藤本 大介, 林 優一, 三浦 典之, 永田 真, 松本 勉

    15 Dec. 2017, ハードウェアセキュリティフォーラム 2017, Japanese

    Summary national conference

  • ICチップの真正性の確保と対策 -ハードウェアセキュリティの根源的課題に向き合う

    NAGATA Makoto

    Jan. 2015, IEICE Fundamentals Review, Vol. 8 (No. 3), 177 - 182, Japanese

    Introduction scientific journal

  • オンチップノイズの発生と干渉の評価

    NAGATA Makoto

    Oct. 2014, 電磁環境工学情報(EMC), No. 318, 31-37, Japanese

    Introduction scientific journal

  • チップ内外での電源電圧取得によるサイドチャネル漏洩情報の一考察

    藤本 大介, 田中 大智, 三浦 典之, 永田 真, 林 優一, 本間 尚文, 青木 孝文, 堀 洋平, 片下 敏広, 﨑山 一男, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Shivam Bhasin, Jean-Luc Danger

    Jan. 2014, 暗号と情報セキュリティシンポジウム, 2A3-3

  • VLSIにおける電磁環境雑音概説

    NAGATA Makoto

    Dec. 2013, 日本信頼性学会誌(REAJ), Vol. 35, 439 - 440, Japanese

    [Invited]

    Introduction scientific journal

  • SRAMの電源ノイズとイミュニティ

    NAGATA Makoto, YOSHIKAWA Kumpei, MIURA Noriyuki

    Dec. 2013, 日本信頼性学会誌(REAJ), Vol. 35, 441, Japanese

    [Invited]

    Introduction scientific journal

  • サイドチャネル攻撃評価のための電源ノイズモデル

    FUJIMOTO Daisuke, MIURA Noriyuki, NAGATA Makoto

    Oct. 2013, 電磁環境工学情報(EMC), No. 306, 31 - 39, Japanese

    [Invited]

    Introduction scientific journal

  • VLSI電源ノイズの観測・解析と究明

    NAGATA Makoto

    科学技術出版, Feb. 2013, 電磁環境工学情報(EMC), (298), 77 - 88, Japanese

    [Invited]

    Introduction scientific journal

  • 研究室訪問:神戸大学大学院システム情報学研究科情報科学専攻・情報システム(永田)研究室

    NAGATA Makoto

    Mar. 2012, エレクトロニクス実装学会誌, Vol. 15, No. 2, pp. 158, Japanese

    Introduction scientific journal

  • 容量充電モデルを用いた高速なサイドチャネル攻撃評価手法

    FUJIMOTO Daisuke, NAGATA Makoto, KATASHITA Toshihiro, SASAKI Akihiro, HORI Yohei, SATOH Akashi

    Jan. 2012, 電子情報通信学会・2012年暗号と情報セキュリティシンポジウム, 1C2-6, 1-7, Japanese

    Report scientific journal

  • (招待講演)VLSIチップの電源ノイズ~シリコン基板から電磁環境まで~

    NAGATA Makoto

    Dec. 2011, 電子情報通信学会技術報告, ICD2011-131, 143-148, Japanese

    Report scientific journal

  • デジタルLSIにおけるオンチップ・オンボード電源雑音の評価・協調解析手法

    YOSHIKAWA Kumpei, SASAKI Yuta, ICHIKAWA Kouji, Saito Yoshiyuki, NAGATA Makoto

    Nov. 2011, 電子情報通信学会技術報告, ICD2011-95, 73-78, Japanese

    Report scientific journal

  • オンチップ診断機構とDPIを用いたSRAMコアのイミュニティ評価

    SAWADA Takuya, TOSHIKAWA Taku, YOSHIKAWA Kumpei, TAKATA Hidehiro, NII Koji, NAGATA Makoto

    Nov. 2011, 電子情報通信学会技術報告, ICD2011-97, 85-90, Japanese

    Report scientific journal

  • オンチップ環境擾乱に対するアナログIPコアの診断テストベンチの提案

    ARAGA Yuuki, HASHIDA Takushi, UEYAMA Shinichiro, NAGATA Makoto

    Jul. 2011, 電子情報通信学会技術報告, ICD2011-29, 79-84, Japanese

    Report scientific journal

  • アナログ基本回路における基板雑音感度の解析法

    TAKAYA Satoshi, BANDO Yoji, OHKAWA Toru, SOUDA Masaaki, TAKARAMOTO Toshiharu, YAMADA Toshio, KUMASHIRO Shigetaka, MOGAMI Tohru, NAGATA Makoto

    Jul. 2011, 電子情報通信学会技術報告, ICD2011-29, 79-84, Japanese

    Report scientific journal

  • (招待講演)LTE級携帯端末におけるRFICの受信部の低ノイズ化技術―近傍磁界ノイズ計測・対策の立場から―

    YAMAGUCHI Masahiro, ENDO Yasushi, NAGATA Makoto

    Jul. 2011, 電子情報通信学会技術報告, ICD2011-30, 85-90, Japanese

    Report scientific journal

  • グラウンド雑音の評価

    TOSHIKAWA Taku, MASUI Tsubasa, SAWADA Takuya, NAGATA Makoto

    Dec. 2010, 電子情報通信学会技術報告, ICD2010-112, pp. 85-88, Japanese

    Report scientific journal

  • アナログ基本回路の基板雑音感度に関する考察

    TAKAYA Satoshi, BANDO Yoji, HASEGAWA Takashi, OHKAWA TORU, SOUDA Masaaki, TAKARAMOTO Toshiharu, YAMADA Toshio, KUMASHIRO Shigetaka, MOGAMI Tohru, NAGATA Makoto

    Nov. 2010, 電子情報通信学会技術報告, ICD2010-85, pp. 13-17, Japanese

    Report scientific journal

  • SRAMコアにおけるオンチップ電源雑音の発生と注入の評価

    SAWADA Takuya, TOSHIKAWA Taku, MASUI Tsubasa, NAGATA Makoto

    Nov. 2010, 電子情報通信学会技術報告, ICD2010-84, pp. 7-12, Japanese

    Report scientific journal

  • CMOSデジタルLSIにおける電源雑音の周波数成分評価

    YOSHIKAWA Kumpei, MATSUMOTO Hiroshi, SASAKI Yuta, NAGATA Makoto

    Nov. 2010, 電子情報通信学会技術報告, ICD2010-83, pp. 1-6, Japanese

    Report scientific journal

  • 2010VLSIサーキットシンポジウム報告

    NAGATA Makoto

    Sep. 2010, 電子材料, 第49巻、第9号、pp. 54-55, Japanese

    Introduction scientific journal

  • オンチップモニタを用いたSoC電源供給系の診断法

    HASHIDA Takushi, MATSUMOTO Hiroshi, NAGATA Makoto

    Jul. 2010, 電子情報通信学会技術報告, ICD2010-21, pp. 1-4, Japanese

    Report scientific journal

  • オンチップモニタの最簡搭載とチップ内環境の観測

    ARAGA Yuuki, HASHIDA Takushi, NAGATA Makoto

    Jul. 2010, 電子情報通信学会技術報告, ICD2010-21, pp. 5-9, Japanese

    Report scientific journal

  • VLSIチップの電源電流シミュレーション

    NAGATA Makoto

    Jul. 2010, エレクトロニクス実装学会誌, Vol. 13, No. 4, pp. 259-262, Japanese

    [Refereed]

    Introduction scientific journal

  • 90 nm CMOS差動対トランジスタのVthとAC応答のその場評価

    BANDO Yoji, TAKAYA Satoshi, HASEGAWA Takashi, OHKAWA TORU, SOUDA Masaaki, TAKARAMOTO Toshiharu, YAMADA Toshio, KUMASHIRO Shigetaka, MOGAMI Tohru, NAGATA Makoto

    Jul. 2010, 電子情報通信学会技術報告, ICD2010-21, pp. 11-14, Japanese

    Report scientific journal

  • 2010 Symposium on VLSI Circuits Report

    NAGATA Makoto

    Jul. 2010, 電子ジャーナル, 第196号, pp. 58-59, Japanese

    Introduction scientific journal

  • デジタルLSI電源ノイズのオンチップ観測とシミュレーション技術

    NAGATA Makoto, IWATA Atsushi

    Dec. 2009, エレクトロニクス実装学会誌, Vol. 12, No. 7, pp. 581-586, Japanese

    [Refereed]

    Introduction scientific journal

  • (招待講演)電源雑音とプロセッサ動作エラーのオンチップ評価技術

    FUKAZAWA Mitsuya, NAGATA Makoto

    Dec. 2009, 電子情報通信学会技術報告, ICD2009-77, pp. 7-12, Japanese

    Report scientific journal

  • CMOSデジタルLSIにおける電源雑音評価のためのリファレンス回路

    MATSUNO Tetsuro, KOSAKA Daisuke, NAGATA Makoto

    Nov. 2009, 電子情報通信学会技術報告, ICD2009-66, pp. 19-22, Japanese

    Report scientific journal

  • 電源線を用いた135Mbps双方向チップ間通信技術

    HASHIDA Takushi, NAGATA Makoto

    Oct. 2009, 電子情報通信学会技術報告, ICD2009-36, pp. 15-18, Japanese

    Report scientific journal

  • マイクロプロセッサにおける基板ノイズの評価と解析

    BANDO Yoji, KOSAKA Daisuke, YOKOMIZO Goichi, TSUBOI Kunihiko, LI Ying Shiun, LIN Shen, NAGATA Makoto

    Oct. 2009, 電子情報通信学会技術報告, ICD2009-35, pp. 11-14, Japanese

    Report scientific journal

  • 65nmCMOSテクノロジによる6bit任意デジタル雑音エミュレータの開発

    FUJIMOTO Daisuke, MATSUNO Tetsuro, KOSAKA Daisuke, HAMANISHI Naoyuki, TANABE Ken, SHIOCHI Masazumi, NAGATA Makoto

    Oct. 2009, 電子情報通信学会技術報告, ICD2009-34, pp. 7-10, Japanese

    Report scientific journal

  • LSIノイズのオンチップ測定とモデリングによる対策

    NAGATA Makoto

    May 2009, M&E, Vol. 36, No. 5, pp. 119-122, Japanese

    Introduction scientific journal

  • LSI電源雑音の研究

    NAGATA Makoto

    Jan. 2009, 電子情報通信学会誌, Vol. 92, No. 1, pp. 55-60, Japanese

    [Refereed]

    Introduction scientific journal

  • ミックストシグナルSoCのためのオンチップモニタ構築技術

    ARAGA Yuuki, HASHIDA Takushi, NAGATA Makoto

    Dec. 2008, 電子情報通信学会技術報告, ICD2008-108, pp. 39-42, Japanese

    Report scientific journal

  • デジタルLSIにおける電源ノイズと動作不良の解析手法

    SAWADA Takuya, NAGATA Makoto

    Dec. 2008, 電子情報通信学会技術報告, ICD2008-110, pp. 47-50, Japanese

    Report scientific journal

  • LSIのEMC~チップとボードを統合した電源ノイズの評価・解析手法~

    YOSHIKAWA Kumpei, NAGATA Makoto

    Dec. 2008, 電子情報通信学会技術報告, ICD2008-109, pp. 43-46, Japanese

    Report scientific journal

  • 容量充電モデルによるプロセッサ電源雑音解析の高速化手法

    IWASA Fukuichi, SAWADA Takuya, FUKAZAWA Mitsuya, NAGATA Makoto

    Nov. 2008, 電子情報通信学会技術報告, ICD2008-94, pp. 31-36, Japanese

    Report scientific journal

  • オンチップ・マルチチャネルモニタにおける波形取得アルゴリズムの実装と評価

    ARAGA Yuuki, HASHIDA Takushi, NAGATA Makoto

    Oct. 2008, 電子情報通信学会技術報告, ICD2008-80, pp. 125-130, Japanese

    Report scientific journal

  • (招待講演)LSIのノイズ問題:アプローチとチャレンジ

    NAGATA Makoto

    May 2008, 電子情報通信学会技術報告, VLD2008-7, pp. 1-6, Japanese

    Report scientific journal

  • デジタルLSIにおけるオンチップ電源雑音とオフチップ電磁雑音の統合評価

    TAKAHASHI Yuki, ICHIKAWA Koji, NAGATA Makoto

    Jan. 2008, 電子情報通信学会技術報告, ICD2007-140, pp. 5-10, Japanese

    Report scientific journal

  • (特別招待講演)オンチップモニタ技術と電源インテグリティ評価

    NAGATA Makoto

    Jan. 2008, 電子情報通信学会技術報告, ICD2007-145, pp. 35-40, Japanese

    Report scientific journal

  • 携帯機器向け625Mbps/3mW/1.5V電流モード通信回路

    OGINO Tetsuhiro, YOSHIKAWA Takefumi, NAGATA Makoto

    Dec. 2007, 電子情報通信学会技術報告, ICD2007-121, pp. 7-12, Japanese

    Report scientific journal

  • LSIと電子機器の電磁環境性能向上技術

    ICHIKAWA Koji, NAGATA Makoto

    Nov. 2007, 日本信頼性学会誌(REAJ), Vol. 29, No. 7, pp. 446-455, Japanese

    [Refereed]

    Introduction scientific journal

  • 超多重RFIDシステム設計のためのミックストシグナル・シミュレーション手法

    GOCHI Naoki, FUKUMIZU Yohei, NAGATA Makoto

    Oct. 2007, 電子情報通信学会技術報告, ICD2007-107, pp. 47-51, Japanese

    Report scientific journal

  • SoCの電源雑音向け微細埋め込み方連続時間雑音検出手法

    FUKAZAWA Mitsuya, MATSUNO Tetsuro, UEMURA Toshifumi, AKIYAMA Rei, KAGEMOTO Tetsuya, MAKINO Hiroyuki, TAKATA Hidehiro, NAGATA Makoto

    Aug. 2007, 電子情報通信学会技術報告, ICD2007-84, pp. 85-90, Japanese

    Report scientific journal

  • CMOSアナログ回路のオンチップ雑音対策

    NAGATA Makoto

    Jul. 2007, 電磁環境工学情報(EMC), No. 231, pp. 106-113, Japanese

    Introduction scientific journal

  • 基板クロストーク対策のためのガードリング構造の等価回路モデル化手法

    KOSAKA Daisuke, NAGATA Makoto, MURASAKA Yoshitaka, IWATA Atsushi

    Mar. 2007, 電子情報通信学会技術報告, ICD2006-206, 55-60, Japanese

    Report scientific journal

  • サブ100nmデジタルシグナルインテグリティのためのオンチップモニタ

    BANDO Yoji, NOGUCHI Koichiro, NAGATA Makoto

    Mar. 2007, 電子情報通信学会技術報告, ICD2006-207, 61-66, Japanese

    Report scientific journal

  • ミックストシグナル回路における基板結合のオンチップモニタリング

    DANJO Takumi, KOSAKA Daisuke, NAGATA Makoto

    Jan. 2007, 電子情報通信学会技術報告, ICD2006-171, 1-5, Japanese

    Report scientific journal

  • ダイナミック電源雑音波形を考慮したデジタル信号遅延変動解析

    FUKAZAWA Mitsuya, NAGATA Makoto

    Jan. 2007, 電子情報通信学会技術報告, ICD2006-175, 25-29, Japanese

    Report scientific journal

  • オンチップマルチチャネル信号モニタによるアナログ回路動作診断

    SATO Shuichi, HASHIDA Takushi, NOGUCHI Koichiro, NAGATA Makoto

    Dec. 2006, 電子情報通信学会技術報告, ICD2006-158, 85-90, Japanese

    Report scientific journal

  • 高速モードと低消費電力モードを有する2線式論理回路の設計手法

    MORIMOTO Masao, NAGATA Makoto, TAKI Kazuo

    Nov. 2006, 電子情報通信学会技術報告, VLD2006-60, 53-58, Japanese

    Report scientific journal

  • 超多重RFIDシステムの高位モデル化とバックエンド設計への応用

    FUKUMIZU Youhei, NAGATA Makoto, TAKI Kazuo

    Oct. 2006, 電子情報通信学会技術報告, ICD2006-114, 29-34, Japanese

    Report scientific journal

  • オンチップマルチチャネル信号モニタを用いたチップ内部信号測定システムの構築

    HASHIDA Takushi, NOGUCHI Kochiro, NAGATA Makoto

    Jul. 2006, 電子情報通信学会技術報告, ICD2006-64, 23-28, Japanese

    Report scientific journal

  • A Simulation Technique of Dynamic Power Supply/Ground Noise

    UEMURA Toshifumi, NAGATA Makoto

    Mar. 2006, IEICE Technical Report, ICD2005-242;pp. 19-24, Japanese

    Report scientific journal

  • Measurements of Digital Signal Delay Variation Due to Dynamic Power Supply Noise

    FUKAZAWA Mitsuya, NAGATA Makoto

    Jan. 2006, IEICE Technical Report, ICD2005-214;pp. 53-57, Japanese

    Report scientific journal

  • Logic Synthesis Technique for High Speed Dynamic Logic with Asymmetric Slope Transition

    MORIMOTO Masao, NAGATA Makoto, TAKI Kazuo

    Nov. 2005, IEICE Technical Report, ICD2005-153;pp. 25-30, Japanese

    Report scientific journal

  • Substrate-Noise and Random-Fluctuations Reduction with Self-Adjusted Forward Body Bias

    KOMATSU Yoshihide, ISHIBASHI Koichiro, YAMAMOTO Masaharu, TSUKADA Toshiro, SHIMAZAKI Kenji, FUKAZAWA Mitsuya, NAGATA Makoto

    Oct. 2005, IEICE Technical Report, ICD2005-135;pp. 7-12, Japanese

    Report scientific journal

  • Chip-Level Substrate Noise Analysis Technique

    MATSUMOTO Tetsuro, KOSAKA Daisuke, NAGATA Makoto, MURASAKA Yoshitaka, IWATA Atsushi

    Aug. 2005, DA Symposium 2005, pp. 157-162, Japanese

    Report scientific journal

  • SoC Design Flow for Noise and On-Chip Measurements in Sub-100-nm Era (Invited Talk)

    NAGATA Makoto

    Aug. 2005, DA Symposium 2005, pp. 1-6, Japanese

    Report scientific journal

  • Isolation Strategy against Substrate Coupling in CMOS Mixed-Signal/RF Circuits

    KOSAKA Daisuke, NAGATA Makoto, MURASAKA Yoshitaka, IWATA Atsushi

    Aug. 2005, IEICE Technical Report, ICD2005-75;pp. 49-53, Japanese

    Report scientific journal

  • On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits

    NOGUCHI Koichiro, NAGATA Makoto

    Jul. 2005, IEICE Technical Report, ICD2005-40;pp. 1-6, Japanese

    Report scientific journal

  • Evaluation of Digital Crosstalk Noise to CMOS-PLL through Si Substrate

    TOYA Akihiro, KOUNO Ayako, IWATA Atsushi, NAGATA Makoto, MURASAKA Yoshitaka

    Jul. 2005, IEICE Technical Report, ICD2005-41;pp. 7-12, Japanese

    Report scientific journal

  • Substrate Integrity beyond 1 GHz

    FUKAZAWA Mitsuya, NAGATA Makoto, HAMANISHI Naoyuki, SHIOCHI Masazumi, IIDA Tetsuya, WATANABE Junichiro, MURASAKA Yoshitaka, IWATA Atsushi

    May 2005, IEICE Technical Report, ICD2005-39;pp. 61-64, Japanese

    Report scientific journal

  • 非対称な信号遷移を用いた高速論理回路方式

    森本 薫夫, 永田 真, 瀧 和男

    Dec. 2004, 電子情報通信学会技術報告, ICD2004-139, 25-30, Japanese

    Others

  • TD-CDMAによる輻輳制御を用いたRFID向けトランスポンダのIC設計と評価

    大野 修治, 福水 洋平, 永田 真, 瀧 和男

    Dec. 2004, 電子情報通信学会技術報告, ICD2004-138, 19-24, Japanese

    Others

  • 高速ウェル制御回路のダイナミック電源・ウェルノイズの測定および解析方法

    島崎 健二, 永田 真, 奥本 健, 平野 将三, 辻川 洋行

    Sep. 2004, 電子情報通信学会技術報告, ICD2004-138, 35-40, Japanese

    Others

  • 高速論理回路方式ASDDL/ASD-CMOSの論理合成手法

    田中 義則, 森本 薫夫, 永田 真, 瀧 和男

    2004, 電子情報通信学会技術報告, ICD2003-235,37-42, Japanese

    Others

  • デジタル回路における電源/ウェル雑音の高分解能測定技術

    奥本 健, 永田 真, 島崎 健二, 平野 将三, 辻川 洋行

    2004, 電子情報通信学会技術報告, ICD2003-230,7-11, Japanese

    Others

  • デジタルLSIの高速化設計と雑音解析技術

    永田 真, 瀧 和男

    2004, Electronic Design and Solution Fair 2004 資料集, 73-85, Japanese

    Others

  • 超多重応答を可能にするRFIDシステムのLSI設計と評価

    福水 洋平, 大野 修治, 永田 真, 瀧 和男

    2003, DAシンポジウム2003, 73-78, Japanese

    Others

  • 大規模デジタル回路におけるグラウンド雑音の解析

    杉本 智彦, 奥本 健, 永田 真, 瀧 和男

    2003, 電子情報通信学会技術報告, ICD2003-175,211-216, Japanese

    Others

  • 高性能LSIのためのデジタル電源/グラウンド雑音低減化設計及び診断技術の開発

    永田 真

    2003, NEDO平成15年度研究助成事業成果報告会予稿集, 188-193, Japanese

    Others

  • ミックストシグナルLSIのための基盤雑音解析技術

    永田 真, 瀧 和男, 森江 隆, 岩田 穆

    2003, Electronic Design and Solution Fair 2003 資料集, 61-69, Japanese

    [Refereed]

    Others

  • 2線2相式論理回路方式ASDDL/ASD-CMOSの論理合成手法

    田中 義則, 森本 薫夫, 永田 真, 瀧 和男

    2003, 電子情報通信学会技術報告, ICD2003-149,55-60, Japanese

    Others

  • 暗号LSIの電源ノイズシミュレーションによるサイドチャネル解析

    片下 敏宏, 佐藤 証, 永田 真, 藤本 大介

    Jul. 2010, マルチメディア,分散,協調とモバイル (DICOMO2010) シンポジウム講演論文集, 7F-2

Books etc

  • OHM大学テキスト アナログ電子回路

    NAGATA Makoto, OHTA Jun, KOBAYASHI Kazutoshi, HIROSE Tetsuya, MATSUOKA Toshimasa

    Others, オーム社, Mar. 2013, Japanese, ISBN: 9784274213441

    Scholarly book

  • アナログCMOS集積回路の設計--演習編--

    NAGATA Makoto

    Joint work, 丸善, Jan. 2009, Japanese

    Textbook

  • EDA for IC Implementation, Circuit Design, and Process Technology, Eds: Scheffer, Lavagno, and Martin, Chapter 23.3

    Nishath Verghese, NAGATA Makoto

    Joint work, CRC Press, Mar. 2006, English

    Scholarly book

Presentations

  • Side-Channel Attack Analysis and Simulation Techniques

    Makoto Nagata

    33rd International Conference on VLSI Design/19th International Conference on Embedded Design (VLSIdesign 2020), 05 Jan. 2020, English

  • オンチップモニタを用いたチップ・チップ間ノイズ結合の評価

    中川大地, 園田大樹, 門田和樹, 三木拓司, 三浦典之, 永田真

    電子情報通信学会・集積回路研究会, Dec. 2019, Japanese, 奄美大島, Domestic conference

    Poster presentation

  • 半導体集積回路(IC)技術によるECDSAハードウェアモジュールの多重接続性能評価

    高橋佑弥, 門田和樹, 佐藤俊寛, 沖殿貴朗, 三木拓司, 三浦典之, 永田真

    電子情報通信学会・集積回路研究会, Dec. 2019, Japanese, 奄美大島, Domestic conference

    Poster presentation

  • IoTデバイスのエミッション評価と対策

    永田真

    第25回EMC環境フォーラム, Nov. 2019, Japanese, 東京, Domestic conference

    Invited oral presentation

  • Side Channel Attacks (Invited)

    Makoto Nagata

    26th IEEE Electronic Design Process Symposium (EDPS 2019), Oct. 2019, English, Milpitas, International conference

    [Invited]

    Invited oral presentation

  • 不要電波干渉のEMC評価とシステムシミュレーション

    永田真

    Keysight Design Forum 2019, Oct. 2019, Japanese, 東京, Domestic conference

    Oral presentation

  • Deployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security

    Makoto Nagata

    The 14th Asia Joint Conference on Information Security (AsiaJCIS 2019), Aug. 2019, English, 神戸, International conference

    [Invited]

    Invited oral presentation

  • ハードウェアトロイとその対策の技術動向

    永田真

    電子情報技術産業協会(JEITA) 2019年度先端電子材料・デバイス技術フォーラム, Jul. 2019, Japanese, 東京, Domestic conference

    Oral presentation

  • Power Noise Simulation of IC Chips for Hardware Security

    Makoto Nagata

    2019 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI 2019), Jul. 2019, English, New Orleans, International conference

    Oral presentation

  • C-P-S Simulation Techniques for Safety and Security

    Makoto Nagata

    Ansys Workshop at DAC 2019, Jun. 2019, English, Las Vegas, International conference

    Oral presentation

  • Diversity in IC labs.

    Makoto Nagata

    IEEE Diversity Luncheon at VLSI Symposium, Jun. 2019, English, 京都, International conference

    Oral presentation

  • 暗号モジュールにおける電源ノイズとサイドチャネル漏洩の対策設計と評価法の検討

    門田和樹, 安田一樹, 三木拓司, 沖殿貴朗, 三浦典之, 永田真

    LSIとシステムのワークショップ2019, May 2019, Japanese, 東京, Domestic conference

    Oral presentation

  • ICチップの電源ノイズ特性に着目したパッケージング構造の評価

    地家幸佑, 渡邊航, 三浦典之, 永田真

    LSIとシステムのワークショップ2019, May 2019, Japanese, 東京, Domestic conference

    Oral presentation

  • インバータ電源装置における不要電波の広帯域測定とノイズ低減手法の評価

    渡邊航, 椙本祥史, 三浦典之, 田中聡, 山口正洋, 永田真

    LSIとシステムのワークショップ2019, May 2019, Japanese, 東京, Domestic conference

    Oral presentation

  • Deployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security

    Makoto Nagata

    The 5th France-Japan Cybersecurity Workshop, May 2019, English, 京都, International conference

    Oral presentation

  • Undesired Radio Waves of IoT Devices: Evaluation and Countermeasures (Invited)

    Makoto Nagata

    The 2nd Croatia - Japan Electromagnetic Compatibility Workshop (CJEMC 2019), May 2019, English, 仙台, International conference

    [Invited]

    Invited oral presentation

  • Leveraging Chip Power Models for System-Level EMC Simulation of Automotive Ics

    Makoto Nagata

    ANSYS Webinar, Apr. 2019, English, Domestic conference

    Oral presentation

  • IoTデバイスにおける不要電波の評価と対策

    NAGATA Makoto

    VCCI協会技術シンポジウム, Jan. 2019, Japanese, 東京, Domestic conference

    Keynote oral presentation

  • Deployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security

    NAGATA Makoto

    ECE Seminar, Sep. 2018, English, Singapore, International conference

    Invited oral presentation

  • ハードウェアセキュリティを担うアナログ技術

    NAGATA Makoto

    IoTセキュリティ・フォーラム, Aug. 2018, Japanese, 東京, Domestic conference

    Invited oral presentation

  • Toward EMC Compliant Design of IC Chips in Automotive Applications

    NAGATA Makoto

    The 1st Croatia-Japan EMC Workshop, May 2018, English, Zagreb, International conference

    Invited oral presentation

  • アナログ計測セキュリティ技術 -センサデータ漏洩を防ぐセキュアAD変換器

    MIKI Takuji, MIURA Noriyuki, NAGATA Makoto

    計測セキュリティフォーラム2018, Apr. 2018, Japanese, 東京, Domestic conference

    Poster presentation

  • レーザーフォールト攻撃対策である電源遮断回路実装時のサイドチャネル耐性評価

    KORI Yoshihiro, FUJIMOTO Daisuke, HAYASHI Yuichi, MIURA Noriyuki, NAGATA Makoto, SAKIYAMA Kazuo

    ハードウェアセキュリティ研究会, Mar. 2018, Japanese, Domestic conference

    Oral presentation

  • ミリ波レーダの環境擾乱応答の評価システムのハードウェア実装

    MACHIDA Tasuya, MATSUDA Kohei, MIURA Noriyuki, NASHIMOTO Shoei, SUZUKI Daisuke, NAGATA Makoto

    ハードウェアセキュリティ研究会, Mar. 2018, Japanese, Domestic conference

    Oral presentation

  • Challenges: Deployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security

    NAGATA Makoto

    COSIC Seminar, Mar. 2018, English, International conference

    Public discourse

  • チップ・パッケージ・ボード非接触インターラクションとカオス発振を利用したPUF

    MIURA Noriyuki, TAKAHASHI Masanori, MATSUDA Kohei, NAGATA Makoto

    ハードウェアセキュリティフォーラム2017, Dec. 2017, Japanese, Domestic conference

    Poster presentation

  • インピーダンス計測に基づくICの周辺に実装されたHT検出手法の検討

    NIN Shota, FUJIMOTO Daisuke, HAYASHI Yuichi, MIURA Noriyuki, NAGATA Makoto, MATSUMOTO Tsutomu

    ハードウェアセキュリティフォーラム2017, Dec. 2017, Japanese, Domestic conference

    Poster presentation

  • ICチップのハードウェア・トロージャンと対策の技術動向

    NAGATA Makoto

    ハードウェアセキュリティフォーラム2017, Dec. 2017, Japanese, Domestic conference

    Invited oral presentation

  • 3D Design for Diagnosis and Characterization with In-Place Waveform Capturing (Invited)

    NAGATA Makoto

    MIITEC Advanced Testing Technology Seminar, Dec. 2017, English, International conference

    Public discourse

  • Protecting Cryptographic Integrated Circuits with Side-Channel Information

    NAGATA Makoto

    2017 IEEE 12th International Conference on ASIC (ASICON 2017), Oct. 2017, English, International conference

    Public discourse

  • ICチップレベルのEMCシミュレーション

    NAGATA Makoto

    ANSYS Day 2017, Oct. 2017, Japanese, Domestic conference

    Public discourse

  • EMI性能の獲得に向けたICチップの電源ノイズシミュレーション

    TSUKIOKA Akihiro, NAGATA Makoto

    ANSYS Day 2017, Oct. 2017, Japanese, Domestic conference

    Poster presentation

  • 高密度半導体永久ストレージの研究

    MIURA Noriyuki, NAGATA Makoto

    ハードウエアセキュリティ研究会, Sep. 2017, Japanese, Domestic conference

    Invited oral presentation

  • Simulation Techniques for EMC compliant Design of Automotive IC Chips and Modules

    TSUKIOKA Akihiro, TANIGUCHI Kohki, FUJIMOTO Daisuke, NAGATA Makoto, EGAMI Takao, AKIMOTO Reiko, NINOMI Kenji, YUHARA Takeshi, Rob Mathews, Karthik Srinivasan, Ying-Shiun Li, Norman Chang

    ACM IEEE Design Automation Conference (DAC 2017), Jun. 2017, English, International conference

    Poster presentation

  • PRINCE暗号プロセッサの超軽量実装

    MATSUDA Kohei, MIURA Noriyuki, NAGATA Makoto, Shivam Bashin, Ville Yli-Mayry, HOMMA Naofumi, Yves Mathieu, Tarik Graba, Jean-Luc Danger

    ハードウェアセキュリティ研究会, Jun. 2017, Japanese, Domestic conference

    Oral presentation

  • 二段階遷移型インバータを利用した500MHz -52.5dB-THD電圧時間変換回路

    MIZUTA Kento, MIKI Takuji, MIURA Noriyuki, DOSHO Shiro, NAGATA Makoto

    LSIとシステムのワークショップ2017, May 2017, Japanese, Domestic conference

    Poster presentation

  • EMI性能の獲得に向けたICチップの電源ノイズシミュレーション

    TSUKIOKA Akihiro, NAKASHIMA Hiroki, MIURA Noriyuki, NAGATA Makoto

    LSIとシステムのワークショップ2017, May 2017, Japanese, Domestic conference

    Poster presentation

  • A Permanent Digital Archive System Based on 4F^2 X-Point Multi-Layer Metal Nano-Dot Structure

    MIURA Noriyuki, Shijia Liu, WATANABE Tsuyoshi, IMAI Shigeki, NAGATA Makoto

    IEEE SSCS Kansai Chapter Technical Seminar, Feb. 2017, Japanese, Domestic conference

    Invited oral presentation

  • ハードウェアセキュリティ:トロイと対策の技術動向

    NAGATA Makoto

    JEITA ハードウェアセキュリティ技術分科会, 2017, Japanese, Domestic conference

    Invited oral presentation

  • 高解像度・高速タッチセンサのノイズ耐性評価とノイズ低減手法の検討

    KIRIYAMA Takuya, MIURA Noriyuki, NAGATA Makoto

    シリコンアナログRF研究会, Mar. 2016, Japanese, Domestic conference

    Oral presentation

  • 基板電位変動モニタリングによるレーザーフォールト注入攻撃対策

    MATSUDA Kohei, MIURA Noriyuki, NAGATA Makoto, HAYASHI Yuichi, FUJII Tatsuya, YAGASAKI Reina, SAKIYAMA Kazuo

    LSIとシステムのワークショップ2016, 2016, Japanese, Domestic conference

    Poster presentation

  • チップ・パッケージ・ボードレベルの物理攻撃対策回路技術

    MIURA Noriyuki, NAGATA Makoto

    ハードウェアセキュリティフォーラム2016, 2016, Japanese, Domestic conference

    Invited oral presentation

  • SystemVueのHILS応用による物理層ノイズの評価と解析(招待講演)

    NAGATA Makoto

    Keysight 5G AKIBA Summit, 2016, Japanese, Domestic conference

    Public discourse

  • SiP Packaging-Compatible Magnetic Thin-Film Noise Suppressor to Countermeasure Digital Noise from Power Electronics Devices (invited)

    YAMAGUCHI Masahiro, TANAKA Satoshi, Jingyan Ma, MIYAZAWA Yasunori, NAGATA Makoto, KONDO Koichi, OKIYONEDA Yasuyuki, NISHIZAWA Masahiro

    The 7th Asia-Pacific International Symposium on Electromagnetic Compatibility & Signal Integrity and Technical Exhibition (APEMC 2016), 2016, English, International conference

    Invited oral presentation

  • IoT時代、混雑する無線機器の内外環境における通信品質向上のための課題と開発の基礎―干渉、ノイズ、EMC等の品質劣化要因の理解と対策の勘所―

    NAGATA Makoto

    第5回移動体通信(LTE)を例としたICチップレベルの自家中毒と通信性能へのインパクト, 2016, Japanese, Domestic conference

    Public discourse

  • IoT時代に向けた不要電波対策技術

    NAGATA Makoto

    エネルギーインテグリティーシステム研究センターシンポジウム, 2016, Japanese, Domestic conference

    Invited oral presentation

  • ICチップのハードウェアセキュリティ:真正性の確保と攻撃への対策

    NAGATA Makoto

    2016 IEEE Metro Area Workshop in Kansai, 2016, Japanese, Domestic conference

    Invited oral presentation

  • FPGA実装した暗号コアからの放射電磁波ノイズ量と情報漏洩量の相関評価

    YOSHIDA Hiroki, MIURA Noriyuki, NAGATA Makoto

    LSIとシステムのワークショップ2016, 2016, Japanese, Domestic conference

    Poster presentation

  • Noise Simulation in Mixed-Signal SoCs

    NAGATA Makoto

    2016 IEEE International Solid-State Circuits Conference, Jan. 2016, English, International conference

    Public discourse

  • IoT時代、混雑する無線機器の内外環境における通信品質向上のための課題と開発の基礎~干渉、ノイズ、EMC等の品質劣化要因の理解と対策の勘所~第5回移動体通信(LTE)を例としたICチップレベルの自家中毒と通信性能へのインパクト

    NAGATA Makoto

    日本情報技術センター, Jul. 2015, Japanese, Domestic conference

    Public discourse

  • IC Chips to be Dependable, Secure, and Robust

    NAGATA Makoto

    International Technical Conference on Circuits Systems /Computers and Communcations 2015 (ITC-CSCC 2015), Jul. 2015, English, International conference

    Keynote oral presentation

  • Securing Cryptographic Engines -- Circuit Techniques against EM Attacks

    NAGATA Makoto

    International Symposium on IoT Enabling Chips, Jun. 2015, English, International conference

    Invited oral presentation

  • Diagnosis, Protection, and Configurability of I/O Circuits for 3D Chip Stacking

    NAGATA Makoto

    Design for three dimensional integration (D43D), Jun. 2015, English, International conference

    Invited oral presentation

  • 製品テストにおける適応型電源共振ノイズ抑制フィルタ

    TANIGUCHI Kohki, MIURA Noriyuki, HAYASHI Taisuke, NAGATA Makoto

    LSIとシステムのワークショップ2015, May 2015, Japanese, Domestic conference

    Poster presentation

  • 暗号処理回路への近傍電磁波解析攻撃を検知する完全デジタル発振器型センサ

    TANAKA Renta, MIURA Noriyuki, FUJIMOTO Daisuke, HOMMA Naofumi, HAYASHI Yuichi, AOKI Takafumi, NAGATA Makoto

    LSIとシステムのワークショップ2015, May 2015, Japanese, Domestic conference

    Poster presentation

  • IC Chips to Be Dependable, Secure, and Robust

    NAGATA Makoto

    CESCA, May 2015, English, International conference

    Keynote oral presentation

  • In-Place Diagnosis of Undesired Power Domain Problems in IC Chips and Stacks

    NAGATA Makoto

    ST Microelectronics Internal Seminar, Mar. 2015, English, ST Microelectronics, Crolles, International conference

    Public discourse

  • Broadband Metal-Insulator-Metal Capacitors on Silicon Interposer for Low Impedance Power Distribution Network

    UEDA Nao, Cesar Roda Neve, Mikael Detalle, Geert Van der Plas, Eric Beyne, NAGATA Makoto

    DATE 2015 Workshop on 3D Integration, Mar. 2015, English, IEEE, Grenoble, International conference

    Oral presentation

  • ICチップの真正性の確保と対策 ~ハードウェアセキュリティの根源的課題に向き合う~

    NAGATA Makoto

    ICシステムセキュリティ協会, Feb. 2015, Japanese, 神田, Domestic conference

    Public discourse

  • IC Chip Immunity Measurements and Analysis

    NAGATA Makoto

    ANSYS Electronics Simulation EXPO 2014, Feb. 2015, English, Ansys, San Jose, International conference

    Public discourse

  • Side Channel Leakage in Cryptographic Modules: Introduction to Physical Origins and Attack Models

    NAGATA Makoto

    ACM and IEEE 20th Asia and South Pacific Design Automation Conference, Jan. 2015, English, ACM and IEEE, 幕張, International conference

    Public discourse

  • IC Chip Level Low Noise Technology for High Speed and High Quality Telecommunication Systems

    YAMAGUCHI Masahiro, TANAKA Satoshi, ENDO Yasushi, NAGATA Makoto, MATSUI Hiroaki, IMAWANAMI Mizuki, TSUKAMOTO Kenta

    IEICE 2014 Asia-Pacific Microwave Conference, Nov. 2014, English, 電子情報通信学会, 仙台, Domestic conference

    Oral presentation

  • 貫通シリコンビアとアクティブインタポーザを用いた4096 bit幅100 Gbyte/秒ワイドI/Oの設計と診断

    NAGATA Makoto, TAKAYA Satoshi, IKEDA Hiroaki

    2014年度第4回TSV応用研究会, Oct. 2014, Japanese, 四谷, Domestic conference

    Oral presentation

  • RF-ICチップにおける基板結合ノイズの解析と実測

    NAGATA Makoto

    ANSYS Electronics Simulation EXPO 2014, Oct. 2014, Japanese, ANSYS, 東京, Domestic conference

    Nominated symposium

  • CDM ESD Testing of a 3D TSV Stacked IC Chip

    NAGATA Makoto, TAKAYA Satoshi, IKEDA Hiroaki, Dimitri Linten, Mirko Scholz, Shih-Hung Chen, HASEGAWA Keiichi, SHINTANI Taizo, SAWADA Masanori

    Fifth IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Oct. 2014, English, IEEE, Seattle, International conference

    Oral presentation

  • バンドギャップ基準電圧回路のオンチップモニタを使ったノイズ解析

    MURATA Akitaka, IKOMA Daisaku, WAGATSUMA Shuji, NAGATA Makoto

    電気学会電子・情報・システム部門大会, Sep. 2014, Japanese, 電気学会, 島根, Domestic conference

    Oral presentation

  • VLSIチップにおける電源雑音の評価とモデリング

    NAGATA Makoto

    電気学会電子・情報・システム部門大会, Sep. 2014, Japanese, 電気学会, 島根, Domestic conference

    Oral presentation

  • 半導体チップにおける電源ノイズとEMCの実際

    NAGATA Makoto

    第57回STARCアドバンストセミナー, Jun. 2014, Japanese, 半導体理工学研究センター, 横浜, Domestic conference

    Public discourse

  • ICチップレベルのサイドチャネル情報漏洩の計測とシミュレーション

    NAGATA Makoto

    JIEP最先端実装技術シンポジウム, Jun. 2014, Japanese, エレクトロニクス実装学会, 東京, Domestic conference

    Public discourse

  • 動作環境変動に応じて動的に動作マージンを拡大する自律制御キャッシュ

    KIMI YUTA, NAKATA YOHEI, OKUMURA SYUNSUKE, JUNG Jinwook, 澤田 卓也, 利川 托, NAGATA MAKOTO, 中野 博文, 藪内 誠, 藤原 英弘, 新居 浩二, 河合 浩行, KAWAGUCHI HIROSHI, YOSHIMOTO MASAHIKO

    LSIとシステムのワークショップ2014 ポスターセッション, May 2014, Japanese, 小倉, Domestic conference

    Poster presentation

  • 基板ノイズによるLTE通信品質への影響のシステムレベル評価

    KOUSAKA Jyunpei, SHIMAZAKI Shunsuke, MIURA Noriyuki, NAGATA Makoto

    電子情報通信学会集積回路研究会・LSIとシステムのワークショップ2014, May 2014, Japanese, 電子情報通信学会集積回路研究会, 北九州, Domestic conference

    Poster presentation

  • Power Noise Awareness in Design and Diagnosis of VLSI Systems

    NAGATA Makoto

    2014 18th IEEE Workshop on Signal and Power Integrity, May 2014, English, IEEE, Ghent, International conference

    Invited oral presentation

  • Measurements and Simulation of RF Noise Coupling and Its Impacts on LTE Wireless Communication Performance

    NAGATA Makoto, SHIMAZAKI Shunsuke, AZUMA Naoya, MUROGA Sho, ENDO Yasushi, TANAKA Satoshi, YAMAGAGUCHI Masahiro

    2014 International Symposium on Electromagnetic Compatibility, Tokyo, May 2014, English, IEEJ, IEICE, IEEE, Tokyo, International conference

    [Invited]

    Nominated symposium

  • Power Noise Awareness in Design and Diagnosis of VLSI Systems

    NAGATA Makoto

    2013 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), Dec. 2013, English, IEEE, Nara, International conference

    Keynote oral presentation

  • Power-Noise Measurements and Simulation Techniques for Side-Channel Analysis

    NAGATA Makoto

    2013 IEEE International Symposium on Electromagnetic Compatibility (EMC 2013), Sep. 2013, English, IEEE, Denver, International conference

    [Invited]

    Nominated symposium

  • In-Place Signal and Power Noise Waveform Capturing within 3D Chip Stacking

    NAGATA Makoto, TAKAYA Satoshi, IKEDA Hiroaki

    Fourth IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST), Sep. 2013, English, IEEE, Anaheim, International conference

    Oral presentation

  • In-Place Signal and Power Noise Waveform Capturing within 3D Chip Stacking

    NAGATA Makoto, TAKAYA Satoshi, IKEDA Hiroaki

    2013 IEEE International Test Conference (ITC 2013), Sep. 2013, English, IEEE, Anaheim, International conference

    Poster presentation

  • Design Strategies using 2D Toolsets for 3D TSV Chip Stacks featuring 4096b Wide I/O at 100GB/s

    NAGATA Makoto, TAKAYA Satoshi, SAKAI Atsushi, UCHIYAMA Shiro, KOBAYASHI Harufumi, IKEDA Hiroaki

    Design Automation Conference 2013 (DAC 2013), Jun. 2013, English, ACM/IEEE, Austin, International conference

    Poster presentation

  • (招待講演)VLSIチップ-パッケージ-ボードを統合した電源系ノイズの実測と解析

    NAGATA Makoto

    シリコンアナログRF研究会, Mar. 2013, Japanese, 電子情報通信学会, Chuo University, Domestic conference

    Invited oral presentation

  • 動的電源電圧変動に対するSRAM コアの動作不良感度

    SAWADA Takuya, TAKATA Hidehiro, NII Koji, NAGATA Makoto

    第27回エレクトロニクス実装学会春季講演大会, Mar. 2013, Japanese, エレクトロニクス実装学会, Tohoku University, Domestic conference

    Oral presentation

  • バッテリー駆動型オンチップ電源雑音モニタシステムの構築

    SASAKI Yuta, TAKEUCHI Yuji, YOSHIKAWA Kumpei, NAGATA Makoto

    電子情報通信学会総合大会, Mar. 2013, Japanese, 電子情報通信学会, Gifu University, Domestic conference

    Oral presentation

  • オンチップ波形モニタ回路における可変スロープ・可変オフセット電圧発生回路の改良

    UEYAMA Shinichiro, AZUMA Naoya, NAGATA Makoto

    電子情報通信学会総合大会, Mar. 2013, Japanese, 電子情報通信学会, Gifu University, Domestic conference

    Oral presentation

  • TEG チップ上に集積化した磁性薄膜によるLTE 帯域内ノイズ抑制効果

    MUROGA Sho, PENG Fan, ENDO Yasushi, ITOU Tetsuo, MURAKAMI Motoki, HORI Kazuaki, TAKAHASHI Satoshi, TANAKA Satoshi, AZUMA Naoya, NAGATA Makoto, YAMAGUCHI Masahiro

    第27回エレクトロニクス実装学会春季講演大会, Mar. 2013, Japanese, エレクトロニクス実装学会, Tohoku University, Domestic conference

    Oral presentation

  • SRAMのAC電源変動に対する不良応答と素子ばらつきの影響

    SAWADA Takuya, YOSHIKAWA Kumpei, TAKATA Hidehiro, NII Koji, NAGATA Makoto

    電子情報通信学会総合大会, Mar. 2013, Japanese, 電子情報通信学会, Gifu University, Domestic conference

    Oral presentation

  • RF基板結合評価のためのマルチトーンノイズ発生回路

    MAKITA Tetsuya, AZUMA Naoya, NAGATA Makoto

    電子情報通信学会総合大会, Mar. 2013, Japanese, 電子情報通信学会, Gifu University, Domestic conference

    Oral presentation

  • LPB統合ノイズ解析~テストチップにおけるオンチップとオンボードのノイズを例題として~【特別展示】LPBゾーン・IBISゾーンにおける講演及び出展

    NAGATA Makoto

    Electronic Design and Solution Fair 2012, Nov. 2012, Japanese, 電子情報技術産業協会, 横浜市, Domestic conference

    Invited oral presentation

  • A Simulation Methodology Aearching Side-Channel Leakage Using Capacitor Charging Model

    FUJIMOTO Daisuke, TANAKA Daichi, NAGATA Makoto

    The 7th International Workshop on Security (IWSEC2012), Nov. 2012, English, 電子情報通信学会, Kyushu University, Domestic conference

    Poster presentation

  • ノイズとLSI回路設計技術

    NAGATA Makoto

    第29回「センサ・マイクロマシンと応用システム」シンポジウム, Oct. 2012, Japanese, 電気学会, 北九州市, Domestic conference

    Invited oral presentation

  • 移動体通信RF-LSIにおける基板雑音の影響評価手法の提案

    IMAI Satoshi, AZUMA Naoya, RIN Shiwa, UEYAMA Shinichiro, MAKITA Tetsuya, KUBOTA Atsuto, TAGA Shota, NAGATA Makoto

    LSIとシステムのワークショップ2012, May 2012, Japanese, 電子情報通信学会, 北九州市, Domestic conference

    Oral presentation

  • LSIとシステムのノイズ問題(招待講演)

    NAGATA Makoto

    LSIとシステムのワークショップ2012, May 2012, Japanese, 電子情報通信学会, 北九州市, Domestic conference

    Invited oral presentation

  • LSIチップ・パッケージ・ボード(LPB)統合電源インピーダンスを考慮した電源雑音の測定と解析

    SASAKI Yuta, YOSHIKAWA Kumpei, HARADA Yuji, NAGATA Makoto

    LSIとシステムのワークショップ2012, May 2012, Japanese, 電子情報通信学会, 北九州市, Domestic conference

    Oral presentation

  • 差動増幅回路における基板雑音感度の評価

    TAKAYA Satoshi, BANDO Yoji, OHKAWA Toru, TAKRAMOTO Toshiharu, YAMADA Toshio, SOUDA Masaaki, KUMASHIRO Shigetaka, MOGAMI Tohru, NAGATA Makoto

    電子情報通信学会総合大会, Mar. 2012, Japanese, 電子情報通信学会, 岡山市, Domestic conference

    Oral presentation

  • オンチップ電源ノイズ離散化手法とRF 直接電力注入によるSRAMのイミュニティ評価への応用

    TOSHIKAWA Taku, SAWADA Takuya, YOSHIKAWA Kumpei, TAKATA Hidehiro, NII Koji, NAGATA Makoto

    電子情報通信学会総合大会, Mar. 2012, Japanese, 電子情報通信学会, 岡山市, Domestic conference

    Oral presentation

  • Variation of Substrate Sensitivity in Differential Pair Transistors

    TAKAYA Satoshi, HASEGAWA Takashi, BANDO Yoji, OHKAWA Toru, TAKARAMOTO Toshiharu, YAMADA Toshio, SOUDA Masaaki, KUMASHIRO Shigetaka, MOGAMI Tohru, NAGATA Makoto

    Workshop on Synthesis and System Integration of Mixed Information Technologies, Mar. 2012, English, IEEE, 別府市, International conference

    Poster presentation

  • CMOSデジタル回路における動的ノイズ

    NAGATA Makoto

    電子情報通信学会・電子デバイス研究会特別ワークショップ, Mar. 2012, Japanese, 電子情報通信学会, 東京都, Domestic conference

    Invited oral presentation

  • VLSIチップの電源ノイズ ~シリコン基板から電磁環境まで~

    NAGATA Makoto

    電気学会・高度化アナログ電子回路の高効率化設計技術調査専門委員会, Jan. 2012, Japanese, 電気学会, 東京都, Domestic conference

    Invited oral presentation

  • VLSIチップの電源ノイズとEMC

    NAGATA Makoto

    IEEE EMC Society Sendai Chapter・東北大学EMC仙台ゼミナール共催学生発表会, Dec. 2011, Japanese, IEEE, 仙台市, Domestic conference

    Invited oral presentation

  • Variation of Substrate Sensitivity in Differential Pair Transistors

    TAKAYA Satoshi, HASEGAWA Takashi, BANDO Yoji, OHKAWA Toru, TAKRAMOTO Toshiharu, YAMADA Toshio, SOUDA Masaaki, KUMASHIRO Shigetaka, MOGAMI Tohru, NAGATA Makoto

    IEEE Workshop on Variability Modeling and Characterization, Nov. 2011, English, IEEE, San Jose, USA, International conference

    Poster presentation

  • デジタルLSIのオンボード電流ノイズおよびPDNインピーダンスの測定評価

    SASAKI Yuta, YOSHIKAWA Kumpei, NAGATA Makoto

    電子情報通信学会ソサイエティ大会, Sep. 2011, Japanese, 電子情報通信学会, 札幌市, Domestic conference

    Oral presentation

  • デジタルLSIのオンチップ電源ノイズ測定とPDNインピーダンスモデリング

    YOSHIKAWA Kumpei, SASAKI Yuta, NAGATA Makoto

    電子情報通信学会ソサイエティ大会, Sep. 2011, Japanese, 電子情報通信学会, 札幌市, Domestic conference

    Oral presentation

  • A Fast Power Current Analysis Methodology using Capacitor Charging Model for Side Channel Attack Evaluation

    FUJIMOTO Daisuke, NAGATA Makoto, KATASHITA Toshihiro, SASAKI Akihiro, HORI Yohei, SATOH Akashi

    CHES2011, Sep. 2011, English, IACR, 奈良市, International conference

    Poster presentation

  • VLSIの電源ノイズ・基板ノイズと測定技術

    NAGATA Makoto

    学振第165委員会 VLSI夏の学校, Aug. 2011, English, 学振第165委員会, 豊中市, Domestic conference

    Invited oral presentation

  • 高周波LSIにおける基板結合の評価とモデリング

    AZUMA Naoya, KANDA Yasutaka, NAGATA Makoto

    ICDシリコンアナログRF研究会, May 2011, Japanese, 電子情報通信学会, 北九州市, Domestic conference

    Oral presentation

  • 差動対トランジスタにおける基板ノイズ応答のオンチップ評価と解析

    BANDO Yoji, TAKAYA Satoshi, HASEGAWA Takashi, OHKAWA TORU, TAKARAMOTO Toshiharu, YAMADA Toshio, SOUDA Masaaki, KUMASHIRO Shigetaka, MOGAMI Tohru, NAGATA Makoto

    電子情報通信学会 総合大会, Mar. 2011, Japanese, 電子情報通信学会, 東京都, Domestic conference

    Oral presentation

  • 高分解能オンチップモニタシステムを用いたミックストシグナルSoCの診断技術

    HASHIDA Takushi, ARAGA Yuuki, NAGATA Makoto

    電子情報通信学会 総合大会, Mar. 2011, Japanese, 電子情報通信学会, 東京都, Domestic conference

    Oral presentation

  • CMOSデジタル回路における動的ノイズ

    NAGATA Makoto

    電子情報通信学会 総合大会, Mar. 2011, Japanese, 電子情報通信学会, 東京都, Domestic conference

    Invited oral presentation

  • On-chip In-situ Measurements of Vth, Signal Gain, and Substrate Sensitivity of Differential Pair Transistors

    TAKAYA Satoshi, BANDO Yoji, OHKAWA Toru, TAKARAMOTO Toshiharu, YAMADA Toshio, SOUDA Masaaki, KUMASHIRO Shigetaka, MOGAMI Tohru, NAGATA Makoto

    IEEE Workshop on Variability Modeling and Characterization, Nov. 2010, English, IEEE, San Jose, USA, International conference

    Poster presentation

  • VLSIの電源ノイズ・基板ノイズと測定技術

    NAGATA Makoto

    学振第165委員会 VLSI夏の学校, Aug. 2010, Japanese, 学振第165委員会, 東京都, Domestic conference

    Invited oral presentation

  • Evaluation of Power Noises in VLSI Circuits (Invited)

    NAGATA Makoto

    ICD in Vietnam 2010, Aug. 2010, English, 電子情報通信学会, Ho Chi Minh, Vietnam, International conference

    Invited oral presentation

  • 2010 Symposium on VLSI Circuits Overview

    NAGATA Makoto

    ICD サマーワークショップ2010, Aug. 2010, Japanese, 電子情報通信学会, 廿日市市, Domestic conference

    Invited oral presentation

  • SoCのオンチップ雑音評価技術

    NAGATA Makoto

    2010最先端実装技術シンポジウム, Jun. 2010, Japanese, エレクトロニクス実装学会, 東京都, Domestic conference

    Invited oral presentation

  • 差動増幅回路におけるVthとAC応答のその場評価技術

    TAKAYA Satoshi, BANDO Yoji, OHKAWA TORU, SOUDA Masaaki, TAKARAMOTO Toshiharu, YAMADA Toshio, KUMASHIRO Shigetaka, MOGAMI Tohru, NAGATA Makoto

    ICD LSIとシステムのワークショップ2010, May 2010, Japanese, 電子情報通信学会, 北九州市, Domestic conference

    Poster presentation

  • On-Chip Power Noise Monitoring and Diagnosis

    NAGATA Makoto

    IEEE International Solid-State Circuits Conference 2010, Feb. 2010, English, IEEE, San Francisco, International conference

    Invited oral presentation

  • CMOSデジタル回路における雑音発生のモデル化と実証

    FUJIMOTO Daisuke, MATSUNO Tetsuro, NAGATA Makoto

    集積回路研究会若手研究会, Dec. 2009, Japanese, 電子情報通信学会, 静岡市, Domestic conference

    Poster presentation

  • CMOSアナログ回路における基板ノイズ応答の解析

    TAKAYA Satoshi, BANDO Yoji, NAGATA Makoto

    集積回路研究会若手研究会, Dec. 2009, Japanese, 電子情報通信学会, 静岡市, Domestic conference

    Poster presentation

  • CMOS-RF回路における基板結合の評価と解析

    AZUMA Naoya, NAGATA Makoto

    集積回路研究会若手研究会, Dec. 2009, Japanese, 電子情報通信学会, 静岡市, Domestic conference

    Poster presentation

  • オンチップ・ノイズモニタ技術

    NAGATA Makoto

    IEEE SSCS Kansai Chapter Technical Seminar, Oct. 2009, Japanese, IEEE SSC Society Kansai Chapter, 神戸市, Domestic conference

    Invited oral presentation

  • スタンダードセルベースCMOSデジタル回路の電源雑音解析手法

    MATSUNO Tetsuro, KOSAKA Daisuke, NAGATA Makoto

    情報処理学会関西支部大会, Sep. 2009, Japanese, 情報処理学会, 神戸市, Domestic conference

    Oral presentation

  • オンチップモニタの搭載技術

    HASHIDA Takushi, NAGATA Makoto

    STARCフォーラム/シンポジウム, Aug. 2009, Japanese, 半導体理工学研究センター, 横浜市, Domestic conference

    Poster presentation

  • Power Supply and Substrate Noise Analysis; Reference Tool Experience with Silicon Validation

    BANDO Yoji, KOSAKA Daisuke, YOKOMIZO Goichi, TSUBOI Kunihiko, LI Ying Shiun, LIN Shen, NAGATA Makoto

    Design Automation Conference 2009, Jul. 2009, English, IEEE, San Francisco, International conference

    Oral presentation

  • On-Chip Power Supply Noise Measurements

    NAGATA Makoto

    2009 VLSI Circuits Short Course, Jun. 2009, English, IEEE, 京都市, International conference

    Invited oral presentation

  • ばらつきを含めたオンチップモニタ回路の性能評価

    BANDO Yoji, TAKAYA Satoshi, NAGATA Makoto

    LSIとシステムのワークショップ2009, May 2009, Japanese, 電子情報通信学会, 北九州市, Domestic conference

    Poster presentation

  • デジタルLSI電源ノイズのオンチップ観測とシミュレーション技術

    NAGATA Makoto

    平成20年技術賞受賞記念講演, May 2009, Japanese, エレクトロニクス実装学会, 東京都, Domestic conference

    [Invited]

    Invited oral presentation

  • チップ間電源線通信を用いたオンチップモニタの搭載容易化手法

    HASHIDA Takushi, NAGATA Makoto

    LSIとシステムのワークショップ2009, May 2009, Japanese, 電子情報通信学会, 北九州市, Domestic conference

    Poster presentation

  • オンチップ・ノイズモニタ技術

    NAGATA Makoto

    第6回 IEEE CPMT Society Japan Chapter イブニングミーティング, May 2009, Japanese, IEEE CPMT Society Japan Chapter, 東京都, Domestic conference

    Invited oral presentation

  • On-Chip Waveform Capturing Functionality Partitioned for 3D Realization

    ARAGA Yuuki, BANDO Yoji, HASHIDA Takushi, NAGATA Makoto

    Design, Automation and Test in Europe 2009 (DATE), Friday Workshop on 3D Integration, Apr. 2009, English, IEEE, Nice, International conference

    Poster presentation

  • (招待講演)オンチップノイズモニタ技術とLSIの電源インテグリティ評価

    NAGATA Makoto

    エレクトロニクス実装学術講演大会, Mar. 2009, Japanese, (社)エレクトロニクス実装学会, 神奈川, Domestic conference

    Oral presentation

  • Performance Variability of On-chip Noise Monitor Circuits

    BANDO Yoji, HASHIDA Takushi, NAGATA Makoto

    Workshop on Test Structure Design for Variability Characterization, Nov. 2008, Japanese, IEEE, San Jose, Domestic conference

    Poster presentation

  • プロセッサ動作エラー検出のための命令レベルプログラミング手法

    SAWADA Takuya, FUKAZAWA Mitsuya, KURIMOTO Masanori, AKIYAMA Rei, TAKADA Hidehiro, NAGATA Makoto

    電子情報通信学会, Sep. 2008, Japanese, (社)電子情報通信学会, 横浜, Domestic conference

    Oral presentation

  • サブ100-nmデジタル回路におけるダイナミック電源雑音を考慮した信号遅延変動の評価と解析

    NAKAI Tohru, FUKAZAWA Mitsuya, NAGATA Makoto

    電子情報通信学会, Sep. 2008, Japanese, (社)電子情報通信学会, 横浜, Domestic conference

    Oral presentation

  • LSIチップ電源配線網の等価回路表現と評価

    YOSHIKAWA Kumpei, KOSAKA Daisuke, NAGATA Makoto

    電子情報通信学会, Sep. 2008, Japanese, (社)電子情報通信学会, 横浜, Domestic conference

    Oral presentation

  • ミックストシグナルSoCのためのオンチップモニタ技術

    NAGATA Makoto

    STARCフォーラム/シンポジウム 2008, Jul. 2008, Japanese, (株)半導体理工学研究センター, 横浜, Domestic conference

    Oral presentation

  • オンチップモニタのためのバックエンドデータ処理系の構築と波形取得性能の評価

    ARAGA Yuuki, NAGATA Makoto

    STARCフォーラム/シンポジウム 2008, Jul. 2008, Japanese, (株)半導体理工学研究センター, 横浜, Domestic conference

    Oral presentation

  • SoCのインテグリティ:オンチップ・モニタとノイズ解析技術

    NAGATA Makoto

    Electronic Design and Solution Fair 2008, Jan. 2008, Japanese, 電子情報技術産業協会(JEITA), 横浜市, Domestic conference

    Others

  • (基調講演)LSIを高性能化する設計技術の挑戦--インテグリティを指向する設計へ

    NAGATA Makoto

    Electronic Design and Solution Fair 2008, Jan. 2008, Japanese, 電子情報技術産業協会(JEITA), 横浜市, Domestic conference

    Invited oral presentation

  • (招待講演)オンチップモニタによるLSIとPCBのノイズ評価

    NAGATA Makoto

    システム実装CAE研究会公開研究会, Dec. 2007, Japanese, エレクトロニクス実装学会(JIEP), 東京, Domestic conference

    Invited oral presentation

  • 埋め込み型検出回路を用いたプロセッサの電源ノイズ評価

    MATSUNO Tetsuro, FUKAZAWA Mitsuya, UEMURA Toshifumi, AKIYAMA Rei, KAGEMOTO Tetsuya, MAKINO Hiroyuki, TAKATA Hidehiro, NAGATA Makoto

    第11回システムLSIワークショップ, Nov. 2007, Japanese, 電子情報通信学会(IEICE), 北九州市, Domestic conference

    Poster presentation

  • 埋め込み型検出回路によるプロセッサの電源雑音評価

    FUKAZAWA Mitsuya, NAGATA Makoto

    VDEC LSIデザイナーフォーラム2007, Sep. 2007, Japanese, 東京大学VDEC, 石狩郡, Domestic conference

    Oral presentation

  • オンチップモニタ・システムのSoC搭載設計法と評価

    HASHIDA Takushi, NAGATA Makoto

    STARCシンポジウム2007, Sep. 2007, Japanese, 半導体理工学研究センター(STARC), 大阪, Domestic conference

    Poster presentation

  • TS-CDMAによる超多重RFIDランスポンダ向け同期回路の検討

    FUKUMIZU Yohei, GOCHI Naoki, NAGATA Makoto, TAKI Kazuo

    電子情報通信学会ソサイエティ大会, Sep. 2007, Japanese, 電子情報通信学会, 鳥取市, Domestic conference

    Oral presentation

  • (招待講演)SoCのオンチップ雑音測定と評価

    NAGATA Makoto

    2007最先端実装技術シンポジウム(JPCA show 2007), May 2007, Japanese, 日本電子回路工業会(JPCA), 東京, Domestic conference

    Invited oral presentation

  • アナログ回路のオンチップ動作診断技術

    HASHIDA Takushi, NOGUCHI Koichiro, NAGATA Makoto

    第10回システムLSIワークショップ予稿集, Nov. 2006, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州国際会議場, Domestic conference

    Poster presentation

  • ダイナミック電源雑音によるデジタル信号遅延変動の評価

    FUKAZAWA Mitsuya, NAGATA Makoto

    VDEC LSIデザイナーフォーラム2006, Sep. 2006, Japanese, 東京大学, 高知, Domestic conference

    Poster presentation

  • Design of High-Frequency Substrate Noise Detector Considering Substarate Model

    FUJIWARA Masaki, KOSAKA Daisuke, DANJO Takumi, NAGATA Makoto

    Siricon Analog RF Group Meeting, Feb. 2006, Japanese, シリコンアナログRF時限研究専門委員会, Yokohama city, Domestic conference

    Oral presentation

  • Chip-Level Analysis and On-Chip Evaluation of Noise in SoC

    NAGATA Makoto

    Electronic Design and Solution Fair 2006, Jan. 2006, Japanese, (社)電子情報技術産業協会, Yokohama city, Domestic conference

    Others

  • Noise Analysis in Mixed Analog-Digital LSI

    NAGATA Makoto

    11th Micro-wave simulator workshop, Dec. 2005, Japanese, マイクロ波シミュレータ時限研究専門委員会, Musashino city, Domestic conference

    Invited oral presentation

  • Substrate Crosstalk Analysis and Remedy

    KOSAKA Daisuke, MATSUMOTO Tetsuro, NAGATA Makoto, MURASKA Yoshitaka, IWATA Atsushi

    9th System LSI Workshop, Nov. 2005, Japanese, 集積回路研究専門委員会, Kitakyushu city, Domestic conference

    Poster presentation

  • Power-Supply/Ground Noise Reduction and Measurements for High-Performance LSIs

    NAGATA Makoto

    NEDO産業技術助成事業:技術シーズ懇話会, Oct. 2005, Japanese, NEDO, Kawasaki city, Domestic conference

    Invited oral presentation

  • On-Chip Diagosis for Mixed-Signal LSI

    NAGATA Makoto

    STARC Symposium, Sep. 2005, Japanese, (株)半導体理工学研究センター, Osaka City, Domestic conference

    Poster presentation

  • On-Chip Multi-Channel Monitor for Signal Measurements in LSI

    NOGUCHI Koichiro, NAGATA Makoto

    VDEC LSI Designers Forum 2005, Aug. 2005, Japanese, 東京大学大規模集積システム設計教育研究センター, Yugawara, Domestic conference

    Poster presentation

  • Modulator/Demodulator Circuits for Highly Multiplexed RFID TAGs

    FUKUMIZU Yohei, ONO Shuji, NAGATA Makoto, TAKI Kazuo

    Siricon Analog RF Group Meeting, May 2005, Japanese, シリコンアナログRF時限研究専門委員会, Kobe city, Domestic conference

    Oral presentation

  • デジタルLSIにおける電源/グラウンド雑音の評価とモデリング

    永田 真

    第19回エレクトロニクス実装学術講演大会, Mar. 2005, Japanese, エレクトロニクス実装学会, 東京理科大学野田キャンパス, Domestic conference

    Oral presentation

  • SoCにおけるデジタルノイズ

    永田 真

    電子情報通信学会 総合大会, Mar. 2005, Japanese, 電子情報通信学会, 未記入, Domestic conference

    Oral presentation

  • 基盤雑音のオンチップ測定とモデル化手法

    永田 真

    シリコン超集積化システム学振第165委員会, Jan. 2005, Japanese, シリコン超集積化システム第165委員会, 未記入, Domestic conference

    Oral presentation

  • デジタルLSIの電源系雑音評価技術と適用事例

    永田 真

    Electronic Design and Solution Fair 2005, Jan. 2005, Japanese, 未記入, 未記入, Domestic conference

    Oral presentation

  • デジタルLSIの埋め込み型電源雑音検出手法

    深澤 光弥, 野口 宏一朗, 永田 真, 瀧 和男

    第8回システムLSIワークショップ, Nov. 2004, Japanese, 未記入, 未記入, Domestic conference

    Oral presentation

  • アナログLSIチップ開発ノウハウ

    永田 真

    映像情報メディア学会 若手研究者のためのイメージセンサLSI設計フォーラム, Oct. 2004, Japanese, 映像情報メディア学会, 東京理科大学, Domestic conference

    Oral presentation

  • 高性能LSIのためのデジタル電源/グラウンド雑音低減化設計及び診断技術の開発

    永田 真

    イノベーション・ジャパン2004, Sep. 2004, Japanese, イノベーションジャパン2004組織委員会, 東京国際フォーラム, Domestic conference

    Oral presentation

  • デジタルLSI における電源/グラウンド雑音の評価とモデリング

    永田 真, 植村 俊文

    電子情報通信学会 ソサエティ大会, Sep. 2004, Japanese, 電子情報通信学会, 未記入, Domestic conference

    Oral presentation

  • オンチップ信号モニタ回路の構成と評価

    野口 宏一朗, 永田 真

    STARCシンポジウム, Sep. 2004, Japanese, (株)半導体理工学研究センター, 新横浜国際ホテル, Domestic conference

    Oral presentation

  • 日本の大学における集積回路設計紹介 --VDECユーザ事例紹介--

    永田 真

    電子情報通信学会 総合大会, 2004, Japanese, 電子情報通信学会, 東京工業大学, Domestic conference

    Oral presentation

  • アナ・デジ混載SoCの下流設計・検証技術

    永田 真

    システムデザインセミナー, 2004, Japanese, 未記入, 未記入, Domestic conference

    Oral presentation

  • Substrate Noise Measurements and Analysis Case Studies

    NAGATA Makoto

    IEEE International Solid-State Circuits Conference, 2004, English, IEEE, San Francisco, International conference

    Oral presentation

  • 超多重応答を可能にするRFIDシステムのLSI設計と評価

    福水 洋平, 大野 修治, 永田 真, 瀧 和男

    第7回システムLSIワークショップ, 2003, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市国際会議場, Domestic conference

    Oral presentation

  • オンチップ電源/グラウンド測定技術

    野口 宏一朗, 奥本 健, 杉本 智彦, 永田 真, 瀧 和男

    第7回システムLSIワークショップ, 2003, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市国際会議場, Domestic conference

    Oral presentation

  • アナログ系設計ツールの課題と基板クロストーク対策

    永田 真

    第7回システムLSIワークショップ, 2003, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市国際会議場, Domestic conference

    Oral presentation

  • VDECユーザのためのアナログ系LSI設計フローと作法

    永田 真

    VDEC LSIデザイナーフォーラム, 2003, Japanese, 東京大学大規模集積システム設計教育センター, 未記入, Domestic conference

    Oral presentation

  • RF混載LSIにおける3GHz帯の基板雑音検出回路の研究

    山川 淳二郎, 河野 彩子, 岩田 穆, 永田 真, 村坂 佳隆

    第7回システムLSIワークショップ, 2003, Japanese, 電子情報通信学会集積回路研究専門委員会, 北九州市国際会議場, Domestic conference

    Oral presentation

Association Memberships

  • エレクトロニクス実装学会

  • IEEE

  • 応用物理学会

  • 電子情報通信学会

Research Projects

  • 永田 真

    科学研究費補助金/基盤研究(A), Apr. 2014 - Mar. 2017, Principal investigator

    Competitive research funding

  • 戦略的イノベーション創造プログラム(SIP)/重要インフラ等におけるサイバーセキュリティの確保/(a4)IoT向けのセキュリティ確認技術(IoT向けのセキュリティ確認技術の研究開発)

    永田 真

    電子商取引安全技術研究組合, 戦略的イノベーション創造プログラム, 2017, Principal investigator

    Competitive research funding

  • Sensor-to-Cloud Security~ビッグデータを守る革新的IoTセキュリティ基盤技術の研究開発

    永田 真

    国立研究開発法人新エネルギー・産業技術総合開発機構, IoT推進のための横断技術開発プロジェクト, 2017, Principal investigator

    Competitive research funding

  • 戦略的イノベーション創造プログラム(SIP)/重要インフラ等におけるサイバーセキュリティの確保/(a4)IoT向けのセキュリティ確認技術(IoT向けのセキュリティ確認技術の研究開発)

    永田 真

    戦略的イノベーション創造プログラム(SIP), 2016, Principal investigator

    Competitive research funding

  • Sensor-to-Cloud Security~ビッグデータを守る革新的IoTセキュリティ基盤技術の研究開発

    永田 真

    IoT推進のための横断技術開発プロジェクト, 2016, Principal investigator

    Competitive research funding

  • 高速・高品質な無線通信実現のためのICチップレベルの低ノイズ化技術の研究開発

    永田 真

    電波資源拡大のための研究開発, 2013, Principal investigator

    Competitive research funding

  • 高速・高品質な無線通信実現のためのICチップレベルの低ノイズ化技術の研究開発

    永田 真

    電波資源拡大のための研究開発, 2012, Principal investigator

    Competitive research funding

  • 永田 真

    科学研究費補助金/基盤研究(B), 2011, Principal investigator

    Competitive research funding

  • 高速・高品質な無線通信実現のためのICチップレベルの低ノイズ化技術の研究開発

    永田 真

    電波資源拡大のための研究開発, 2011, Principal investigator

    Competitive research funding

Industrial Property Rights

  • タイミング信号発生回路

    NAGATA Makoto, HASHIDA Takushi

    特願156755, 01 Jul. 2009, 企業単独, 特許未登録, 01 Jul. 2009

    Patent right